DISPLAY DEVICE, METHOD OF MANUFACTURING THE SAME AND ELECTRONIC DEVICE INCLUDING THE DISPLAY DEVICE

[0001] This application claims priority to Korean Patent Application No. 10-2025-0031939, filed on Mar. 12, 2025, and all the benefits accruing therefrom under 35 U.S.C. §119, the content of which in its entirety is herein incorporated by reference.

[0002] Embodiments relate to a display device, a method of manufacturing the display device, and an electronic device including the display device.

[0003] A display device displays an image to provide visual information to a user. The display device may be operated by thin film transistors, capacitors, and a plurality of lines that are interconnected in a complex manner.

[0004] Recently, as demand for compact and high-resolution display devices increases, there is a growing desire for efficient spatial arrangement, connection structures, and driving methods among the thin film transistors, the capacitors, and the lines included in the display device, as well as improving quality of displayed images.

[0005] Embodiments provide a display device including a capacitor with improved capacitance characteristics.

[0006] Embodiments provide a method of manufacturing the display device.

[0007] Embodiments provide an electronic device including the display device.

[0008] A display device in an embodiment of the disclosure includes a transistor, a capacitor electrically connected to the transistor and including a first capacitor electrode including a first conductive layer and a plasma-treated layer disposed on the first conductive layer and a second capacitor electrode disposed on the first capacitor electrode and including a second conductive layer, and an insulating layer disposed between the first capacitor electrode and the second capacitor electrode.

[0009] In an embodiment, the plasma-treated layer may be disposed between the first conductive layer and the second conductive layer, and a dielectric constant of the plasma-treated layer may be greater than a dielectric constant of the insulating layer.

[0010] In an embodiment, the plasma-treated layer may cover an upper surface of the first conductive layer.

[0011] In an embodiment, the plasma-treated layer may include titanium oxide.

[0012] In an embodiment, the plasma-treated layer may cover a side surface and an upper surface of the first conductive layer.

[0013] In an embodiment, the first conductive layer may include a first sub-conductive layer, a second sub-conductive layer disposed on the first sub-conductive layer and including a material different from a material of the first sub-conductive layer, and a third sub-conductive layer disposed on the second sub-conductive layer and including a material different from the material of the second sub-conductive layer, and the plasma-treated layer may include a first sub-plasma-treated layer covering a side surface of the first sub-conductive layer, a second sub-plasma-treated layer covering a side surface of the second sub-conductive layer, and a third sub-plasma-treated layer covering a side surface of the third sub-conductive layer and an upper surface of the third sub-conductive layer.

[0014] In an embodiment, each of the first sub-plasma-treated layer and the third sub-plasma-treated layer may include titanium oxide, and the second sub-plasma-treated layer may include aluminum oxide.

[0015] In an embodiment, a thickness of the plasma-treated layer along a thickness direction may be in a range of about 50 angstroms (Å) to about 700 Å.

[0016] In an embodiment, a dielectric constant of the plasma-treated layer may be in a range of about 10 to about 100.

[0017] In an embodiment, the plasma-treated layer may be an insulating layer.

[0018] A method of manufacturing a display device in an embodiment of the disclosure includes forming a first capacitor electrode including a first conductive layer and a plasma-treated layer disposed on the first conductive layer, forming an insulating layer on the first capacitor electrode, forming a second capacitor electrode on the insulating layer, the second capacitor electrode including a second conductive layer and defining a capacitor with the first capacitor electrode, and forming a transistor electrically connected to the capacitor.

[0019] In an embodiment, in the forming the first capacitor electrode, the plasma-treated layer may be formed by oxidizing at least a portion of a preliminary first conductive layer by treating the preliminary first conductive layer with oxygen plasma.

[0020] In an embodiment, the plasma-treated layer may be disposed between the first conductive layer and the second conductive layer, and a dielectric constant of the plasma-treated layer may be greater than a dielectric constant of the insulating layer.

[0021] In an embodiment, the forming the first capacitor electrode may include forming a preliminary first conductive layer, plasma-treating an upper surface of the preliminary first conductive layer to form a preliminary plasma-treated layer, and patterning the preliminary first conductive layer and the preliminary plasma-treated layer to form the first conductive layer and the plasma-treated layer.

[0022] In an embodiment, the plasma-treated layer may cover an upper surface of the first conductive layer.

[0023] In an embodiment, the plasma-treated layer may include titanium oxide.

[0024] In an embodiment, the forming the first capacitor electrode may include forming a preliminary first conductive layer, patterning the preliminary first conductive layer, and plasma-treating a side surface and an upper surface of the preliminary first conductive layer to form the first conductive layer and the plasma-treated layer.

[0025] In an embodiment, the plasma-treated layer may include a first sub-plasma-treated layer covering a side surface of the first conductive layer and a second sub-plasma-treated layer covering an upper surface of the first conductive layer and including a material different from a material of the first sub-plasma-treated layer.

[0026] In an embodiment, the first sub-plasma-treated layer may include aluminum oxide, and the second sub-plasma-treated layer may include titanium oxide.

[0027] An electronic device in an embodiment of the disclosure includes a display device and a processor that provides a control signal and input image data to the display device. The display device includes a transistor, a capacitor electrically connected to the transistor and including a first capacitor electrode including a first conductive layer and a plasma-treated layer disposed on the first conductive layer and a second capacitor electrode disposed on the first capacitor electrode and including a second conductive layer, and an insulating layer disposed between the first capacitor electrode and the second capacitor electrode.

[0028] In a display device in embodiments of the disclosure, the display device may include a capacitor defined by a first capacitor electrode including a plasma-treated layer and a second capacitor electrode. As the plasma-treated layer includes a high dielectric constant (or high-k) material, a capacitance of the capacitor may be secured. Accordingly, the display device including the capacitor with improved capacitance characteristics may be implemented.

[0040] Hereinafter, embodiments of the disclosure will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0041] It will be understood that when an element is referred to as being “on” another element, it may be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0042] It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

[0044] Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower,” may therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” may, therefore, encompass both an orientation of above and below.

[0045] "About" or "approximately" as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). The term such as "about" may mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value, for example.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0047] FIG. 1 is a plan view illustrating an embodiment of a display device according to the disclosure. FIG. 2 is a block diagram illustrating the display device of FIG. 1.

[0048] Referring to FIGS. 1 and 2, a display device DD may include a display panel PN and a driver that drives the display panel PN. The display panel PN may include a display area DA and a non-display area NDA.

[0049] The display area DA may be an area that displays an image. A plurality of pixels PX may be disposed in the display area DA. In an embodiment, the pixels PX may be repeatedly arranged along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, for example. As each of the pixels PX emits light, the display area DA may display an image. In an embodiment, the display area DA may display an image in a third direction DR3 intersecting each of the first direction DR1 and the second direction DR2, for example.

[0050] The non-display area NDA may be an area that does not display an image. The non-display area NDA may be disposed around the display area DA. In an embodiment, the non-display area NDA may surround the display area DA in a plan view, for example. The driver may be disposed in the non-display area NDA. In an embodiment, the driver may provide signals and/or voltages to the pixels PX, for example. In an embodiment, the driver may include a gate driver GDV, a light-emitting driver EDV, a data driver DDV, and a controller CON, for example.

[0051] Each of the pixels PX may be electrically connected to the gate driver GDV, the light-emitting driver EDV, and the data driver DDV. Each of the pixels PX may be electrically connected to the gate driver GDV through a gate line GL, may be electrically connected to the light-emitting driver EDV through a light-emitting line EML, and may be electrically connected to the data driver DDV through a data line DL. Accordingly, each of the pixels PX may receive a gate signal GS, a light-emitting signal EM, and a data voltage DATA.

[0052] The gate driver GDV may receive a gate control signal GCTRL from the controller CON. The gate driver GDV may generate the gate signal GS based on the gate control signal GCTRL. The gate signal GS may be supplied to each of the pixels PX through the gate line GL.

[0053] The light-emitting driver EDV may receive a light-emitting control signal ECTRL from the controller CON. The light-emitting driver EDV may generate the light-emitting signal EM based on the light-emitting control signal ECTRL. The light-emitting signal EM may be supplied to each of the pixels PX through the light-emitting line EML.

[0054] The data driver DDV may receive a data control signal DCTRL and output image data ODAT from the controller CON. The data driver DDV may generate the data voltage DATA based on the data control signal DCTRL and the output image data ODAT. The data voltage DATA may be supplied to each of the pixels PX through the data line DL.

[0055] The controller CON may receive a control signal CTRL and input image data IDAT from an external device (e.g., a processor 12 of FIG. 13). The controller CON may generate the gate control signal GCTRL, the light-emitting control signal ECTRL, the data control signal DCTRL, and the output image data ODAT based on the control signal CTRL and the input image data IDAT. The controller CON may control the gate driver GDV, the light-emitting driver EDV, and the data driver DDV.

[0056] Although FIG. 1 illustrates that the gate driver GDV is disposed on a first side of the display device DD, and the light-emitting driver EDV is disposed on a second side of the display device DD, the disclosure is not limited thereto. In an embodiment, the gate driver GDV and the light-emitting driver EDV may be disposed together on the first side or the second side of the display device DD, for example. In another embodiment, the gate driver GDV and the light-emitting driver EDV may be integrally formed (or unitary).

[0057] FIG. 3 is a circuit diagram illustrating an embodiment of a pixel included in the display device of FIG. 1.

[0058] Referring to FIG. 3, each of the pixels PX may include a pixel circuit PC and a light-emitting element LE. The pixel circuit PC may include at least one thin film transistor and at least one capacitor. In an embodiment, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, and a second capacitor C2.

[0059] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode to which a first power supply voltage ELVDD is applied, and a second electrode connected to a second node N2. The first transistor T1 may generate a driving current applied to the light-emitting element LE according to a voltage of the gate electrode of the first transistor T1 (i.e., the first node N1). In an embodiment, the first transistor T1 may be also referred to as a driving transistor, for example.

[0060] The second transistor T2 may include a gate electrode to which a compensation gate signal GC is applied, a first electrode connected to a third node N3, and a second electrode connected to the second node N2. In an embodiment, the second transistor T2 may be also referred to as a compensation transistor, for example.

[0061] The third transistor T3 may include a gate electrode to which a write gate signal GW is applied, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. In an embodiment, the third transistor T3 may be also referred to as a write transistor, for example.

[0062] The first capacitor C1 may include a first electrode to which an initialization voltage VINT is applied and a second electrode connected to the first node N1. In an embodiment, the first capacitor C1 may be also referred to as a storage capacitor, for example.

[0063] The second capacitor C2 may include a first electrode connected to the third node N3 and a second electrode to which a data voltage DATA is applied. In an embodiment, the second capacitor C2 may be also referred to as a programming capacitor, for example.

[0064] The light-emitting element LE may include a first electrode connected to the second node N2 and a second electrode to which a second power supply voltage ELVSS is applied. In an embodiment, the second power supply voltage ELVSS may be a voltage having a lower level than the first power supply voltage ELVDD, for example. The light-emitting element LE may emit light based on the driving current generated by the first transistor T1.

[0065] Although FIG. 3 illustrates that each of the pixels PX includes three transistors, two capacitors, and one light-emitting element, this is merely illustrative and the disclosure is not limited thereto. In an embodiment, each of the pixels PX may include one or more transistors, one or more capacitors, and one or more light-emitting elements, for example.

[0066] In addition, although FIG. 3 illustrates that each of the first, second, and third transistors T1, T2, and T3 is a p-type transistor (e.g., a p-channel metal-oxide-semiconductor (“PMOS”) transistor), this is merely illustrative and the disclosure is not limited thereto. In an embodiment, at least one of the first, second, and third transistors T1, T2, and T3 may be an n-type transistor (e.g., an n-channel metal-oxide-semiconductor (“NMOS”) transistor), for example.

[0067] FIG. 4 is a cross-sectional view illustrating an embodiment of a display panel included in the display device of FIG. 1.

[0068] Referring to FIG. 4, the display panel PN may include a substrate SUB, at least one semiconductor layer, a plurality of conductive layers, a plurality of insulating layers, and the light-emitting element LE.

[0069] The display panel PN may include a first active pattern AP1, a second active pattern AP2, a first insulating layer IL1, a first gate electrode GE1 (or a first capacitor electrode CPE1), a second gate electrode GE2, a first connection electrode CNE1, a second insulating layer IL2, a second capacitor electrode CPE2, a second connection electrode CNE2, a third connection electrode CNE3, a third insulating layer IL3, a third capacitor electrode CPE3, a fourth connection electrode CNE4, a fourth insulating layer IL4, a fourth capacitor electrode CPE4, a fifth insulating layer IL5, a fifth capacitor electrode CPE5, a fifth connection electrode CNE5, a sixth insulating layer IL6, a first electrode E1, a pixel defining layer PDL, a light-emitting layer EL, and a second electrode E2.

[0070] The substrate SUB may include a transparent or opaque material. The substrate SUB may include glass, quartz, plastic, or the like. These may be used alone or in combination.

[0071] The first active pattern AP1 and the second active pattern AP2 may be disposed on the substrate SUB. The first and second active patterns AP1 and AP2 may include a silicon semiconductor material or an oxide semiconductor material. In embodiments, the silicon semiconductor material may include amorphous silicon, polycrystalline silicon, or the like. In embodiments, the oxide semiconductor material may include indium gallium zinc oxide (“IGZO”), indium tin zinc oxide (“ITZO”), or the like. These may be used alone or in combination.

[0072] The first active pattern AP1 may include a first source area S1, a first drain area D1, and a first channel area CH1 between the first source area S1 and the first drain area D1. The first active pattern AP1 may exhibit different electrical properties depending on whether it is doped. In an embodiment, the first source area S1 and the first drain area D1 may be areas doped with a p-type impurity or an n-type impurity, for example. In an embodiment, the first source area S1 may be the first electrode of the first transistor T1, the first drain area D1 may be the second electrode of the first transistor T1, and the first channel area CH1 may be a channel of the first transistor T1, for example.

[0073] The second active pattern AP2 may include a second source area S2, a second drain area D2, and a second channel area CH2 between the second source area S2 and the second drain area D2. The second active pattern AP2 may exhibit different electrical properties depending on whether it is doped. In an embodiment, the second source area S2 and the second drain area D2 may be areas doped with a p-type impurity or an n-type impurity, for example. In an embodiment, the second source area S2 may be the first electrode of the second transistor T2, the second drain area D2 may be the second electrode of the second transistor T2, and the second channel area CH2 may be a channel of the second transistor T2, for example.

[0074] The first insulating layer IL1 may be disposed on the first and second active patterns AP1 and AP2, and may cover the first and second active patterns AP1 and AP2. The first insulating layer IL1 may include an inorganic insulating material such as silicon oxide (SiO_x), silicon nitride (SiN_x), silicon oxynitride (SiO_xN_y), or the like. The first insulating layer IL1 may have a single-layer structure or a multilayer structure including a plurality of insulating layers.

[0075] The first gate electrode GE1, the second gate electrode GE2, and the first connection electrode CNE1 may be disposed on the first insulating layer IL1. The first gate electrode GE1 may be also referred to as the first capacitor electrode CPE1. The first and second gate electrodes GE1 and GE2 and the first connection electrode CNE1 may include a conductive material such as metal, alloy, conductive metal oxide, conductive metal nitride, transparent conductive material, or the like. Each of the first and second gate electrodes GE1 and GE2 and the first connection electrode CNE1 may have a single-layer structure or a multilayer structure including a plurality of conductive layers.

[0076] The first gate electrode GE1 may at least partially overlap the first active pattern AP1 in a plan view. At least a portion of the first gate electrode GE1 may overlap the first channel area CH1 of the first active pattern AP1 in a plan view. The portion of the first gate electrode GE1 overlapping the first channel area CH1 in a plan view may be the gate electrode of the first transistor T1.

[0077] The second gate electrode GE2 may at least partially overlap the second active pattern AP2 in a plan view. At least a portion of the second gate electrode GE2 may overlap the second channel area CH2 of the second active pattern AP2 in a plan view. The portion of the second gate electrode GE2 overlapping the second channel area CH2 in a plan view may be the gate electrode of the second transistor T2.

[0078] The second insulating layer IL2 may be disposed on the first and second gate electrodes GE1 and GE2 and the first connection electrode CNE1, and may cover the first and second gate electrodes GE1 and GE2 and the first connection electrode CNE1. The second insulating layer IL2 may include an inorganic insulating material. The second insulating layer IL2 may have a single-layer structure or a multilayer structure including a plurality of insulating layers.

[0079] The second capacitor electrode CPE2, the second connection electrode CNE2, and the third connection electrode CNE3 may be disposed on the second insulating layer IL2. The second capacitor electrode CPE2 and the second and third connection electrodes CNE2 and CNE3 may include a conductive material. Each of the second capacitor electrode CPE2 and the second and third connection electrodes CNE2 and CNE3 may have a single-layer structure or a multilayer structure including a plurality of conductive layers.

[0080] The second capacitor electrode CPE2 may at least partially overlap the first capacitor electrode CPE1 in a plan view. At least a portion of the second capacitor electrode CPE2 may overlap the first capacitor electrode CPE1 in a plan view. In an embodiment, the first capacitor electrode CPE1 and the portion of the second capacitor electrode CPE2 overlapping the first capacitor electrode CPE1 in a plan view may define the first capacitor C1. In an embodiment, the first capacitor electrode CPE1 may be the second electrode of the first capacitor C1, and the second capacitor electrode CPE2 may be the first electrode of the first capacitor C1, for example. In an embodiment, the initialization voltage VINT of FIG. 3 may be applied to the second capacitor electrode CPE2, for example.

[0081] The second connection electrode CNE2 may be connected to the second source area S2 of the second active pattern AP2 through a contact hole penetrating a lower insulating layer (e.g., the first and second insulating layers IL1 and IL2). In addition, the second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole penetrating a lower insulating layer (e.g., the second insulating layer IL2).

[0082] The third insulating layer IL3 may be disposed on the second capacitor electrode CPE2 and the second and third connection electrodes CNE2 and CNE3, and may cover the second capacitor electrode CPE2 and the second and third connection electrodes CNE2 and CNE3. The third insulating layer IL3 may include an inorganic insulating material. The third insulating layer IL3 may have a single-layer structure or a multilayer structure including a plurality of insulating layers.

[0083] The third capacitor electrode CPE3 and the fourth connection electrode CNE4 may be disposed on the third insulating layer IL3. The third capacitor electrode CPE3 and the fourth connection electrode CNE4 may include a conductive material. Each of the third capacitor electrode CPE3 and the fourth connection electrode CNE4 may have a single-layer structure or a multilayer structure including a plurality of conductive layers.

[0084] The fourth connection electrode CNE4 may be connected to the third connection electrode CNE3 through a contact hole penetrating a lower insulating layer (e.g., the third insulating layer IL3).

[0085] The fourth insulating layer IL4 may be disposed on the third capacitor electrode CPE3 and the fourth connection electrode CNE4, and may cover the third capacitor electrode CPE3 and the fourth connection electrode CNE4. The fourth insulating layer IL4 may include an inorganic insulating material. The fourth insulating layer IL4 may have a single-layer structure or a multilayer structure including a plurality of insulating layers.

[0086] The fourth capacitor electrode CPE4 may be disposed on the fourth insulating layer IL4. The fourth capacitor electrode CPE4 may include a conductive material. The fourth capacitor electrode CPE4 may have a single-layer structure or a multilayer structure including a plurality of conductive layers.

[0087] The fourth capacitor electrode CPE4 may at least partially overlap the third capacitor electrode CPE3 in a plan view. At least a portion of the fourth capacitor electrode CPE4 may overlap the third capacitor electrode CPE3 in a plan view. In an embodiment, the third capacitor electrode CPE3 and the portion of the fourth capacitor electrode CPE4 overlapping the third capacitor electrode CPE3 in a plan view may define a first sub-capacitor C2_1. In an embodiment, the third capacitor electrode CPE3 may be a first electrode of the first sub-capacitor C2_1, and the fourth capacitor electrode CPE4 may be a second electrode of the first sub-capacitor C2_1, for example. In an embodiment, the first sub-capacitor C2_1 may be a portion of the second capacitor C2.

[0088] The fifth insulating layer IL5 may be disposed on the fourth capacitor electrode CPE4, and may cover the fourth capacitor electrode CPE4. The fifth insulating layer IL5 may include an inorganic insulating material. The fifth insulating layer IL5 may have a single-layer structure or a multilayer structure including a plurality of insulating layers.

[0089] The fifth capacitor electrode CPE5 and the fifth connection electrode CNE5 may be disposed on the fifth insulating layer IL5. The fifth capacitor electrode CPE5 and the fifth connection electrode CNE5 may include a conductive material. Each of the fifth capacitor electrode CPE5 and the fifth connection electrode CNE5 may have a single-layer structure or a multilayer structure including a plurality of conductive layers.

[0090] The fifth capacitor electrode CPE5 may at least partially overlap the fourth capacitor electrode CPE4 in a plan view. At least a portion of the fifth capacitor electrode CPE5 may overlap the fourth capacitor electrode CPE4 in a plan view. In an embodiment, the fourth capacitor electrode CPE4 and the portion of the fifth capacitor electrode CPE5 overlapping the fourth capacitor electrode CPE4 in a plan view may define a second sub-capacitor C2_2. In an embodiment, the fourth capacitor electrode CPE4 may be a first electrode of the second sub-capacitor C2_2, and the fifth capacitor electrode CPE5 may be a second electrode of the second sub-capacitor C2_2, for example. In an embodiment, the second sub-capacitor C2_2 may be a portion of the second capacitor C2.

[0091] In an embodiment, the second sub-capacitor C2_2 may at least partially overlap the first sub-capacitor C2_1 in a plan view. In an embodiment, the first sub-capacitor C2_1 and the second sub-capacitor C2_2 may be arranged in the third direction DR3, for example.

[0092] In an embodiment, the second capacitor C2 may include the first sub-capacitor C2_1 and the second sub-capacitor C2_2. The second capacitor C2 may have a multi-capacitor structure (e.g., a dual-capacitor structure), and the first and second sub-capacitors C2_1 and C2_2 may function as a single capacitor. The first and second sub-capacitors C2_1 and C2_2 may be defined in different layers, and may overlap each other in a plan view. Accordingly, a capacitance of the second capacitor C2 may be secured even within a limited area.

[0093] The fifth connection electrode CNE5 may be connected to the second drain area D2 of the second active pattern AP2 through a contact hole penetrating a lower insulating layer (e.g., the first, second, third, fourth, and fifth insulating layers IL1, IL2, IL3, IL4, and IL5). In addition, the fifth connection electrode CNE5 may be connected to the third connection electrode CNE3 through a contact hole penetrating a lower insulating layer (e.g., the third, fourth, and fifth insulating layers IL3, IL4, and IL5).

[0094] The sixth insulating layer IL6 may be disposed on the fifth capacitor electrode CPE5 and the fifth connection electrode CNE5, and may cover the fifth capacitor electrode CPE5 and the fifth connection electrode CNE5. The sixth insulating layer IL6 may include an organic insulating material such as phenol resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin, epoxy resin, or the like. The sixth insulating layer IL6 may have a single-layer structure or a multilayer structure including a plurality of insulating layers.

[0095] The first electrode E1 may be disposed on the sixth insulating layer IL6. The first electrode E1 may include a conductive material. In an embodiment, the first electrode E1 may be the first electrode (e.g., an anode) of the light-emitting element LE, for example.

[0096] The first electrode E1 may be connected to the fifth connection electrode CNE5 through a contact hole penetrating a lower insulating layer (e.g., the sixth insulating layer IL6). The first electrode E1 may be connected to the second drain area D2 of the second active pattern AP2 (i.e., the second electrode of the second transistor T2) through the fifth connection electrode CNE5. Accordingly, the light-emitting element LE and the pixel circuit PC of FIG. 3 may be electrically connected.

[0097] The pixel defining layer PDL may be disposed on the sixth insulating layer IL6 and the first electrode E1. The pixel defining layer PDL may cover an edge portion of the first electrode E1, and may define an opening exposing at least a portion of an upper surface of the first electrode E1. The pixel defining layer PDL may include an inorganic insulating material and/or an organic insulating material.

[0098] The light-emitting layer EL may be disposed on the first electrode E1. The light-emitting layer EL may be disposed on the first electrode E1 exposed by the opening of the pixel defining layer PDL. The light-emitting layer EL may include a light-emitting material that emits light of a selected color.

[0099] The second electrode E2 may be disposed on the light-emitting layer EL and the pixel defining layer PDL. The second electrode E2 may include a conductive material. In an embodiment, the second electrode E2 may be the second electrode (e.g., a cathode) of the light-emitting element LE, for example.

[0100] FIG. 5 is an enlarged cross-sectional view of area A in FIG. 4. FIG. 5 may be an enlarged view illustrating the first capacitor electrode CPE1 and the second capacitor electrode CPE2 defining the first capacitor C1.

[0101] Referring to FIG. 5, the second capacitor electrode CPE2 may be disposed on the first capacitor electrode CPE1, and the second insulating layer IL2 may be disposed between the first capacitor electrode CPE1 and the second capacitor electrode CPE2 in a cross-sectional view.

[0102] The first capacitor electrode CPE1 may have a multilayer structure in which a plurality of layers are stacked. The first capacitor electrode CPE1 may include a first conductive layer ML1 and a plasma-treated layer PTL.

[0103] The first conductive layer ML1 may include a first sub-conductive layer SML1, a second sub-conductive layer SML2, and a third sub-conductive layer SML3. The second sub-conductive layer SML2 may be disposed on an upper surface of the first sub-conductive layer SML1, and the third sub-conductive layer SML3 may be disposed on an upper surface of the second sub-conductive layer SML2.

[0104] The first conductive layer ML1 may include a conductive material. In an embodiment, the second sub-conductive layer SML2 may include a material (e.g., a conductive material) different from each of the first sub-conductive layer SML1 and the third sub-conductive layer SML3. In an embodiment, each of the first sub-conductive layer SML1 and the third sub-conductive layer SML3 may include titanium (Ti), and the second sub-conductive layer SML2 may include aluminum (Al), for example. However, the disclosure is not limited thereto, and the first, second, and third sub-conductive layers SML1, SML2, and SML3 may include the same material, or at least one of the first, second, and third sub-conductive layers SML1, SML2, and SML3 may include a different material, for example.

[0105] The plasma-treated layer PTL may be disposed on the first conductive layer ML1. In an embodiment, the first, second, and third sub-conductive layers SML1, SML2, and SML3 and the plasma-treated layer PTL may be sequentially disposed along the third direction DR3 on the first insulating layer IL1, for example. The plasma-treated layer PTL may be disposed on an upper surface of the third sub-conductive layer SML3. In an embodiment, the plasma-treated layer PTL may substantially cover the entirety of the upper surface of the third sub-conductive layer SML3.

[0106] The plasma-treated layer PTL may include an inorganic insulating material. The plasma-treated layer PTL may be an insulating layer. The plasma-treated layer PTL may include a high-k material. In an embodiment, the high-k material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO_x) or silicon nitride (SiN_x), for example. A dielectric constant (or permittivity) of the plasma-treated layer PTL may be greater than a dielectric constant (or permittivity) of the second insulating layer IL2.

[0107] In an embodiment, the plasma-treated layer PTL may include titanium oxide (TiO_x). In an embodiment, the plasma-treated layer PTL may include titanium dioxide (TiO₂), titanium(III) oxide (Ti₂O₃), or the like, for example. In an embodiment, the dielectric constant of the plasma-treated layer PTL may be about 10 to about 100, for example, but the disclosure is not limited thereto.

[0108] The plasma-treated layer PTL may be formed by plasma-treating an upper surface of the first conductive layer ML1 (i.e., the upper surface of the third sub-conductive layer SML3). In an embodiment, the upper surface of the third sub-conductive layer SML3 may be treated with oxygen plasma, and the plasma-treated layer PTL may be formed by oxidizing the upper surface of the third sub-conductive layer SML3. That is, the plasma-treated layer PTL may be different from an oxide film (i.e., a naturally oxidized film) that may be formed by naturally oxidizing the upper surface of the first conductive layer ML1.

[0109] A thickness TH of the plasma-treated layer PTL may be greater than a thickness of the oxide film that may be formed by naturally oxidizing the upper surface of the first conductive layer ML1. Here, the thickness TH of the plasma-treated layer PTL may refer to a length in a thickness direction (e.g., the third direction DR3) of the plasma-treated layer PTL. In an embodiment, a minimum value of the thickness TH of the plasma-treated layer PTL may be a thickness of an oxide film that may be formed by naturally oxidizing the upper surface of the third sub-conductive layer SML3, and a maximum value of the thickness TH of the plasma-treated layer PTL may be a thickness of the third sub-conductive layer SML3 before the plasma-treated layer PTL is formed. In an embodiment, the thickness TH of the plasma-treated layer PTL may be about 50 angstroms (Å) to about 700 Å, for example. However, the disclosure is not limited thereto, and the thickness TH of the plasma-treated layer PTL may vary depending on conditions (e.g., exposure time, power, or the like) of a plasma treatment process to form the plasma-treated layer PTL, a capacitance of the first capacitor C1, a thickness of the first capacitor electrode CPE1, or the like.

[0110] The second insulating layer IL2 may cover the first capacitor electrode CPE1, and the second capacitor electrode CPE2 may be disposed on the second insulating layer IL2. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may at least partially overlap each other in a plan view. In an embodiment, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be disposed along the third direction DR3, for example.

[0111] The second capacitor electrode CPE2 may have a multilayer structure in which a plurality of layers are stacked. The second capacitor electrode CPE2 may include a second conductive layer ML2.

[0112] The second conductive layer ML2 may include a fourth sub-conductive layer SML4, a fifth sub-conductive layer SML5, and a sixth sub-conductive layer SML6. The fifth sub-conductive layer SML5 may be disposed on an upper surface of the fourth sub-conductive layer SML4, and the sixth sub-conductive layer SML6 may be disposed on an upper surface of the fifth sub-conductive layer SML5. In an embodiment, the fourth, fifth, and sixth sub-conductive layers SML4, SML5, and SML6 may be sequentially disposed along the third direction DR3 on the second insulating layer IL2, for example.

[0113] The second conductive layer ML2 may include a conductive material. In an embodiment, the fifth sub-conductive layer SML5 may include a material (e.g., a conductive material) different from each of the fourth sub-conductive layer SML4 and the sixth sub-conductive layer SML6. In an embodiment, each of the fourth sub-conductive layer SML4 and the sixth sub-conductive layer SML6 may include titanium (Ti), and the fifth sub-conductive layer SML5 may include aluminum (Al). However, the disclosure is not limited thereto, and the fourth, fifth, and sixth sub-conductive layers SML4, SML5, and SML6 may include the same material, or at least one of the fourth, fifth, and sixth sub-conductive layers SML4, SML5, and SML6 may include a different material.

[0114] The first capacitor electrode CPE1 and the second capacitor electrode CPE2 overlapping each other in a plan view may define the first capacitor C1. Since the first capacitor electrode CPE1 includes the plasma-treated layer PTL having a high dielectric constant, a dielectric constant of a dielectric layer between the two electrodes may increase, so that the first capacitor C1 with increased capacitance may be defined. Accordingly, the capacitance of the first capacitor C1 may be secured even within a limited area. The capacitance of the first capacitor C1 may be further increased without increasing an area in which the first and second capacitor electrodes CPE1 and CPE2 overlap in a plan view, or without reducing a thickness of the dielectric layer between the two electrodes (e.g., a thickness of the second insulating layer IL2 between the first and second capacitor electrodes CPE1 and CPE2).

[0115] Although FIG. 5 illustrates that the first capacitor C1 includes the plasma-treated layer PTL, the disclosure is not limited thereto, and the plasma-treated layer PTL may be applied to various electrodes defining a capacitor requiring secured capacitance. In an embodiment, the third capacitor electrode CPE3 or the fourth capacitor electrode CPE4 of FIG. 4 may include the plasma-treated layer PTL, for example.

[0116] The display device DD in an embodiment of the disclosure may include the first capacitor C1 defined by the first capacitor electrode CPE1 including the plasma-treated layer PTL and the second capacitor electrode CPE2. As the plasma-treated layer PTL includes a high dielectric constant (or high-k) material, the capacitance of the first capacitor C1 may be secured. Accordingly, the display device DD including the first capacitor C1 with improved capacitance characteristics may be implemented.

[0117] FIGS. 6, 7, and 8 are cross-sectional views illustrating an embodiment of a method of manufacturing a display device according to the disclosure.

[0118] The method of manufacturing the display device described with reference to FIGS. 6, 7, and 8 may be a method of manufacturing the display device DD described with reference to FIGS. 1, 2, 3, 4, and 5. The cross-sectional views of FIGS. 6, 7, and 8 may correspond to the cross-sectional view of FIG. 5. Hereinafter, redundant descriptions will be omitted or simplified.

[0119] Referring to FIG. 6, a preliminary first conductive layer P_ML1 may be formed on the first insulating layer IL1.

[0120] The preliminary first conductive layer P_ML1 may have a multilayer structure in which a plurality of layers are stacked. The preliminary first conductive layer P_ML1 may include a preliminary first sub-conductive layer P_SML1, a preliminary second sub-conductive layer P_SML2, and a preliminary third sub-conductive layer P_SML3. The preliminary second sub-conductive layer P_SML2 may be formed on an upper surface of the preliminary first sub-conductive layer P_SML1, and the preliminary third sub-conductive layer P_SML3 may be formed on an upper surface of the preliminary second sub-conductive layer P_SML2. In an embodiment, the preliminary first sub-conductive layer P_SML1, the preliminary second sub-conductive layer P_SML2, and the preliminary third sub-conductive layer P_SML3 may be sequentially disposed on the first insulating layer IL1 along the third direction DR3, for example. In an embodiment, the preliminary first sub-conductive layer P_SML1, the preliminary second sub-conductive layer P_SML2, and the preliminary third sub-conductive layer P_SML3 may be formed through a sputtering process, for example.

[0121] The preliminary first conductive layer P_ML1 may include a conductive material. In an embodiment, the preliminary second sub-conductive layer P_SML2 may include a material (e.g., a conductive material) different from each of the preliminary first sub-conductive layer P_SML1 and the preliminary third sub-conductive layer P_SML3. In an embodiment, each of the preliminary first sub-conductive layer P_SML1 and the preliminary third sub-conductive layer P_SML3 may include titanium, and the preliminary second sub-conductive layer P_SML2 may include aluminum.

[0122] Referring further to FIG. 7, an upper surface of the preliminary first conductive layer P_ML1 may be plasma-treated. An upper surface of the preliminary third sub-conductive layer P_SML3 may be plasma-treated, and a preliminary plasma-treated layer P_PTL may be formed on the upper surface of the preliminary third sub-conductive layer P_SML3.

[0123] In an embodiment, the preliminary first conductive layer P_ML1 (i.e., the preliminary third sub-conductive layer P_SML3) may be plasma-treated through an oxygen (O₂) plasma process. In an embodiment, a display device formed up to the preliminary first conductive layer P_ML1 may be provided inside a vacuum chamber, and oxygen plasma may be injected into the vacuum chamber through a plasma generator to plasma-treat the upper surface of the preliminary third sub-conductive layer P_SML3, for example. The upper surface of the preliminary third sub-conductive layer P_SML3 may be oxidized through the oxygen plasma process to form the preliminary plasma-treated layer P_PTL.

[0124] The preliminary plasma-treated layer P_PTL may be an insulating layer, and may include a high dielectric constant (or high-k) material. In an embodiment, the preliminary third sub-conductive layer P_SML3 may include titanium, and the preliminary plasma-treated layer P_PTL may include titanium oxide. In an embodiment, the preliminary plasma-treated layer P_PTL may include titanium dioxide, titanium (III) oxide, or the like, for example.

[0125] The preliminary plasma-treated layer P_PTL may be formed with the thickness TH. The thickness TH may be a length in a thickness direction (i.e., in the third direction DR3) of the preliminary plasma-treated layer P_PTL. A minimum value of the thickness TH of the preliminary plasma-treated layer P_PTL may be a thickness of an oxide film that may be formed by naturally oxidizing the upper surface of the preliminary third sub-conductive layer P_SML3 in which the preliminary plasma-treated layer P_PTL is not formed (e.g., the preliminary third sub-conductive layer P_SML3 of FIG. 6), and a maximum value of the thickness TH of the preliminary plasma-treated layer P_PTL may be a thickness of the preliminary third sub-conductive layer P_SML3 before the preliminary plasma-treated layer P_PTL is formed (e.g., the preliminary third sub-conductive layer P_SML3 of FIG. 6). The thickness TH of the preliminary plasma-treated layer P_PTL may be adjusted by controlling conditions of the plasma treatment process (e.g., an exposure time of the upper surface of the preliminary first conductive layer P_ML1, power of the plasma, or the like).

[0126] Referring further to FIG. 8, the preliminary first conductive layer P_ML1 and the preliminary plasma-treated layer P_PTL may be patterned to form the first conductive layer ML1 and the plasma-treated layer PTL. Accordingly, the first capacitor electrode CPE1 including the first, second, and third sub-conductive layers SML1, SML2, and SML3 and the plasma-treated layer PTL may be formed on the first insulating layer IL1.

[0127] Referring back to FIG. 5, the second insulating layer IL2 may be formed on the first capacitor electrode CPE1. The second insulating layer IL2 may cover the first capacitor electrode CPE1.

[0128] The second capacitor electrode CPE2 may be formed on the second insulating layer IL2. The second capacitor electrode CPE2 may be formed to overlap at least a portion of the first capacitor electrode CPE1 in a plan view. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 overlapping in a plan view may define the first capacitor C1. Accordingly, the display device DD illustrated in FIG. 5 may be manufactured.

[0129] FIG. 9 is a cross-sectional view illustrating an embodiment of a display device according to the disclosure.

[0130] A display device DD’ described with reference to FIG. 9 may be substantially the same as or similar to the display device DD described with reference to FIGS. 1, 2, 3, 4, and 5, except for a first capacitor electrode CPE1’. The cross-sectional view of FIG. 9 may correspond to the cross-sectional view of FIG. 5. That is, FIG. 9 may be an enlarged view of the first capacitor electrode CPE1’ and a second capacitor electrode CPE2 defining a first capacitor C1. Hereinafter, redundant descriptions will be omitted or simplified.

[0131] Referring to FIG. 9, the display device DD’ may include a first insulating layer IL1, the first capacitor electrode CPE1’, a second insulating layer IL2, the second capacitor electrode CPE2, and a third insulating layer IL3.

[0132] The first capacitor electrode CPE1’ may be disposed on the first insulating layer IL1. The first capacitor electrode CPE1’ may include a first conductive layer ML1 and a plasma-treated layer PTL’. The first conductive layer ML1 may include a first sub-conductive layer SML1, a second sub-conductive layer SML2 disposed on the first sub-conductive layer SML1, and a third sub-conductive layer SML3 disposed on the second sub-conductive layer SML2.

[0133] The first conductive layer ML1 may include a conductive material. In an embodiment, each of the first sub-conductive layer SML1 and the third sub-conductive layer SML3 may include titanium, and the second sub-conductive layer SML2 may include aluminum.

[0134] The plasma-treated layer PTL’ may be disposed on the first conductive layer ML1. The plasma-treated layer PTL’ may be disposed on a side surface of the first sub-conductive layer SML1, a side surface of the second sub-conductive layer SML2, and a side surface and an upper surface of the third sub-conductive layer SML3. The plasma-treated layer PTL’ may substantially cover a side surface and an upper surface of the first conductive layer ML1.

[0135] The plasma-treated layer PTL’ may include a first sub-plasma-treated layer SPL1, a second sub-plasma-treated layer SPL2, and a third sub-plasma-treated layer SPL3. The first sub-plasma-treated layer SPL1 may cover the side surface of the first sub-conductive layer SML1, the second sub-plasma-treated layer SPL2 may cover the side surface of the second sub-conductive layer SML2, and the third sub-plasma-treated layer SPL3 may cover the side surface and the upper surface of the third sub-conductive layer SML3.

[0136] The plasma-treated layer PTL’ may include an inorganic insulating material, and may be an insulating layer. The plasma-treated layer PTL’ may include a high dielectric constant (or high-k) material. A dielectric constant (or permittivity) of each of the first, second, and third sub-plasma-treated layers SPL1, SPL2, and SPL3 may be greater than a dielectric constant (or permittivity) of the second insulating layer IL2. In an embodiment, each of the first and third sub-plasma-treated layers SPL1 and SPL3 may include titanium oxide, and the second sub-plasma-treated layer SPL2 may include aluminum oxide. In an embodiment, the dielectric constant of each of the first, second, and third sub-plasma-treated layers SPL1, SPL2, and SPL3 may be about 8 to about 100, for example, but the disclosure is not limited thereto.

[0137] The plasma-treated layer PTL’ may be formed by plasma-treating the side surface and the upper surface of the first conductive layer ML1. In an embodiment, the side surface of the first sub-conductive layer SML1 may be treated with oxygen plasma, and the first sub-plasma-treated layer SPL1 may be formed by oxidizing the side surface of the first sub-conductive layer SML1. The side surface of the second sub-conductive layer SML2 may be treated with oxygen plasma, and the second sub-plasma-treated layer SPL2 may be formed by oxidizing the side surface of the second sub-conductive layer SML2. The side surface and the upper surface of the third sub-conductive layer SML3 may be treated with oxygen plasma, and the third sub-plasma-treated layer SPL3 may be formed by oxidizing the side surface and the upper surface of the third sub-conductive layer SML3. That is, the plasma-treated layer PTL’ may be different from an oxide film that may be formed by naturally oxidizing the side surface and the upper surface of the first conductive layer ML1.

[0138] A first thickness TH1 of the plasma-treated layer PTL’ may be greater than a thickness of an oxide film that may be formed by naturally oxidizing the upper surface of the first conductive layer ML1, and a second thickness TH2 of the plasma-treated layer PTL’ may be greater than a thickness of an oxide film that may be formed by naturally oxidizing the side surface of the first conductive layer ML1. Here, the first thickness TH1 of the plasma-treated layer PTL’ may be a length in a thickness direction of the plasma-treated layer PTL’ formed on the upper surface of the first conductive layer ML1, and the second thickness TH2 of the plasma-treated layer PTL’ may be a length in a width direction, e.g., in a direction (e.g., a horizontal direction in FIG. 9) parallel to a main plane extension direction of the substrate SUB (refer to FIG. 4), of the plasma-treated layer PTL’ formed on the side surface of the first conductive layer ML1. In an embodiment, the first thickness TH1 of the plasma-treated layer PTL’ may be about 50 Å to about 700 Å, and the second thickness TH2 of the plasma-treated layer PTL’ may be greater than or equal to about 50 Å, for example, but the disclosure is not limited thereto.

[0139] The second insulating layer IL2 may be disposed on the first capacitor electrode CPE1, and may cover the first capacitor electrode CPE1.

[0140] The second capacitor electrode CPE2 may be disposed on the second insulating layer IL2, and may at least partially overlap the first capacitor electrode CPE1 in a plan view. The second capacitor electrode CPE2 may include a second conductive layer ML2. The second conductive layer ML2 may include a fourth sub-conductive layer SML4, a fifth sub-conductive layer SML5 disposed on the fourth sub-conductive layer SML4, and a sixth sub-conductive layer SML6 disposed on the fifth sub-conductive layer SML5.

[0141] The second conductive layer ML2 may include a conductive material. In an embodiment, each of the fourth sub-conductive layer SML4 and the sixth sub-conductive layer SML6 may include titanium, and the fifth sub-conductive layer SML5 may include aluminum.

[0142] The first capacitor electrode CPE1’ and the second capacitor electrode CPE2 overlapping each other in a plan view may define the first capacitor C1. Since the first capacitor electrode CPE1’ includes the plasma-treated layer PTL’ having a high dielectric constant, a dielectric constant of a dielectric layer between the two electrodes may increase, so that the first capacitor C1 with increased capacitance may be defined. Accordingly, the capacitance of the first capacitor C1 may be secured even within a limited area. The capacitance of the first capacitor C1 may be further increased without increasing an area in which the first and second capacitor electrodes CPE1’ and CPE2 overlap in a plan view, or without reducing a thickness of the dielectric layer between the two electrodes (e.g., a thickness of the second insulating layer IL2 between the first and second capacitor electrodes CPE1’ and CPE2).

[0143] The third insulating layer IL3 may be disposed on the second capacitor electrode CPE2, and may cover the second capacitor electrode CPE2.

[0144] The display device DD’ in an embodiment of the disclosure may include the first capacitor C1 defined by the first capacitor electrode CPE1’ including the plasma-treated layer PTL’ and the second capacitor electrode CPE2. Since the plasma-treated layer PTL’ includes a high dielectric constant (or high-k) material, the capacitance of the first capacitor C1 may be secured. Accordingly, the display device DD’ including the first capacitor C1 with improved capacitance characteristics may be implemented.

[0145] FIGS. 10, 11, and 12 are cross-sectional views illustrating an embodiment of a method of manufacturing a display device according to the disclosure.

[0146] The method of manufacturing the display device described with reference to FIGS. 10, 11, and 12 may be a method of manufacturing the display device DD’ described with reference to FIG. 9. The cross-sectional views of FIGS. 10, 11, and 12 may correspond to the cross-sectional view of FIG. 9. Hereinafter, redundant descriptions will be omitted or simplified.

[0147] Referring to FIG. 10, a preliminary first conductive layer P_ML1 may be formed on the first insulating layer IL1.

[0148] The preliminary first conductive layer P_ML1 may include a preliminary first sub-conductive layer P_SML1, a preliminary second sub-conductive layer P_SML2 formed on the preliminary first sub-conductive layer P_SML1, and a preliminary third sub-conductive layer P_SML3 formed on the preliminary second sub-conductive layer P_SML2. In an embodiment, the preliminary first sub-conductive layer P_SML1, the preliminary second sub-conductive layer P_SML2, and the preliminary third sub-conductive layer P_SML3 may be formed through a sputtering process, for example.

[0149] The preliminary first conductive layer P_ML1 may include a conductive material. In an embodiment, each of the preliminary first sub-conductive layer P_SML1 and the preliminary third sub-conductive layer P_SML3 may include titanium, and the preliminary second sub-conductive layer P_SML2 may include aluminum.

[0150] Referring further to FIG. 11, the preliminary first conductive layer P_ML1 may be patterned. In an embodiment, the preliminary first conductive layer P_ML1 may be patterned in a shape substantially the same as or similar to the first capacitor electrode CPE1’ of FIG. 9, for example.

[0151] Referring further to FIG. 12, a side surface and an upper surface of the preliminary first conductive layer P_ML1 may be plasma-treated to form the first capacitor electrode CPE1’ including the first conductive layer ML1 and the plasma-treated layer PTL’ disposed on the first conductive layer ML1.

[0152] A side surface of the preliminary first sub-conductive layer P_SML1 may be plasma-treated, and the plasma-treated layer PTL’ may be formed on the side surface of the preliminary first sub-conductive layer P_SML1, so that the first sub-conductive layer SML1 and the first sub-plasma-treated layer SPL1 covering the side surface of the first sub-conductive layer SML1 may be formed. A side surface of the preliminary second sub-conductive layer P_SML2 may be plasma-treated, and the plasma-treated layer PTL’ may be formed on the side surface of the preliminary second sub-conductive layer P_SML2, so that the second sub-conductive layer SML2 and the second sub-plasma-treated layer SPL2 covering the side surface of the second sub-conductive layer SML2 may be formed. A side surface and an upper surface of the preliminary third sub-conductive layer P_SML3 may be plasma-treated, and the plasma-treated layer PTL’ may be formed on the side surface and the upper surface of the preliminary third sub-conductive layer P_SML3, so that the third sub-conductive layer SML3 and the third sub-plasma-treated layer SPL3 covering the side surface and the upper surface of the third sub-conductive layer SML3 may be formed.

[0153] In an embodiment, the preliminary first conductive layer P_ML1 may be plasma-treated through an oxygen plasma process. The surfaces of the preliminary first sub-conductive layer P_SML1, the preliminary second sub-conductive layer P_SML2, and the preliminary third sub-conductive layer P_SML3 may be oxidized through the oxygen plasma process to form the plasma-treated layer PTL’. The first thickness TH1 and the second thickness TH2 of the plasma-treated layer PTL’ may be adjusted by controlling conditions of the plasma treatment process (e.g., an exposure time of the surface of the preliminary first conductive layer P_ML1, power of the plasma, or the like).

[0154] Referring back to FIG. 9, the second insulating layer IL2 and the second capacitor electrode CPE2 may be sequentially formed on the first capacitor electrode CPE1’.

[0155] The second capacitor electrode CPE2 may be formed to overlap at least a portion of the first capacitor electrode CPE1’ in a plan view, and the first capacitor electrode CPE1’ and the second capacitor electrode CPE2 overlapping in a plan view may define the first capacitor C1. Accordingly, the display device DD’ illustrated in FIG. 9 may be manufactured.

[0156] The display device DD and DD’ in embodiments of the disclosure may be applied to various electronic devices. An electronic device in an embodiment of the disclosure may include the display device described above, and may further include a module or device having other additional functions in addition to the display device.

[0157] FIG. 13 is a block diagram illustrating an embodiment of an electronic device according to the disclosure.

[0158] Referring to FIG. 13, an electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0159] The processor 12 may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphic processing unit (“GPU”), a communication processor (“CP”), and an image signal processor (“ISP”). The processor 12 may provide a control signal (e.g., the control signal CTRL of FIG. 2) and input image data (e.g., the input image data IDAT of FIG. 2) to a controller (e.g., the controller CON of FIG. 2) of the display module 11.

[0160] The memory 13 may store data information desired for operation of the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, an input image data signal and/or a control signal may be transmitted to the display module 11, and the display module 11 may process the received signal and output image information through a display screen.

[0161] The power module 14 may include a power supply module, such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power desired for operation of the electronic device 10.

[0162] At least one of components of the electronic device 10 may be included in the display device in embodiments of the disclosure described above. In addition, some of individual modules functionally included in one module may be included in the display device, and other portions may be provided separately from the display device. In an embodiment, the display device may include the display module 11, and the processor 12, the memory 13, and the power module 14 may be provided in form of other devices within the electronic device 10 other than the display device, for example.

[0163] FIG. 14 is a schematic view illustrating an embodiment of electronic devices according to the disclosure.

[0164] Referring to FIG. 14, various electronic devices to which the display device in an embodiment of the disclosure is applied may include not only image display electronic devices such as a smartphone 10_1a, a tablet personal computer 10_1b, a laptop 10_1c, a television (“TV”) 10_1d, and a desktop monitor 10_1e, but also wearable electronic devices including display modules, such as smart glasses 10_2a, a head-mounted display 10_2b, and a smart watch 10_2c, automotive electronic devices 10_3 including display modules, such as a Center Information Display (“CID”) arranged on a cluster, a center fascia, and dashboard of a car, and a room mirror display, or the like.

[0165] The disclosure may be applied to various display devices and electronic devices. For example, the disclosure is applicable to various display devices such as display devices for vehicles, ships and aircraft, portable communication devices, display devices for exhibition or information transmission, medical display devices, or the like.

[0166] The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the illustrative embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.