DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE

[0001] This application is a continuation of U.S. Application No. 18/024,594 filed on March 3, 2023, which is the U.S. national phase of PCT Application No. PCT/CN2022/089268 filed on April 26, 2022, the disclosures of which are incorporated in their entirety by reference herein.

[0002] The present disclosure relates to the technical field of displays, and more particularly, relates to a display substrate, a method for manufacturing the same, and a display device.

[0003] In related art, signal lines of a display substrate are generally made of cuprum (Cu), signal lines of different layers intersect with each other, and an insulating layer is provided between the signal lines of different layers at an intersection position. However, the signal lines are prone to Cu ion diffusion and Cu ion penetrating the insulating layer may cause a short circuit between the signal lines of different layers, affecting a product yield of the display substrate.

[0004] The technical problem to be solved in the present disclosure is to provide a display substrate, a method for manufacturing the same, and a display device, which can ensure the product yield of the display substrate.

[0005] In order to solve the above technical problem, the technical solutions provided by embodiments of the present disclosure are as follows.

[0006] In one aspect, a display substrate is provided, including:

[0007] a first signal line, located on a base substrate and extending in a first direction;

[0008] a second signal line, located on the base substrate and extending in a second direction, where the second signal line is arranged in a different layer from the first signal line, the second direction intersects with the first direction,

[0009] the first signal line includes a first portion, and a first orthographic projection of the first portion on the base substrate is located within an orthographic projection of the second signal line on the base substrate;

[0010] the display substrate further includes:

[0011] an isolation pattern, located on a side of the first signal line away from the base substrate, where the isolation pattern is located on a side of the second signal line close to the base substrate, and the first orthographic projection is located in a second orthographic projection of the isolation pattern on the base substrate.

[0012] In some embodiments, the display substrate further includes:

[0013] an insulating layer, located between the first signal line and the second signal line,

[0014] where the isolation pattern is located on a side of the insulating layer close to the base substrate; or

[0015] the isolation pattern is located on a side of the insulating layer away from the base substrate.

[0016] In some embodiments, the isolation pattern is made of a semiconductor material.

[0017] In some embodiments, the isolation pattern is made of a metal oxide semiconductor.

[0018] In some embodiments, an active layer of a thin film transistor of the display substrate is arranged in the same layer and material as the isolation pattern.

[0019] In some embodiments, the first signal line includes a second portion other than the first portion, and an orthographic projection of the second portion on the base substrate does not overlap with an orthographic projection of the second signal line on the base substrate.

[0020] In some embodiments, in the second direction, a boundary of the second orthographic projection exceeds a boundary of the first orthographic projection and the minimum distance between the boundary of the first orthographic projection and the boundary of the second orthographic projection is greater than 0.2 microns.

[0021] In some embodiments, in the first direction, the boundary of the second orthographic projection exceeds the boundary of the first orthographic projection and the minimum distance between the boundary of the first orthographic projection and the boundary of the second orthographic projection is greater than 0.2 microns.

[0022] In some embodiments, the first signal line includes a plurality of the first portions which are independent from each other, each of the first portions corresponds to one isolation pattern, a first orthographic projection of the first portion on the base substrate falls within a second orthographic projection of the corresponding isolation pattern on the base substrate, and a plurality of isolation patterns corresponding to the same first signal line are integrally structured.

[0023] In some embodiments, the first signal line is a gate line and the second signal line is a data line; or

[0024] the first signal line is a first clock signal line and the second signal line is a second clock signal line.

[0025] A display device is provided by the embodiments of the present disclosure, including the above display substrate.

[0026] A method for manufacturing a display substrate is provided by the embodiments of the present disclosure, including:

[0027] forming a first signal line extending in a first direction on a base substrate;

[0028] forming a second signal line extending in a second direction on the base substrate, where the second signal line is arranged in a different layer from the first signal line, the second direction intersects with the first direction, the first signal line includes a first portion, and a first orthographic projection of the first portion on the base substrate is located within an orthographic projection of the second signal line on the base substrate; and

[0029] forming an isolation pattern on a side of the first signal line away from the base substrate, where the isolation pattern is located on a side of the second signal line close to the base substrate, and the first orthographic projection is located in a second orthographic projection of the isolation pattern on the base substrate.

[0030] In some embodiments, the method specifically includes:

[0031] forming an active layer of a thin film transistor of the display substrate and the isolation pattern by one patterning process.

[0032] Embodiments of the present disclosure have the following beneficial effects.

[0033] In the above solution, an isolation pattern is provided between the first signal line and the second signal line, and the isolation pattern can block metal ion diffusion of the first signal line and the second signal line, slow down the metal ion diffusion and chemical reaction between crossing metal signal lines due to an action of an electric field, and ensure the product yield of the display substrate.

[0048] In order to make the technical problems, technical solutions, and advantages of the embodiments of the present disclosure more apparent, technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings and specific embodiments.

[0049] A display substrate, a method for manufacturing the same, and a display device are provided in the embodiments of the present disclosure, to ensure the product yield of the display substrate.

[0050] Embodiments of the present disclosure provide a display substrate, as shown in FIG. 1, including:

[0051] a first signal line 01 located on a base substrate and extending in a first direction;

[0052] a second signal line 02 located on the base substrate and extending in a second direction, where the second signal line 02 is arranged in a different layer from the first signal line 01, the second direction intersects with the first direction,

[0053] the first signal line 01 includes a first portion (a portion in a dotted line frame), and a first orthographic projection of the first portion on the base substrate is located within a orthographic projection of the second signal line 02 on the base substrate;

[0054] the display substrate further including:

[0055] an isolation pattern 03 located on a side of the first signal line 01 away from the base substrate, where the isolation pattern is located on a side of the second signal line 02 close to the base substrate and the first orthographic projection is located in a second orthographic projection of the isolation pattern on the base substrate.

[0056] In this embodiment, an isolation pattern is provided between the first signal line and the second signal line, and the isolation pattern can block metal ion diffusion of the first signal line and the second signal line, slow down metal ion diffusion and chemical reaction between crossing metal signal lines due to an action of an electric field, and ensure the product yield of the display substrate.

[0057] Due to the good conductivity of Cu, signal lines of the display substrate are generally made of Cu, which include a first signal line and a second signal line. As shown in FIG. 2, in the related art, an insulating layer 03 is provided between a first signal line 01 and a second signal line 02 and the insulating layer 03 is generally made of silicon oxide, silicon nitride, or silicon oxynitride. Limited by a manufacturing process, thickness of the insulating layer 03 is relatively small, and metal ion diffusion occurs in the first signal line 01 and the second signal line 02, resulting in that the first signal line 01 and the second signal line 02 have a risk of a short circuit at an intersection position between the first signal line 01 and the second signal line 02. After the short circuit occurs, temperature at the intersection position of the signal lines will be increased, thus causing the insulating layer at the intersection position of the signal lines to be easily damaged, damaging sealing performance of the display substrate, water vapor easily invading, corroding the signal lines and causing chemical reactions, and water vapor also diffusing in the direction of the signal lines and reducing the product yield of the display substrate.

[0058] As shown in FIG. 3, in the present embodiment, an isolation pattern 03 is provided between the first signal line 01 and the second signal line 02, and the isolation pattern 03 has a certain thickness, which can block the metal ion diffusion of the first signal line 01 and the second signal line 02, slow down the metal ion diffusion and chemical reaction between crossing metal signal lines due to the action of an electric field, and ensure the product yield of the display substrate.

[0059] In some embodiments, the first signal line includes a second portion other than the first portion, and an orthographic projection of the second portion on the base substrate does not overlap with an orthographic projection of the second signal line on the base substrate. The orthographic projection of the first signal line at the intersection position of the signal lines on the base substrate is all located in the orthographic projection of the isolation pattern 03 on the base substrate. As shown in FIG. 1, the first orthographic projection of the first portion 011 (the portion inside the dotted line frame) on the base substrate is located in the orthographic projection of the isolation pattern 03 on the base substrate, and an area of the isolation pattern 03 is greater than an area of the first portion 011. As shown in FIG. 3, after metal ion diffusion occurs in the first signal line 01, metal ions are distributed on the isolation pattern 03. Since the area of the isolation pattern 03 is relatively large, the area of the isolation pattern 03 directly opposite the first signal line 01 is relatively large (compared with the area of the second signal line 02 directly opposite the first signal line 01), which can reduce a distribution density of metal ions and slow down the diffusion and chemical reaction of metal ions between crossing metal signal lines due to the action of an electric field. In contrast, after metal ion diffusion occurs in the second signal line 02, metal ions are distributed on the isolation pattern 03. Since the area of the isolation pattern 03 is relatively large, the area of the isolation pattern 03 directly opposite the second signal line 02 is relatively large (compared with the area of the first signal line 01 directly opposite the first signal line 01), which can reduce the distribution density of the metal ions can be reduced and slow down the diffusion and chemical reaction of the metal ions between crossing metal signal lines due to the action of the electric field.

[0060] As shown in FIG. 3, the isolation pattern 03 may be located between the insulating layer 04 and the second signal line 02; alternatively, as shown in FIG. 4, the isolation pattern 03 may be located between the insulating layer 04 and the first signal line 01 as long as the isolation pattern 03 is located between the first signal line 01 and the second signal line 02.

[0061] In order to ensure the waterproofness of the display substrate, the isolation pattern 03 may be made of a material having good waterproofness. In this embodiment, the isolation pattern 03 may be made of a semiconductor material, where the semiconductor material has a certain electron mobility. After the metal ions diffused in the signal lines reach the isolation pattern 03, the isolation pattern 03, as a semiconductor, may change electric field distribution, slow down the metal ion diffusion and chemical reaction between crossing metal signal lines due to the action of the electric field, avoid corrosion at the intersection position of the signal lines, and further avoid the diffusion of water vapor along the signal lines to ensure the yield of display products.

[0062] The isolation pattern 03 may be made of a metal oxide semiconductor, amorphous silicon, and polysilicon, and preferably, the isolation pattern 03 is made of a metal oxide semiconductor, such as indium gallium zinc oxide, (IGZO), which has a good electron mobility and can effectively reduce electric field density at the intersection position of the signal lines.

[0063] In some embodiments, an active layer of the thin film transistor of the display substrate is arranged in the same layer and material as the isolation pattern 03, so that the active layer of the thin film transistor of the display substrate and the isolation pattern 03 can be formed by one patterning process, and there is no need to prepare the isolation pattern 03 by a special patterning process, the number of patterning processes for preparing the display substrate can be reduced, and production cost of the display substrate can be reduced. The thickness of the isolation pattern 03 may be the same as a thickness of the active layer of the thin film transistor, and the thickness of the isolation pattern 03 may also be adjusted. The thickness of the isolation pattern 03 is designed to be greater than the thickness of the active layer of the thin film transistor to better reduce the electric field density at the intersection position of the signal lines, and the thickness of the isolation pattern 03 is preferably not less than 100 nm.

[0064] In order to better reduce the electric field density at the intersection position of the signal lines, as shown in FIG. 1, in the second direction, a boundary of the second orthographic projection exceeds a boundary of the first orthographic projection and the minimum distance d1 between the boundary of the first orthographic projection and the boundary of the second orthographic projection is greater than 0.2 microns. Thus, the isolation pattern 03 can spatially block the metal ion diffusion between the first signal line 01 and the second signal line 02. Also, since water vapor diffuses along the signal lines after corrosion of the signal lines, d1 greater than 0.2 microns can change the water vapor diffusion path and reduce the possibility of water vapor intrusion.

[0065] Further, d1 may be greater than a+0.2 microns, where a is a maximum fluctuation value of critical dimensions of the first signal line 01 and the isolation pattern 03 in the manufacturing process, which may reduce the influence of the manufacturing process on the product yield of the display substrate.

[0066] In order to better reduce the electric field density at the intersection position of the signal lines, as shown in FIG. 1, in the first direction, the boundary of the second orthographic projection exceeds the boundary of the first orthographic projection and the minimum distance d2 between the boundary of the first orthographic projection and the boundary of the second orthographic projection is greater than 0.2 microns. Thus, the isolation pattern 03 can spatially block the metal ion diffusion between the first signal line 01 and the second signal line 02. Also, since water vapor diffuses along the signal lines after corrosion of the signal lines, d1 greater than 0.2 microns can change the water vapor diffusion path and reduce the possibility of water vapor intrusion.

[0067] Further, d2 may be greater than b+0.2 microns, where b is the maximum fluctuation value of critical dimensions of the second signal line 02 and the isolation pattern 03 in the manufacturing process, which may reduce the influence of the manufacturing process on the product yield of the display substrate.

[0068] In this embodiment, the signal lines may be in various shapes. As shown in FIG. 1, the first signal line 01 and the second signal line 02 may be in a straight-line shape. As shown in FIG. 5, the second signal line 02 may further include a plurality of hollowed-out regions 021 at the intersection position of the signal lines, and the first signal line may also include a plurality of hollowed-out regions at the intersection position of the signal lines to reduce a direct area between the signal lines, reduce the electric field density at the intersection position of the signal lines, slow down the metal ion diffusion and chemical reaction between crossing metal signal lines due to the action of an electric field, avoid corrosion at the intersection position of the signal lines, and further avoid the diffusion of water vapor along the signal lines to ensure the yield of the display products. As shown in FIG. 6, the second signal line 02 may also be in a serpentine shape at the intersection position of the signal lines.

[0069] In the present embodiment, the first signal line is a gate line and the second signal line is a data line; or the first signal line is a first clock signal line and the second signal line is a second clock signal line. The first signal line is not limited to the gate line and the first clock signal line, the second signal line is not limited to the data line and the second clock signal line, and the first signal line and the second signal line may be other signal lines.

[0070] In the display region, the gate line intersects with the data line, an isolation pattern 03 is provided at the intersection position of the gate line and the data line, which can block the metal ion diffusion of the gate line and the data line, slow down the metal ion diffusion and chemical reaction between crossing metal signal lines due to the effect of an electric field, and ensure the product yield of the display substrate.

[0071] In the GOA region, as shown in FIG. 7, a first clock signal line 07 intersects with a second clock signal line 08, and at a position of a via 06, the first clock signal line 07 and the second clock signal line 08 are connected through the via 06. In addition to the position of the via 06, an isolation pattern 03 is provided at the intersection position of the first clock signal line 07 and the second clock signal line 08, which can block the metal ion diffusion of the first clock signal line 07 and the second clock signal line 08, slow down the metal ion diffusion and chemical reaction between the intersecting metal signal lines due to the electric field, and ensure the product yield of the display substrate.

[0072] FIG. 8 is a schematic enlarged view of a position of an oval frame in FIG. 7. At the intersection position of the first clock signal line 07 and the second clock signal line 08, the first clock signal line 07 may include a hollowed-out region which divides the first clock signal line 07 into two independent first portions (the hollowed-out region may also divide the first clock signal line 07 into more than three independent first portions), each of the first portions corresponds to one of the isolation patterns 03, and a first orthographic projection of the first portion on the base substrate falls within a second orthographic projection of the corresponding isolation pattern on the base substrate.

[0073] In order to simplify the manufacturing process, a plurality of isolation patterns corresponding to the same first signal line may be in a unitary structure, as shown in FIG. 9.

[0074] In a particular embodiment, the minimum distance d1 between the boundary of the first orthographic projection and the boundary of the second orthographic projection in the second direction may be 2.5-3.3 microns. In the first direction, the minimum distance d2 between the boundary of the first orthographic projection and the boundary of the second orthographic projection may be 4.5-5.05 microns. When the above dimensions are used, metal ion diffusion of the first clock signal line 07 and the second clock signal line 08 can be effectively blocked, metal ion diffusion and chemical reaction between crossing metal signal lines due to the action of an electric field can be slowed down, and the product yield of the display substrate can be ensured.

[0075] A display device is provided in the embodiments of the present disclosure, including the above display substrate.

[0076] The display device includes, but is not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. It can be understood by those skilled in the art that the configuration of the display device described above is not intended to be limiting and that the display device may include more or fewer of the components described above, or some combinations of the components, or different arrangements of the components. In embodiments of the present disclosure, the display device includes, but are not limited to, a display, a cell phone, a tablet, a television, a wearable electronic, or a navigation display device.

[0077] The display device may include: any product or component with a display function, such as a television, a liquid crystal display, a digital photo frame, a mobile phone, or a tablet computer, where the display device further includes a flexible circuit board, a printed circuit board, and a back panel.

[0078] A method for manufacturing a display device is provided in the embodiments of the present disclosure, including:

[0079] forming a first signal line extending in a first direction on a base substrate;

[0080] forming a second signal line extending in a second direction on the base substrate, where the second signal line is arranged in a different layer from the first signal line, the second direction intersects with the first direction, the first signal line includes a first portion, and a first orthographic projection of the first portion on the base substrate is located within a orthographic projection of the second signal line on the base substrate; and

[0081] forming an isolation pattern on a side of the first signal line away from the base substrate, where the isolation pattern is located on a side of the second signal line close to the base substrate, and the first orthographic projection is located in a second orthographic projection of the isolation pattern on the base substrate.

[0082] In this embodiment, an isolation pattern is provided between the first signal line and the second signal line, and the isolation pattern can block metal ion diffusion of the first signal line and the second signal line, slow down metal ion diffusion and chemical reaction between crossing metal signal lines due to the action of an electric field, and ensure the product yield of the display substrate.

[0083] Due to the good conductivity of Cu, signal lines of the display substrate are generally made of Cu, which include a first signal line and a second signal line. As shown in FIG. 2, in the related art, an insulating layer 03 is provided between a first signal line 01 and a second signal line 02 and the insulating layer 03 is generally made of silicon oxide, silicon nitride, or silicon oxynitride. Limited by a manufacturing process, thickness of the insulating layer 03 is relatively small, and metal ion diffusion occurs in the first signal line 01 and the second signal line 02, resulting in that the first signal line 01 and the second signal line 02 have a risk of a short circuit at an intersection position between the first signal line 01 and the second signal line 02. After the short circuit occurs, temperature at the intersection position of the signal lines will be increased, thus causing the insulating layer at the intersection position of the signal lines to be easily damaged, damaging sealing performance of the display substrate, water vapor easily invading, corroding the signal lines and causing chemical reactions, and water vapor also diffusing in the direction of the signal lines and reducing the product yield of the display substrate.

[0084] As shown in FIG. 3, in the present embodiment, an isolation pattern 03 is provided between the first signal line 01 and the second signal line 02, and the isolation pattern 03 has a certain thickness, which can block the metal ion diffusion of the first signal line 01 and the second signal line 02, slow down the metal ion diffusion and chemical reaction between crossing metal signal lines due to the action of an electric field, and ensure the product yield of the display substrate.

[0085] In some embodiments, the first signal line includes a second portion other than the first portion, and an orthographic projection of the second portion on the base substrate does not overlap with an orthographic projection of the second signal line on the base substrate. The orthographic projection of the first signal line at the intersection position of the signal lines on the base substrate is all located in the orthographic projection of the isolation pattern 03 on the base substrate. As shown in FIG. 1, the first orthographic projection of the first portion 011 (the portion inside the dotted line frame) on the base substrate is located in the orthographic projection of the isolation pattern 03 on the base substrate, and an area of the isolation pattern 03 is greater than an area of the first portion 011. As shown in FIG. 3, after metal ion diffusion occurs in the first signal line 01, metal ions are distributed on the isolation pattern 03. Since the area of the isolation pattern 03 is relatively large, the area of the isolation pattern 03 directly opposite the first signal line 01 is relatively large (compared with the area of the second signal line 02 directly opposite the first signal line 01), which can reduce a distribution density of metal ions and slow down the diffusion and chemical reaction of metal ions between crossing metal signal lines due to the action of an electric field. In contrast, after metal ion diffusion occurs in the second signal line 02, metal ions are distributed on the isolation pattern 03. Since the area of the isolation pattern 03 is relatively large, the area of the isolation pattern 03 directly opposite the second signal line 02 is relatively large (compared with the area of the first signal line 01 directly opposite the first signal line 01), which can reduce the distribution density of the metal ions can be reduced and slow down the diffusion and chemical reaction of the metal ions between crossing metal signal lines due to the action of the electric field.

[0086] As shown in FIG. 3, the isolation pattern 03 may be located between the insulating layer 04 and the second signal line 02; alternatively, as shown in FIG. 4, the isolation pattern 03 may be located between the insulating layer 04 and the first signal line 01 as long as the isolation pattern 03 is located between the first signal line 01 and the second signal line 02.

[0087] In order to ensure the waterproofness of the display substrate, the isolation pattern 03 may be made of a material having good waterproofness. In this embodiment, the isolation pattern 03 may be made of a semiconductor material, where the semiconductor material has a certain electron mobility. After the metal ions diffused in the signal lines reach the isolation pattern 03, the isolation pattern 03, as a semiconductor, may change electric field distribution, slow down the metal ion diffusion and chemical reaction between crossing metal signal lines due to the action of the electric field, avoid corrosion at the intersection position of the signal lines, and further avoid the diffusion of water vapor along the signal lines to ensure the yield of display products.

[0088] The isolation pattern 03 may be made of a metal oxide semiconductor, amorphous silicon, and polysilicon, and preferably, the isolation pattern 03 is made of a metal oxide semiconductor, such as IGZO, which has a good electron mobility and can effectively reduce electric field density at the intersection position of the signal lines.

[0089] In some embodiments, the an layer of the thin film transistor of the display substrate is arranged in the same layer and material as the isolation pattern 03, so that the active layer of the thin film transistor of the display substrate and the isolation pattern 03 can be formed by one patterning process, and there is no need to prepare the isolation pattern 03 by a special patterning process, the number of patterning processes for preparing the display substrate can be reduced, and production cost of the display substrate can be reduced. The thickness of the isolation pattern 03 may be the same as a thickness of the active layer of the thin film transistor, and the thickness of the isolation pattern 03 may also be adjusted. The thickness of the isolation pattern 03 is designed to be greater than the thickness of the active layer of the thin film transistor to better reduce the electric field density at the intersection position of the signal lines, and the thickness of the isolation pattern 03 is preferably not less than 100 nm.

[0090] In this embodiment, the signal lines may be in various shapes. As shown in FIG. 1, the first signal line 01 and the second signal line 02 may be in a straight-line shape. As shown in FIG. 5, the second signal line 02 may further include a plurality of hollowed-out regions 021 at the intersection position of the signal lines, and the first signal line may also include a plurality of hollowed-out regions at the intersection position of the signal lines to reduce a direct area between the signal lines, reduce the electric field density at the intersection position of the signal lines, slow down the metal ion diffusion and chemical reaction between crossing metal signal lines due to the action of an electric field, avoid corrosion at the intersection position of the signal lines, and further avoid the diffusion of water vapor along the signal lines to ensure the yield of the display products. As shown in FIG. 6, the second signal line 02 may also be in a serpentine shape at the intersection position of the signal lines.

[0091] In the present embodiment, the first signal line is a gate line and the second signal line is a data line; or the first signal line is a first clock signal line and the second signal line is a second clock signal line. The first signal line is not limited to the gate line and the first clock signal line, the second signal line is not limited to the data line and the second clock signal line, and the first signal line and the second signal line may be other signal lines.

[0092] In the display region, the gate line intersects with the data line, an isolation pattern 03 is provided at the intersection position of the gate line and the data line, which can block the metal ion diffusion of the gate line and the data line, slow down the metal ion diffusion and chemical reaction between crossing metal signal lines due to the effect of an electric field, and ensure the product yield of the display substrate.

[0093] In the GOA region, as shown in FIG. 7, a first clock signal line 07 intersects with a second clock signal line 08, and at a position of a via 06, the first clock signal line 07 and the second clock signal line 08 are connected through the via 06. In addition to the position of the via 06, an isolation pattern 03 is provided at the intersection position of the first clock signal line 07 and the second clock signal line 08, which can block the metal ion diffusion of the first clock signal line 07 and the second clock signal line 08, slow down the metal ion diffusion and chemical reaction between the intersecting metal signal lines due to the electric field, and ensure the product yield of the display substrate.

[0094] FIG. 8 is a schematic enlarged view of a position of an oval frame in FIG. 7. At the intersection position of the first clock signal line 07 and the second clock signal line 08, the first clock signal line 07 may include a hollowed-out region which divides the first clock signal line 07 into two independent first portions (the hollowed-out region may also divide the first clock signal line 07 into more than three independent first portions), each of the first portions corresponds to one of the isolation patterns 03, and a first orthographic projection of the first portion on the base substrate falls within a second orthographic projection of the corresponding isolation pattern on the base substrate.

[0095] In order to simplify the manufacturing process, a plurality of isolation patterns corresponding to the same first signal line may be in a unitary structure, as shown in FIG. 9.

[0096] It should be noted that the various embodiments described herein are described in a progressive manner with reference to the same or similar parts throughout the various embodiments, with each embodiment focusing on differences from the other embodiments. In particular, the embodiments are described more simply because they are approximately similar to the product embodiments, with reference to the partial description of the product embodiments.

[0097] Unless defined otherwise, technical or scientific terms used in the present disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of “first”, “second”, and the like in the present disclosure does not denote any order, quantity, or importance, but rather is used to distinguish one element from another. The terms “comprising” or “comprises”, and the like, means that the presence of an element or item preceding the word covers the presence of the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms “connected” or “connected”, and the like are not limited to physical or mechanical connections, but may comprise electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right”, and the like are used only to indicate relative positional relationships that may change accordingly when the absolute position of the object being described changes.

[0098] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “directly under” the other element or intervening elements may be present.

[0099] In the description of the embodiments above, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

[0100] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. Accordingly, the protection sought herein is as set forth in the claims below.