SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

[0001] This application is a continuation application of U.S. Application No. 18/220,839, filed on July 12th, 2023. The content of the application is incorporated herein by reference.

[0002] The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of using hard mask to protect fin-shaped structures on low-voltage (LV) region while a thermal treatment process is conducted on the medium-voltage (MV) region for forming gate dielectric layer.

[0003] In current semiconductor processing, controllers, memories, circuits of low-voltage operation and power devices of high-voltage operation are largely integrated into a single chip to achieve a single-chip system. The power device, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral diffusion MOS (LDMOS), is employed to increase power switching efficiency and decrease the loss of energy resources. It is often required that the switching transistors withstand high breakdown voltages and operate at a low on-resistance.

[0004] Moreover with the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.

[0005] However as the scale of current devices continue to decrease the integration of high-voltage devices and FinFET devices start to face numerous challenges such as current leakage and control of breakdown voltage. Hence, how to improve the current fabrication for improving performance of the device has become an important task in this field.

[0006] According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.

[0007] According to another aspect of the present invention, a semiconductor device includes a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, a first hump on the substrate of the MV region, and a gate electrode on the first hump. Preferably, the hump includes a first ring-shape under a top view perspective.

[0008] According to yet another aspect of the present invention, a semiconductor device includes a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, a first hump on one side of the substrate of the MV region, a second hump on another side of the substrate of the MV region, and a gate electrode on the first hump and the second hump.

[0009] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0014] Referring to FIGS. 1-5, FIGS. 1-5 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention, in which FIG. 1 illustrates a 3-dimensional view for fabricating the semiconductor device according to an embodiment of the present invention and FIGS. 2-5 illustrate cross-section views for fabricating the semiconductor device along the sectional lines AA’ of FIG. 1. As shown in FIGS. 1-2, a substrate 12 such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided and two or more transistor regions including a medium-voltage (MV) region 16 and a low-voltage (LV) region 18 are defined on the substrate 12, in which a MV device is disposed on an active area 62 on the MV region 16, the LV region 18 could further include a core region and/or an input/output (I/O) region, and a LV device is disposed on the LV region 18. Preferably, left portions in FIGS. 2-5 are cross-section views illustrating a method for fabricating the semiconductor device on the MV region 16 and right portions in FIGS. 2-5 are cross-section views illustrating a method for fabricating the semiconductor device on the LV region 18.

[0015] In this embodiment, the regions 16, 18 could be transistor regions having same conductive type or different conductive types. For instance, each of the two regions 16, 18 could be a PMOS region or a NMOS region and the regions 16, 18 are defined to fabricate gate structures having different threshold voltages in the later process. Preferably, it would be desirable to first conduct an implantation process to form p-type deep wells on the MV region 16 and a n-type deep well on the LV region 18 but not limited thereto.

[0016] Next, a base 22 is formed on the MV region 16 and a plurality of fin-shaped structures 24 are formed on the substrate 12 of the LV region 18. Preferably, the fin-shaped structures 24 could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained.

[0017] Alternatively, the base 22 and the fin-shaped structures 24 could also be obtained by first forming a patterned mask (not shown) on the substrate, 12, and through an etching process, the pattern of the patterned mask is transferred to the substrate 12 to form the base 22 and the fin-shaped structures 24. Moreover, the formation of the base 22 and the fin-shaped structures 24 could also be accomplished by first forming a patterned hard mask (not shown) on the substrate 12, and a semiconductor layer composed of silicon germanium is grown from the substrate 12 through exposed patterned hard mask via selective epitaxial growth process to form the corresponding the base 22 and fin-shaped structures 24. These approaches for forming the base 22 and fin-shaped structures 24 are all within the scope of the present invention.

[0018] In this embodiment, a pad layer 26 made of silicon oxide (SiO₂) and a pad layer (not shown) made of silicon nitride (SiN) could be formed on each of the base 22 and the fin-shaped structures 24 during the aforementioned patterning process. In this MV region 16, the pad layer 26 preferably covers the surface of the entire active area 62.

[0019] Next, as shown in FIG. 2, a flowable chemical vapor deposition (FCVD) process is conducted to form an insulating layer 28 made of silicon oxide on the base 22 and the fin-shaped structures 24 and filling the trenches between the base 22 and the fin-shaped structures 24, and a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the insulating layer 28 for forming a shallow trench isolation (STI). Next, part of the pad layer made of silicon nitride could be removed to expose the pad layer 26 made of silicon oxide. It should be noted that to emphasize the fabrication conducted on the surface of the substrate 12 on the MV region 16 in the later process, only the pad layer 26 on the substrate 12 of the MV region 16 is shown while the pad layer 26 on the LV region 18 is omitted in the figures afterwards.

[0020] Next, as shown in FIG. 3, a hard mask 32 is formed on the MV region 16 and the LV region 18 to cover the pad layers 26 on both regions 16, 18. In this embodiment, the hard mask 32 preferably includes a dielectric material including but not limited to for example silicon oxide, silicon nitride, or silicon carbonitride (SiCN).

[0021] Next, as shown in FIG. 4, a photo-etching process is conducted by using a patterned mask (not shown) such as patterned resist as mask to remove the hard mask 32 and the pad layer 26 on the MV region 16 for exposing the surface of the substrate 12. It should be noted that the etching process conducted at this stage for removing the hard mask 32 made of SiN and the pad layer 26 made of SiO₂ on the MV region 16 preferably removes all of the hard mask 32 first and then removes most of the pad layer 26 afterwards. Specifically, after the hard mask 32 is removed completely, a small portion of the pad layer 26 is remained on two sides of the substrate in particular at corners contacted between the substrate 12 and the STI 30. Viewing from a cross-section perspective, the surface of the substrate 12 on the MV region 16 remains to be a planar surface while the top surface of the remaining pad layer 26 disposed at corners between the substrate 12 and the STI 30 could be an inclined planar surface or a curved surface. Viewing from a top view perspective, the remaining pad layer 26 at this stage preferably forms a ring disposed on the active area 62 of the substrate 12 on the MV region 16 and surrounding four corners of the active area 62.

[0022] Next, as shown in FIG. 5, an oxide growth process or more specifically a rapid thermal oxidation (RTO) process 42 is conducted to form a gate dielectric layer 34 made of SiO₂ on the substrate 12 of MV region 16. It should be noted that since some pad layer 26 made of SiO₂is remained on corners between the substrate 12 and the STI 30, the oxygen gas injected during the RTO process 42 at this stage preferably reacts with the substantially central portion of the substrate 12 surface or active area 62 surface to form the gate dielectric layer 34 made of SiO₂, and then gradually reacts with active area 62 outside the central portion and then finally reacts with edge portion of the active area 62 to form the gate dielectric layer 34.

[0023] Since the central portion of the substrate 12 on the MV region 16 is reacted first to form the gate dielectric layer 34 made of SiO₂ while peripheral or edge portion of the substrate 12 is reacted afterwards, the overall process of conducting the RTO process 42 for oxidizing the surface of the substrate 12 on MV region 16 preferably forms a hump 36 on the substrate 12 surface. Preferably, the hump 36 is formed by the elevated edge or peripheral portion of the substrate 12 hence the hump 36 and the substrate 12 are made of same material.

[0024] It should be noted that since the gate dielectric layer 34 is formed along with the hump 36 on the substrate 12 surface, the top surface of the gate dielectric layer 34 on two adjacent sides also forms another hump 46. Similarly, since the hump 46 is formed by the edge portion of the gate dielectric layer 34, the hump 46 and the gate dielectric layer 34 are made of same material.

[0025] Referring to FIGS. 5-6, FIG. 5 illustrates a cross-section for forming humps 36, 46 on the substrate 12 surface and gate dielectric layer 34 surface of the MV region 16 according to an embodiment of the present invention and FIG. 6 illustrates a 3-dimensional view for forming the humps 36, 46 on the substrate 12 surface and gate dielectric layer 36 surface of MV region 16 according to an embodiment of the present invention. As shown on the left portion of FIG. 5, the hump 36 on the substrate 12 surface of the MV region 16 could further include a hump 38 adjacent to one side such as left side of the substrate 12 and another hump 40 adjacent to another side such as right side of the substrate 12, in which the top surface of each of the humps 38, 40 could be an inclined planar surface, a curved surface, an L-shape surface, or a V-shape surface, which are all within the scope of the present invention.

[0026] Similarly, the hump 46 on the surface of the gate dielectric layer 34 on MV region 16 could further include a hump 48 adjacent to one side such as left of the gate dielectric layer 34 and another hump 50 adjacent to another side such as right side of the gate structure layer 34, in which the top surface of each of the humps 48, 50 could be an inclined planar surface, a curved surface, an L-shape surface, or a V-shape surface, which are all within the scope of the present invention. From a top view perspective, the hump 36 on the active area 62 surface of the substrate 12 includes a ring shape that surrounds the four corners of the active area 62. Similarly, the hump 46 on the gate dielectric layer 34 surface also includes a ring that surrounds the four corners of the active area 62, in which the ring formed by the hump 46 on the gate dielectric layer 34 surface could completely overlap or partially overlap the ring formed by the hump 36 on the substrate 12 surface underneath. In other words, the area of the ring formed by the hump 46 on gate dielectric layer 34 surface could be greater than, equal to, or less than the area of the ring formed by the hump 36 on substrate 12 surface underneath, which are all within the scope of the present invention.

[0027] Referring to FIGS. 7-8, FIG. 7 illustrates a structural view for fabricating gate structures on the MV region 16 and LV region 18 after FIG. 6 and FIG. 8 illustrates a top view for fabricating a gate structure on the MV region 16 according to an embodiment of the present invention. As shown in FIG. 7, it would be desirable to first remove the hard mask 32 and part of the STI 30 on the LV region 18 so that the top surface of the STI 30 is slightly lower than the top surface of the fin-shaped structure 24, and then conduct an oxidation process such as an in-situ steam generation (ISSG) process to form a gate dielectric layer 52 made of SiO₂ on the surface of the fin-shaped structures 24 on the LV region 18. Next, gate structures or gate electrodes 54, 56 could be formed on the base 22 and fin-shaped structures 24 on the MV region 16 and LV region 18 respectively, in which the formation of the gate electrodes 54, 56 could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process.

[0028] Next, a standard metal-oxide semiconductor (MOS) transistor fabrication process could be carried out by forming elements such as source/drain regions 58 in the substrate 12 adjacent to two sides of the gate electrodes 54, 56. Since the fabrication of a standard MOS transistor process is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. Viewing from a top view of FIG. 8, after the gate electrode 54 is formed on the MV region 16, the hump 36 on the substrate 12 would still surround the four corners of the active area 62. Nevertheless, the hump 46 on the gate dielectric layer 34 could also overlap the hump 36 on the substrate 12 surface entirely or as shown in FIG. 8 be patterned along with the gate electrode 54 so that the remaining hump 46 would only be disposed on edges of the active area 62 directly under the gate electrode 54, which are all within the scope of the present invention.

[0029] Overall, the present invention first forms a STI around the substrate on the MV region and fin-shaped structures on the LV region, forms a hard mask made of SiN on both MV region and LV region, removes the hard mask on the MV region, and then conducts a RTO process 42 to form a gate dielectric layer on the substrate surface of the MV region. Since the fin-shaped structures on the LV region is covered with hard mask 32 during the RTO process 42, the high temperature used during the RTO process 42 would not affect the density of the fin-shaped structures to result in fin width shrinkage and performance of the transistors would be preserved.

[0030] The foregoing outlines the features of several embodiments, enabling those skilled in the art to fully appreciate the aspects of the present disclosure. Those skilled in the art should recognize that the present disclosure provides a foundation for designing or modifying other processes and structures to achieve substantially the same functions and/or substantially the same results as those of the embodiments introduced herein. Furthermore, such equivalent arrangements do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without so departing.