High Electron Mobility Transistor and Method for Manufacturing Same

[0001] The present application claims priority to U.S. Provisional Patent Application No. 63/755,692 filed on Feb. 7, 2025, the contents of which are hereby incorporated by reference in their entirety.

[0002] The present disclosure relates high electron mobility transistors (HEMTs), and more specifically to high performance HEMTs and methods for manufacturing same to improve the drive current and to reduce the leakage current of the HEMT.

[0003] According to an aspect of one or more examples, there is provided a High-Electron-Mobility-Transistor that may include a substrate, a first doped structure formed within the substrate, a first barrier layer formed over the first doped structure and formed over the substrate, a first buffer layer formed over the first barrier layer, a second barrier layer formed over the first buffer layer, a second doped structure formed over the second barrier layer, a second buffer layer formed over the second barrier layer, a third barrier layer formed over the second buffer layer and formed over the second doped structure, the third barrier layer surrounds the second doped structure, a third buffer layer formed over the third barrier layer, an upper insulating layer formed over the third buffer layer, a first spacer formed on a portion of the first doped structure through the first barrier layer, through the first buffer layer, through the second barrier layer, through the second buffer layer, through the third barrier layer, through the third buffer layer and through the upper insulating layer, a second spacer formed on a portion of the second doped structure partially through an upper portion of the third barrier layer, through the third buffer layer and through the upper insulating layer, a first gate electrode formed through the upper insulating layer, within the first spacer through the third buffer layer, through the third barrier layer, through the second buffer layer, through the second barrier layer, through the first buffer layer, through the first barrier layer, the first gate electrode connected to the first doped structure, a second gate electrode formed through the upper insulating layer, within the second spacer through the third buffer layer and partially into the upper portion of the third barrier layer, the second gate electrode connected to the second doped structure, a drain terminal formed at a first side of the first gate electrode, and a source terminal formed at a second side of the first gate electrode. The first doped structure may be insulated from the substrate by a lower insulating layer. The first buffer layer may comprise a first III-V compound semiconductor such as gallium nitride. The second buffer layer may comprise a second III-V compound semiconductor such as gallium nitride. The third buffer layer may comprise a third III-V compound semiconductor such as gallium nitride. The first barrier layer, the second barrier layer and the third barrier layer may comprise aluminum gallium nitride. The first doped structure may comprise P-doped gallium nitride. The second doped structure may comprise P-doped gallium nitride. The upper insulating layer and the lower insulating layer may comprise polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide.

[0004] According to an aspect of one or more examples, there is provided method for producing a High-Electron-Mobility-Transistor. The method may include providing a substrate, forming a first doped structure within the substrate, forming a first barrier layer over the first doped structure and over the substrate, forming a first buffer layer over the first barrier layer, forming a second barrier layer over the first buffer layer, forming a second doped structure over the second barrier layer, forming a second buffer layer over the second barrier layer, forming a third barrier layer over the second buffer layer and over the second doped structure, the third barrier layer surrounds the second doped structure, forming a third buffer layer over the third barrier layer, forming an upper insulating layer over the third buffer layer, forming a first spacer on a portion of the first doped structure through the first barrier layer, through the first buffer layer, through the second barrier layer, through the second buffer layer, through the third barrier layer, through the third buffer layer and through the upper insulating layer, forming a second spacer on a portion of the second doped structure partially through an upper portion of the third barrier layer, through the third buffer layer and through the upper insulating layer, forming a first gate electrode through the upper insulating layer, within the first spacer through the third buffer layer, through the third barrier layer, through the second buffer layer, through the second barrier layer, through the first buffer layer, through the first barrier layer, the first gate electrode connected to the first doped structure, forming a second gate electrode through the upper insulating layer, within the second spacer through the third buffer layer and partially into the upper portion of the third barrier layer, the second gate electrode connected to the second doped structure, forming a drain terminal at a first side of the first gate electrode, and forming a source terminal at a second side of the first gate electrode. The first doped structure may be insulated from the substrate by a lower insulating layer. The first buffer layer may comprise a first III-V compound semiconductor such as gallium nitride. The second buffer layer may comprise a second III-V compound semiconductor such as gallium nitride. The third buffer layer may comprise a third III-V compound semiconductor such as gallium nitride. The first barrier layer, the second barrier layer and the third barrier layer may comprise aluminum gallium nitride. The first doped structure may comprise P-doped gallium nitride. The second doped structure may comprise P-doped gallium nitride. The upper insulating layer and the lower insulating layer may comprise polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide.

[0014] Reference will now be made in detail to the following various examples, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The following examples may be embodied in various forms without being limited to the examples set forth herein.

[0015] FIG. 1A shows a cross sectional view of a High-Electron-Mobility-Transistor 10 according to one or more examples. As shown in FIG. 1, the High-Electron-Mobility-Transistor 10 may have a substrate 20 with a first doped structure 100 within the substrate 20. The first doped structure 100 may be insulated from the substrate 20 by a lower insulating layer 85. The lower insulating layer 85 may comprise polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide or any other insulating material or a mixture of all these. The substrate 20 may comprise gallium nitride, diamond, silicon carbide, sapphire, aluminum nitride or silicon. A first barrier layer 40 may be formed over the first doped structure 100 and formed over the substrate 20. The first barrier layer 40 may comprise aluminum gallium nitride. The first doped structure 100 may comprise P-doped gallium nitride. A first buffer layer 50 may be formed over the first barrier layer 40. The first buffer layer 50 may comprise a first III-V compound semiconductor such as gallium nitride. A second barrier layer 60 may be formed over the first buffer layer 50. A second doped structure 110 may be formed over the second barrier layer 60. The second barrier layer 60 may comprise aluminum gallium nitride. The second doped structure 110 may comprise P-doped gallium nitride. A second buffer layer 70 may be formed over the second barrier layer 60. The second buffer layer 70 may comprise a second III-V compound semiconductor such as gallium nitride. A third barrier layer 80 may be formed over the second buffer layer 70 and formed over the second doped structure 110. The third barrier layer 80 may surround the second doped structure 110. The third barrier layer 80 may comprise aluminum gallium nitride. A third buffer layer 90 may be formed over the third barrier layer 80. The third buffer layer 90 may comprise a third III-V compound semiconductor such as gallium nitride. Due to the nature of gallium nitride/aluminum gallium nitride band bending a 2DEG (Two-Dimensional Electron Gas) is formed at the interfaces of these two materials (the first buffer layer 50 and the first barrier layer 40, the first buffer layer 50 and the second barrier layer 60, the second buffer layer 70 and the second barrier layer 60, the second buffer layer 70 and the third barrier layer 80, and the third buffer layer 90 and the third barrier layer 80). This is like electron gas that is free to move in 2 dimensions and confined in the third dimension. An upper insulating layer 200 may be formed over the third buffer layer 90. The upper insulating layer 200 may comprise polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide or any other insulating material or a mixture of all these. A first spacer 120 may be formed on a portion of the first doped structure 100 through the first barrier layer 40, through the first buffer layer 50, through the second barrier layer 60, through the second buffer layer 70, through the third barrier layer 80, through the third buffer layer 90 and through the upper insulating layer 200. A second spacer 140 may be formed on a portion of the second doped structure 110 partially through an upper portion of the third barrier layer 80, through the third buffer layer 90 and through the upper insulating layer 200. A first gate electrode 130 may be formed through the upper insulating layer 200, within the first spacer 120 through the third buffer layer 90, through the third barrier layer 80, through the second buffer layer 70, through the second barrier layer 60, through the first buffer layer 50, through the first barrier layer 40. The first gate electrode 130 may be connected to the first doped structure 100. A second gate electrode 150 may be formed through the upper insulating layer 200, within the second spacer 140 through the third buffer layer 90 and partially into the upper portion of the third barrier layer 80. The second gate electrode 150 may be connected to the second doped structure 110. In FIG. 1A, the second gate electrode 150 is shown laterally shifted to the first gate electrode 130 since this is a two dimensional drawing. However, in most cases, the second gate electrode 150 is in alignment with the first gate electrode 130. In addition, the first gate electrode 130 may be shorted to the second gate electrode 150 so that there is a single gate electrode. Alternatively, the first gate electrode 130 can operate independent of the second gate electrode 150. A drain terminal 160 may be formed at a first side of the first gate electrode 130. A source terminal 170 may be formed at a second side of the first gate electrode 130.

[0016] FIG. 1B shows a top view of a High-Electron-Mobility-Transistor 10 according to one or more examples. As shown in FIG. 1B, the High-Electron-Mobility-Transistor 10 may have a first spacer 120 with a first gate electrode 130 that may be formed within the first spacer 120. A second spacer 140 with a second gate electrode 150 that may be formed within the second spacer 140. A drain terminal 160 may be formed at a first side of the first gate electrode 130. A source terminal 170 may be formed at a second side of the first gate electrode 130.

[0017] FIGS. 2A-2G show a method of manufacturing a High-Electron-Mobility-Transistor 10 according to one or more example. Although the example method shown in FIGS. 2A-2G includes steps shown in a particular order, the steps may be performed in a different order, and may include additional steps that are not explicitly shown. In addition, each step presented herein may have multi-steps necessary to carry out the stated step that are not explicitly shown or stated herein.

[0018] FIG. 2A is cross sectional view of some of the steps in a method of manufacturing a High-Electron-Mobility-Transistor 10 according to one or more examples. In FIG. 2A, the example method may include forming a first doped structure 100 within a substrate 20. The substrate 20 may comprise gallium nitride, diamond, silicon carbide, sapphire, aluminum nitride or silicon. The first doped structure 100 may comprise P-doped gallium nitride. The first doped structure 100 may be insulated from the substrate by a lower insulating layer 85. The lower insulating layer 85 may comprise polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide or any other insulating material or a mixture of all these.

[0019] FIG. 2B is cross sectional view of some of the steps in a method of manufacturing a High-Electron-Mobility-Transistor 10 according to one or more examples. FIG. 2B shows the formation of a first barrier layer 40 over the first doped structure 100 and over the substrate 20. The first barrier layer 40 may comprise aluminum gallium nitride. A first buffer layer 50 may be formed over the first barrier layer 40. The first buffer layer 50 may comprise a first III-V compound semiconductor such as gallium nitride. A second barrier layer 60 may be formed over the first buffer layer 50. The second barrier layer 60 may comprise aluminum gallium nitride. A doped layer 115 may be formed over the second barrier layer 60. The doped layer 115 may comprise P-doped gallium nitride.

[0020] FIG. 2C is cross sectional view of some of the steps in a method of manufacturing a High-Electron-Mobility-Transistor 10 according to one or more examples. FIG. 2C shows the formation of a gate mask 190 that may be formed over the doped layer 115.

[0021] FIG. 2D is cross sectional view of some of the steps in a method of manufacturing a High-Electron-Mobility-Transistor 10 according to one or more examples. FIG. 2D shows the patterning of the doped layer 115 of FIG. 2C into a second doped structure 110.

[0022] FIG. 2E is cross sectional view of some of the steps in a method of manufacturing a High-Electron-Mobility-Transistor 10 according to one or more examples. FIG. 2E includes forming a second buffer layer 70 over the second barrier layer 60. The second buffer layer 70 may comprise a second III-V compound semiconductor such as gallium nitride. FIG. 2E includes depositing or epitaxially growing a third barrier layer 80 over the second buffer layer 70 and over the second doped structure 110 and onto side surfaces of the second doped structure 110 to completely surround the second doped structure 110. The third barrier layer 80 may comprise aluminum gallium nitride. FIG. 2E includes forming a third buffer layer 90 over the third barrier layer 80. The third buffer layer 90 may comprise a third III-V compound semiconductor such as gallium nitride.

[0023] FIG. 2F is cross sectional view of some of the steps in a method of manufacturing a High-Electron-Mobility-Transistor 10 according to one or more examples. FIG. 2F shows the formation of an upper insulating layer 200 that may be formed over the third buffer layer 90. The upper insulating layer 200 may comprise polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide or any other insulating material or a mixture of all these. FIG. 2F shows the formation of a first spacer 120 that may be formed on a portion of the first doped structure 100 through the first barrier layer 40, through the first buffer layer 50, through the second barrier layer 60, through the second buffer layer 70, through the third barrier layer 80, through the third buffer layer 90 and through the upper insulating layer 200. FIG. 2F shows the formation of a second spacer 140 that may be formed on a portion of the second doped structure 110 partially through an upper portion of the third barrier layer 80, through the third buffer layer 90 and through the upper insulating layer 200.

[0024] FIG. 2G is cross sectional view of some of the steps in a method of manufacturing a High-Electron-Mobility-Transistor 10 according to one or more examples. FIG. 2G shows the formation of a first gate electrode 130 that may be formed through the upper insulating layer 200, within the first spacer 120 through the third buffer layer 90, through the third barrier layer 80, through the second buffer layer 70, through the second barrier layer 60, through the first buffer layer 50 and through the first barrier layer 40. The first gate electrode 130 may be connected to the first doped structure 100. FIG. 2G shows the formation of a second gate electrode 150 that may be formed through the upper insulating layer 200, within the second spacer 140 through the third buffer layer 90 and partially into the upper portion of the third barrier layer 80. The second gate electrode 150 may be connected to the second doped structure 110. In FIG. 2G, the second gate electrode 150 is shown laterally shifted to the first gate electrode 130 since this is a two dimensional drawing. However, in most cases, the second gate electrode 150 is in alignment with the first gate electrode 130. In addition, the first gate electrode 130 can be shorted to the second gate electrode 150 so that there is a single gate electrode. Alternatively, the first gate electrode 130 can operate independent of the second gate electrode 150. A drain terminal 160 may be formed at a first side of the first gate electrode 130. A source terminal 170 may be formed at a second side of the first gate electrode 130. Due to the nature of gallium nitride/aluminum gallium nitride band bending a 2DEG (Two-Dimensional Electron Gas) is formed at the interfaces of these two materials (the first buffer layer 50 and the first barrier layer 40, the first buffer layer 50 and the second barrier layer 60, the second buffer layer 70 and the second barrier layer 60, the second buffer layer 70 and the third barrier layer 80, and the third buffer layer 90 and the third barrier layer 80). This is like electron gas that is free to move in 2 dimensions and confined in the third dimension.

[0025] Various examples have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious to literally describe and illustrate every combination and subcombination of these examples. Accordingly, all examples may be combined in any way and/or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the examples described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

[0026] It will be appreciated by persons skilled in the art that the examples described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings.