SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

[0001] This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2024-156790, filed Sep. 10, 2024, the entire contents of which are incorporated herein by reference.

[0002] Embodiments described herein relate generally to a semiconductor device, and to a manufacturing method thereof.

[0003] When manufacturing a semiconductor device such as a semiconductor storage device, there is a case where a semiconductor part is mounted on a substrate using reflow soldering. In such case, thermal warping of the substrate caused by the reflow soldering may occur.

[0011] Embodiments provide a semiconductor device, and a manufacturing method thereof, such that warping of a substrate can be reduced.

[0012] In general, according to one embodiment, a semiconductor device includes a substrate, at least one semiconductor part, and a non-semiconductor part. The substrate has a first face and a second face on a side opposite to that of the first face, and has a first linear expansion coefficient. The at least one semiconductor part is disposed on a first region of the first face, and has a second linear expansion coefficient that is smaller than the first linear expansion coefficient. The non-semiconductor part is disposed on a second region of the first face, on which no semiconductor part is disposed, and has a third linear expansion coefficient that is greater than the first linear expansion coefficient.

[0013] Hereafter, an embodiment will be described while referring to the drawings. In order to facilitate understanding of the description, identical reference signs will be allotted, as far as possible, to identical components in the drawings, and redundant descriptions will be omitted.

[0014] FIG. 1 is a sectional view showing an example of a configuration of a semiconductor device 1 according to an embodiment. FIG. 2 is a perspective view showing an example of a configuration of the semiconductor device 1 according to the embodiment. FIG. 1 corresponds to an I-I section of the semiconductor device shown in FIG. 2. FIG. 3 is a plan view showing an example of a configuration of the semiconductor device 1 according to the embodiment. FIG. 1 shows one portion of the semiconductor device 1 shown in FIGS. 2 and 3. The semiconductor device 1 shown in FIGS. 2 and 3 is divided into a plurality of portions, each of which can be mounted in a semiconductor storage device.

[0015] The semiconductor device 1 can, for example, be advantageously used in a semiconductor storage device, such as a large-scale solid-state drive (SSD), in which a plurality of semiconductor parts are mounted. As shown in FIGS. 1 to 3, the semiconductor device 1 includes a substrate 2, a plurality of semiconductor parts 3, and an additional part 4. The additional part 4 is one example of a first part.

[0016] As shown in FIG. 1, the substrate 2 has a first face 21, and a second face 22 positioned on a side opposite to that of the first face 21. As shown in FIG. 1, a direction following a thickness direction of the substrate 2 is defined as a Z direction. Also, a direction from the second face 22 toward the first face 21 is defined as an upward direction. A direction from the first face 21 toward the second face 22 is defined as a downward direction. The upward direction is a direction opposite to the downward direction. In this case, the first face 21 can also be called an upper face of the substrate 2. These expressions are for the sake of the description, and do not define a direction of gravitational force. Also, the second face 22 can also be called a lower face of the substrate 2. An X direction and a Y direction are directions parallel to the first face 21 of the substrate 2. The X direction is a direction that intersects (for example, is perpendicular to) the Y direction. The X direction and the Y direction are directions that intersect (for example, are perpendicular to) the Z direction. The X direction is one example of a first direction. The Y direction is one example of a second direction.

[0017] The substrate 2 has a first linear expansion coefficient. A linear expansion coefficient is also called a linear expansion rate. The first linear expansion coefficient is a ratio between an amount of change in length of the substrate 2 per 1° C. of change in temperature of the substrate 2 and an original length of the substrate 2. The first linear expansion coefficient can be expressed using, for example, the following equation [1].

$\begin{array}{cc}{\alpha }_1=\left(1/L_1\right)\times \left({\mathrm{dL}}_1/{\mathrm{dT}}_1\right)& \left[1\right]\end{array}$

[0018] Here, α₁ is the first linear expansion coefficient. L₁ is an original length (for example, an X direction length) of the substrate 2. dL₁ is the amount of change in length of the substrate 2. dT₁ is the amount of change in temperature of the substrate 2.

[0019] The first linear expansion coefficient can be calculated based on, for example, a result of a simulation or an experiment measuring a change in the length of the substrate 2 in response to a change in temperature of the substrate 2.

[0020] In the example shown in FIG. 3, the substrate 2 has an approximately rectangular form when seen from the Z direction (that is, in plan view). The substrate 2, for example, contains a resin material, and is a wiring substrate on which wiring (not shown) is provided. The substrate 2 has a plurality of wiring layers. The substrate 2 may further include a via that connects wiring or an electrode on an upper layer side and wiring on a lower layer side. The first linear expansion coefficient is, for example, approximately 15 ppm/° C.

[0021] As shown in FIG. 1, the semiconductor part 3 is disposed on a first region 21a of the first face 21. The first region 21a is a region of the first face 21 on which the semiconductor part 3 is disposed. The first region 21a can also be called a mounting region of the semiconductor part 3. The plurality of semiconductor parts 3 are disposed neighboring in the X direction and the Y direction in FIGS. 1 to 3. The semiconductor part 3 has a second linear expansion coefficient smaller than the first linear expansion coefficient.

[0022] The second linear expansion coefficient is a ratio between an amount of change in length of the semiconductor part 3 per 1° C. of change in temperature of the semiconductor part 3 and an original length of the semiconductor part 3. The second linear expansion coefficient can be expressed using, for example, the following equation [2].

$\begin{array}{cc}{\alpha }_2=\left(1/L_2\right)\times \left({\mathrm{dL}}_2/{\mathrm{dT}}_2\right)& \left[2\right]\end{array}$

[0023] Here, α₂ is the second linear expansion coefficient. L₂ is an original length (for example, an X direction length) of the semiconductor part 3. dL₂ is the amount of change in length of the semiconductor part 3. dT₂ is the amount of change in temperature of the semiconductor part 3.

[0024] The second linear expansion coefficient can be calculated based on, for example, a result of a simulation or an experiment measuring a change in the length of the semiconductor part 3 in response to a change in temperature of the semiconductor part 3.

[0025] The semiconductor part 3 is, for example, a NAND flash memory. A NAND flash memory has, for example, a wiring substrate on which a terminal such as a solder ball to be electrically connected to the substrate 2 is provided, at least one memory chip mounted on the wiring substrate, and a sealing resin that seals the memory chip. When the semiconductor part 3 is a NAND flash memory, the second linear expansion coefficient is, for example, approximately 3.5 ppm/° C.

[0026] The additional part 4 is a part additionally disposed on the substrate 2 in order to reduce thermal warping of the substrate 2 caused by a difference between the linear expansion coefficients of the semiconductor part 3 and the substrate 2. The additional part 4 is disposed on a second region 21b of the first face 21 on which the semiconductor part 3 is not disposed. The second region 21b can also be called a non-mounting region on which the semiconductor part 3 is not mounted. The second region 21b can also be called an empty space. The additional part 4 has a third linear expansion coefficient greater than the first linear expansion coefficient.

[0027] The third linear expansion coefficient is a ratio between an amount of change in length of the additional part 4 per 1° C. of change in temperature of the additional part 4 and an original length of the additional part 4. The third linear expansion coefficient can be expressed using, for example, the following equation [3].

$\begin{array}{cc}{\alpha }_3=\left(1/L_3\right)\times \left({\mathrm{dL}}_3/{\mathrm{dT}}_3\right)& \left[3\right]\end{array}$

[0028] Here, α₃ is the third linear expansion coefficient. L₃ is an original length (for example, an X direction length) of the additional part 4. dL₃ is the amount of change in length of the additional part 4. dT₃ is the amount of change in temperature of the additional part 4.

[0029] The third linear expansion coefficient can be calculated based on, for example, a result of a simulation or an experiment measuring a change in the length of the additional part 4 in response to a change in temperature of the additional part 4.

[0030] The additional part 4 is a part excluding a semiconductor part, that is, a part other than a semiconductor part. In other words, the additional part 4 is a part that does not include a semiconductor as a component thereof. The additional part 4 can also be called a part that is not involved in electrical properties of the semiconductor device 1. The additional part 4 is not electrically connected to any wiring included in the substrate 2. The additional part 4 is provided on an insulating layer (for example, a solder resist layer) provided on the substrate 2. The additional part 4 is made of, for example, metal. The linear expansion coefficient of the additional part 4 is greater than the linear expansion coefficients of the substrate 2 and the semiconductor part 3. The metal of the additional part 4 is preferably aluminum. By using aluminum, the additional part 4 that has a large linear expansion coefficient can be formed at a low cost. When the additional part 4 is formed of aluminum, the third linear expansion coefficient is 23.9 ppm/° C. The additional part 4 may also be formed of copper.

[0031] As described above, when the first linear expansion coefficient is expressed using equation [1], the second linear expansion coefficient is expressed using equation [2], and the third linear expansion coefficient is expressed using equation [3], the following equation [4] is established among the three linear expansion coefficients.

$\begin{array}{cc}{\alpha }_2<{\alpha }_1<{\alpha }_3& \left[4\right]\end{array}$

[0032] In the example shown in FIG. 3, the additional part 4 is disposed in a vicinity of a center of the first face 21. That is, the additional part 4 is disposed in a vicinity of a central position in the X direction of the first face 21, and in a vicinity of a central position in the Y direction of the first face 21. In other words, the additional part 4 is disposed in a position nearer than the semiconductor part 3 to the center of the first face 21.

[0033] Two additional parts 4 are disposed across an interval in the Y direction on the first face 21 of the substrate 2. In the example shown in FIG. 3, a dimension of the additional part 4 in the X direction of the first face 21 is smaller than that of the semiconductor part 3. Specifically, the additional part 4 has a rod shape extending in the Y direction that intersects the X direction of the first face 21. Also, in the example shown in FIG. 3, a dimension of the additional part 4 in the Z direction is greater than that of the semiconductor part 3.

[0034] Also, in the example shown in FIG. 3, the additional part 4 extends in the Y direction to a length such as to oppose two or more semiconductor parts 3 in the X direction. That is, the additional part 4 extends in the Y direction in such a way as to straddle two or more semiconductor parts 3 when seen from the X direction.

[0035] The semiconductor part 3 is mechanically and electrically connected to the substrate 2 via a conductive layer (not shown) disposed on the first region 21a. For example, the semiconductor part 3 is electrically connected to the substrate 2 by being connected to an electrode provided on the substrate 2 across the conductive layer. The additional part 4 is mechanically connected to the substrate 2 across a conductive layer (not shown) disposed on the second region 21b. The additional part 4 is not electrically connected to wiring of the substrate 2. The conductive layer is, for example, a solder layer. That is, the semiconductor part 3 and the additional part 4 are connected onto the substrate 2 using conductive layers of the same material.

[0036] Next, a method of manufacturing the semiconductor device 1 having the heretofore described configuration will be described. FIG. 4 is a sectional view showing a method of manufacturing the semiconductor device 1 according to the embodiment. Firstly, as shown in FIG. 4, a solder paste 6 is formed on a plurality of electrodes 23 provided inside the first region 21a of the first face 21 of the substrate 2. The plurality of electrodes 23, for example, include the electrode 23 used for a transmission and a reception of a signal between the semiconductor part 3 and another circuit (for example, a memory controller) disposed on the substrate 2. Also, the plurality of electrodes 23, for example, include the electrode 23 connected to a power supply line (not shown) provided in an interior of the substrate 2. Also, the plurality of electrodes 23, for example, include the electrode 23 connected to a ground line (not shown) provided in the interior of the substrate 2. In FIG. 4, a via V connected to one electrode 23 and a wiring W connected to the via V are shown as representative of a structure inside the substrate 2.

[0037] When forming the solder paste 6 on the electrode 23 on the first region 21a, the solder paste 6 is also formed on the second region 21b. In the example shown in FIG. 4, the wiring W is not provided in the second region 21b. Also, a pad 230 is provided on the second region 21b. The pad 230 contains, for example, copper. The pad 230 can also be called a metal film or a dummy electrode. The solder paste 6 on the second region 21b is formed on a surface of the substrate 2 (that is, a surface of an insulating layer) across the pad 230. Because the solder paste 6 on the first region 21a and the solder paste 6 on the second region 21b are formed simultaneously, the semiconductor part 3 and the additional part 4 can be mounted efficiently. Also, because the pad 230 is provided on the second region 21b, which does not coincide with the wiring W, a mechanical connection of the substrate 2 and the additional part 4 can be carried out appropriately, while avoiding an electrical connection of the substrate 2 and the additional part 4.

[0038] FIG. 5 is a sectional view, continuing from FIG. 4, showing a method of manufacturing the semiconductor device 1 according to the embodiment. After forming the solder paste 6, the semiconductor part 3 is disposed on the solder paste 6 formed on the electrode 23, as shown in FIG. 5. Specifically, the semiconductor part 3 is disposed in such a way that a terminal (not shown) provided on a lower face (a face opposing the substrate 2) of the semiconductor part 3 comes into contact on the solder paste 6. At this time, the additional part 4 is disposed on the solder paste 6 formed on the pad 230.

[0039] FIG. 6 is a sectional view, continuing from FIG. 5, showing a method of manufacturing the semiconductor device 1 according to the embodiment. After disposing the semiconductor part 3 and the additional part 4, the solder paste 6 is melted by being heated inside a reflow furnace 7, as shown in FIG. 6. Subsequently, the solder paste 6 is cured by stopping the heating. That is, a reflow soldering (that is, a reflow process) of the semiconductor part 3 and the additional part 4 is implemented. Because of this, the substrate 2 and the semiconductor part 3 are mechanically and electrically connected via the solder paste 6 on the electrode 23. Also, the substrate 2 and the additional part 4 are mechanically connected via the solder paste 6 on the pad 230, without being electrically connected.

[0040] FIG. 7 is a plan view showing a result of simulating thermal warping (that is, deformation) of the substrate 2 of the semiconductor device 1 according to the embodiment. In FIG. 7, thermal warping of the semiconductor device 1 according to the embodiment, which is such that the additional part 4 is disposed in a vicinity of the center and an X direction end portion of the first face 21, is indicated by a contour diagram on the first face 21. Also, in FIG. 7, thermal warping of a semiconductor device 10 according to a comparative example, in which the additional part 4 is not disposed, is indicated by a contour diagram on the first face 21. In FIG. 7, contour lines C1 to C13 indicate, in order from C1, places in which an amount of displacement in the Z direction is large after the substrate 2 on which reflow soldering is implemented cools. That is, a region enclosed by the contour line C1 is a region in which the amount of displacement in the Z direction after reflow soldering is largest. Meanwhile, a region on an outer side of the contour line C13 is a region in which the amount of displacement in the Z direction after reflow soldering is smallest.

[0041] When the additional part 4 is not disposed on the substrate 2, as is the case with the semiconductor device 10 according to the comparative example, places in which the amount of displacement in the Z direction is large appear after the substrate 2 on which reflow soldering is implemented cools, as indicated by contour lines C1 to C5. That is, when the additional part 4 is not disposed on the substrate 2, considerable thermal warping of the substrate 2 occurs.

[0042] As opposed to this, because the semiconductor device 1 according to the embodiment has the additional part 4 disposed on the substrate 2, displacement in the Z direction is limited to the contour lines C6 to C13, which indicate smaller warping than the contour lines C1 to C5. Consequently, the semiconductor device 1 according to the embodiment is such that thermal warping of the substrate 2 is reduced more than is the case with the semiconductor device 10 according to the comparative example.

[0043] As heretofore described, the semiconductor device 1 according to the embodiment includes the substrate 2, which has the first linear expansion coefficient, at least one semiconductor part 3, and the additional part 4. The semiconductor part 3 is disposed on the first region 21a of the first face 21, and has the second linear expansion coefficient, which is smaller than the first linear expansion coefficient. The additional part 4 is disposed on the second region 21b of the first face 21, on which the semiconductor part 3 is not disposed, and has the third linear expansion coefficient, which is greater than the first linear expansion coefficient.

[0044] Herein, a case in which the additional part 4 is not disposed on the substrate 2 is such that when the substrate 2 cools after the semiconductor part 3 is mounted on the substrate 2 by soldering, considerable thermal warping of the substrate 2 occurs due to a difference in the linear expansion coefficients of the substrate 2, which has a large linear expansion coefficient, and the semiconductor part 3, which has a small linear expansion coefficient. Specifically, as the linear expansion coefficient of the semiconductor part 3 is smaller than the linear expansion coefficient of the substrate 2, an amount of contraction of the substrate 2 during the cooling process after reflow soldering is greater than an amount of contraction of the semiconductor part 3. Because of this, thermal warping such that the substrate 2 curves in the Z direction occurs in the substrate 2, as shown in the comparative example of FIG. 7.

[0045] As opposed to this, because the semiconductor device 1 according to the embodiment has the additional part 4, whose linear expansion coefficient is greater than that of the substrate 2, thermal warping (that is, distortion) can be caused to occur in a direction opposite to that of the thermal warping (distortion) that occurs due to the difference in the linear expansion coefficients of the semiconductor part 3 and the substrate 2. Because of this, thermal warping in mutually opposing directions can be sufficiently offset, meaning that thermal warping of the substrate 2 can be effectively reduced. As thermal warping of the substrate 2 can be reduced, mounting of another semiconductor part on the second face 22 of the substrate 2 can be carried out easily and appropriately. Also, as the additional part 4 is not a semiconductor part, a degree of freedom of layout is extensive in comparison with a case in which a semiconductor part is disposed. For example, the additional part 4 can also be disposed in a constricted space where a semiconductor part cannot be disposed.

[0046] Also, the semiconductor device 1 according to the embodiment is such that the additional part 4 is disposed in a vicinity of the center of the first face 21.

[0047] As the additional part 4 can be disposed in a vicinity of the center of the first face 21, whose amount of displacement in the Z direction of the substrate 2 is considerable, thermal warping of the substrate 2 can be more effectively reduced.

[0048] Also, the semiconductor device 1 according to the embodiment is such that the dimension of the additional part 4 in the X direction of the first face 21 is smaller than that of the semiconductor part 3.

[0049] Because of this, warping of the substrate 2 can be reduced, while making effective use of an empty constricted space on the substrate 2.

[0050] Also, the semiconductor device 1 according to the embodiment is such that the additional part 4 has a rod shape extending in the Y direction that intersects the X direction of the first face 21.

[0051] Because of this, warping of the substrate 2 can be effectively reduced by the additional part 4 of a simple configuration.

[0052] Also, the semiconductor device 1 according to the embodiment is such that the additional part 4 extends in the Y direction to a length such as to oppose two or more semiconductor parts 3 when seen from the X direction.

[0053] Because of this, an area of the additional part 4 can be increased as much as possible, meaning that warping of the substrate 2 can be more effectively reduced.

[0054] Also, the semiconductor device 1 according to the embodiment is such that the additional part 4 is configured of metal.

[0055] As the additional part 4 can be configured of metal, which has excellent heat resistance, reflow soldering can be carried out appropriately.

[0056] Also, the semiconductor device 1 according to the embodiment is such that the metal contains aluminum.

[0057] Because of this, the additional part 4 can be provided at low cost.

[0058] Also, the semiconductor device 1 according to the embodiment is such that the semiconductor part 3 is mechanically and electrically connected to the substrate 2 via the solder paste 6 disposed on the first region 21a. Also, the additional part 4 is mechanically connected to the substrate 2 across the solder paste 6 disposed on the second region 21b, without being electrically connected.

[0059] Because of this, the additional part 4 can be mounted using the solder paste 6 used in mounting the semiconductor part 3, meaning that warping of the substrate 2 can be reduced at low cost.

[0060] Also, according to the embodiment, disposition of the semiconductor part 3 and disposition of the additional part 4 are carried out simultaneously.

[0061] Because of this, the semiconductor part 3 and the additional part 4 can be efficiently mounted, in addition to which warping of the substrate 2 can be effectively reduced.

[0062] Also, according to the embodiment, disposition of the semiconductor part 3 and disposition of the additional part 4 are carried out using reflow soldering.

[0063] Because of this, the semiconductor part 3 and the additional part 4 can be mounted with high accuracy.

[0064] A plurality of modifications shown below can be applied to the embodiment.

[0065] FIG. 8 is a plan view showing the semiconductor device 1 according to a first modification of the embodiment. The example described thus far is such that the additional part 4 has a rod shape extending in the Y direction. As opposed to this, the additional part 4 may have a rod shape extending in the X direction, as shown in FIG. 8. A dimension of the additional part 4 in the X direction of the first face 21 is greater than that of the semiconductor part 3. Because of this, the degree of freedom in laying out the additional part 4 can be further increased.

[0066] FIG. 9 is a sectional view showing the semiconductor device 1 according to a second modification of the embodiment. In the example shown in FIG. 9, a second semiconductor part 3 is disposed on the second face 22. In the same way as the semiconductor part 3 on the first face 21, the second semiconductor part 3 is mounted on the second face 22 using reflow soldering. In the example shown in FIG. 9, the second semiconductor part 3 is disposed in a position immediately opposite the semiconductor part 3 on the first face 21 in the Z direction. As warping of the substrate 2 is reduced by the additional part 4 disposed on the first face 21, the second semiconductor part 3 can be appropriately mounted on the second face 22.

[0067] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.