SYNCHRONOUS RECTIFIER DRIVER CIRCUIT, RELATED INTEGRATED CIRCUIT, ELECTRONIC RESONANT CONVERTER AND METHOD

[0001] The embodiments of the present description refer to a synchronous rectifier driver circuit for two synchronous rectifier switches, such as synchronous rectifier switches of a switching resonant converter.

[0002] Resonant converters are a wide range of switching converters characterized by the presence of a resonant circuit playing an active role in determining the input-output power flow. Considering the most common implementations, in these converters, a full-bridge (or half bridge) consisting of four (or two) power switches (typically power Field Effect Transistors, FET, such as Metal-Oxide-Semiconductor Field-Effect Transistors, MOSFET), supplied by a direct voltage generates a voltage square wave that is applied to a resonant circuit tuned to a frequency close to the fundamental frequency of said square wave. Thereby, because of the selective features thereof, the resonant circuit mainly responds to the fundamental component and negligibly to the higher-order harmonics of the square wave.

[0003] As a result, the circulating power may be modulated by changing the frequency of the square wave, while holding the duty cycle constant at 50%. Moreover, depending on the resonant circuit configuration, the currents and/or voltages associated with the power flow have a sinusoidal or a piecewise sinusoidal shape.

[0004] These voltages are rectified and filtered so as to provide DC power to a load. In offline applications, to comply with safety regulations, the rectification and filtering system supplying the load is coupled often to the resonant circuit via a transformer providing the isolation between source and load, required by the above-mentioned regulations. As in all isolated network converters, also in this case a distinction is made between a primary side (as related to the primary winding of the transformer) connected to the input source and a secondary side (as related to the secondary winding(s) of the transformer) providing power to the load through the rectification and filtering system.

[0005] Presently, among the many types of resonant converters, the so-called LLC resonant converter is widely used, especially in the half bridge version thereof. The designation LLC comes from the resonant circuit employing two inductances/inductors (L) and a capacitor (C).

[0006] Considering the foregoing, various embodiments of the present disclosure provide a new driver circuit for two synchronous rectifier switches, which in particular deals with the switch-off condition for the synchronous rectifier switches.

[0007] According to one or more embodiments, one or more of the above technical benefits are achieved by a synchronous rectifier driver circuit having the distinctive elements set forth herein. Embodiments moreover concern a related integrated circuit, electronic resonant converter and method.

[0008] The claims form an integral part of the technical teaching of the description provided herein.

[0009] As mentioned before, various embodiments of the present disclosure relate to a synchronous rectifier driver circuit configured to drive a synchronous rectifier FET comprising a drain, a source and a gate terminal. In various embodiments, the synchronous rectifier driver circuit, e.g., in the form of an integrated circuit, comprises a first terminal configured to be connected to the source terminal of the synchronous rectifier FET, a second terminal configured to be connected to the drain terminal of the synchronous rectifier FET and a third terminal configured to be connected to the gate terminal of the synchronous rectifier FET.

[0010] In various embodiments, the synchronous rectifier driver circuit is configured to measure the voltage between the second terminal and the first terminal, and detect a switch-on instant where the measured voltage reaches a first threshold value and a switch-off instant where the measured voltage reaches a second threshold value.

[0011] In various embodiments, the synchronous rectifier driver circuit is configured to generate a drive signal between the third terminal and the first terminal as a function of the measured voltage by:

• • [0012] between a further instant and the switch-off instant, varying the drive signal as a function of the instantaneous value of the measured voltage; and
  • [0013] between the switch-off instant and the next switch-on instant, setting the drive signal to a second value.

[0014] In various embodiments, the synchronous rectifier driver circuit may be configured to also vary the drive signal as a function of the instantaneous value of the measured voltage between the switch-on instant and the further instant. Alternatively, the synchronous rectifier driver circuit may be configured to set the drive signal to a second value between the switch-on instant and the further instant. For example, the further instant may be determined by

• • [0015] determining an instant where the measured voltage reaches a peak value between the switch-on instant and the switch-off instant;
  • [0016] waiting a given time with respect to the switch-on instant; or
  • [0017] determining an instant where the measured voltage reaches a given threshold value.

[0018] For example, in various embodiments, the instant where the measured voltage reaches the peak value may be determined by determining the duration between a previous switch-on instant and a respective previous switch-off instant and estimating the further instant at half of this duration.

[0019] According to a first aspect, the synchronous rectifier driver circuit may be configured to vary the drive signal between the further instant and the switch-off instant by setting the drive signal to a voltage corresponding to the sum of a constant voltage and a voltage proportional with a given proportionality constant to the instantaneous value of the measured voltage.

[0020] In various embodiments, the synchronous rectifier driver circuit comprises a sample-and-hold circuit configured to store the peak value. In this case, the synchronous rectifier driver circuit may be configured to determine the second value as a function of the stored peak value. For example, the second value may correspond to the sum of a constant voltage and a voltage proportional with the given proportionality constant to the stored peak value.

[0021] For example, in various embodiments, the synchronous rectifier driver may comprise a fourth terminal and a variable current generator configured to generate a variable current applied to the fourth terminal, wherein the variable current is proportion to a voltage received at an input of the variable current generator. Accordingly, a control circuit may be configured to connect the input of the variable current generator to:

• • [0022] the stored peak value between the switch-on instant and the further instant,
  • [0023] the measured voltage between the further instant and the switch-off instant, or
  • [0024] the first terminal between the switch-off instant and the next switch-on instant.

[0025] As will be explained in greater detail in the following, in various embodiments, the voltage at the fourth terminal may be used to directly generate the drive signal for the gate terminal of the synchronous rectifier driver, e.g., via a voltage follower.

[0026] However, in various embodiments, the synchronous rectifier driver circuit may comprise also a fifth terminal, a constant current generator configured to generate a constant current applied to the fifth terminal, and a summation circuit configured to generate the drive signal by summing the voltage at the fourth terminal and the voltage at the fifth terminal.

[0027] According to a second aspect, the synchronous rectifier driver circuit may be configured to vary the drive signal between the further instant and the switch-off instant in order to directly regulate the measured voltage to a given (constant) reference value. For example, for this purpose, the synchronous rectifier driver circuit may comprise a regulator circuit configured to receive the measured voltage and the given reference value, and generate a regulation signal. Specifically, in various embodiments, the regulator circuit comprises or implements at least an Integral component. Accordingly, in this case, the drive signal may be determined (at least) between the further instant and the switch-off instant as a function of (or may correspond to) the regulation signal.

[0028] Various embodiments relate also to an electronic resonant converter comprising:

• • [0029] two input terminals for receiving an input voltage and two output terminals for providing an output voltage or output current;
  • [0030] a transformer comprising a primary winding and a first and a second secondary winding;
  • [0031] a switching stage connected via a resonant tank to the primary winding;
  • [0032] a first synchronous rectifier FET connected in series with the first secondary winding between the two output terminals;
  • [0033] a second synchronous rectifier FET connected in series with the second secondary winding between the two output terminals; and
  • [0034] two synchronous rectifier driver circuits as described herein.

[0044] In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

[0045] Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0046] The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

[0047] FIG. 1 shows an example of an LLC resonant converter 20. In general, an electronic converter 20 comprises:

• • [0048] a positive input terminal 200a and a negative input terminal 200b for receiving a DC input voltage Vin; and
  • [0049] a positive output terminal 202a and a negative output terminal 202b for providing a regulated (DC) output voltage Vout or output current Iout.

[0050] For example, the input voltage Vin may be provided by a DC voltage generator 10, such as a battery. However, the input voltage Vin may also be obtained from an AC voltage, e.g., by means of a rectifier circuit, such as a bridge rectifier, and an optional filter circuit, such as a capacitor. Conversely, the regulated output voltage Vout or output current Iout may be used to supply a load 30.

[0051] In the example considered, the electronic converter 20 comprises a half bridge comprising two electronic switches SW1 and SW2, such as FET, such as n-channel FET, e.g., NMOS, connected (e.g., directly) in series between the input terminals 200a and 200b, wherein the negative input terminal 200b usually represents a first ground GND1. For example, in the example considered, the drain terminal of the transistor SW1 is connected directly to the terminal 200a, the source terminal of the transistor SW1 is connected directly to the drain terminal of the transistor SW2 and the source terminal of the transistor SW2 is connected directly to the terminal 200b.

[0052] Accordingly, the half-bridge SW1, SW2 is supplied via the input voltage Vin and the intermediate node between the electronic switches SW1 and SW2 (e.g., the drain terminal of the transistor SW1) represents a switching node HB.

[0053] In the example considered, the switching node HB between the electronic switches SW1 and SW2 is connected to a (resonant) circuit block.

[0054] Specifically, in the example considered, this circuit comprises a transformer T comprising a primary winding T1 and a central tapped secondary winding comprising a first secondary winding T2a and a second secondary winding T2b connected in series.

[0055] In the example considered, the primary winding T1 of the transformer T is connected (e.g., directly) with a capacitor Cr and a first inductance Ls between the switching node HB and the negative terminal 200b. Moreover, a second inductance Lp is connected (e.g., directly) in parallel with the primary winding T1. Thus, in the example considered the capacitor Cr, the first inductance Ls and the second inductance Lp are connected in series (from which derives the naming LLC converter), and the inductance Lp is connected in parallel to the primary winding T1. For example, in FIG. 1, a first terminal of the capacitor Cr is connected (e.g., directly) to the switching node HB, a second terminal of the capacitor Cr is connected (e.g., directly) via the inductance Ls to a first terminal of the primary winding T1 and a second terminal of the primary winding T1 is connected (e.g., directly) to the terminal 200b.

[0056] In a real transformer T, anyway, the two windings T1 and T2 are not perfectly coupled, and a transformed T comprises also a leakage inductance and a magnetizing inductance. Substantially, such a leakage inductance may be modelled via an inductance connected in series with the primary winding T1. Conversely, the magnetizing inductance of the transform T (used to model the magnetic flux) may be modelled with an inductance connected in parallel with the primary winding T1. Thus, the inductance Ls may consist in the leakage inductance of the transformer T, may be implemented with an inductor connected in series with the primary winding T1, or may result from both the leakage inductance of the transformer T and such an inductor. Similarly, the inductance Lp may consist in the magnetizing inductance of the transformer T, may be implemented with an inductor connected in parallel with the primary winding T1, or may result from both the magnetizing inductance of the transformer T and such an inductor. Thus, in general, the inductances Lp an Ls and the transformer T may be integrated in a single component.

[0057] As mentioned before, in FIG. 1 is used a center-tap arrangement on the secondary side, i.e., the secondary winding comprises a first, a second and a center-tap terminal. Specifically, in the example considered, the center-tap terminal is connected (e.g., directly) to one of the output terminals 202a/202b, and the first and second terminal of the secondary winding T2 are connected (e.g., directly) via a respective diode D2 and D1 to the other output terminal 202a/202b. For example, in the example considered, the center-tap terminal is connected (e.g., directly) to the output terminals 202b, and the first and second terminal of the secondary winding T2 are connected (e.g., directly) to the anodes of respective diodes D1 and D2 and the cathodes of the diodes D1 and D2 are connected (e.g., directly) to the terminal 202a. Accordingly, due to the rectification function of the diodes D1 and D2, the terminal 202a corresponds to the positive output terminal and the terminal 202b corresponds to the negative output terminal, which usually corresponds to a second ground GND2. However, by inverting the orientation of the diodes D1 and D2, the terminal 202b would correspond to the positive output terminal.

[0058] Often, the electronic converter 20 may also comprise an output filter connected between the rectifier and the output terminals 202a and 202b. For example, in FIG. 1 a capacitor Cout is connected (e.g., directly) between the output terminals 202a and 202b.

[0059] In the example considered, the control terminals, e.g., the gate terminals of respective FETs, of the electronic switches SW1 and SW2 are driven via a driver circuit 210, which is configured to generate respective drive signals HSGD and LSGD for the electronic switches SW1 and SW2.

[0060] As mentioned before, the driver circuit 210 drives the switches SW1 and SW2 usually in order to apply a square wave at a frequency close to that of the resonant circuit to the switching node HB. In this way the resonant tank (Lp, Ls and Cr) behaves as a tuned filter and the current is formed by the single fundamental harmonic of the Fourier series development therefore practically sinusoidal.

[0061] More specifically, the driver circuit 210 is often configured to generate the drive signals HSGD and LSGD in order to repeat the following four phases for each switching cycle:

• • [0062] during a first time-interval, closing the first electronic switch SW1 and opening the second electronic switch SW2, whereby the switching node HB is connected to the positive input node 200a, i.e., the input voltage Vin;
  • [0063] during a second time-interval, opening both the first and the second electronic switch SW1/SW2;
  • [0064] during a third time-interval, opening the first electronic switch SW1 and closing the second electronic switch SW2, whereby the switching node HB is connected to the negative input node 200a, e.g., ground GND1; and
  • [0065] during a fourth time-interval, opening both the first and the second electronic switch SW1/SW2.

[0066] The second and fourth time-interval may be useful in order to use the resonances of resonant circuit in order to achieve soft switching. For example, the LLC topology shown in FIG. 1 permits a ZVS (Zero Voltage Switching) of the switches SW1 and SW2 on the primary side and a ZCS (Zero Current Switching) of the diodes D1 and D2 on the secondary side, which thus permits to operate the converter at high switching frequencies with high efficiency.

[0067] Thus, in the example considered, the electronic converter provides via the output terminals 202a and 202b a voltage Vout and a current Iout. Often a closed-loop (usually implemented with a negative-feedback control system) keeps thus either the output voltage Vout or the output current Iout of the converter constant upon changing the operating conditions, e.g., variation of the input voltage Vin and/or the output load 30. As mentioned before, the regulation of the converter output voltage Vout or the output current Iout is achieved by changing the switching frequency of the square waveform at the switching node HB/the input of the resonant tank.

[0068] For example, FIG. 2 shows an example of a control circuit for a generic half-bridge resonant converter 20.

[0069] As mentioned before, a half-bridge resonant converter 20 comprises a half-bridge comprising two electronic switches connected in series between the input terminals 200a and 200b of the electronic converter 20. Moreover, the converter 20 comprises a circuit 204 comprising a resonant tank (e.g., capacitor Cr, inductances Ls and Lp, and transformer T), a rectifier circuit (e.g., diodes Da and Db) and an optional filter circuit (e.g., capacitor Cout). Specifically, the circuit 204 is connected on one side to the switching node HB (between the electronic switches SW1 and SW2) and the negative input terminal 200b (or alternatively the positive input terminal 200a) in order to receive a substantially square wave signal, and on the other side to the output terminals 202a and 202b in order to provide an output voltage Vout or output current Iout.

[0070] In order to implement a closed loop control, the converter 20 comprises a sensor 212 configured to monitor the output voltage Vout (for a voltage source) or output current Iout (for a current source). For example, in FIG. 2, the converter 20 is configured to provide a regulated voltage. Accordingly, the sensor 212 may be a voltage sensor configured to monitor the output voltage Vout. For example, in FIG. 2 is used a voltage divider comprising two resistors R1 and R2 connected between the terminals 202a and 202b, whereby the voltage sensor provides a measurement signal proportional to the output voltage Vout.

[0071] The measurement signal (indicative of the current Iout or voltage Vout) provided by the sensor 212 is provided to an error amplifier configured to generate an error signal Er. For example, the error amplifier may compare the measurement signal with a reference signal, such as a reference voltage Vref, and generate an error signal Er indicative of the difference between the measurement signal and the reference voltage Vref.

[0072] In the example considered, the error signal Er is then provided to the driver circuit 210 in order to modify a given control quantity x, wherein the energy transferred during each switching cycle substantially depends on the control quantity x (e.g., the switching frequency of the switches SW1 and SW2) Generally, the error signal Er may be provided directly to the driver circuit 210 or indirectly, e.g., via an optocoupler 218 (which is usually used in case of isolated electronic converters). Moreover, the error signal Er or a signal indicative of (e.g., proportional to) the error signal Er (e.g., in case an optocoupler 218 is also used) provided to the driver circuit 210 may be any suitable control signal, such as a voltage Vc or a current Ic.

[0073] Often, the error amplifier is implemented with an operational amplifier 214 receiving at input the measurement signal (e.g., at the inverting/negative input) and the reference signal (e.g., at the non-inverting/positive input). Moreover, the operation amplifier 214 has associated a feedback network 216 connected between the output of the operation amplifier and one of the input terminals (usually the inverting input terminal). For example, the feedback network 216 may comprise components for implementing the error amplifier as a regulator having a proportional (P) component (e.g., via resistor) and/or an integrative (I) component (e.g., via a capacitor). Thus, in general, the feedback network 216 implements a filter of the error amplifier. For example, such a filter 216 may be useful in order to select an appropriate frequency response of the error amplifier, e.g., in order to ensure:

• • [0074] a stable control loop (i.e., that, upon disturbances of the operating conditions of the converter, once the transient caused by the disturbance has subsided, the output parameter Vout/Iout tends to recover a constant steady state;
  • [0075] a good regulation (i.e., the new constant value recovered by the output parameter Vout/Iout following a disturbance is very close to that preceding the perturbation); and
  • [0076] a good dynamic performance (i.e., during the transient following a disturbance, the output parameter Vout/Iout does not excessively deviate from the desired value and the transient itself is short).

[0077] As shown in FIG. 3, in order to improve the efficiency of resonant converters, the diodes D1 and D2 on the secondary side (FIG. 1) are often replaced with synchronous rectifier (SR) electronic switches SR1 and SR2, which are controlled by a synchronous rectifier driver 222 to emulate an ideal diode.

[0078] In order to simplify a driving of the synchronous rectifier switches SR1 and SR2, one of the terminals of each synchronous rectifier switches SR1 and SR2 is usually connected to ground (e.g., GND2 for an isolated converter.

[0079] For example, in FIG. 3, the synchronous rectifier electronic switches are implemented with n-channel FET, such as MOSFET.

[0080] Accordingly, in FIG. 3, also remaining connection at the secondary side has changed, i.e.:

• • [0081] center-tap terminal of the transformer T is connected (e.g., directly) to the (positive) output terminal (202a);
  • [0082] the first terminal of the secondary winding T2 (terminal of the winding T2a) is connected (e.g., directly) to a first (drain) terminal of the synchronous rectifier FET SR2, and a second (source) terminal of the synchronous rectifier switch SR2 is connected (e.g., directly) to the (negative) terminal 202b, which represents a ground GND2; and
  • [0083] the second terminal of the secondary winding T2 (terminal of the winding T2b) is connected (e.g., directly) to a first (drain) terminal of the synchronous rectifier FET SR1, and a second (source) terminal of the synchronous rectifier switch SR1 is connected (e.g., directly) to the (negative) terminal 202b.

[0084] Again, a capacitor Cout may be connected (e.g., directly) between the output terminals 202a and 202b.

[0085] FIG. 3 shows also that the capacitor Cr may not be connected between the primary winding T1 and the switching node HB, but between the primary winding T1 and the terminal 200b, e.g., ground GND1.

[0086] The core function of synchronous rectifier driver 222 is to switch on each synchronous rectifier switch SR1 and SR2 whenever the corresponding transformer half winding T2a or T2b starts conducting.

[0087] Specifically, when using FETs, each of the synchronous rectifier switches SR1 and SR2 has also associated a body diode. In general, each synchronous rectifier switches SR1 and SR2 may thus have associated (in particular connected in parallel) a diode. Accordingly, in this case, the synchronous rectifier driver 222 should switch-on a given synchronous rectifier switch SR1 and SR2 when the respective diode starts conducting and t switch-off the synchronous rectifier switch when the flowing current approaches zero.

[0088] In order to achieve high efficiency, the rectifier driver 222 may also control the channel conduction time, trying to minimize the diode conduction time.

[0089] Several techniques have been proposed to control synchronous rectifier switches SR1 and SR2 for (e.g., LLC) resonant converters. The solutions can be grouped in two types: voltage driven and current driven control. The latter group uses the currents I_SR1 and I_SR2 flowing through the synchronous rectifier switches SR1 and SR2. Generally, the currents I_SR1 and I_SR2 may be measured directly via one or more current sensors connected in series with the synchronous rectifier switches SR1 and SR2, or may be estimated by measuring the current flowing through the primary side via a current transformer. Both cases can reach a high accuracy at the expense of extra components; and requires a large size current transformer impacting efficiency.

[0090] The voltage driven solutions are based on the measurement of the voltages DVS1 and DVS2 between the terminals of the current path of the synchronous rectifier switches SR1 and SR2, e.g., between the drain and source terminals of respective FETs.

[0091] For example, FIG. 4 shows possible waveforms of the currents I_SR1 and I_SR2 flowing through the synchronous rectifier switches SR1 and SR2 and the voltages DVS1 and DVS2 at the synchronous rectifier switches SR1 and SR2 and the drive signals GD1 and GD2 for the synchronous rectifier switches SR1 and SR2.

[0092] Moreover, FIG. 5 shows a detailed view of the current I_SR1 and I_SR2 flowing through one of the synchronous rectifier switches SR1 and SR2 and the respective voltage DVS and drive signal GD.

[0093] The waveforms show that the secondary winding T2 provides substantially a sine wave, wherein during a first half-period should be closed the synchronous rectifier switch SR1 (with SR2 opened) and during a second half-period should be closed the synchronous rectifier switch SR2 (with SR1 opened).

[0094] Each of the half-periods may thus be divided into three zones (a), (b) and (c).

[0095] During the first zone (a), i.e., before the synchronous rectifier switch is turned on (i.e., with the respective signal GD being low), the voltage DVS decreases, becomes negative and the respective diode starts conducting at a given threshold V_{TH_ON} (more or less at −0.7 V, corresponding to the forward voltage of the diode).

[0096] Once the synchronous rectifier switch SR is switched on at an instant t₁, the following zone (b) starts. During, this zone (b) the voltage DVS drops to:

DVS=R_DSON·I_SR  (1)

where R_DSON corresponds to the switch-on resistance of the synchronous rectifier switch SR. Accordingly, the voltage DVS has a sinusoidal behavior during this zone (and considering the direction of the current I_RS and voltage DVS, opposed to the current I_RS).

[0097] Thus, during the zone (b), the voltage decreases and then increases again. Accordingly, when the current I_RS approaches again zero, the synchronous rectifier switch SR may be switched off when the voltage DVS reaches a given second threshold V_{TH_OFF}.

[0098] Once, the synchronous rectifier switch SR is switched off (and assuming that the winding is still conducting), the voltage DVS drops again to the forward voltage of the diode (approximately −0.7 V). The voltage DVS then increases until the voltage at the transformer winding T2 reverses.

[0099] Accordingly, due to the higher voltage drop caused by the forward biasing of the diode turn-on (700 mV) compared to resistive voltage drop (usually in the range of 10-20 mV), power losses are much higher during phases (a) and (c) than during phase (b).

[0100] FIG. 6, shows again the LLC converter schematic, wherein the voltage V_P at the primary winding T1 and the voltages V_Sa and V_Sb at the secondary windings T2a and T2b are shown.

[0101] Generally, due to the coupling of the transformer, the voltages correspond to V_Sa and V_Sb, i.e., V_Sa=V_Sb=V_S. Specifically, assuming a primary winding with N_P windings and secondary windings with Ns windings, the voltage V_S of each switching cycle may be determined as follows:

$\begin{array}{cc}{V}_s=V_p·\frac{N_s}{N_p}& \left(2\right)\end{array}$

[0102] Moreover, due to the connection the following relation applies:

−V_Sa+DVS2=V_Sb+DVS1.  (3)

[0103] Thus, in steady state condition, i.e., when the capacitor C_OUT is charged to the requested output voltage V_OUT, the maximum values for the voltages DVS1 and DVS2 are alternately:

• • [0104] during a first switching semi-period, the voltage drop DVS1 is neglectable and the voltage DVS2 corresponds to 2·V_out; and
  • [0105] during a second switching semi-period, the voltage drop DVS2 is neglectable and the voltage DVS1 corresponds to 2·V_out.

[0106] Thus, this maximum value has to be taken into account in order to select the correct electronic switches for the synchronous rectifier switches SR1 and SR2.

[0107] Moreover, indeed, often spikes occur during the switching activity of the electronic converter. For example, such spikes are often generated by a current inversion in the previous cycle, and when the LLC converter works above resonance. These spikes imply, e.g., that a higher voltage class SR MOSFET with lower performance and higher cost has to be used.

[0108] In this respect, example solutions aimed to limit the voltage spikes by avoiding (or at least reducing) current inversions, which is however not always possible.

[0109] In FIGS. 7 to 17 described below, parts, elements or components that have already been described with reference to FIGS. 1 to 6 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

[0110] As explained in the foregoing, various embodiments of the present description concern solutions for determining the switch-off instant for switching off a synchronous rectifier switch.

[0111] As described with respect to equation (1), during each zone/time interval (b), the respective voltage DVS1 and DVS2 measured by the synchronous rectifier controller 222 is proportional to the switch on resistance R_DSON of the respective synchronous rectifier switch SR1/SR2.

[0112] However, the inventors have observed, and as also shown in FIG. 7, indeed the electronic circuit comprises also parasitic inductances, which may be modelled with an inductance L_SR connected in series (with the current path of) the synchronous rectifier switch SR1/SR2, wherein the inductance L_SR may be calculated as:

L_RS=L_DS+L_TRACE.  (4)

where L_DS represents the inductance of the synchronous rectifier switch SR1/SR2 between the terminals (of the current path), e.g., between the drain and source terminals of a respective FET, and L_TRACE represents an additional inductance of the traces of the printed circuit board for connecting the synchronous rectifier switch SR1/SR2 to the synchronous rectifier controller 222.

[0113] Thus, the synchronous rectifier controller 222 indeed monitors a voltage DVS′, which does not correspond exactly to the voltage DVS at the terminals of the synchronous rectifier switch SR1/SR2, but:

$\begin{array}{cc}{\mathrm{DVS}}^{\prime }=R_{\mathrm{DSON}}·I_{\mathrm{SR}}+L_{\mathrm{RS}}·\frac{{\delta I}_{\mathrm{SR}}}{\delta t}.& \left(5\right)\end{array}$

[0114] The inventors have observed, and as also shown in FIG. 8, this inductance L_SR introduces an anticipative effect insofar as the synchronous rectifier controller 222 will determine, with respect to the start of the zone (b) (i.e., with respect to the rising edge of the signal GD), that the measured voltage DVS' reaches the switch-off threshold V_{TH_OFF}(see also FIG. 5) after a time ΔT′ and not after the expected time ΔT when the voltage DVS indeed reaches the switch-off threshold V_{TH_OFF}, with ΔT=ΔT′+T_LSRAY, i.e., the zero crossing of the voltage DVS′ occurs before the zero crossing of the voltage DVS.

[0115] In a first approximation, this anticipative effect may be assumed to be constant, i.e., T_LSRAY may be assumed to be constant. However, as will be described in greater detail in the following, this approximation may not be accurate enough.

[0116] In the following will now be discussed a possible approximation of this anticipative effect.

[0117] Specifically, in the following will be assumed that the current I_S=I_RS1+I_RS2 at the secondary side has a substantially sinusoidal shape during (at least the last part of) the switching cycle, i.e., at least at the end of the zone/interval (b), i.e.:

I_SR(t)=I_PK·sin(ω_SW·t)  (6)

where I_PK represents the amplitude of the oscillation. For example, as described in the foregoing, this is often the case for (e.g., LLC) resonant converters, in particular when operating in the vicinity of the fundamental resonant frequency of the resonant tank of the converter.

[0118] In this condition, the measured voltage DVS′ may be written (at least at the end of the zone (b) as:

DVS′=R_DSON·I_PK·sin(ω_SW·t)+L_RS·ω_SW·I_PK·cos(ω_SW·t)  (7)

The inventors have observed that this expression may be rewritten by splitting the time component and the phase shift component:

DVS′=K·sin(ω_SW·t−φ)=K·sin(ω_SW·(t−φ/ω_SW))  (8)

where the time T_LRS represents the L_RS anticipation:

T_LRS=φ/ω_SW  (9)

[0119] Equation (8) may further be reformulated:

DVS′=K·sin(ω_SW−t)·cos(φ)+K·cos(ω_SW−t)·sin(φ)  (10)

[0120] Finally, by comparing equation (7) with equation (10), it is possible to observe that:

K·sin(φ)=L_RS·ω_SW·I_PK

K·cos(φ)=R_DSON·I_PK

which permits to obtain the phase shift expression:

$\begin{array}{cc}\phi =\arctan \left(\frac{L_{\mathrm{RS}}}{R_{\mathrm{DSON}}}{\omega }_{\mathrm{SW}}\right)& \left(11\right)\end{array}$

[0121] Thus, equation (9) may be reformulated as follows:

$\begin{array}{cc}{T}_{\mathrm{LRS}}=\frac{\phi }{{\omega }_{\mathrm{SW}}}=\frac{1}{{\omega }_{\mathrm{SW}}}\arctan \left(\frac{L_{\mathrm{RS}}}{R_{\mathrm{DSON}}}{\omega }_{\mathrm{SW}}\right)& \left(12\right)\end{array}$

[0122] Assuming that L_RS/R_DSON is usually significantly smaller than 1/ω_SR and assuming that the anticipation time T_LRS is constant, equation (12) may be approximated:

$\begin{array}{cc}{T^{\prime }}_{\mathrm{LRS}}\approx \frac{L_{\mathrm{RS}}}{R_{\mathrm{DSON}}}& \left(13\right)\end{array}$

[0123] FIG. 9 shows an example of the anticipation time T_LRS as a function of the switching frequency f_SW, for the exemplary case L_SR=4 nH and R_DSON=4 mΩ. Specifically, line 100 shows the behavior with the approximation of equation (13), and line 102 shows the behavior for equation (12), which thus takes also into account the switching frequency f_SW, with ω_SR=2πf_SW.

[0124] Thus, generally, an error ΔT_LSR exists for each frequency between the real value (line 102) and the approximation (line 100).

[0125] FIG. 10 shows in this respect examples of the error T_LSR for different values T′_LSR=L_RS/R_DSON. For example, lines 104, 106, 108 and 110 shows the behavior for T′_LSR=250 ns, 1 s, 2 s and 4 s, respectively.

[0126] FIG. 10 also highlights that the simple approximation may lead to very high errors when the value T′_LSR increases.

[0127] For example, after a high to low load current transient, the primary loop of the LLC converter (see e.g., FIG. 2) may increases the frequency to compensate the output voltage V_out regulation. This frequency variation may result in a variation of the switching frequency in the order of 10%-15% causing a variation of the value ΔT_LSR.

[0128] The inventors have observed that this variable anticipative effect should be taken into account when driving the synchronous rectifier switches SR1 and SR2.

[0129] In the following will now be described embodiments of a new driving method implemented within a synchronous rectifier controller/driver circuit 222a configured to drive two synchronous rectifier switches SR1 and SR2, such as the synchronous rectifier switches SR1 and SR2 of a (e.g., LLC) resonant converter as described with respect to FIGS. 1 to 6.

[0130] Specifically, in various embodiments, the synchronous rectifier driver circuit 222a is configured to drive the synchronous rectifier switches SR1 and SR2 by taking into account also the load current of the electronic (e.g., LLC) converter, i.e., the current i_out provided to a load 30 (see FIG. 1).

[0131] Generally, also other solutions exist, which already take into the load current. For example, reference can be made to document US 2017/0085188 A1, which discloses a driver circuit for two synchronous rectifier switches SR1 and SR2. Substantially, this document describes a gate driving strategy for two synchronous rectifier MOSFET, which optimizes the conversion efficiency in all load conditions applying a constant voltage along all the conduction window.

[0132] Conversely, various embodiments of the present disclosure propose a new gate driving strategy, identified in the following as “DVS Shaping Gate Driving” (abbreviated as DVS SGD), which tries to reduce the current inversion as much as possible.

[0133] Specifically, in various embodiments, the synchronous rectifier driver circuit 222a is configured to change the drive voltage of the synchronous rectifier switches SR1 and SR2, e.g., the gate voltage of respective (e.g., n-channel) FETs, as a function of the instantaneous value of the voltage DVS rather than the average value of the voltage DVS as described in document US 2017/0085188 A1.

[0134] Specifically, by varying the amplitude of a drive signal GD (i.e., GD1 or GD2), the synchronous rectifier driver circuit 222a is able to change the switch-on resistance R_DSON of the respective synchronous rectifier FET SR1 or SR2. Specifically, as shown in equations (12) and (13), the anticipation time T_LRS decreases, when the switch-on resistance R_DSON increases.

[0135] Thus, in various embodiments, the synchronous rectifier driver circuit 222a is configured to, when a given synchronous rectifier FET SR1 or SR2 is switched on, vary the drive signal GD, such that the switch-on resistance R_DSON of the respective synchronous rectifier FET SR1 or SR2 increases at the end of the switch-on pulse, i.e., at the end of the interval/zone (b) (see also FIG. 5).

[0136] Specifically, as shown in FIG. 11A, in various embodiments, the drive the synchronous rectifier driver circuit 222a may be configured to vary the drive signal GD directly as a function of the voltage DVS (or more precisely the measure voltage DVS′):

GD=V_x+K·|DVS′|  (14)

The above equation may be reformulated according to equation (5):

$\begin{array}{cc}\mathrm{GD}=V_x+K·\left[R_{\mathrm{DSON}}·I_{\mathrm{SR}}+L_{\mathrm{RS}}·\frac{{\delta I}_{\mathrm{SR}}}{\delta t}\right].& \left(15\right)\end{array}$

[0137] The inventors have observed that the resistance R_DSON should be varied in order to obtain a voltage GD that tends towards the (constant offset) value V_x when the current I_SR approaches the zero crossing.

[0138] The effect of the inductance L_SR helps to reduce the voltage GD, thereby increasing the resistance R_DSON, when the current I_SR approaches zero. This permits to avoid (or at least reduce) current inversions, but at the expense of a small reduction of conversion efficiency.

[0139] In order to provide a design criterion independent from the value L_SR, its value will be hereinafter supposed to be zero, i.e.:

GD=V_x+K·R_DSON·I_SR  (16)

[0140] This assumption does not lack of generality, but actually helps to improve the immunity with respect to parasitic effects, which would lead to an anticipated switch of the synchronous rectifier FET. In fact, the inductance L_SR only leads to a lower value GD than the one shown in equation (16), thereby increasing the actual switch-on resistance R_DSON and voltage |DVS| for a given current I_SR.

[0141] FIG. 11A shows an embodiment of the operation of the synchronous rectifier driver circuit 222a for each of the synchronous rectifier FETs SR1 or SR2.

[0142] In general, due to the switching activity at the primary winding T1, the voltage DVS at a given synchronous rectifier FET SR1 or SR2 will become negative at an instant t₀.

[0143] In various embodiments, during this phase (a) the synchronous rectifier driver circuit 222a is configured to compare the voltage DVS with a threshold voltage V_{TH_ON}. Considering the direction of the voltage DVS, this threshold voltage has a negative value. For example, for this purpose, the synchronous rectifier driver circuit 222a may comprise an analog comparator.

[0144] In the embodiment considered, when the voltage DVS reaches the threshold voltage V_{TH_ON} at the instant t₁ the synchronous rectifier driver circuit 222a generates the drive signal GD in order to close the synchronous rectifier FET SR1 or SR2.

[0145] As mentioned before, the disclosed control method is mainly used to determine the switch-off instant t₂.

[0146] In general, the synchronous rectifier driver circuit 222 may use equation (14) for the complete duration between the instants t₁ and t₂. However, in order to reduce switching losses, the synchronous rectifier driver circuit 222 may use a portion during phase (b), wherein the synchronous rectifier driver circuit 222 uses a constant or predetermined value for the drive signal GD.

[0147] For example, in various embodiments, the synchronous rectifier driver circuit 222 is configured to use:

• • [0148] a first mode M1, wherein the synchronous rectifier driver circuit 222 sets the drive signal GD to a given (constant or predetermined) value; and
  • [0149] a second mode, wherein the synchronous rectifier driver circuit 222 varies the drive signal GD as a function of the signal DVS.

[0150] Specifically, in various embodiments, the synchronous rectifier driver circuit 222 uses mode M2 between an instant t₃ during phase (b) and the instant t₂. Conversely, the synchronous rectifier driver circuit 222 may be configured to use during the remaining initial portion of phase (b) (between the instants t₁ and t₃):

• • [0151] only mode M1 (between the instants t₁ and t₃), or
  • [0152] first mode M2 (between the instant t₁ and an instant t₄) and then mode M1 (between the instants t₄ and t₃).

[0153] For example, in various embodiments, the synchronous rectifier driver circuit 222 may be configured to determine the instant t₃ by:

• • [0154] adding a constant or predetermined time interval to the instant t₁; or
  • [0155] determining when the absolute value of the voltage DVS decreases and reaches a given threshold value.

[0156] Similarly, the synchronous rectifier driver circuit 222 may be configured to determine the instant t₄ by:

• • [0157] adding a constant or predetermined time interval to the instant t₁; or
  • [0158] determining when the absolute value of the voltage DVS increases and reaches the given threshold value.

[0159] For example, as shown in FIG. 11B, between the instants t₁ and t₂ the current I_SR will have a sinusoidal or partially sinusoidal behavior and will reach a peak value at an instant t₃. Similarly, the measured voltage DVS will reach a peak value DVS_PK at a given instant.

[0160] Specifically, in the embodiments considered, the synchronous rectifier driver circuit 222a uses this instant for the instant t₃. Accordingly, in various embodiments, the synchronous rectifier driver circuit 222a is configured to determine or estimate this instant t₃. For example, the synchronous rectifier driver circuit 222a may be configured to:

• • [0161] determine the instant t₃ by detecting the instant when the signal DVS reaches its peak value DVS_PK; or
  • [0162] determine the middle of a given switching half-period and use this instant for the instant t₃; or
  • [0163] determine the instant t₃ by detecting an instant when the signal DVS reaches a given (preferably fixed) threshold voltage, such as −40 mV.

[0164] For example, the synchronous rectifier driver circuit 222a may determine the middle of a given switching half-period by:

• • [0165] receiving a trigger signal from the circuit 210;
  • [0166] monitoring the drive signals for the switches SW1 and SW2; or
  • [0167] determine the duration between the switch-on instant t₁ and the switch-off instant t₂ and calculate the instant t₃(k) for a given cycle k as:

t₃(k)=t₁(k)+(t₂(k−1)−t₁(k−1))/2.

[0168] Specifically, in the embodiment considered, the synchronous rectifier driver circuit 222a is configured to generate the drive signal GD with two modes:

• • [0169] between the switch-on instant t₁ and the detected/estimated instant t₃ with the first mode M1, and
  • [0170] between the detected/estimated instant t₃ and the switch-off instant t₂ with the second mode M2.

[0171] Specifically, as mentioned before, in various embodiments, the synchronous rectifier driver circuit 222a sets during the first mode M1 the drive signal GD to a given constant voltage, such 3 V or in general a voltage being greater than the switch-off threshold V_{TH_OFF} of the synchronous rectifier FET SR1 or SR2.

[0172] Specifically, in various embodiments, the synchronous rectifier driver circuit 222a sets during the first mode M1 the drive signal GD to:

GD=V_x+K·|DVS′_PK|

[0173] In various embodiments, the value DVS′_PK may correspond to one of:

• • [0174] the peak value DVS_PK of a previous switching cycle, or a filtered version thereof, such as the average value of the peak value DVS_PK for a plurality of switching cycles; or
  • [0175] a sampled version of the signal DVS at the instant t₃ of a previous switching cycle, or a filtered version thereof, such as the average value of the value DVS(t₃) for a plurality of switching cycles.

[0176] Conversely, during the second mode M2, the synchronous rectifier driver circuit 222a varies the signal GD as shown in equation (15).

[0177] The above operation is also shown in FIG. 11B, wherein:

• • [0178] the voltage GD is constant between the switch-on instant t₁ and the detected/estimated instant t₃,
  • [0179] the voltage GD then decreases proportionally with the voltage DVS until the voltage DVS reaches the threshold voltage V_TH of the synchronous rectifier FET SR1 or SR2 at the instant t₂ and the synchronous rectifier FET SR1 or SR2 is switched off.

[0180] FIG. 11B also shows that the switch-on resistance RDS_ON of the synchronous rectifier FET SR1 or SR remains substantially constant between the switch-on instant t₁ and an instant t₄ and then increases significantly near the switch-off instant t₂.

[0181] As mentioned before, in various embodiments, the synchronous rectifier driver circuit 222a sets the signal GD to zero after the instant t₂ where the voltage DVS reaches the threshold VTH_OFF. In order to deal also with the turn-off phase before the current I_SR becomes positive, equation (14) may be modified to include a term A V:

GD=V_x−ΔV+K·|DVS′|.  (17)

[0182] Thus, in various embodiments, three variables V_x, K and ΔV have to be selected. For example, in various embodiments, a series of design criteria are taken into account.

[0183] Generally, the value of the switch-on resistance R_DSON has to be increased when the current I_SR is approaching the zero crossing. Thus, essentially, when I_SR approaches zero (I_SR→0), the voltage GD should correspond to a given value V_TH, which is sufficient to switch the synchronous rectifier FET on with a high R_SDSON, i.e.:

GD=V_TH=x.  (18)

This condition should be satisfied also in the worst conditions, when the threshold voltage V_TH of the FET has it minimum value V_TH,min. For example, the minimum value V_TH,min has to take into account temperature drift and technological spreads, i.e.:

GD=V_TH,min=V_x.  (19)

[0184] Moreover, in order to guarantee a proper immunity from parasitic effects when GD=V_TH,min, the amplitude of the voltage DVS (i.e., |DVS|) should not be smaller than a given minimum value DVS_sat, i.e., in the worst case:

GD=V_TH,min−ΔV+K·|DVS_sat|.  (20)

Thus, by combining equations (18) and (20):

ΔV=K·|DVS_sat|.  (21)

[0185] The inventors have observed that the value DVS_sat should be chosen as a trade-off between noise immunity and circuitry speed. A higher value DVS_sat offers better immunity to noise (less anticipated turn-offs) and it requires a lower change rate capability for the signal GD.

[0186] Moreover, the signal GD should have its maximum value GD_max when the voltage |DVS| becomes higher than a ratio α of a given maximum value |DVS_max| in order to maximize the converter efficiency. Usually, the maximum value GD_max depends on the supply voltage VCC of the synchronous rectifier driver circuit 222a and possible voltage drops V_DROP used to generate the signal GD, i.e., GD_max=VCC−V_DROP.

[0187] In various embodiments, the value DVS_max is determined taking into account the switch-on resistance R_DSON and the maximum power supply.

[0188] For example, based on equations (17), (18) and (20):

GD_max=V_TH,min−ΔV+K·|α·DVS_max|  (22)

GD_max=V_TH,min−K·|DVS_sat|+K·|α·DVS_max|  (23)

GD_max=V_TH,min+K·(|α·DVS_max|−|DVS_sat|)  (24)

[0189] Thus, the parameter K can be calculated as:

$\begin{array}{cc}K=\frac{{\mathrm{GD}}_{\max }-V_{\mathrm{TH},\min }}{\alpha ·{\mathrm{DVS}}_{\max }-{\mathrm{DVS}}_{\mathrm{sat}}}& \left(25\right)\end{array}$

[0190] Summarizing the above equations, in various embodiments, the parameters V_x, K and ΔV are selected as follows:

V_x=V_TH,min

$\begin{array}{cc}K=\frac{{\mathrm{GD}}_{\max }-V_{\mathrm{TH},\min }}{\alpha ·{\mathrm{DVS}}_{\max }-{\mathrm{DVS}}_{\mathrm{sat}}}\mathrm{\Delta V}=K·{\mathrm{DVS}}_{\mathrm{sat}}& \left(26\right)\end{array}$

[0191] For example, assuming synchronous rectifier MOSFETs SR1 and SR2 being IPP084N06L4 transistors, these transistors have a switch-on resistance R_DSON of 8.1 mΩ and a typical threshold value V_{TH_TYP} of 2.7 V having a spread ΔV_{spread_from_DS} of 0.5 V. Thus, the minimum threshold value V_TH,min may be calculated as 2.7 V-0.5 V=2.2 V (V_{TH_TYP}−ΔV_{spread_from_DS}).

[0192] Moreover, assuming a supply voltage VCC of 12 V and a voltage drop V_DROP of 1 V, the maximum drive voltage is GD_max is 11 V.

[0193] Finally, by selecting |DVS_sat| as 4 mV, |DVS_max| as 100 mV and α as 0.5, the parameters may be calculated according to equation (26): V_x=2.2 V K=191 and ΔV=764 mV.

[0194] As shown in the foregoing, most of the used parameters depend on the application, i.e., the operation parameters of the electronic converter, such as the supply voltage VCC, the voltage-drop V_DROP in the synchronous rectifier driver circuit 222a, and also the parameters |DVS_sat| and |DVS_max| and may be fixed. Thus, in various embodiments, the driver circuit 222a is configured to permit a setting/programming of the minimum threshold value V_TH,min, for example in order to permit a use of different synchronous rectifier FETs.

[0195] In fact, assuming that the transistor has its maximum threshold value (V_{TH_TYP}+ΔV_{spread_from_DS}) of 3.2 V, and the above parameters V_x, K and ΔV, the driver circuit would operate with a minimum value |DVS_sat| of 9.2 mV (and the maximum value GD_max remains unchanged), which is still acceptable for a proper FET turn-off and conversion efficiency.

[0196] Thus, as mentioned before, in various embodiments, the driver circuit 222a is configured to permit a setting of the minimum threshold value V_TH,min of at least one (and preferably both) the synchronous rectifier switch SR1 and SR2.

[0197] Embodiments of analog solutions are shown in FIGS. 12, 13 and 14. The selection of one of the embodiments may depend, e.g., on the number of pins to be used by the package of the synchronous rectifier driver 222a and on the minimum for the parameter V_TH,min to be settable.

[0198] Generally, in the embodiments shown, the synchronous rectifier driver circuit 222a is configured to generate the signal GD_CTRL indicative of (e.g., proportional to or corresponding to) the amplitude of the signal GD to be applied to the gate terminal of a synchronous rectifier switch (e.g., SR1) as a function of the voltage DVS (or more precisely the measure voltage DVS′) between the drain and source terminal of the synchronous rectifier switch (e.g., SR1). Accordingly, when using a synchronous rectifier driver circuit 222a being integrated in an integrated circuit, the integrated circuit may comprise:

• • [0199] a terminal 2232 configured to be connected to a ground, such as the ground GND2 shown in FIG. 3;
  • [0200] a terminal 2234 configured to be connected to a supply voltage VCC;
  • [0201] a terminal 2226 configured to be connected to the drain terminal of the synchronous rectifier switch, thereby receiving the voltage DVS insofar as the source terminal of the synchronous rectifier switch is connected to ground, i.e., the terminal 2232; and
  • [0202] a terminal (see also FIG. 3) configured to be connected to the gate terminal of the synchronous rectifier switch, whereby the signal GD is applied to this terminal.

[0203] Thus, when driving two synchronous rectifier switches SR1 and SR2 with the same synchronous rectifier driver circuit 222a, this circuit 222a includes two of the circuits shown in FIGS. 12 and 13.

[0204] In the embodiments, the synchronous rectifier driver circuit 222a comprises a variable current generator 2220 configured to generate a current I₁ as a function of (the instantaneous value of) the voltage DVS (DVS′), e.g., the voltage received at the terminal 2226. Specifically, in various embodiments, the current I₁ is proportional to the voltage DVS:

$\begin{array}{cc}{I}_1=\frac{1}{R_1}\mathrm{DVS}& \left(27\right)\end{array}$

[0205] As mentioned before, the synchronous rectifier driver circuit 222a may indeed use two modes M1 and M2 during given periods of the phase (b). For example, as shown in FIG. 15, the synchronous rectifier driver circuit 222a may comprise for this purpose:

• • [0206] a sample-and-hold circuit 2240 configured to sample the value DVS′_PK;
  • [0207] an electronic switch 2242 configured to selectively provide to the variable current generator 2220 the current value DVS, the value DVS′_PK or a zero voltage; and
  • [0208] a control circuit 2244 configured to drive the electronic switch 2242.

[0209] For example, the sample-and-hold circuit 2240 may be implemented with an analog peak detector, or a sample-and-hold circuit configured to sample the signal DVS in response to a trigger signal provided by the control circuit 2244, wherein the trigger signal signals the instant t₃.

[0210] In line with the previous description, the control circuit 2244 may be configured to provide to the variable current generator 2220 via the electronic switch 2242:

• • [0211] between the instants t₁ and t₃, the value DVS′_PK provided by the sample-and-hold circuit 2240;
  • [0212] between the instant t₃ and one of the instants t₂, the value DVS received at the pin 2226; and
  • [0213] after the instant t₂ (and until the next instant t₁) the zero voltage.

[0214] For this purpose, the control circuit 2244 may be configure to:

• • [0215] determine the switch-on instant t₁, e.g., by comparing via a first comparator the signal DVS with the threshold V_{TH_ON};
  • [0216] determine the instant t₃, as described in the foregoing; and
  • [0217] determine the switch-off instant t₂, e.g., by comparing via a second comparator the signal DVS with the threshold V_{TH_OFF}.

[0218] The speed of the second comparator should be high in order to avoid an inversion of the current I_SR. In fact, thanks to the reduction of the L_SR anticipation, the switch-off instant t₂ is now very close to the zero crossing of the current I_SR.

[0219] In FIG. 12, the output of the current generator 2220 is connected (e.g., directly) to node 2228, which in turn is connected (e.g., directly) to a first terminal of a resistor R₂ and the second terminal of the resistor R₂ is connected (e.g., directly) via a Zener diode Dz to ground/terminal 2232. In various embodiments, the resistor R₂ and/or the Zener diode Dz may be external with respect to the integrated circuit of the synchronous rectifier driver circuit 222a. For example, for this purpose, the node 2228 may be a terminal of such an integrated circuit and the resistor R₂ and the Zener diode Dz may be connected in series between the terminal 2228 and the terminal 2232.

[0220] Thus, in FIG. 12, the signal GD_CTRL corresponds to:

$\begin{array}{cc}{\mathrm{GD}}_{\mathrm{CTRL}}=V_{\mathrm{DZ}}+\frac{R_2}{R_1}\mathrm{DVS}& \left(28\right)\end{array}$

where V_DZ corresponds to the Zener voltage of the diode Dz.

[0221] In this case, by comparing equations (28) and (26), the following relations may be obtained:

$\begin{array}{cc}{V}_{\mathrm{DZ}}=V_{\mathrm{TH},\min }-\mathrm{\Delta V},K=\frac{R_2}{R_1}& \left(29\right)\end{array}$

[0222] For example, for the above exemplary values, V_Dz would have to correspond to 1.436 V.

[0223] Conversely, in FIG. 13, the output of the current generator 2220 is again connected (e.g., directly) to node 2228, which in turn is connected (e.g., directly) to a first terminal of a resistor R₂ and the second terminal of the resistor R₂ is connected (e.g., directly) to ground/terminal 2232. Also in this case, the resistor R₂ may be external with respect to the integrated circuit of the synchronous rectifier driver circuit 222a, i.e., the node 2228 may be a terminal of such an integrated circuit and the resistor R₂ may be connected between the terminal 2228 and the terminal 2232.

[0224] Accordingly, in the embodiment considered, the following voltage V_{REF_DVS} is generated at the node 2228:

$\begin{array}{cc}{V}_{\mathrm{REF}\_\mathrm{DVS}}=\frac{R_2}{R_1}\mathrm{DVS}& \left(30\right)\end{array}$

[0225] Moreover, in the embodiment considered, the synchronous rectifier driver circuit 222a comprises a second current generator 2222 configured to generate a (constant, but optionally settable/programmable) current I₂.

[0226] In the embodiment considered, the output of the current generator 2222 is connected (e.g., directly) to node 2230, which in turn is connected (e.g., directly) to a first terminal of a resistor R₃ and the second terminal of the resistor R₃ is connected (e.g., directly) to ground/terminal 2232. Also the resistor R₃ may be external with respect to the integrated circuit of the synchronous rectifier driver circuit 222a, i.e., the node 2230 may be a terminal of such an integrated circuit and the resistor R₃ may be connected between the terminal 2230 and the terminal 2232.

[0227] Accordingly, in the embodiment considered, the following voltage V_{REF_VTH} is generated at the node 2230:

V_{REF_VTH}=R₃·I₂  (31)

[0228] In the embodiment considered, the voltage V_{REF_DVS} and V_{REF_VTH} are provided to a voltage adder circuit 2224, which provides at output the signal GD_CTRL, i.e.:

$\begin{array}{cc}{\mathrm{GD}}_{\mathrm{CTRL}}=V_{\mathrm{REF}\_\mathrm{DVS}}+V_{\mathrm{REF}\_\mathrm{VTH}}& \left(32\right)\\ {\mathrm{GD}}_{\mathrm{CTRL}}=R_3·I_2+\frac{R_1}{R_3}\mathrm{DVS}& \left(33\right)\end{array}$

[0229] Thus, assuming that the current I₂ is constant, the following relations may be obtained:

$\begin{array}{cc}{R}_3·I_2=V_{\mathrm{TH},\min }-\mathrm{\Delta V},K=\frac{R_2}{R_1}& \left(34\right)\end{array}$

[0230] For example, for the above exemplary values, R₃·I₂ would have to correspond to 1.436 V.

[0231] Finally, in the embodiment shown in FIG. 14, the output of the current generator 2220 is connected again (e.g., directly) to node 2228. In the embodiment considered, the node 2228 is connected (e.g., directly) via a first resistor R₂ to the output voltage Vout/node 202a and via a second resistor R₃ to ground GND, e.g., node 202b. In various embodiments, the resistors R₂ and/or R₃ may be external with respect to the integrated circuit of the synchronous rectifier driver circuit 222a. For example, for this purpose, the node 2228 may be a terminal of such an integrated circuit and the resistors R₂ and R₃ may be connected in series between the terminals 202a and 202b, wherein the intermediate node between the resistors R₂ and R₃ is connected to the terminal 2228. Generally, instead of using the output voltage Vout, the resistors R₂ and R₃ may also be connected between any other (substantially) constant voltage.

[0232] Accordingly, in the embodiment considered, the voltage at the node 2228 (corresponding to the voltage GD_CTRL) may be expressed similar to equation (32) as follows:

GD_CTRL=V_{REF_DVS}+V_{REF_VTH}  (35)

where the first term V_{REF_DVS} may be solved as:

V_{REF_DVS}=V_out·R₃(R₂+R₃)  (36)

and the second term V_{REF_DTH} may be solved as:

V_{REF_DTH}=I₁·(R₂//R₃)=(DVS/R₁)(R₂//R₃)  (37)

[0233] Thus, in view of equation (14), the following correspondences may be determined:

V_x=V_out·R₃(R₂+R₃)  (38)

and

K=(R₂//R₃)/R₁  (39)

[0234] Thus, from a circuit point of view, the integrated circuit of the synchronous rectifier driver circuit 222a shown in FIG. 14 may correspond to the integrated circuit of the synchronous rectifier driver circuit 222a shown in FIG. 12, but only the connection of external components may change. Thus, the integrated circuit may support both connections.

[0235] Accordingly, the circuits shown with respect to FIGS. 12 to 15 provide low-complexity solutions for varying the signal GD as a function of the voltage DVS, wherein the signal GD may optionally be set to a constant value, e.g., determined as a function of the peak value DVS_PK.

[0236] The DVS SGD technique has several advantages, such as:

• • [0237] the current inversion occurrence is reduced, because when the synchronous rectifier FET is driven near to the threshold voltage V_TH, the switch-on resistance R_DSON is increased, thereby reducing the anticipation effect of the inductance L_RS, i.e., the instant of zero-voltage crossing of the signal DVS corresponds to a zero-current instant of the current flowing through the synchronous rectifier FET;
  • [0238] the associated effects of current inversions, such as DVS spikes, are reduced, e.g., because even with a late turn-off of the synchronous rectifier FET (i.e., with current inversion):

[0239] 1) the high switch-on resistance R_DSON does not allow to have a high reverse current in the transformer secondary windings; and

[0240] 2) the load current I_out still flows through the synchronous rectifier FET channel and not through the diode associated with the synchronous rectifier FET body diode, i.e., there is no diode reverse recovery charge whose effect is to reverse charging the transformer secondary side windings.

[0241] The above described turn-off methodology has some drawbacks that should be taken into account.

[0242] The DVS SGD technique does not aim to obtain a shape of the signal GD able to keep the voltage DVS almost constant while the current I_SR approaches zero. Such approach would require a “true” closed loop driving of the synchronous rectifier switches.

[0243] The DVS SGD technique simply requires that the voltage GD is determined as a function of the (instantaneous value of the) signal DVS. However, this variation of the signal GD implies that the switch-on resistance varies and thus the signal DVS itself. In fact, as shown in FIG. 11, a feedback loop indeed exists and is closed via the synchronous rectifier switch SR. This loop implies that any change to the signal GD (or DVS) has an effect on the signal DVS (or GD) too.

[0244] This may result in oscillations (noise) propagated from the signal DVS signal to the signal GD. In various embodiments, a (e.g., low-pass) filter circuit may thus be provided:

• • [0245] between the drain terminal of the synchronous rectifier switch SR and the input node 2226 of the driver circuit 22a; and/or
  • [0246] between the signal GD and the gate terminal of the synchronous rectifier switch SR.

[0247] Generally, the amount of filtering should not be too high, insofar as this would introduce a high delay e.g., between the actual voltage DVS (pre-filter) and the measure voltage DVS′ (post-filter).

[0248] Moreover, when the stray inductance L_SR is big, still a premature turn-off of the synchronous rectifier switch SR may occur, resulting in a high current I_SR flowing through the diode associated with the synchronous rectifier switch SR, leading to a diode reverse recovering charge and subsequent DVS spike. However, compared to the comparative example solution, this effect is still reduced and by choosing a lower value for the parameter K the loop stability may be improved.

[0249] However, lowering the parameter K implies that the desired final value DVS_sat (e.g., 4 mV of the previous design examples) has to be obtained with a smaller voltage GD (higher value for R_DSON). Such a lower voltage GD may require a more complex driver circuit of the synchronous rectifier switch SR.

[0250] FIG. 16 shows a further embodiment, wherein the synchronous rectifier driver circuit 222a uses a closed loop control of the voltage DVS.

[0251] As mentioned before, the synchronous rectifier driver circuit 222a is configured to use, at least during the last portion of the phase (b), a mode M1, wherein the synchronous rectifier driver circuit 222a varies the voltage GD as a function of the voltage DVS. For example, in the embodiment considered, the synchronous rectifier driver circuit 222a uses again two modes:

• • [0252] a mode M2 between the start of the phase (b) at the instant t₁ and an instant t₃; and
  • [0253] a mode M1 between the instant t₃ and the end of the phase (b) at the an instant t₂.

[0254] Specifically, during mode M2, the synchronous rectifier driver circuit 222a sets the voltage GD to a given constant (fixed or predetermined) value. Accordingly, in this case, the voltage DVS will have a shape corresponding to the current I_SR.

[0255] In the embodiment considered, the synchronous rectifier driver circuit 222a is configured to determine the instant t₃ by detecting whether the absolute value of the voltage DVS decreases and reaches a given threshold voltage V_REF. Specifically, once the voltage DVS decreases and reaches a given threshold voltage V_REF, the synchronous rectifier driver circuit 222a switches to mode M1, where the synchronous rectifier driver circuit 222a varies the voltage GD as a function of the voltage DVS.

[0256] Specifically, in the embodiment considered, the synchronous rectifier driver circuit 222a is configured to vary the voltage GD in order to keep the voltage DVS constant, i.e., in order to maintain the voltage DVS at the value of V_REF. Generally, due to the fact that the current I_SR continuous to decrease, the synchronous rectifier driver circuit 222a has to increase the switch on resistance RDS_ON, i.e., the synchronous rectifier driver circuit 222a has to reduce the drive signal GD, until the drive signal GD falls below the threshold voltage V_TH of the FET and the FET is opened, which corresponds to the instant t₂.

[0257] FIG. 17 shows a possible embodiment of the synchronous rectifier driver circuit 222a operating as shown in FIG. 16.

[0258] As mentioned before, in this case, the synchronous rectifier driver circuit 222a is configured to use during mode M1 a closed loop control for the drive signal GD in order to keep the voltage DVS constant. In order to keep the voltage DVS constant, the synchronous rectifier driver circuit 222a comprises thus a closed feedback loop, which compares the voltage DVS with the threshold voltage V_REF. The voltage V_REF at which the feedback loop regulates should be chosen in range 0>V_REF>DVS_PK, e.g., in range of between 10% and 30% of DVS_PK. For example, the reference/threshold voltage V_REF may be provided by a voltage reference 2254. The reference voltage V_REG may be obtained also as a fraction of maximum DVS voltage DVS_PK during the phase b, via a digital core and a digital-to-analog converter, an external reference supply, components connected externally to the integrated circuit comprising the synchronous rectifier driver circuit 222a, etc.

[0259] For example, in the embodiment considered, the feedback loop comprises a (digital and/or analog) regulator circuit 2250 receiving at input the signals DVS and V_REF, and generating at output a regulation signal REG. Specifically, in various embodiments, the regulator circuit 2250 comprises at least an Integral (I) component, and optionally a Proportion (P) and/or Derivative (D) component. For example, an analog regulator circuit 2250 may be implemented with an operational amplifier having associates a respective feedback network, e.g., comprising at least a capacitor for the Integral component. In various embodiments, the inputs and/or the outputs of the regulator circuit 2250 may have associates filter circuits, e.g., low-pass filters configured to filter noise in the voltage DVS measurement and/or the signal GD. The speed of the filters should be chosen, such that the dynamic of gate voltage control can be maintained.

[0260] Accordingly, in the embodiment considered, the signal GD may be generated as a function of the signal REG. For example, in case the synchronous rectifier driver circuit 222a also supports mode M2, the synchronous rectifier driver circuit 222a may be configured to use as voltage GD:

• • [0261] in mode M2, a constant voltage, e.g., Vcc; and
  • [0262] in mode M1, the signal REG.

[0263] Specifically, as mentioned before, the control circuit 2244 should also be able to set the signal GD to zero once the phase (b) ends, i.e., when the voltage DVS falls to zero. Accordingly, in various embodiments, the synchronous rectifier driver circuit 222a is configured to selectively apply to the terminal GD:

• • [0264] the constant voltage (mode M2), when the voltage DVS reaches the switch-on threshold V_{TH_ON} (instant t₁);
  • [0265] the signal REG voltage (mode M1), when the voltage DVS reaches the threshold VREF (instant t₃); or
  • [0266] zero (in response to detecting the instant t₂)

[0267] For example, in the embodiment considered, the synchronous rectifier driver circuit 222a comprises for this purpose a switching circuit 2256 and 2258, and a control circuit 2244. For example, in various embodiments, the control circuit 2244 is configured to monitor the voltage DVS and drive the switching circuit 2256 and 2258 in order to select (in sequence):

• • [0268] the constant voltage (mode M2), when the voltage DVS reaches the switch-on threshold V_{TH_ON} (instant t₁);
  • [0269] the signal REG (mode M1), when the voltage DVS reaches the threshold V_REF(instant t₃); and
  • [0270] zero, when the voltage DVS reaches zero (instant t₂).

[0271] For example, as schematically shown, the last condition may be verified via a zero-voltage comparator 2252.

[0272] FIG. 17 also shows a possible embodiment of the switching circuit. Specifically, in the embodiment considered, the switching circuit comprises a multiplexer 2258, schematically shown via an electronic switch. Accordingly, in the embodiment considered, the control circuit 2244 may drive the multiplexer 2256 in order to switch between modes M1 and M2. In the embodiment considered, the signal at the output of the multiplexer 2256 is thus not used directly as signal GD, but the synchronous rectifier driver circuit 222a comprises a circuit 2256 configured to select either the signal at the output of the multiplexer 2256 or a zero voltage.

[0273] For example, in the embodiment considered, the synchronous rectifier driver circuit 222a comprises a driver circuit 2256, wherein the driver circuit 2256 receives as supply voltage the signal at the output of the multiplexer 2256, which thus corresponds to the maximum output voltage of the driver circuit 2256, and the input of the driver circuit 2256 is driven by the control circuit 2244, which thus may set the signal GD to zero or to the signal at the output of the multiplexer 2256.

[0274] Accordingly, once the control circuit 2244 detects that the voltage DVS reaches the threshold V_{TH_ON} (instant t₁), the control circuit 2244 drives the switching circuit 2256/2258 in order to apply to the terminal GD a constant voltage (full drive voltage). Next, once the control circuit 2244 detects that the voltage DVS reaches the voltage V_REF (instant t₃), the control circuit 2244 drives the switching circuit 2256/2258 in order to apply to the terminal GD the signal REG, thereby activating the gate voltage shaping. Finally, once the control circuit 2244 detects that the voltage DVS reaches zero (instant t₂), the control circuit 2244 drives the switching circuit 2256/2258 in order to apply to the terminal GD a zero voltage.

[0275] Accordingly, from the instant t₃ the voltage DVS is kept constant by decreasing the signal GD. As mentioned before, the control circuit 2244 could also be configured to detect the instant t₃ by:

• • [0276] determining the instant when the voltage DVS reaches a peak value DVS_PK, or
  • [0277] waiting for a given time with respect to the instant t₁.

[0278] Alternatively, the synchronous rectifier driver circuit 222a could also support only mode M1 and use always the gate voltage shaping, thereby reducing the complexity of the circuit.

[0279] Of course, without prejudice to the principle of the disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure.

[0280] A synchronous rectifier driver circuit (222a) configured to drive a synchronous rectifier FET (SR1, SR2) comprising a drain, a source and a gate terminal, may be summarized as including: a first terminal (2232) configured to be connected to the source terminal of said synchronous rectifier FET (SR1, SR2); a second terminal (2226) configured to be connected to the drain terminal of said synchronous rectifier FET (SR1, SR2); a third terminal (GD) configured to be connected to the gate terminal of said synchronous rectifier FET (SR1, SR2); wherein said synchronous rectifier driver circuit (222a) may be configured to: measure the voltage (DVS) between said second terminal (2226) and said first terminal (2232), detect a switch-on instant (t₁) wherein said measured voltage (DVS) reaches a first threshold value (V_{TH_ON}); detect a switch-off instant (t₂) wherein said measured voltage (DVS) reaches a second threshold value (V_{TH_OFF}); generate a drive signal (GD) between said third terminal (GD) and said first terminal (2232) as a function of said measured voltage (DVS) by: between a further instant (t₃) and said switch-off instant (t₂), varying said drive signal (GD) as a function of the instantaneous value of said measured voltage (DVS); and between said switch-off instant (t₂) and the next switch-on instant (t₁), setting said drive signal (GD) to a first value.

[0281] Said synchronous rectifier driver circuit (222a) may be configured to, between said switch-on instant (t₁) and said further instant (t₃), set said drive signal (GD) to a second value. Said synchronous rectifier driver circuit (222a) may be configured to determine said further instant (t₃) by: determining an instant (t₃) where said measured voltage (DVS) reaches a peak value (DVS_PK) between said switch-on instant (t₁) and said switch-off instant (t₂); waiting a given time from said switch-on instant (t₁); or determining an instant (t₃) where said measured voltage (DVS) reaches a given threshold value (V_REF). Said synchronous rectifier driver circuit (222a) may be configured to determine the instant where said measured voltage reaches said peak value (DVS_PK) by: determining the duration between a previous switch-on instant (t₁) and a respective previous switch-off instant (t₂) and estimating said further instant (t₃) at half of said duration. Said synchronous rectifier driver circuit (222a) may be configured to vary said drive signal (GD) between said further instant (t₃) and said switch-off instant (t₂) by setting said drive signal (GD) to a voltage corresponding to the sum of a constant voltage (V_x, ΔV) and a voltage proportional with a given proportionality constant (K) to said instantaneous value of said measured voltage (DVS). Said synchronous rectifier driver circuit (222a) may include a sample-and-hold circuit (2240) configured to store said peak value (DVS_PK), and wherein said synchronous rectifier driver circuit (222a) is configured to determine said second value as a function of said stored peak value (DVS_PK). The second value may correspond to the sum of said constant voltage (V_x, ΔV) and a voltage proportional with said given proportionality constant (K) to said stored peak value (DVS_PK).

[0282] The synchronous rectifier driver circuit may include: a fourth terminal (2228); a variable current generator (2220) configured to generate a variable current (I₁) applied to said fourth terminal (2228), wherein said variable current (I₁) may be proportionate to a voltage received at an input of said variable current generator (2220); and a control circuit (2242, 2244) configured to connect said input of said variable current generator (2220) to: said stored peak value (DVS_PK) between said switch-on instant (t₁) and said further instant (t₃), said measured voltage (DVS) between said further instant (t₃) and said switch-off instant (t₂); and said first terminal (2232) between said switch-off instant (t₂) and the next switch-on instant (t₁).

[0283] The voltage at said fourth terminal (2228) may reproduce said drive signal (GD).

[0284] The synchronous rectifier driver circuit (222a) may include: a fifth terminal (2230); a constant current generator (2220) configured to generate a constant current (I₂) applied to said fifth terminal (2230); and a summation circuit (2224) configured to generate said drive signal (GD) by summing the voltage at said fourth terminal (2228) and the voltage at said fifth terminal (2230). Said synchronous rectifier driver circuit (222a) may be configured to vary said drive signal (GD) between said further instant (t₃) and said switch-off instant (t₂) in order to regulate (2250) said measured voltage (DVS) to a given reference value (V_REF). Said synchronous rectifier driver circuit (222a) may include: a regulator circuit (2250) configured to receive at input said measured voltage (DVS) and said given reference value (V_REF), and generate at output a regulation signal (REG), wherein said regulator circuit (2250) may include at least an Integral component, and wherein said drive signal (GD) is determined (2244, 2256, 2258) between said further instant (t₃) and said switch-off instant (t₂) as a function of said regulation signal (REG).

[0285] An integrated circuit may be summarized as a synchronous rectifier driver circuit (222a) as described above.

[0286] An electronic resonant converter (20) may be summarized as including: two input terminals (200a, 200b) for receiving an input voltage and two output terminals (202a, 202b) for providing an output voltage (Vout) or output current (iout); a transformer (T) including a primary winding and a first (T2a) and a second (T2b) secondary winding; a switching stage (SW1, SW2) connected via a resonant tank (Cr, Ls, Lp) to said primary winding; a first synchronous rectifier FET (SR1) connected in series with said first secondary winding (T2a) between said two output terminals (202a, 202b); a second synchronous rectifier FET (SR1) connected in series with said second secondary winding (T2b) between said two output terminals (202a, 202b); and two synchronous rectifier driver circuits (222a).

[0287] A method of operating a synchronous rectifier driver circuit (222a) may be summarized as including: measuring the voltage (DVS) between said second terminal (2226) and said first terminal (2232); detecting a switch-on instant (t₁) wherein said measured voltage (DVS) reaches a first threshold value (V_{TH_ON}); detecting a switch-off instant (t₂) wherein said measured voltage (DVS) may reach a second threshold value (V_{TH_OFF}); generating a drive signal (GD) between said third terminal (GD) and said first terminal (2232) as a function of said measured voltage (DVS) by: between a further instant (t₃) and said switch-off instant (t₂), varying said drive signal (GD) as a function of the instantaneous value of said measured voltage (DVS); and between said switch-off instant (t₂) and the next switch-on instant (t₁), setting said drive signal (GD) to a first value.

[0288] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.