Device Structure for a 3-Dimensional NOR Memory Array and Methods for Improved Erase Operations Applied Thereto

[0001] The present application is related to and claims priority of U.S. provisional patent application (“Provisional Application I”), Ser. No. 62/697,060, entitled “Device Structure for a 3-Dimensional NOR Memory Array and Methods for Improved Erase Operations Applied Thereto,” filed on Jul. 12, 2018.

[0002] The present application relates to (i) U.S. provisional patent application (“Provisional Application II”), Ser. No. 62/522,666, entitled “Replacement Metal and Strut for 3D Memory Array”, filed on Jun. 20, 2017; and (ii) U.S. provisional patent application (“Provisional Application III”), Ser. No. 62/550,553, entitled “3-Dimensional NOR Memory Array Architecture and Methods for Fabrication Thereof,” filed on Aug. 25, 2017. (iii) U.S. patent application (“Non-provisional Application I”), Ser. No. 15/846,766, entitled “Multi-gate NOR Flash Thin-film Transistor Strings Arranged in Stacked Horizontal Active Strips with Vertical Control Gates,” filed on Dec. 19, 2017, now published as U.S. 2018/0108423; (iv) U.S. patent application (“Non-provisional Application II”), Ser. No. 15/837,734, entitled “Three-Dimensional Vertical NOR Flash Thin-film Transistor Strings,” filed on Dec. 11, 2017, now published as U.S. 2018/0108416; and (v) U.S. patent application (“Non-provisional Application III”), Ser. No. 15/248,420, entitled “Capacitive-coupled Non-volatile Thin-film Transistor Strings in Three-Dimensional Arrays,” filed on Aug. 26, 2016, now published as U.S. 2017/0092371. The disclosures of Provisional Applications I, II and III, and Non-provisional Applications I, II and III (collectively, the “Related Applications”) are hereby incorporated by reference in their entireties.

[0003] References herein to Non-Provisional Applications I, II and III are made by paragraph numbers of their respective publications.

[0004] The present invention relates to memory structures providing non-volatile memory strings. In particular, the present invention relates to structure modifications to improve erase or program operation performance in a 3-dimensional structure containing such non-volatile memory strings, e.g., NOR-type memory strings.

[0005] The lightly-doped channel region of a thin-film transistor in a high-density 3-dimensional memory structure, such as any of those described in the Provisional Applications II and III, has only a small number of donor or acceptor sites and may become depleted of charge carriers (i.e., holes or electrons) under normal biasing conditions during read, program and erase operations. Unlike non-volatile memory transistors fabricated on bulk silicon, non-volatile thin-film memory transistors (e.g., those disclosed in the Related Applications) have floating channels and therefore suffer from a limited supply of donor or acceptor sites. During an erase operation, the gate, source and drain bias conditions of an NMOS thin-film memory transistor may completely deplete the floating channel region of electrons, so that there are insufficient number of holes to accumulate at the surface of the channel region, thereby leading to a slow erase operation.

[0006] The present invention provides one or more sources of holes in close proximity to a floating P⁻ channel region of a thin-film storage transistor to facilitate a more efficient erase operation.

[0007] According to one embodiment of the present invention, a thin-film storage transistor includes (a) first and second semiconductor layers (e.g., polysilicon) of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third semiconductor layer of a second conductivity, adjacent both the first and second semiconductor layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping structure including, for example, an oxide-nitride-oxide (ONO) multi-layer separating the gate conductor from the channel region. In the ONO charge-trapping structure, a charge-trapping nitride layer is separated from the conductor by a first blocking dielectric layer and from the third semiconductor layer by a second tunnel dielectric layer. The third semiconductor layer may have a dopant concentration greater than 1.0×10¹⁸ cm⁻³ or it may be undoped. This channel region may be made sufficiently thin, typically in the range of 3-15 nm, with its dopant concentration sufficiently low to facilitate its complete depletion when the thin-film storage transistor is biased to a non-conducting state. In some embodiments, the third semiconductor layer may comprise polysilicon or another semiconductor material (e.g., germanium, silicon germanium. recrystallized silicon, or indium gallium zinc oxide (also called “Igzo”). In one embodiment, the third semiconductor layer (i.e., the channel material) is formed inside a recess of an insulation layer. A shallow recess (e.g., 3-15 nm deep) can conveniently accommodate a depletable thin channel region. In addition, in some embodiments, a fourth semiconductor layer of the second conductivity (“a body layer”) having a dopant concentration that is at least that of the third semiconductor layer may be included in direct or indirect contact with the channel region. The fourth semiconductor layer's primary function is to provide free charge carriers to the channel region, so as to speed up device operations such as an erase operation. To increase the number of free charge carriers, the body layer may have a dopant concentration that is one or more orders of magnitude greater than the dopant concentration of the channel material. In such an embodiment, care must be taken to ensure that the dopants in the body layer are prevented from excessively doping any channel region adjacent to the body layer. Dopant redistribution may be avoided by exposing the memory structure to prolonged high temperature steps in the manufacturing process or, alternatively, by providing a thin dielectric diffusion barrier film, typically just a few nanometers thick, to separate the channel region from the body region. In one embodiment, the body region is adjacent to an ONO multi-layer. In another embodiment, the body layer is substantially separated from the ONO multi-layer by the channel region, so as to avoid or reduce the higher dopant concentration of the body layer from unduly impacting the threshold voltage of the thin-film storage transistor.

[0008] Alternatively, the charge-trapping structure may include a thin tunneling dielectric film (e.g., a silicon oxide layer, a nitrogen-rich silicon oxide, or a silicon oxide-silicon nitride-silicon oxide (“ONO”) triple-layer) that is bandgap-engineered, as is known to those of ordinary skill in the art). The thin tunneling dielectric film is preferably 3 nm or less, and is followed after its deposition by a deposition of a 3-10 nm thick layer of charge-trapping material (e.g., silicon nitride, silicon-rich nitride or oxide, nanocrystals, nanodots embedded in a thin dielectric film, or isolated floating gates), then followed by a blocking dielectric film. The blocking dielectric film may be a 4-15 nm thick layer consisting of, for example, an ONO layer, or a high dielectric constant film (e.g., aluminum oxide, hafnium oxide or some combination thereof with silicon oxide). The charge-trapping structure may also include SONOS, TANOS, nanodot storage, isolated floating gates or any suitable charge-trapping structures known to those of ordinary skill in the art.

[0009] Thin-film storage transistors of the present invention may be organized as a NOR memory string, in which the thin-film storage transistors share the common source and drain regions, provided by the first and second semiconductor layers, respectively.

[0010] In one embodiment, a conductive material is provided as part of a staircase or inverse staircase structure to electrically connect the body layer to either the common source or drain layers or regions. In one embodiment, the conductive material is provided at a connection region of a memory structure where the body layers of the NOR memory strings of the memory structure are connected to circuitry formed in or on a semiconductor substrate using a staircase structure or an inverse staircase structure. The conductive structure may include a silicide, such as a nickel silicide, a cobalt silicide or a tungsten silicide, another silicide, or a refractive metal (e.g., tungsten, tantalum or cobalt). Alternatively, the conductive material may be a polysilicon spacer with a dopant concentration of 1.0×10¹⁹ cm⁻³ or higher.

[0011] According to one embodiment of the present invention, a channel region of the second conductivity type has a higher than conventional dopant concentration, so as to provide sufficient donors or acceptors to facilitate erase or program operations. For example, thin-film storage transistor of the present invention may have a mean intrinsic threshold voltage between 1.5 to 6.0 volts, or higher. An erase operation may optionally be used to bring the thin-film storage transistor to a state in which its threshold voltage is below the intrinsic threshold voltage, and during programming the device is programmed substantially back to its intrinsic threshold voltage.

[0012] According to some embodiments of the present invention, an added P-doped body layer or P-doped region provides sufficient electrical carriers (i.e., holes for NMOS thin-film transistors and electrons for PMOS thin-film transistors) to the channel region, when the channel region is otherwise completely depleted under electric field conditions applied to the source, the drain and the gate regions. For example, a p⁻ channel region (e.g., lightly boron doped) of a non-volatile NMOS thin-film transistor with a floating channel (i.e., no direct electrical connection to the P-doped silicon substrate) may be depleted of electrons during an erase operation, when the gate terminal is biased at a high negative voltage relative to the source and drain terminals, and there are very few holes in the lightly doped channel region. In that situation, the more heavily P-doped body layer or P-doped region provides additional holes to the channel region to facilitate the erase operation. Therefore, the P doped body or the P-doped layer of a floating thin film transistor serves the function of a P-doped bulk silicon substrate of a conventional non-volatile NMOS transistor.

[0013] The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings.

[0021] To simplify the following detailed description, like elements in the drawings are assigned like reference numerals. The figures, although drawn for clarity of illustration, are not drawn to scale.

[0022] The present invention provides one or more sources of holes in close proximity to a floating P⁻ channel in a thin-film storage transistor in order to facilitate a more efficient erase operation. One way to supply excess holes to a channel region to facilitate erase is by generating holes using the well-known GIDL mechanism¹. Although it is a relatively slow mechanism (typically a few milliseconds), GIDL is employed extensively in 3-D NAND memory structures to generate holes in the channel region during an erase operation. GIDL bias conditions can be employed equally well to generate excess holes during an erase operation for the thin-film transistors disclosed in the Related Applications. The GIDL mechanism can be applied whether erasing an entire thin-film transistor string or individually selected thin-film transistors. ¹ GIDL is the acronym for “gate-induced drain leakage current.”

[0023] Another way to facilitate an erase operation is to connect the P⁻ channel regions of the thin-film transistor string to a bulk P-type substrate, which has essentially unlimited supply of holes. For example, in paragraph [0072] and in FIG. 3, Non-provisional Application I discloses providing optional connection 290 to P⁻ sublayers 222 to access back-bias voltage V_bb, from substrate 201. There, paragraph [0072] teaches: “ . . . In some embodiments a high positive V_bb voltage can be applied during an erase operation to tunnel-erase TFTs whose control gates are held at ground potential . . . .” Similarly, in FIG. 5 and paragraph [0054], Non-provisional Application II teaches: “ . . . buried contact 556 optionally connects P⁻ body region on the active strip to body bias source 506 (V_bb) in the substrate . . . .” Connecting the P⁻ channels to the bulk P substrate is a viable source of excess holes for erasing a vertical NOR thin film transistor string but is somewhat more complicated to implement with a horizontal NOR thin film transistor string.

[0024] Various embodiments of the present invention are described generally herein. After the various embodiments are described, some specific examples of materials and fabrication steps are described that can be applied to forming the various embodiments.

[0025] In this detailed description, the term “patterning” refers to (i) providing a masking layer (e.g., a photoresist layer or a hard mask layer) over the target layer, and (ii) creating a pattern in the masking layer using suitable photolithography techniques. The pattern created in the masking layer is typically transferred to one or more target layers using one or more etching steps.

[0026] In this detailed description, memory structures and methods of fabricating the memory structures over a semiconductor substrate are described as illustrative examples of the present invention. Prior to forming the memory structure, various devices and circuitry are formed on or in the semiconductor substrate using conventional techniques. One or more layers of individually addressed conductors may be provided to connect bit lines and other electrical elements of the memory structure to devices or circuitry on or in the semiconductor substrate and may be formed beneath or above the memory structure. The layers of conductors are insulated from each other by a dielectric material, which is provided between the conductors and between the layers of conductor. The surface of the dielectric is then planarized using, for example, chemical-mechanical polishing (CMP), known to those skilled in the art. In FIG. 1, described below, this planarized surface is represented by the surface of dielectric layer 201. In this description, to facilitate description of the 3-dimensional memory structure, the surface of dielectric layer 201 defines an X-Y plane—X and Y being mutually orthogonal directions parallel to the surface of dielectric layer 201—and the direction perpendicular to the X-Y plane defines the Z direction.

[0027] FIG. 1 shows a Y-Z cross-sectional view of various material layers in memory structure 500, according to one embodiment of the present invention. In FIG. 1, active layers 502-0 to 502-7 are provided, each active layer including drain sublayer 521, source sublayer 523 and sacrificial material 1 (“SAC1”) sublayer 522 (to be subsequently partially or completely replaced by a channel sublayer). In addition, sacrificial material 4 (SAC4) sublayer 524 is provided, to be subsequently replaced by a conductive sublayer which electrically contacts drain sublayer 521 throughout substantially its entire length. Sacrificial material 4 can also be provided (not shown) adjacent to source layers 523 to be also subsequently replaced by a conductor sublayer which electrically contacts portions of, or substantially the entire length of, source sublayer 523. The conductive sublayer replacing sacrificial material 4 provides a low-resistivity path for its adjacent source or drain sublayer. Initially, the material layers of memory structure 500 are deposited over the entire surface of planarized dielectric layer 201.

[0028] Deep trenches are then etched in the material layers (e.g., lengthwise along the Y direction and along the Z direction in depth to buried contacts in dielectric layer 201, or even through dielectric layer 201 to expose conductors in dielectric layer 201 to contacts formed on the surface of the semiconductor substrate, or both) to form individual stacks of the material layers (“active stacks”) separated from each other along the X direction. In each active stack, each active layers form a strip of material layers (“active strip”). FIG. 1 may represent, for example, a cross section in the Y-Z plane through an active stack. Storage transistors are then formed out of each active strip in each active stack along one or both side walls of the active strip. The storage transistors may be organized as multiple NOR memory strings each extending along the Y direction. To form the storage transistors, among other steps, (i) sacrificial sublayer 522 is recessed along its length in the Y direction, or completely excavated, so that a lightly-doped polysilicon may be deposited to fill the resulting void, thus forming channel regions that are in contact with the common source and drain regions (ii) a charge-trapping material (e.g., an ONO multi-layer) is provided over each sidewall of the active stacks in the deep trenches, (iii) gate terminals (“word lines”) are formed as conductor columns in the trenches, each extending along the Z directions and arrayed side-by-side along the Y direction. Each storage transistor of the NOR memory string is thus formed by (i) a common source region, provided by source sublayer 523 of an active strip, (ii) a common drain region (“bit line”), provided by drain sublayer 521 of the active strip, (iii) a channel region, provided by a portion of the lightly-doped polysilicon in the recess or excavated cavity of sacrificial layer 522, (iv) a charge trapping material (e.g., an ONO multi-layer), and (v) a gate terminal, provided by one of the conductor columns. As would be understood by one of ordinary skill in the art, the source and drain regions are interchangeable with each other—i.e. region 523 can serve as the drain region and region 521 can serve as the source region.

[0029] Various processes may be used, such as those disclosed in Provisional Applications II and III, illustrate various exemplary ways to form the NOR memory strings of the memory structure. For example, FIGS. 3-11 and 12A-12D of Provisional Application III, in conjunction with the description of the specification therein, illustrate a process that forms NOR memory strings that extend along a direction (e.g., Y direction) parallel to the surface of a semiconductor substrate.

[0030] FIGS. 2A-2C illustrate schematically, in accordance with embodiments of the present invention, improved device structures of the thin-film storage transistors in a NOR memory string that may be formed, with slight modifications, using the processes taught in Provisional Application III, for example. In FIGS. 2A-2C the charge trapping material (e.g., an ONO multi-layer), the gate terminals, and the conductor layers (e.g., conductor layer 524 illustrated in FIG. 1) strapping source layer 523 and drain layer 521 are not shown for reasons of highlighting only features in focus; these omitted elements; however, are understood to be present and required for proper device operations. In the device structures of FIG. 2A, a P⁻-doped polysilicon material 222 is provided as a channel material in the recessed portions of sacrificial sublayer (SAC1) 522.

[0031] In a conventional polysilicon thin-film transistor, the boron dopant concentration in the channel region is typically around 10¹⁸ (e.g., 1.0×10¹⁷ cm⁻³-1.5×10¹⁸ cm⁻³), which provides a mean threshold voltage (“mean intrinsic threshold voltage”) of 1.5-2.0 volts, with the corresponding charge-trapping material being uncharged. Increasing the thickness of the channel material (e.g., to greater than 10 nm) both widens the spread of the threshold voltage distribution in both the programmed and erased state and weakens the “macaroni” effect² known to a person of ordinary skill in the art. ² The “macaroni” effect refers to the substantial reduction in the parasitic subthreshold leakage current of the transistor when the channel region is sufficiently thin (e.g., 20 nm or less) as to be completely depleted during the transistor's non-conducting state.

[0032] In the conventional thin-film transistor, the mean intrinsic threshold voltage is typically less than 2.0 volts, and the programmed state may be set at a higher voltage than 2.0 volts, as illustrated in FIG. 3A. To program a thin-film storage transistor to a programmed state, electrons are injected from an inverted layer of the channel material into the charge-trapping layer or material. As shown in FIG. 3A, when the mean threshold voltage of the programmed state is set sufficiently high, so that the threshold distributions of the programmed and erased states are sufficiently separated, a read-voltage (V_R) slightly higher than 2.0 volts may be used to distinguish between the programmed state and the erased state in the thin-film storage transistor.

[0033] According to one embodiment of the present invention, polysilicon material 222 of FIG. 2A may be provided a higher boron dopant concentration (e.g., 5.0×10¹⁸ cm³ to 1.0×10¹⁹ cm³) than a conventional thin-film storage transistor. At a boron dopant concentration above around 5.0×10¹⁸ cm⁻³, the mean intrinsic threshold voltage is between 3.0-6.0 volts. An alternative to a programmed state having a mean threshold voltage that is above the mean intrinsic threshold voltage of around 3.0-6.0 volts may be achieved by designating the mean intrinsic threshold voltage as the programmed state and a lower mean threshold voltage state as the erased state, as illustrated in FIG. 3B. As shown in FIG. 3B, erasing a thin-film storage transistor is achieved by bringing the thin-film storage transistor from its intrinsic threshold voltage state to its lower threshold erased state. To bring a thin-film storage transistor to its erased state, electrons are driven out from the charge-trapping region into the channel material or holes are injected from the channel material to the charge-trapping region. A read-voltage (V_R) between the two distributions (e.g., V_R=1.0 volt below the intrinsic threshold voltage) would distinguish between the erased and programmed states.

[0034] In one embodiment, as shown in FIG. 2A, (i) N⁺ common drain and source regions 521 and 523 may each be 40 nm thick along the vertical or Z direction, (ii) sacrificial layer 522 may be 80 nm thick (along the Z-direction) about 30 nm wide (along a horizontal or X-direction), (iii) P-doped polysilicon 222 may be 9.0-13.0 nm thick (along the horizontal or X direction), and (iv) the number of thin-film storage transistors along the Y direction in each NOR memory string may be 1000 or more. Each NOR memory string is isolated from other NOR memory strings above or below it by interlayer dielectric 503. When P-doped polysilicon 222 has a boron dopant concentration of 1.0×10¹⁹ cm⁻³ and its thickness along the Z-direction is greater than the depleted region of a PN junction, it is estimated 40 free charge carriers may be available in the channel region of each thin-film storage transistor, so that the total free charge carriers in the shared channel regions of the NOR memory string approximate 40,000, contributing to an enhanced erase efficiency. In some embodiments, one or both of common drain and source regions 521 and 523 may also include a 30 nm sacrificial layer 524, which may be replaced by a high conductivity layer (e.g., tungsten (W)) prior or subsequent to deposition of P-doped polysilicon 222.

[0035] FIG. 2B shows, in one embodiment of the present invention, N⁺ common drain sublayer 521 being implemented as N⁺ sublayer 521a and P⁺ sublayer 521b, each being about 20 nm thick, with P-doped sublayer 521b to be adjacent and in contact with P-doped polysilicon 222 to supply additional free charge carriers to the channel region of the storage transistor being erased. P⁺ sublayer 521b may have the same or higher boron dopant concentration as P⁻-doped polysilicon layer 222 (e.g., 1.0×10¹⁹ cm⁻³). In such a configuration, each thin-film storage transistor would have 920 free charge carriers in the channel region, with a total of 920,000 free carriers per NOR memory string. However, although P⁺ layer 521b aids in the erase operation, a high boron concentration or an excessive thickness may hinder the formation of a continuous inverted channel between the source region (i.e., N⁺ polysilicon) 523 and the drain region (N⁺ polysilicon 521a) in a read operation. Care must also be taken to avoid excessive diffusion of dopants between N⁺ polysilicon 521a and P⁺ polysilicon 521b during any high temperature manufacturing processing step. Such cross diffusion can be mitigated considerably by depositing or growing an ultra-thin dopant diffusion-blocking dielectric (not shown), typically 1-3 nm thick silicon oxide or silicon nitride between N⁺ polysilicon 521a and P⁺ polysilicon 521b (see below).

[0036] FIG. 2C shows, in one embodiment of the present invention, sacrificial layer 522 being completely replaced by P-doped polysilicon body 520 (e.g., with a boron dopant concentration of up to around 1.0×10¹⁹ cm⁻³). In this configuration, the macaroni effect is diminished and the native threshold voltage is quite high (e.g. 3.0-6.0 volts), but each thin-film storage transistor would have 9000 free charge carriers (holes) in the channel region, for a total of 9 million or more free charge carriers in the channel regions of the NOR memory string.

[0037] FIGS. 2D(i) and 2D(ii) illustrate schematically, another improved device structure 550 of the thin-film storage transistors in a NOR memory string, in accordance with one embodiment of the present invention. In device structure 550, P⁺ layer 551 is separated from sacrificial layer 522 by N⁺ common source layer 553. As in each of the device structures of FIGS. 2A-2B, sacrificial layer 522 is recessed or excavated at a subsequent step and filled by an undoped or P⁻-doped material 222 (e.g., boron, at 1.0×10¹⁷ cm⁻³ to around 1.5×10¹⁸ cm⁻³), which serves as a channel material in the completed device. In FIG. 2D(i), for a reason to be discussed below, N⁺ common source region 553 has a lower dopant concentration (e.g., arsenic, at 1.0×10¹⁸ cm⁻³ to 1.0×10¹⁹ cm⁻³) than N⁺ common drain layer 552 (e.g., 1.0×10²⁰ cm⁻³). P⁺ layer 551 has a dopant concentration (e.g., boron, at 1.0×10¹⁸ cm⁻³ to 1.0×10¹⁹ cm³) that is approximately equal to the dopant concentration of N⁺ common source layer 553. A depletion layer 570 naturally forms between P⁺ layer 551 and N⁺ common source layer 553. As in the devices in FIGS. 2A-2C discussed above, the material layers of device structure 550 may be formed by layer-by-layer depositions, using the processes of Provisional Applications II and III. FIG. 2D(i) also shows the charge-trapping layers 560 and gate electrodes 558, provided on the side walls of device structure 550 and adjacent charge-trapping layers 560, respectively.

[0038] A thin-film storage transistor having device structure 550 of FIG. 2D(i), as shown, has a mean intrinsic threshold voltage of typically less than 2.0 volts. Such a device may be programmed to threshold voltages higher than 2.0 volts. During a read operation, gate electrode 558 is biased to a read voltage slightly above the device's threshold voltage (e.g., 2.0 to 4.0 volts). During a programming operation, the voltage at gate electrode 558 is set to a relatively high value (e.g., 10.0 to 15.0 volts), while N⁺ common source layer 553, P⁺ layer 551 and the N⁺ common drain layer 552 are biased at or near the ground reference voltage. In that configuration, the surface of undoped or P⁻ material at the interface with charge-trapping material 560 (e.g., an ONO multi-layer) is inverted (i.e., becomes N-type conductivity) to provide a conduction path between N⁺ common source layer 553 and N⁺ common drain layer 552. In both reading and programming operations, the inverted N-type conductivity layer ends on N⁺ common source layer 553 and the P⁺ layer 551 is isolated and does not affect the device operation of the thin-film storage transistor.

[0039] FIG. 2D(ii) illustrates device structure 550 of FIG. 2D(ii) during an erase operation. As shown in FIG. 2D(ii), during the erase operation, gate electrode 558 is biased to a relatively large negative value (e.g., between −15.0 and −10.0 volts), while N⁺ common source layer 553, P⁺ layer 551 and N⁺ common drain layer 552 are biased at a low voltage (e.g., the ground reference voltage). In this configuration, electrons at the surface of N⁺ common source layer 553 and undoped or P⁻ layer 222, are driven away, so that the surface of N⁺ common source layer 553 at the interface with charge-trapping material 560 (e.g., an ONO multi-layer) becomes inverted (i.e., P-type conductivity) and the surface of undoped or P⁻ layer 222 at the interface with charge-trapping layer 560 becomes accumulated. In this configuration, charge carriers (e.g., holes) are supplied from P⁺ layer 551 to undoped or P⁻ layer 222 to facilitate the erase operation. The same effect may be achieved, for example, with the voltage at gate electrode 558 set to or near ground voltage, while N⁺ common drain layer 552, N⁺ common source layer 553 and P⁺ layer 551 are biased to a high positive voltage (e.g., 10.0-15.0 volts).

[0040] The present invention is applicable not only in providing efficient erase operations in the horizontal NOR memory strings in the various embodiments discussed herein and in the Non-provisional Applications I and III, it is also applicable to improving erase efficiency in the vertical NOR memory strings, for example, disclosed in Non-provisional Application II. For example, in FIG. 6a and paragraph [0056], Non-provisional Application II discloses storage transistors TFT 685 (T_L) and TFT 584 (T_R) of the same or a pair of vertical NOR strings, storage transistor having a P⁻-doped polysilicon layer (656L or 656R) channel region between N⁺ common source line 655 and N⁺ common drain line 654. The channel regions (i.e., P⁻-doped polysilicon layers 656L and 656R are provided on the surface of a dielectric core (i.e., isolation material 640). The present invention may be incorporated into the storage transistors of vertical NOR memory strings, as illustrated in FIG. 5.

[0041] As illustrated by FIG. 5, instead of providing isolation material 640, in situ boron-doped P⁺⁺ region 520a is provided as a P⁺ body to supply holes to P⁻ channel layers 656L and 656R. In FIG. 5, an ultra-thin diffusion barrier layer 550 is also provided to prevent out-diffusion of dopants from P⁺⁺ region 520 to P⁻ channel regions 656L and 656R. Under the bias conditions of an erase operation, the holes supplied from P⁺⁺ region 520 to P⁻ channel regions 656L or 656R draw electrons trapped in charge trapping layer 634 to direct-tunnel out (as indicated by arrow 540c) into depleted P⁻ doped channel 656R or 656L. Note that, all storage transistors of a NOR memory string may be erased in parallel, if desired. (Storage transistors may be inhibited from erase by providing their gate electrodes a non-erase bias voltage or left floating).

[0042] In fact, the localized P⁺ body region of the present invention can be similarly applied to vertical 3-D NAND-type memory structures to enhance erase efficiency in NAND series transistors sharing a vertical P⁻ channel layer (“NAND memory string”). Normally, the holes at the center of a conventional memory structure for a vertical NAND memory string has a cylindrical dielectric core with a thin polysilicon P⁻ channel (e.g., 6-9 nm) provided on its surface. The dielectric core may comprise an oxide, a nitride or air). At that thickness, the P⁻ channel takes advantage of the macaroni effect seen with fully depleted P⁻ channel along the full height of the NAND memory string. In such a structure, holes may be generated, for example, using a GIDL biasing technique using designated transistors provided at the top or bottom (or both) of the memory structure. The holes thus generated make their way through the entire length of the highly resistive P⁻ channel, which is a rather inefficient process that can require milliseconds to completely erase the storage transistors of the NAND memory string. (In other conventional 3-D NAND memory strings, a P⁻ body is provided instead of the dielectric core; however, while the P⁻ body facilitates hole movements along the length of the memory structure, the advantages of the macaroni effect is sacrificed, as it is difficult to completely deplete the P⁻ body. However, providing a P⁺ body and an appropriate diffusion barrier layer to protect the P⁻ channel region in place of the dielectric core or the P⁻ body in such a memory structure, the present invention provides 3-D memory structure for NAND memory strings that can greatly improve erase efficiency.

[0043] The advantages of the present invention are numerous. For example, as shown above with respect to the examples of FIGS. 4A-4D and 5, merely by providing an additional P-doped layer or a P-doped body—which can be conveniently provided by an in situ boron-doped polysilicon or silicon germanium at a low temperature (e.g., no greater than 500° C.)—a thin P⁻-doped polysilicon layer can be used as channel material with its numerous attendant advantages, such as the macaroni effect. With a bit line-channel junction limited to the 10 nm or less thickness of P⁻ doped channel material, bipolar leakage current is well-contained. Further, by providing ultra-thin diffusion barrier layer (e.g., diffusion barrier layers 522a and 522b), dopant out-diffusion from N⁺ common source or common drain regions would not contaminate the P-doped body. Further, using the alternative step of recessing a P-doped body layer, an adverse impact on mean threshold voltage in the resulting thin-film storage transistor may be avoided. Also, by careful design of dopant profiles in the N⁺ common drain and source regions (e.g., arsenic) and in P-doped body (e.g., boron), short channel effects-may be avoided.

[0044] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.