STORING DATA SEQUENTIALLY IN ZONES IN A DISPERSED STORAGE NETWORK

[0001] Not applicable.

[0002] Not applicable.

[0003] This invention relates generally to computer networks and more particularly to dispersing error encoded data.

[0004] Computing devices are known to communicate data, process data, and/or store data. Such computing devices range from wireless smart phones, laptops, tablets, personal computers (PC), work stations, and video game devices, to data centers that support millions of web searches, stock trades, or on-line purchases every day. In general, a computing device includes a central processing unit (CPU), a memory system, user input/output interfaces, peripheral device interfaces, and an interconnecting bus structure.

[0005] As is further known, a computer may effectively extend its CPU by using “cloud computing” to perform one or more computing functions (e.g., a service, an application, an algorithm, an arithmetic logic function, etc.) on behalf of the computer. Further, for large services, applications, and/or functions, cloud computing may be performed by multiple cloud computing resources in a distributed manner to improve the response time for completion of the service, application, and/or function. For example, Hadoop is an open source software framework that supports distributed applications enabling application execution by thousands of computers.

[0006] In addition to cloud computing, a computer may use “cloud storage” as part of its memory system. As is known, cloud storage enables a user, via its computer, to store files, applications, etc. on an Internet storage system. The Internet storage system may include a RAID (redundant array of independent disks) system and/or a dispersed storage system that uses an error correction scheme to encode data for storage.

[0017] FIG. 1 is a schematic block diagram of an embodiment of a dispersed, or distributed, storage network (DSN) 10 that includes a plurality of computing devices 12 -16, a managing unit 18, an integrity processing unit 20, and a DSN memory 22. The components of the DSN 10 are coupled to a network 24, which may include one or more wireless and/or wire lined communication systems; one or more non-public intranet systems and/or public internet systems; and/or one or more local area networks (LAN) and/or wide area networks (WAN).

[0018] The DSN memory 22 includes a plurality of storage units 36 that may be located at geographically different sites (e.g., one in Chicago, one in Milwaukee, etc.), at a common site, or a combination thereof. For example, if the DSN memory 22 includes eight storage units 36, each storage unit is located at a different site. As another example, if the DSN memory 22 includes eight storage units 36, all eight storage units are located at the same site. As yet another example, if the DSN memory 22 includes eight storage units 36, a first pair of storage units are at a first common site, a second pair of storage units are at a second common site, a third pair of storage units are at a third common site, and a fourth pair of storage units are at a fourth common site. Note that a DSN memory 22 may include more or less than eight storage units 36. Further note that each storage unit 36 includes a computing core (as shown in FIG. 2, or components thereof) and a plurality of memory devices for storing dispersed error encoded data.

[0019] In various embodiments, each of the storage units operates as a distributed storage and task (DST) execution unit, and is operable to store dispersed error encoded data and/or to execute, in a distributed manner, one or more tasks on data. The tasks may be a simple function (e.g., a mathematical function, a logic function, an identify function, a find function, a search engine function, a replace function, etc.), a complex function (e.g., compression, human and/or computer language translation, text-to-voice conversion, voice-to-text conversion, etc.), multiple simple and/or complex functions, one or more algorithms, one or more applications, etc. Hereafter, a storage unit may be interchangeably referred to as a dispersed storage and task (DST) execution unit and a set of storage units may be interchangeably referred to as a set of DST execution units.

[0020] Each of the computing devices 12-16, the managing unit 18, and the integrity processing unit 20 include a computing core 26, which includes network interfaces 30-33. Computing devices 12-16 may each be a portable computing device and/or a fixed computing device. A portable computing device may be a social networking device, a gaming device, a cell phone, a smart phone, a digital assistant, a digital music player, a digital video player, a laptop computer, a handheld computer, a tablet, a video game controller, and/or any other portable device that includes a computing core. A fixed computing device may be a computer (PC), a computer server, a cable set-top box, a satellite receiver, a television set, a printer, a fax machine, home entertainment equipment, a video game console, and/or any type of home or office computing equipment. Note that each managing unit 18 and the integrity processing unit 20 may be separate computing devices, may be a common computing device, and/or may be integrated into one or more of the computing devices 12-16 and/or into one or more of the storage units 36. In various embodiments, computing devices 12-16 can include user devices and/or can be utilized by a requesting entity generating access requests, which can include requests to read or write data to storage units in the DSN.

[0021] Each interface 30, 32, and 33 includes software and hardware to support one or more communication links via the network 24 indirectly and/or directly. For example, interface 30 supports a communication link (e.g., wired, wireless, direct, via a LAN, via the network 24, etc.) between computing devices 14 and 16. As another example, interface 32 supports communication links (e.g., a wired connection, a wireless connection, a LAN connection, and/or any other type of connection to/from the network 24) between computing devices 12 & 16 and the DSN memory 22. As yet another example, interface 33 supports a communication link for each of the managing unit 18 and the integrity processing unit 20 to the network 24.

[0022] Computing devices 12 and 16 include a dispersed storage (DS) client module 34, which enables the computing device to dispersed storage error encode and decode data as subsequently described with reference to one or more of FIGS. 3-8. In this example embodiment, computing device 16 functions as a dispersed storage processing agent for computing device 14. In this role, computing device 16 dispersed storage error encodes and decodes data on behalf of computing device 14. With the use of dispersed storage error encoding and decoding, the DSN 10 is tolerant of a significant number of storage unit failures (the number of failures is based on parameters of the dispersed storage error encoding function) without loss of data and without the need for a redundant or backup copies of the data. Further, the DSN 10 stores data for an indefinite period of time without data loss and in a secure manner (e.g., the system is very resistant to unauthorized attempts at accessing the data).

[0023] In operation, the managing unit 18 performs DS management services. For example, the managing unit 18 establishes distributed data storage parameters (e.g., vault creation, distributed storage parameters, security parameters, billing information, user profile information, etc.) for computing devices 12-14 individually or as part of a group of user devices. As a specific example, the managing unit 18 coordinates creation of a vault (e.g., a virtual memory block associated with a portion of an overall namespace of the DSN) within the DSN memory 22 for a user device, a group of devices, or for public access and establishes per vault dispersed storage (DS) error encoding parameters for a vault. The managing unit 18 facilitates storage of DS error encoding parameters for each vault by updating registry information of the DSN 10, where the registry information may be stored in the DSN memory 22, a computing device 12-16, the managing unit 18, and/or the integrity processing unit 20.

[0024] The DSN managing unit 18 creates and stores user profile information (e.g., an access control list (ACL)) in local memory and/or within memory of the DSN memory 22. The user profile information includes authentication information, permissions, and/or the security parameters. The security parameters may include encryption/decryption scheme, one or more encryption keys, key generation scheme, and/or data encoding/decoding scheme.

[0025] The DSN managing unit 18 creates billing information for a particular user, a user group, a vault access, public vault access, etc. For instance, the DSN managing unit 18 tracks the number of times a user accesses a non-public vault and/or public vaults, which can be used to generate a per-access billing information. In another instance, the DSN managing unit 18 tracks the amount of data stored and/or retrieved by a user device and/or a user group, which can be used to generate a per-data-amount billing information.

[0026] As another example, the managing unit 18 performs network operations, network administration, and/or network maintenance. Network operations includes authenticating user data allocation requests (e.g., read and/or write requests), managing creation of vaults, establishing authentication credentials for user devices, adding/deleting components (e.g., user devices, storage units, and/or computing devices with a DS client module 34) to/from the DSN 10, and/or establishing authentication credentials for the storage units 36. Network administration includes monitoring devices and/or units for failures, maintaining vault information, determining device and/or unit activation status, determining device and/or unit loading, and/or determining any other system level operation that affects the performance level of the DSN 10. Network maintenance includes facilitating replacing, upgrading, repairing, and/or expanding a device and/or unit of the DSN 10.

[0027] The integrity processing unit 20 performs rebuilding of ‘bad’ or missing encoded data slices. At a high level, the integrity processing unit 20 performs rebuilding by periodically attempting to retrieve/list encoded data slices, and/or slice names of the encoded data slices, from the DSN memory 22. For retrieved encoded slices, they are checked for errors due to data corruption, outdated version, etc. If a slice includes an error, it is flagged as a ‘bad’ slice. For encoded data slices that were not received and/or not listed, they are flagged as missing slices. Bad and/or missing slices are subsequently rebuilt using other retrieved encoded data slices that are deemed to be good slices to produce rebuilt slices. The rebuilt slices are stored in the DSN memory 22.

[0028] FIG. 2 is a schematic block diagram of an embodiment of a computing core 26 that includes a processing module 50, a memory controller 52, main memory 54, a video graphics processing unit 55, an input/output (IO) controller 56, a peripheral component interconnect (PCI) interface 58, an IO interface module 60, at least one IO device interface module 62, a read only memory (ROM) basic input output system (BIOS) 64, and one or more memory interface modules. The one or more memory interface module(s) includes one or more of a universal serial bus (USB) interface module 66, a host bus adapter (HBA) interface module 68, a network interface module 70, a flash interface module 72, a hard drive interface module 74, and a DSN interface module 76.

[0029] The DSN interface module 76 functions to mimic a conventional operating system (OS) file system interface (e.g., network file system (NFS), flash file system (FFS), disk file system (DFS), file transfer protocol (FTP), web-based distributed authoring and versioning (WebDAV), etc.) and/or a block memory interface (e.g., small computer system interface (SCSI), internet small computer system interface (iSCSI), etc.). The DSN interface module 76 and/or the network interface module 70 may function as one or more of the interface 30-33 of FIG. 1. Note that the IO device interface module 62 and/or the memory interface modules 66-76 may be collectively or individually referred to as IO ports.

[0030] FIG. 3 is a schematic block diagram of an example of dispersed storage error encoding of data. When a computing device 12 or 16 has data to store it disperse storage error encodes the data in accordance with a dispersed storage error encoding process based on dispersed storage error encoding parameters. Here, the computing device stores data object 40, which can include a file (e.g., text, video, audio, etc.), or other data arrangement. The dispersed storage error encoding parameters include an encoding function (e.g., information dispersal algorithm (IDA), Reed-Solomon, Cauchy Reed-Solomon, systematic encoding, non-systematic encoding, on-line codes, etc.), a data segmenting protocol (e.g., data segment size, fixed, variable, etc.), and per data segment encoding values. The per data segment encoding values include a total, or pillar width, number (T) of encoded data slices per encoding of a data segment i.e., in a set of encoded data slices); a decode threshold number (D) of encoded data slices of a set of encoded data slices that are needed to recover the data segment; a read threshold number (R) of encoded data slices to indicate a number of encoded data slices per set to be read from storage for decoding of the data segment; and/or a write threshold number (W) to indicate a number of encoded data slices per set that must be accurately stored before the encoded data segment is deemed to have been properly stored. The dispersed storage error encoding parameters may further include slicing information (e.g., the number of encoded data slices that will be created for each data segment) and/or slice security information (e.g., per encoded data slice encryption, compression, integrity checksum, etc.).

[0031] In the present example, Cauchy Reed-Solomon has been selected as the encoding function (a generic example is shown in FIG. 4 and a specific example is shown in FIG. 5); the data segmenting protocol is to divide the data object into fixed sized data segments; and the per data segment encoding values include: a pillar width of 5, a decode threshold of 3, a read threshold of 4, and a write threshold of 4. In accordance with the data segmenting protocol, the computing device 12 or 16 divides data object 40 into a plurality of fixed sized data segments (e.g., 1 through Y of a fixed size in range of Kilo-bytes to Tera-bytes or more). The number of data segments created is dependent of the size of the data and the data segmenting protocol.

[0032] The computing device 12 or 16 then disperse storage error encodes a data segment using the selected encoding function (e.g., Cauchy Reed-Solomon) to produce a set of encoded data slices. FIG. 4 illustrates a generic Cauchy Reed-Solomon encoding function, which includes an encoding matrix (EM), a data matrix (DM), and a coded matrix (CM). The size of the encoding matrix (EM) is dependent on the pillar width number (T) and the decode threshold number (D) of selected per data segment encoding values. To produce the data matrix (DM), the data segment is divided into a plurality of data blocks and the data blocks are arranged into D number of rows with Z data blocks per row. Note that Z is a function of the number of data blocks created from the data segment and the decode threshold number (D). The coded matrix is produced by matrix multiplying the data matrix by the encoding matrix.

[0033] FIG. 5 illustrates a specific example of Cauchy Reed-Solomon encoding with a pillar number (T) of five and decode threshold number of three. In this example, a first data segment is divided into twelve data blocks (D1-D12). The coded matrix includes five rows of coded data blocks, where the first row of X11-X14 corresponds to a first encoded data slice (EDS 1_1), the second row of X21-X24 corresponds to a second encoded data slice (EDS 2_1), the third row of X31-X34 corresponds to a third encoded data slice (EDS 3_1), the fourth row of X41-X44 corresponds to a fourth encoded data slice (EDS 4_1), and the fifth row of X51-X54 corresponds to a fifth encoded data slice (EDS 5_1). Note that the second number of the EDS designation corresponds to the data segment number.

[0034] Returning to the discussion of FIG. 3, the computing device also creates a slice name (SN) for each encoded data slice (EDS) in the set of encoded data slices. A typical format for a slice name 80 is shown in FIG. 6. As shown, the slice name (SN) 80 includes a pillar number of the encoded data slice (e.g., one of 1-T), a data segment number (e.g., one of 1-Y), a vault identifier (ID), a data object identifier (ID), and may further include revision level information of the encoded data slices. The slice name functions as, at least part of, a DSN address for the encoded data slice for storage and retrieval from the DSN memory 22.

[0035] As a result of encoding, the computing device 12 or 16 produces a plurality of sets of encoded data slices, which are provided with their respective slice names to the storage units for storage. As shown, the first set of encoded data slices includes EDS 1_1 through EDS 5_1 and the first set of slice names includes SN 1_1 through SN 5_1 and the last set of encoded data slices includes EDS 1_Y through EDS 5_Y and the last set of slice names includes SN 1_Y through SN 5_Y.

[0036] FIG. 7 is a schematic block diagram of an example of dispersed storage error decoding of a data object that was dispersed storage error encoded and stored in the example of FIG. 4. In this example, the computing device 12 or 16 retrieves from the storage units at least the decode threshold number of encoded data slices per data segment. As a specific example, the computing device retrieves a read threshold number of encoded data slices.

[0037] To recover a data segment from a decode threshold number of encoded data slices, the computing device uses a decoding function as shown in FIG. 8. As shown, the decoding function is essentially an inverse of the encoding function of FIG. 4. The coded matrix includes a decode threshold number of rows (e.g., three in this example) and the decoding matrix in an inversion of the encoding matrix that includes the corresponding rows of the coded matrix. For example, if the coded matrix includes rows 1, 2, and 4, the encoding matrix is reduced to rows 1, 2, and 4, and then inverted to produce the decoding matrix.

[0038] FIG. 9 is a schematic block diagram of another embodiment of a dispersed storage network (DSN) that includes a computing device 16 of FIG. 1, the network 24 of FIG. 1, and at least one storage unit 910. The storage unit 910 can include the interface 32 of FIG. 1 and the computing core 26 of FIG. 1, and can be implemented by utilizing the storage unit 36 of FIG. 1. The storage unit 910 can include one or more memory devices 920, and each memory device 920 can be divided into a plurality of storage zones, including storage zones 922-1 and 922-2. Each storage zone can include a subset of data objects, data segments, and/or data slices stored by the memory device 920, which can include data slices 930-1, 930-2, 930-3, and 930-4. The storage unit can also include a RAM 945, which can include a volatile memory or other memory, and which can be implemented by utilizing computing core 26. The RAM 945 can include a plurality of append points, including append point 956-1 and append point 956-2, where the plurality of append points correspond to memory locations of the plurality of storage zones where the next data should be stored according to a sequential or append only write protocol. The RAM 945 can also include a plurality of pointers corresponding to data slices stored in the storage unit that include memory locations, offset information, zone information, and/or memory device information such that the corresponding data slice can be fetched from memory by utilizing its corresponding pointer. The DSN functions to store data sequentially in zones.

[0039] A major component of request latency on a DSN is the time storage units spend reading data from and writing data to memory devices. Generally, a large portion of the time a memory device spends reading or writing data is seeking to the track and sector where the requested data is located. One way to fully control memory device seeking is to bypass formatting memory devices of storage units with a filesystem and instead read and write directly on the raw memory device over supported protocols, for example, by utilizing the Small Computer System Interface (SCSI) protocol or other protocol that supports writing directly to raw memory. To support sequential writes and/or data removal, one or more memory devices 920 of a storage unit can be split into fixed-sized zones, where the storage unit utilizes a fully sequential write protocol. For example, a storage unit can be implemented by utilizing Append Optimal Storage Devices (AOSD) or other memory devices for which appended writes are the optimal form of access, and/or for which an append-only write scheme is utilized when storing data. The append-only write scheme dictates that new data objects and/or slices are written by being appended to an end, or “append point” of a zone in storage, such as storage zone 922-1 and 922-2. As data slices are written, they are written to the next space in their respective zone of memory according to the corresponding append point of the zone, and the append point is updated based on the length of newly written data, such as data slices 930-1-930-4. Append points for each zone, such as append points 956-1 and 956-2, can be maintained in a volatile memory such as RAM 945 or other memory of the storage unit, and can be stored as a pointer or other reference to the append point location of the memory device.

[0040] The storage unit can dynamically allocate new zones and un-allocate old zones of one or more memory devices to maintain a fixed number of active zones and/or a number of active zones that is determined to be optimal. The number of zones and/or the zones selected in the subset can be determined based on zone allocation parameters and/or zone reallocation parameters, which can be based on I/O request frequency, memory and/or processing requirements, I/O speed requirements, and/or other zone allocation and/or reallocation requirements. Selecting a smaller subset of zones open for write can further minimize seeking and thus improve I/O speed. In some embodiments, exactly one zone per memory device is open for writing at any given time. This can eliminates seeking on each memory device as writing is fully sequential on each memory device. In various embodiments, the active zone can be selected based on available space in the zone, based on a previously selected zone, and/or selected randomly. The storage unit can maintain information regarding which zones are designated as open to writes and/or reads, and which zones are closed to writes and/or reads, and can change these designations in response to determining a reallocation requirement is met. The storage unit can also maintain zone priority information and/or available capacity information for each of the zones. This information can be stored in RAM 945 or other memory of the storage unit.

[0041] In a purely write-based workload on a DSN, the aforementioned enhancements can reduce memory device seeking to a single time when a new zone is allocated and no further seeking will be required until a new zone needs to be allocated. There are also enhancements that can be employed with regard to reading data from memory devices. This can include maintaining pointers, such as pointers 940-1-940-3, for all data that describe exactly where on the memory device any requested data is stored, thereby reducing to a single seek for reading the data. Such pointers can be stored on a faster memory, such as a RAM 945 or other memory of the storage device. The pointers can include information about the memory device, zone, file, offset, and/or length of the data slice.

[0042] Another strategy used by storage units to facilitate faster reads includes caching reads intelligently in faster volatile memory such as RAM 945, for example on a frequency-based policy where data that is used frequently stays in the volatile memory. The read frequency of a data slice can be received from a computing device 16 or other entity via the network, for example as a priority indicator when the data is first written or later based on a change in data priority. The storage unit can also track read frequency of data slices, and can determine to move a data slice to the volatile memory when the read frequency, for example, a number of reads in a fixed time period, exceeds or otherwise compares favorably to a predefined read frequency threshold.

[0043] Another strategy used by storage units to minimize the time spent seeking during I/O includes caching incoming reads and/or writes in faster volatile memory, such as RAM 945, and/or writing larger amounts of data sequentially in batches to the persistent memory device and/or zone. Flushing data from the cache may be done on a periodic basis, for example every one second, at another fixed time interval, in response to receiving a flush requirement, and/or if the usage of the volatile memory is approaching, exceeds, or otherwise compares unfavorably to a predefined threshold. Flushing the data can include generating a large data object that includes the plurality of data slices, where the data slices are organized within the large data object based on a protocol that may or may not be sequential. The large data object is written sequentially to the persistent memory device and/or zone.

[0044] Caching incoming reads and/or writes can also be used to minimize the number and frequencies of switching between zones. While writing to one zone in a memory device, writes of new data destined for one or more other zones can be queued in one or more corresponding caches, for example, stored in RAM 945. The storage unit can queue data based on time received or other data priority requirements. The storage unit can determine which zone data is queued for based on data dependency, the size of the data, the available space in the other zones, namespace and/or mapping requirements, or other location requirements that dictate if certain data must be stored in a certain zone. In various embodiments, some or all data is queued up randomly. A storage unit can determines it is optimal to switch zones and/or select the new zone in response to cache capacity approaching, exceeding, or otherwise comparing unfavorably to a predefined cache capacity threshold. A storage unit can switch to a new zone based on data timing and/ or data dependency requirements, for example, by determining a journal entry must be written prior to some content entry, determining that a large amount of high priority data is stored in a queue, and/or determining that a data slice in a queue must be written by a certain deadline. Once the switch is performed, the storage unit can write the new data in the cache, and flush the cache of a queue destined for the new zone.

[0045] In various embodiments, a processing system a storage unit of a DSN includes at least one processor and a memory that stores operational instructions, that when executed by the at least one processor cause the processing system to select a first one of a plurality of storage zones of a memory device of the storage unit based on zone allocation parameters. The first one of the plurality of storage zones is designated as open for writes. A first data slice is received via a network for storage. The first data slice is written sequentially at a memory location of the first one of the plurality of storage zones based on determining that the first one of the plurality of storage zones is designated as open for writes. A pointer corresponding to the first data slice that indicates the first one of the plurality of storage zones and the memory location is generated. A first read request is received via the network from a requesting entity that indicates the first data slice. The first data slice is retrieved from the memory device based on the pointer, and is transmitted to the requesting entity.

[0046] FIG. 10 is a flowchart illustrating an example of storing data sequentially in zones. In particular, a method is presented for use in association with one or more functions and features described in conjunction with FIGS. 1-9, for execution by a storage unit includes a processor or via another processing system of a dispersed storage network that includes at least one processor and memory that stores instruction that configure the processor or processors to perform the steps described below. Step 1002 includes selecting a first one of a plurality of storage zones of a memory device of the storage unit based on zone allocation parameters. Step 1004 includes designating the first one of the plurality of storage zones as open for writes. Step 1006 includes receiving, via a network, a first data slice for storage. Step 1008 includes writing the first data slice sequentially at a memory location of the first one of the plurality of storage zones based on determining that the first one of the plurality of storage zones is designated as open for writes. Step 1010 includes generating a pointer corresponding to the first data slice that indicates the first one of the plurality of storage zones and the memory location. Step 1012 includes receiving, via the network, a first read request from a requesting entity that indicates the first data slice. Step 1014 includes retrieving the first data slice from the memory device based on the pointer. Step 1016 includes transmitting the first data slice to the requesting entity.

[0047] In various embodiments, the first data slice is written sequentially based on a small computer system interface protocol. In various embodiments, the first data slice is written sequentially based on an append point, and the append point is updated after the first data slice is written based on a length of the first data slice.

[0048] In various embodiments, a zone reallocation requirement is determined at a time after the first data slice is written. A second one of the plurality of storage zones that is designated as closed for writes is selected based on the zone reallocation requirement, and the second one of the plurality of storage zones is then designated as open for writes. A second data slice is received via the network for storage. The second data slice is written sequentially at a memory location of the second one of the plurality of storage zones based on determining that the second one of the plurality of storage zones is designated as open for writes.

[0049] In various embodiments, exactly one storage zone is selected and designated as open for writes based on the zone allocation parameters, where the exactly one storage zone is the first one of the plurality of storage zones. All remaining storage zones of the plurality of storage zones that are not the exactly one storage zone are designated as closed for writes. In various embodiments, a subset of storage zones is selected from the plurality of storage zones based on the zone allocation parameters. A size of the subset of storage zones is selected based on the zone allocation parameters, and the subset of storage zones includes the first one of the plurality of storage zones. The subset of storage zones is designated as open for writes. All storage zones in the plurality of storage zones that are not included in the subset of storage zones are designated as closed for writes.

[0050] In various embodiments, a subset of data slices from a plurality of data slices stored on the memory device that compare favorably to a read frequency threshold is identified. The subset of data slices is stored in a volatile memory of the storage unit, where reading the subset of data slices from the volatile memory is faster than reading the subset of data slices from the memory device. a second read request that indicates a second data slice is received via the network. The storage unit determines that the second data slice is stored in the volatile memory, and retrieves the second data slice from the volatile memory for transmission to the requesting entity via the network.

[0051] In various embodiments, a plurality of data slice write requests are received via the network, where the plurality of data slice write requests include a plurality of data slices. The plurality of data slices in a cache of the storage unit. The cache is flushed in response to a determining a cache flush requirement by generating a data object that includes the plurality of data slices, by writing the data object sequentially to the to the first one of the plurality of storage zones in response to determining the first one of the plurality of storage zones is designated as open for writes, and by removing the plurality of data slices from the cache.

[0052] In various embodiments, a subset of the plurality of storage zones that does not include the first one of the plurality of storage zones are designated as closed for writes. A plurality of data slice write requests are received via the network, where the plurality of data slice write requests includes a plurality of data slices. The plurality of data slices are stored in a cache of the storage unit, where storing the data slices includes assigning each of the plurality of data slices to one of a plurality of queues in the cache, and where each one of the plurality of queues corresponds to a storage zone in the subset of the plurality of storage zones designated as closed for writing. A zone reallocation requirement is determined after the plurality of data slices are stored in the cache. A second one of the plurality of storage zones is selected based on the zone reallocation requirement, the second one of the plurality of storage zones is included in the subset. The second one of the plurality of storage zones is designated as open for writes. A first one of the plurality of queues that corresponds to the second one of the plurality of storage zones is flushed from the cache, where the flushing includes writing the plurality of data slices in the first one of the plurality of queues sequentially to the second one of the plurality of storage zones in response to determining the second one of the plurality of storage zones is designated as open for writes and further includes deleting the first one of the plurality of queues from the cache.

[0053] In various embodiments, the zone reallocation requirement is based on a capacity of the cache comparing unfavorably to a cache capacity requirement. In various embodiments, the second one of the plurality of storage zones is selected based on a queue priority ranking corresponding to the plurality of queues, and the second one of the plurality of storage zones corresponds to a highest priority ranking of the queue priority ranking. In various embodiments, the queue priority ranking is based on a data dependency requirement, and the second one of the plurality of storage zones is assigned the highest priority ranking in response to determining that a second data slice in the second one of the plurality of storage zones must be written before a third data slice in a third one of the plurality of storage zones according to the data dependency requirement.

[0054] In various embodiments, a non-transitory computer readable storage medium includes at least one memory section that stores operational instructions that, when executed by a processing system of a dispersed storage network (DSN) that includes a processor and a memory, causes the processing system to select a first one of a plurality of storage zones of a memory device based on zone allocation parameters. The first one of the plurality of storage zones is designated as open for writes. A first data slice is received via a network for storage. The first data slice is written sequentially at a memory location of the first one of the plurality of storage zones based on determining that the first one of the plurality of storage zones is designated as open for writes. A pointer corresponding to the first data slice that indicates the first one of the plurality of storage zones and the memory location is generated. A first read request is received via the network from a requesting entity that indicates the first data slice. The first data slice is retrieved from the memory device based on the pointer, and is transmitted to the requesting entity.

[0055] It is noted that terminologies as may be used herein such as bit stream, stream, signal sequence, etc. (or their equivalents) have been used interchangeably to describe digital information whose content corresponds to any of a number of desired types (e.g., data, video, speech, audio, etc. any of which may generally be referred to as ‘data’).

[0056] As may be used herein, the terms “substantially” and “approximately” provides an industry-accepted tolerance for its corresponding term and/or relativity between items. Such an industry-accepted tolerance ranges from less than one percent to fifty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. Such relativity between items ranges from a difference of a few percent to magnitude differences. As may also be used herein, the term(s) “configured to”, “operably coupled to”, “coupled to”, and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for an example of indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”. As may even further be used herein, the term “configured to”, “operable to”, “coupled to”, or “operably coupled to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform, when activated, one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term “associated with”, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item.

[0057] As may be used herein, the term “compares favorably”, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1. As may be used herein, the term “compares unfavorably”, indicates that a comparison between two or more items, signals, etc., fails to provide the desired relationship.

[0058] As may also be used herein, the terms “processing module”, “processing circuit”, “processor”, and/or “processing unit” may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processing module, module, processing circuit, and/or processing unit may be, or further include, memory and/or an integrated memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of another processing module, module, processing circuit, and/or processing unit. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, module, processing circuit, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via a wired and/or wireless bus structure) or may be distributedly located (e.g., cloud computing via indirect coupling via a local area network and/or a wide area network). Further note that if the processing module, module, processing circuit, and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory element storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Still further note that, the memory element may store, and the processing module, module, processing circuit, and/or processing unit executes, hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the Figures. Such a memory device or memory element can be included in an article of manufacture.

[0059] One or more embodiments have been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claims. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality.

[0060] To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claims. One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.

[0061] In addition, a flow diagram may include a “start” and/or “continue” indication. The “start” and “continue” indications reflect that the steps presented can optionally be incorporated in or otherwise used in conjunction with other routines. In this context, “start” indicates the beginning of the first step presented and may be preceded by other activities not specifically shown. Further, the “continue” indication reflects that the steps presented may be performed multiple times and/or may be succeeded by other activities not specifically shown. Further, while a flow diagram indicates a particular ordering of steps, other orderings are likewise possible provided that the principles of causality are maintained.

[0062] The one or more embodiments are used herein to illustrate one or more aspects, one or more features, one or more concepts, and/or one or more examples. A physical embodiment of an apparatus, an article of manufacture, a machine, and/or of a process may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the embodiments discussed herein. Further, from figure to figure, the embodiments may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers and, as such, the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different ones.

[0063] Unless specifically stated to the contra, signals to, from, and/or between elements in a figure of any of the figures presented herein may be analog or digital, continuous time or discrete time, and single-ended or differential. For instance, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. While one or more particular architectures are described herein, other architectures can likewise be implemented that use one or more data buses not expressly shown, direct connectivity between elements, and/or indirect coupling between other elements as recognized by one of average skill in the art.

[0064] The term “module” is used in the description of one or more of the embodiments. A module implements one or more functions via a device such as a processor or other processing device or other hardware that may include or operate in association with a memory that stores operational instructions. A module may operate independently and/or in conjunction with software and/or firmware. As also used herein, a module may contain one or more sub-modules, each of which may be one or more modules.

[0065] As may further be used herein, a computer readable memory includes one or more memory elements. A memory element may be a separate memory device, multiple memory devices, or a set of memory locations within a memory device. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. The memory device may be in a form a solid state memory, a hard drive memory, cloud memory, thumb drive, server memory, computing device memory, and/or other physical medium for storing digital information.

[0066] While particular combinations of various functions and features of the one or more embodiments have been expressly described herein, other combinations of these features and functions are likewise possible. The present disclosure is not limited by the particular examples disclosed herein and expressly incorporates these other combinations.