Organic Light Emitting Diode (OLED) Display

[0001] This application claims the benefit of Republic of Korea Patent Application No. 10-2015-0138255 filed on Sep. 30, 2015, which is incorporated herein by reference for all purposes as if fully set forth herein.

[0002] Field of the Invention

[0003] The present disclosure relates to an active matrix Organic Light Emitting Diode (OLED) display.

[0004] Discussion of the Related Art

[0005] A Flat Panel Display (FPD) is widely used for a desktop monitor, a laptop, a Personal Distal Assistant (PDA), and any other mobile computer or mobile phone terminal, because the FPD can be implemented in a smaller form factor with reduced weight. The FPD includes a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), a Field Emission Display (FED), and an Organic Light Emitting Diode (OLED) display.

[0006] The OLED display has a fast response speed and a wide viewing angle, and is able to output an image with high luminous efficiency. An example structure of self-luminous OLED is shown in FIG. 1. An OLED includes, an anode electrode, a cathode electrode, and organic compound layers formed between the anode electrode and the cathode electrode. The organic compound layers include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Emission Layer (EML), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). Once a driving voltage is applied to the anode electrode and the cathode electrode, a hole having passed the HTL and an electron having passed the ETL are moved to the EML to thereby form an exciton. As a result, the EML generates visible lights.

[0007] Generally, an OLED display uses a scan transistor, which is turned on by a scan signal, to apply a data voltage to a gate electrode of a driving transistor, and enables an OLED to emit light using the data voltage supplied to the driving transistor. In addition, the OLED display uses an emission control signal to perform switching of a transistor coupled to the driving transistor and a high-potential voltage input terminal.

[0008] Driving circuits generating a scan signal and an emission control signal may be formed in a Gate In Pale (GIP) method in a bezel area of a display panel. However, it is difficult to reduce the size of the bezel area because of a GIP circuit.

[0009] An Organic Light Emitting Diode (OLED) display according to the present disclosure includes a plurality of pixels and a shift register which drives transistors arranged in the pixels. The plurality of pixels include a first group of pixels disposed on a first row, and a second group of pixels disposed on a second row. The shift register applies a first scan signal to the first group of pixels and the second group of pixels simultaneously. In addition, the shift register applies a second scan signal to the first group of pixels and the second group of pixels sequentially.

[0010] In one or more embodiments, each of the plurality of pixels comprises an OLED, a driving transistor including a gate electrode connected to a first node, a drain electrode connected to a second node, and a source electrode connected to a third node, the driving transistor configured to control a driving current supplied to the OLED, a first transistor connected between the first node and the second node, and a second transistor connected between the third node and a respective data line. The shift register comprises a first scan signal stage configured to, simultaneously, apply a first scan signal to first transistors of the first group of pixels and first transistors of the second group of pixels, and a second scan signal stage configured to apply a second scan signal to second transistors of the first group of pixels and subsequently apply the second scan signal to second transistors of the second group of pixels.

[0011] In one or more embodiments, the first scan signal causes the first transistors of the first group of pixels and the first transistors of the second group of pixels to be turned on simultaneously to cause driving transistors of the first group of pixels and driving transistors of the second group of pixels to be diode-connected.

[0012] In one or more embodiments, the second scan signal stage is configured to apply the second scan signal to the second transistors of the first group of pixels and subsequently apply the second scan signal to the second transistors of the second group of pixels, while the first scan signal stage applies the first scan signal to the first transistors of the first group of pixels and the first transistors of the second group of pixels.

[0013] In one or more embodiments, each of the plurality of pixels further comprises a capacitor coupled between the first node and a fourth node, the OLED coupled to the fourth node, the driving transistor to control the driving current according to charges stored in the capacitor, and a third transistor coupled between the fourth node and an initialization voltage input terminal, the initialization voltage input terminal to supply an initialization voltage. Third transistors of the first group of pixels and third transistors of the second group of pixels may be simultaneously turned on in response to the first scan signal to apply the initialization voltage to capacitors of the first group of pixels and capacitors of the second group of pixels.

[0014] In one or more embodiments, the first scan signal stage is configured to turn on the first transistors of the first group of pixels and the first transistors of the second group of pixels for a period, the period comprising a first sub-period, a second sub-period, and a third sub-period. During the first sub-period, the second scan signal stage may be configured to turn off the second transistors of the first group of pixels and the second transistors of the second group of pixels. During the second sub-period, the second scan signal stage may be configured to turn on the second transistors of the first group of pixels and to turn off the second transistors of the second group of pixels. During the third sub-period, the second scan signal stage may be configured to turn off the second transistors of the first group of pixels and to turn on the second transistors of the second group of pixels.

[0015] In one or more embodiments, the plurality of pixels further comprise a third group of pixels disposed on a third row adjacent to the first row, the first row disposed between the second row and the third row. During the first sub-period, the first scan signal stage may be configured to turn on first transistors of the third group of pixels, the first transistors of the first group of pixels, and the first transistors of the second group of pixels. During the second sub-period and the third sub-period, the first scan signal stage may be configured to turn on the first transistors of the first group of pixels, and the first transistors of the second group of pixels, and to turn off the first transistors of the third group of pixels.

[0016] In one or more embodiments, each of the plurality of pixels further comprises a fourth transistor coupled between the second node and a high-potential voltage input terminal, the high-potential voltage input terminal to supply a high-potential voltage; and a fifth transistor coupled between the third node and the OLED.

[0017] In one or more embodiments, the shift register further comprises an emission control signal stage configured to, during the first sub-period, turn off fourth transistors of the third group of pixels and turn off fifth transistors of the third group of pixels, turn on fourth transistors of the first group of pixels and turn off fifth transistors of the first group of pixels, and turn on fourth transistors of the second group of pixels and turn on fifth transistors of the second group of pixels.

[0018] In one or more embodiments, the emission control signal stage is further configured to, during the second sub-period, turn off the fourth transistors of the third group of pixels and turn on the fifth transistors of the third group of pixels, turn off the fourth transistors of the first group of pixels and turn off the fifth transistors of the first group of pixels, and turn on the fourth transistors of the second group of pixels and turn off the fifth transistors of the second group of pixels.

[0019] One or more embodiments relate to a method of displaying an image by the OLED display. The method comprises: simultaneously applying, by a first scan signal stage of the shift register, a first scan signal to first transistors of the first group of pixels and first transistors of the second group of pixels; and sequentially applying, by a second scan signal stage of the shift register, a second scan signal to second transistors of the first group of pixels and second transistors of the second group of pixels.

[0030] Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, and the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings and redundant descriptions thereof will be omitted. In embodiments of the present disclosure, transistors of a pixel are all implemented as N-type transistors. However, aspects of the present disclosure are not limited thereto, and the transistors may be implemented as P-type transistors.

[0031] FIG. 2 is a diagram illustrating an Organic Light Emitting Diode (OLED) display according to an embodiment of the present disclosure.

[0032] Referring to FIG. 2, the OLED display according an embodiment of the present disclosure includes a display panel 100 in which pixels P are arranged in matrix, a data driver 120, a gate driver comprising a level shifter 130 and a shift register 140, and a timing controller 110.

[0033] The display panel 100 includes a display portion 100A in which the pixels P are arranged to display an image, and a non-display portion 100B in which a shift register 140 is arranged and which does not display an image.

[0034] A plurality of pixels P are included in the display portion 100A, and an image is displayed based on gray scales displayed by the pixels P. The pixels P are arranged along the first horizontal line HL1 to a n-th horizontal line HLn.

[0035] Each of the pixels P is connected to a corresponding data line DL arranged along a column line, and to a corresponding gate line GL arranged along a horizontal line HL disposed in a row. As illustrated in FIG. 2, the gate line GL includes a first scan line SL1, a second scan line SL2, and an emission control signal line EML. In addition, each of the pixels P includes an OLED, a driving transistor DT, and first to fifth transistors T1 to T5, and a storage capacitor Cst. Each of the transistors DT and T1 to T5 may be implemented as an oxide Thin Film Transistor (TFT) including an oxide semiconductor layer. However, aspects of the present disclosure are not limited thereto, and the semiconductor layer of a transistor may be formed of an amorphous silicon semiconductor or an oxide semiconductor.

[0036] The timing controller 110 is configured to control operation timing of the data driver 120 and the gate driver comprising the level shifter 130 and the shift register 140. To this end, the timing controller 110 realigns digital video data RGB, which is received from the outside, to fit the resolution of the display panel 100, and supplies the realigned digital video data RGB to the data driver 120. In addition, the timing controller 110 generates a control signal DDC for controlling operation timing of the data driver 120, and a gate control signal GDC for controlling operation timing of the gate driver, based on timing signals, such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK, and a data enable signal DE.

[0037] The data driver 120 is configured to drive data lines DL. To this end, based on the data control signal DDC, the data driver 120 converts digital video data RGB, which is received from the timing controller 110, into an analog data voltage, and supplies the analog data voltage to the data lines DL.

[0038] The gate driver includes a level shifter 130 and a shift register 140. The level shifter 130 is formed as an Integrated Circuit (IC) on a Printed Circuit Board (PCB) (now shown) connected to the display panel 100. The shift register 140 is formed on the non-display portion 100B of the display panel 100 by using a Gate In Panel (GIP) scheme.

[0039] The level shifter 130 performs level shifting of the clock signals CLK and a start signal VST under the control of the timing controller 110, and supplies the level-shifted clock signals CLK and the level-shifted start signal VST to the shift register 140. The shift register 140 is formed as a combination of multiple TFTs (hereinafter referred to simply as transistors) in the non-display portion 100B of the display panel 100 by using the GIP scheme. The shift register 140 is comprised of stages which shift scan signals and output the shifted scan signals in response to the clock signals CLK and the start signal VST.

[0040] Referring to FIG. 3, there is shown a stage of the shift register 140 for driving pixels Pj arranged along a j-th horizontal line and pixels Pj+1 arranged along a (j+1)-th horizontal line. As shown in FIG. 4, the pixels arranged along the j-th horizontal line include a j-th emission control signal line EML(j) and a (j+1)-th emission control signal line EML(j+1).

[0041] To drive the pixels arranged along the two adjacent horizontal lines HLj and HL(j+1), the shift register 140 includes a j-th first scan signal stage SCAN1_STG(j), a j-th second scan signal stage SCAN2_STG(j), a (j+1)-th second scan signal stage SCAN2_STG(j+1), a j-th emission control signal stage EM_STG(j), and a (j+1)-th emission control signal stage EM_STG(j+1).

[0042] The j-th first scan signal stage SCAN1_STG(j) generates a j-th first scan signal SCAN1(j), and applies the j-th first scan signal SCAN1(j) to a j-th first scan line SL1(j) arranged along a j-th horizontal line and to a (j+1)-th first scan line SL1(j+1) arranged along a (j+1)-th horizontal line.

[0043] The j-th second scan signal stage SCAN2_STG(j) generates a j-th second scan signal SCAN2(j), and applies the j-th second scan signal SCAN2(j) to a j-th second scan line SL2(j) arranged along the j-th horizontal line.

[0044] The (j+1)-th second scan signal stage SCAN2_STG(j+1) generates a (j+1)-th second scan signal SCAN(j+1), and applies the (j+1)-th second scan signal SCAN(j+1) to a (j+1)-th second scan line SL2(j+1) arranged along a (j+1)-th horizontal line.

[0045] The j-th emission control signal stage EM_STG(j) generates a j-th emission control EM(j), and applies the j-th emission control EM(j) to a j-th emission control signal line EML(j) arranged along the j-th horizontal line and to a (j−1)-th emission control signal line EML(j−1) arranged along a (j−1)-th horizontal line.

[0046] As such, a first scan signal is applied to the pixels Pj and Pj+1 arranged along a pair of two adjacent horizontal lines, so it is possible to drive pixels arranged along n number of horizontal lines using n/2 number of the first scan signal stages. That is, it is possible to reduce the entire area of the shift register 140 and thus reduce a bezel area of the non-display portion 100B.

[0047] FIG. 3 is a waveform diagram showing a pixel structure according to an embodiment of the present disclosure. FIG. 4 is a waveform diagram showing a data signal and a gate signal applied to a pixel shown in FIG. 3.

[0048] Referring to FIG. 3, each pixel PXL arranged on a j-th pixel line (j indicates a natural number) includes an OLED, a driving transistor DT, first to fifth transistors T1 to T5, and a storage capacitor Cst.

[0049] The OLED emits light by a driving current supplied from the driving transistor DT. As shown in FIG. 1, multiple organic compound layers are formed between an anode electrode and a cathode electrode of the OLED. The organic compound layers include Hole Injection Layers (HIL), Hole Transport Layers (HTL), Emission Layers (EML), Electron Transport Layers (ETL), and Electron Injection Layers (EIL). The anode electrode of the OLED is connected to a node D, and a cathode electrode of the OLED is connected to an input terminal of low-potential driving voltage ELVSS.

[0050] The driving transistor DT uses its gate-source voltage Vgs to control a driving current applied to the OLED. The driving transistor DT includes a gate electrode connected to a node A, a drain electrode connected to a node B, and a source electrode connected to a node C.

[0051] The first transistor T1 is connected between the node A and the node B, and turned on/off in accordance with a first scan signal SCAN1. The first transistor T1 includes a gate electrode connected to the j-th first scan line SL1(j) to which the first scan signal SCAN1 is applied, a drain electrode connected to the node B, and a source electrode connected to the node A.

[0052] The second transistor T2 is connected between the node D and an input terminal of an initialization voltage Vinit, and turned on/off in accordance with a j-th first scan signal SCAN1(j). The second transistor T2 includes a gate electrode connected to the j-th first scan line SL(j) to which the j-th first scan signal SCAN1(j) is applied, a drain electrode connected to the node D, and a source electrode connected to the input terminal of the initialization voltage Vinit.

[0053] The third transistor T3 is connected between a data line DL and the node C, and turned on/off in accordance with a j-th second scan signal SCAN2(j). The third transistor T3 includes a gate electrode connected to the j-th second scan line SL2(j) to which the second scan signal SCAN2(j) is applied, a drain electrode connected to the data line DL, and a source electrode connected to the node C.

[0054] The fourth transistor T4 is connected between an input terminal of the high-potential voltage VDD and the node B, and turned on/off in accordance with a (j+1)-th emission control signal EM(j+1). The fourth transistor T4 includes a gate electrode connected to a (j+1)-th emission control signal line EML(j+1) to which a (j+1)-th emission control signal EM(j+1) is applied, a drain electrode connected to the input terminal of the high-potential voltage VDD, and a source electrode connected to the node B.

[0055] The fifth transistor T5 is connected between the node D and the node C, and turned on/off in accordance with a j-th emission control signal EM(j). The fifth transistor T5 includes a gate electrode connected to the j-th emission control signal line EML(j) to which the j-th emission control signal EM(j) is applied, a drain electrode connected to the node C, and a source electrode connected to the node D.

[0056] The storage capacitor Cst is connected between the node A and the node D.

[0057] Followings are descriptions about an operation of a pixel P in the above-described structure. FIG. 5 is a waveform diagram showing signals EM, SCAN, and DATA applied to the pixel shown in FIG. 4. In the drawings, a j-th horizontal period jH indicates a scanning period of pixels P arranged along a j-th horizontal line HLj.

[0058] FIGS. 6A to 6C are equivalent circuits of a pixel P in an initialization period Pi, a sampling period Ps, and an emission period Pe. In FIGS. 6A to 6C, a solid line indicates an activated element or a connected current path, and a dotted line indicates an inactivated element or a disconnected current path.

[0059] As shown in FIG. 5, one frame period may be divided into: the initialization period Pi for initializing the node A and the node D; the sampling period Ps for sampling a threshold voltage of the driving transistor DT and storing the sampled threshold voltage in the node A; and the emission period Pe for programming a gate-source voltage of the driving transistor DT based on the sampled threshold voltage, and driving the OLED to emit light by a driving current according to the programmed gate-source voltage.

[0060] The present disclosure initializes pixels arranged along the j-th horizontal line HLj in a (j−1)-th horizontal period (j−1)H, so that a j-th horizontal period jH may be spent only for sampling operation. If the sampling period Ps is secured long enough, it is possible to more accurately sample a threshold voltage of the driving transistor DT.

[0061] Followings are descriptions about an operation of pixels arranged along the j-th horizontal line HLj.

[0062] During the initialization period Pi, a j-th first scan signal SCAN1(j) and a (j+1)-th emission control signal EM(j+1) are applied at on level, and a j-th second scan signal SCAN2(j) and a j-th emission control signal EM(j) are applied at off level. In the initialization period Pi, the first and second transistors T1 and T2 are turned on in response to the j-th first scan signal SCAN1(j), and the fourth transistor T4 is turned on in response to the (j+1)-th emission control signal EM(j+1). Accordingly, the node A is initialized to the high-potential voltage VDD, and the node D is initialized to the initialization voltage Vinit. The reason that the nodes A and D are initialized before sampling operation is to prevent unnecessary emission of the OLED. To this end, the initialization voltage Vinit is selected from a voltage range sufficiently lower than a driving voltage of the OLED. That is, the initialization voltage Vinit may be set to be equal to or lower than the low-potential voltage VSS.

[0063] During the sampling period Ps, the j-th first scan signal SCAN1(j) and the j-th second scan signal SCAN1(j) are applied with on level, and the j-th emission control signal EM(j) and the (j+1)-th emission control signal EM(j+1) are applied with off level. In the sampling period Ps, the first and second transistors T1 and T2 are turned on in response to the j-th first scan signal SCAN1(j), and the third transistor T3 is turned on in response to the j-th second scan signal SCAN2(j). Accordingly, the driving transistor DT is diode-connected (which means that a gate electrode and a drain electrode of the driving transistor DT are short-circuited, so the driving transistor DT acts as a diode), and a data voltage Vdata(j) is applied to the node C. Here, a sufficiently low voltage such that Vdata(j)<VDD-Vth is applied, thus the driving transistor DT may be turned on in the sampling period Ps. In the sampling period Ps, a current Ids flows between the drain electrode and the source electrode of the driving transistor DT, and the potential of the node A is reduced by the current Ids to Vdata(j)+Vth which is the sum of the data voltage Vdata(j) and a threshold voltage Vth of the driving transistor DT.

[0064] The j-th first scan signal SCAN1(j) and the j-th second scan signal SCAN2(j) are applied at off level in the emission period Pe, and the j-th emission control signal EM(j) and the (j+1)-th emission control signal EM(j+1) are applied at on level after one horizontal period 1H has elapsed from the beginning in time of the emission period Pe.

[0065] In the emission period Pe, the fourth transistor T4 is turned on in response to the (j+1)-th emission control signal EM(j+1), thereby connecting the high-potential voltage VDD to the drain electrode of the driving transistor DT. In addition, in the emission period Pe, the fifth transistor T5 is turned on in response to the j-th emission control signal EM(j), thereby causing the potential of the nodes C and D to be equal to an operation voltage Voled of the OLED.

[0066] In the emission period Pe, the potential of the node D is changed from the initialization voltage Vinit to the operation voltage Voled of the OLED. In the emission period Pe, the node A is floating and coupled to the node D through the storage capacitor Cst. As a result, the potential of the node A is also changed from the voltage Vdata(j)+Vth set in the sampling period Ps according to the variation in the potential of the node D Voled−Vinit. That is, the potential of the node C and node D are set to “Voled”, and accordingly the gate-source voltage Vgs, which is the gate voltage Vg of the driving transistor DT subtracted by the source voltage Vs thereof, is programmed to be “Vdata(j)+Vth-Vinit.”

[0067] The function regarding a driving current Ioled flowing in the OLED in the emission period Pe is expressed as in Equation 1 as below. The OLED emits light according to the driving current, thereby producing a desired gray scale.

$\begin{array}{cc}\begin{array}{c}\mathrm{Ioled}={\frac{k}{2}\left[\left(\mathrm{Vgs}-\mathrm{Vth}\right)\right]}^2\\ ={\frac{k}{2}\left[\mathrm{Vdata}\left(n\right)-\mathrm{Vinit}\right]}^2\end{array}& \left[\mathrm{Equation}1\right]\end{array}$

[0068] In Equation 1, k denotes a proportional factor that is determined by electron mobility of the driving transistor DT, parasitic capacitance, and a channel capacity.

[0069] The expression of the driving current Ioled is k/2(Vgs−Vth)², but the gate-source voltage Vgs programmed in the emission period Pe already includes a threshold voltage component Vth of the driving transistor DT. Thus, as shown in Equation 1, the threshold voltage component Vth of the transistor DT is removed from the expression of the driving current Ioled. Accordingly, any variation in the threshold voltage Vth may not affect the driving current Ioled.

[0070] Meanwhile, another factor deteriorating luminance uniformity of an OLED display is deviation of high-potential voltage VDD applied to each pixel. However, the present disclosure does not include a high potential voltage component VDD in the expression of the driving voltage Ioled, so that any influence of the deviation of the high-potential voltage VDD does not affect the driving current Ioled.

[0071] FIG. 7 is a diagram illustrating a pixel structure according to another embodiment of the present disclosure, and FIG. 8 is a diagram illustrating a shift register for driving a pixel P shown in FIG. 7.

[0072] In the above embodiments, the fourth transistor T4 receives an emission control signal generated by a rear-end stage. That is, a (j+1)-th emission control signal EM1(j+1) is applied to the fourth transistors of pixels arranged along a j-th horizontal line, and to the fifth transistors of pixels arranged along a (j+1)-th horizontal line. One horizontal period immediately after the end of a sampling period of the j-th horizontal line corresponds to a sampling period of the (j+1)-th horizontal line. In the sampling period of the (j+1)-th horizontal line, a fifth transistor T5 has to be maintained turned-off, so an emission period of the j-th horizontal line starts one horizontal period after the sampling period ends. In the pixel structure shown in FIG. 7, an emission control signal is applied to each individual pixel arranged along each horizontal line, and thus, an emission period starts immediately after a sampling period ends.

[0073] Referring to FIGS. 7 and 8, a pixel structure according to another embodiment of the present disclosure, and a shift register for driving the pixel are described in the following. In FIGS. 7 and 8, constituent elements, components or structures substantially identical to those shown in the aforementioned examples are indicated by the same reference numerals, and detailed descriptions thereof are herein omitted.

[0074] In FIG. 7, the fourths transistors T4 of pixels Pj arranged along a j-th horizontal line are turned on or off by a j-th second emission control signal EM2(j). The fifth transistors T5 of the pixels Pj arranged along the j-th horizontal line are turned on or off by a j-th first emission control signal EM1(j). Referring to FIG. 8, the j-th first emission control signal EM1(j) is generated by a j-th first emission control stage EM1 STG(j), and the j-th second emission control signal EM2(j) is generated by a j-th second emission control signal stage EM2 STG(j).

[0075] FIG. 9 is a diagram illustrating timing of signals EM, SCAN, and DATA applied to a pixel P shown in FIG. 7. A method for driving the pixel P shown in FIG. 7 using the signals shown in FIG. 9 is substantially identical to the describe above with respect to FIGS. 3 through 6.

[0076] That is, in the initialization period Pi of pixels Pj arranged along a j-th horizontal line, a first scan signal SCAN1(j) is used to turn on the first and second transistors T1 and T2, thereby initializing the node A and the node D.

[0077] In the sampling period Ps, the first scan signal SCAN1(j) and a j-th second scan signal SCAN2(j) are used to cause the driving transistor DT to be diode-connected.

[0078] In the emission period Pe, a j-th first emission control signal EM1(j) and a j-th second emission control signal EM2(j) are used to set the nodes C and D to a driving voltage of the OLED and then supply a current to the OLED.

[0079] Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.