ENCRYPTION OF EXECUTABLES IN COMPUTATIONAL MEMORY

[0001] The present disclosure relates generally to semiconductor memory and methods, and more particularly, to encryption of executables in computational memory.

[0002] Memory devices are typically provided as internal, semiconductor, integrated circuits in computing devices or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., user data, error data, etc.) and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

[0003] Computing systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units (e.g., herein referred to as functional unit circuitry (FUC)) such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can execute instructions to perform logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on data (e.g., one or more operands).

[0004] A number of components in a computing system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be generated, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed to perform the logical operations) may be stored in a memory array that is accessible by the FUC. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the FUC begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the FUC, intermediate results of the operations and/or data may also be sequenced and/or buffered. In many instances, the processing resources (e.g., processor and/or associated FUC) may be external to the memory array, and data can be accessed (e.g., via a bus between the processing resources and the memory array) to execute instructions. Data can be moved from the memory array to registers external to the memory array via a bus.

[0011] Most modern computer architectures use a register-memory technique, where operations are executed in two separate domains. Logical operations (e.g., arithmetic, flow control, and combinatorial operations) are generally executed on a number of register files. Memory operations (e.g., load, store, etc.) are generally executed on memory devices. Instructions in register-memory architectures utilize register indices or memory addresses to indicate how/where to perform an operation.

[0012] Computational memory, such as processing in memory (PIM) or processing near memory devices can be classified as memory-memory devices in computing architecture taxonomies. In computational memory, both logical operations and memory operations are performed on the memory devices in-situ. Instructions in memory-memory architectures use physical addresses to indicate how/where to perform an operation.

[0013] Attempts to attack or insert malicious software into a computing system usually include a virus or malware that alters the instruction flow or instructions executed by the host processor. Some embodiments of the present disclosure use computational memory to encrypt executables (executable instructions such as host processor instructions). The encryption can polymorphically randomize the executables such that an attacker would have to know the encryption state to inject malevolent software that would have a negative effect on such a system. Randomization of executables can obfuscate and/or change the executable to create an ecosystem of binary diversity, which can reduce and/or eliminate a source of malware and/or system compromises. Any malicious software that attempts to inject code (e.g., binary injection, buffer overflow attacks, Morris worm, Code Red, Blaster Virus, uniform resource locator (URL) heap exploits, etc.) would have to understand the underlying instruction set architecture in order to run code.

[0014] The present disclosure is related to encryption of executables in computational memory. Computational memory can traverse an operating system page table in the computational memory for a page marked as executable. In response to finding a page marked as executable, the computational memory can determine whether the page marked as executable has been encrypted. In response to determining that the page marked as executable is not encrypted, the computational memory can generate a key for the page marked as executable. The computational memory can encrypt the page marked as executable using the key. Some embodiments of the present disclosure provide encryption for executables, but not data, which advantageously allows data to be changed, read, written, etc. without an encryption and/or decryption process, while providing protection for executables, which may be the target of particular attacks. Executable instructions are referred to generally herein as executables.

[0015] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “M” and “N”, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory devices can refer to one or more memory devices). As used herein, the terms “first” and “second” are used to differentiate between one feature from another and do not necessarily imply an order between the features so designated.

[0016] The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 110 may reference element “10” in FIG. 1, and a similar element may be referenced as 210 in FIG. 2. Multiple analogous elements within one figure may be referenced with a reference numeral followed by a hyphen and another numeral or a letter. For example, 240-1 may reference element 20-1 in FIGS. 2 and 240-N may reference element 40-N, which can be analogous to element 240-1. Such analogous elements may be generally referenced without the hyphen and extra numeral or letter. For example, elements 240-1, . . . , 240-N may be generally referenced as 240. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

[0017] FIG. 1 is a block diagram of an apparatus in the form of a computing system 100 including at least one computational memory system 104 in accordance with a number of embodiments of the present disclosure. As used herein, a host 102, a computational memory system 104, a computational memory device 110, a memory array 111, and/or sensing circuitry 124, including sensing amplifiers and compute circuitry might each also be separately considered an “apparatus.”

[0018] The computing system 100 can include a host 102 coupled to the computational memory system 104, which includes a computational memory device 110 (e.g., including a memory array 111 and/or sensing circuitry 124). The computational memory system 104 can act as a conventional memory and/or a computational memory. The host 102 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. The host 102 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry), such as central processing unit (CPU) 106. The CPU 106 can be coupled to mass storage 114. The mass storage 114 can be a storage device or other media not directly accessible by the CPU 106 such as hard disk drives, solid state drives, optical disc drives, and can be non-volatile memory. In some embodiments, the mass storage 114 can be external to the host 102. The host 102 can be configured with an operating system. The operating system is executable instructions (software) that manages hardware resources and provides services other executable instructions (applications) that run on the operating system. The operating system can implement a virtual memory system.

[0019] The CPU 106 can include a logic unit 118 coupled to a translation lookaside buffer (TLB) 120 and CPU cache 122. An example of a logic unit 118 is an arithmetic logic unit (ALU), which is a circuit that can perform arithmetic and bitwise logic operations on integer binary numbers. A number of ALUs can be used to function as a floating point unit (FPU), which is a circuit that operates on floating point numbers and/or a graphics processing unit (GPU), which is a circuit that accelerates the creation of images in a frame buffer intended for output to a display. The TLB 120 is a cache that memory management hardware can use to improve virtual address translation speed. The TLB 120 can be a content addressable memory, where the search key is a virtual address and the search result is a physical address. As described in more detail with respect to FIGS. 3-5, the TLB 120 can include operating system page table entries, which map virtual addresses to physical addresses and the operating system page table can be stored in memory (e.g., in the memory array 130). The CPU cache 122 can be an intermediate stage between relatively faster registers and relatively slower main memory (not specifically illustrated). Data to be operated on by the CPU 106 may be copied to CPU cache 122 before being placed in a register, where the operations can be effected by the logic unit 118. Although not specifically illustrated, the CPU cache 122 can be a multilevel hierarchical cache.

[0020] The computing system 100 can include separate integrated circuits or both the host 102 and the computational memory system 104 can be on the same integrated circuit. The computing system 100 can be, for instance, a server system and/or a high performance computing system and/or a portion thereof. Although the example shown in FIG. 1 illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures (e.g., a Turing machine), which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

[0021] For clarity, the computing system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 111 can be a hybrid memory cube (HMC), computational memory such as a processing in memory random access memory (PIMRAM) array, which can include one or more of a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The memory array 111 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although a single computational memory device 110 is shown in FIG. 1, embodiments are not so limited. For instance, the computational memory system 104 may include a number of computational memory devices 110 (e.g., a number of banks of DRAM cells).

[0022] The computational memory system 104 can include address circuitry 126 to latch address signals provided over an input/output “I/O” bus 138 (e.g., data bus and/or address bus) through I/O circuitry 130 (e.g., provided to external ALU circuitry and to DRAM DQs via local I/O lines and global I/O lines). Address signals can be received and decoded by a row decoder 128 and a column decoder 134 to access the computational memory device 110. Data can be read from the memory array 111 by sensing voltage and/or current changes on the sense lines using sensing circuitry 124. The sensing circuitry 124 can read and latch a page (e.g., row) of data from the memory array 111. The I/O circuitry 130 can be used for bi-directional data communication with host 102 over the I/O bus 138. The write circuitry 132 can be used to write data to the computational memory device 110.

[0023] Controller 108 can decode signals provided by control bus 136 from the host 102. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control memory operations performed on the computational memory device 110, including data read, data write, and data erase operations. The signals can also be used to control logical operations performed on the computational memory device 110 including arithmetic, flow control, and combinatorial operations, among others. In various embodiments, the controller 108 is responsible for executing instructions from the host 102. The controller 108 can be a state machine, a sequencer, a processor, and/or other control circuitry.

[0024] In some previous approaches, data associated with a logical operation, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and/or global I/O lines). The external ALU circuitry could include a number of registers and would perform logical operations using the data (which may be referred to as operands or inputs), and the result would be transferred back to the array via the I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry 124 is configured to perform logical operations on data stored in memory array 111 and store the result back to the memory array 111 without enabling an I/O line (e.g., a local I/O line) coupled to the sensing circuitry 124. Enabling an I/O line can include enabling (e.g., turning on) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. However, embodiments are not limited to not enabling an I/O line. For instance, in a number of embodiments, the sensing circuitry 124 can be used to perform logical operations without enabling column decode lines of the array; however, the local I/O line(s) may be enabled in order to transfer a result to a suitable location other than back to the array 111 (e.g., to an external register).

[0025] As such, in a number of embodiments, circuitry external to array 111 and sensing circuitry 124 is not needed to perform the logical operation as the sensing circuitry 124 can be operated to perform the logical operation using the address space of the memory array 111 without the use of an external processing resource. Therefore, the sensing circuitry 124 may be used to complement and/or to replace, at least to some extent, such an external processing resource (or at least the bandwidth consumption of such an external processing resource).

[0026] The sensing circuitry 124 can be formed on pitch with the memory cells of the array. Although not specifically illustrated, in some embodiments, additional peripheral sense amplifiers and/or logic (e.g., function components that each store instructions for execution of a logical function) can be coupled to the sensing circuitry 124. The sensing circuitry 124 and the peripheral sense amplifier and logic can cooperate in performing logical operations, according to embodiments described herein.

[0027] However, in a number of embodiments, the sensing circuitry 124 may be used to perform logical operations (e.g., to execute instructions) in addition to logical operations performed by an external processing resource (e.g., host 102). For instance, host 102 and/or sensing circuitry 124 may be limited to performing only certain logical operations and/or a certain number of logical operations.

[0028] An example of the sensing circuitry 124 is described further below in association with FIG. 2. For instance, in a number of embodiments, the sensing circuitry 124 can comprise a number of sense amplifiers and a number of compute components, which may comprise a latch serving as an accumulator and that can be used to perform logical operations (e.g., on data associated with complementary sense lines). Logical operations can include Boolean operations (e.g., AND, OR, NOR, XOR, etc.), combinations of Boolean operations to perform other mathematical operations, as well as non-Boolean operations. In a number of embodiments, the sensing circuitry 124 can be used to perform logical operations using data stored in the memory array 111 as inputs and store the results of the logical operations back to the memory array 111 without transferring via a sense line address access (e.g., without firing a column decode signal). As such, a logical operation can be performed using sensing circuitry 124 rather than and/or in addition to being performed by processing resources external to the sensing circuitry 124 (e.g., by the host CPU 106 and/or other processing circuitry, such as ALU circuitry, located on the computational memory system 104, such as on the controller 108, or elsewhere).

[0029] FIG. 2 is a schematic diagram of a portion of a computational memory device 210 in accordance with a number of embodiments of the present disclosure. The computational memory device 210 is analogous to the computational memory device 110 illustrated in FIG. 1. The computational memory device 210 can include a memory array 211 that includes memory cells 240-1, 240-2, 240-3, 240-4, 240-5, 240-6, 240-7, 240-8, . . . , 240-N coupled to rows of access lines 242-1, 242-2, 242-3, 242-4, 242-5, 242-6, 242-7, . . . , 242-M and columns of sense lines 244-1, 244-2, 244-3, 244-4, 244-5, 244-6, 244-7, 244-8, . . . , 244-N. The memory array 211 is not limited to a particular number of access lines and/or sense lines, and use of the terms “rows” and “columns” does not intend a particular physical structure and/or orientation of the access lines and/or sense lines. Although not pictured, each column of memory cells can be associated with a corresponding pair of complementary sense lines.

[0030] Each column of memory cells can be coupled to sensing circuitry 224, which can be analogous to sensing circuitry 124 illustrated in FIG. 1. In this example, the sensing circuitry includes a number of sense amplifiers 246-1, 246-2, 246-3, 246-4, 246-5, 246-6, 246-7, 246-8, . . . , 246-N coupled to the respective sense lines 244. The sense amplifiers 246 are coupled to input/output (I/O) line 254 (e.g., a local I/O line) via access devices (e.g., transistors) 250-1, 250-2, 250-3, 250-4, 250-5, 250-6, 250-7, 250-8, . . . , 250-N. In this example, the sensing circuitry also includes a number of compute components 248-1, 248-2, 248-3, 248-4, 248-5, 248-6, 248-7, 248-8, . . . , 248-N coupled to the respective sense lines 244. Column decode lines 252-1, 252-2, 252-3, 252-4, 252-5, 252-6, 252-7, 252-8, . . . , 252-N are coupled to the gates of access devices 250 respectively, and can be selectively activated to transfer data sensed by respective sense amps 246 and/or stored in respective compute components 248 to a secondary sense amplifier 256. In a number of embodiments, the compute components 248 can be formed on pitch with the memory cells of their corresponding columns and/or with the corresponding sense amplifiers 246.

[0031] In a number of embodiments, the sensing circuitry (e.g., compute components 248 and sense amplifiers 246) is configured to perform a number of logical operations on elements stored in array 211. As an example, a first plurality of elements can be stored in a first group of memory cells coupled to a particular access line (e.g., access line 242-1) and to a number of sense lines 244, and a second plurality of elements can be stored in a second group of memory cells coupled to a different access line (e.g., access line 242-2) and the respective number of sense lines 244. Each element of the first plurality of elements can have a logical operation performed thereon with a respective one of the second plurality of elements, and the result of the logical operation can be stored (e.g., as a bit-vector) in a third group of memory cells coupled to a particular access line (e.g., access line 242-3) and to the number of sense lines 244.

[0032] FIG. 3 is a block flow diagram illustrating a read or write access according to a number of embodiments of the present disclosure. FIGS. 3-6 illustrate different flow diagrams representing operations for analogous architectures. FIG. 3 includes an illustration of a mass storage device 314, which is analogous to the mass storage 114 described with respect to FIG. 1. The functionality of the mass storage device 314 is described in more detail with respect to FIG. 4. FIG. 3 includes a CPU 306, which is analogous to the CPU 106 illustrated in FIG. 1. The CPU 306 is illustrated as including a logic unit 318, TLB 320, and CPU cache 322. FIG. 3 includes a computational memory system 304 including I/O circuitry 330, memory array 311, and computational memory system cache 312. The computational memory system cache 312 is described in more detail with respect to FIGS. 5-6. The memory system 304 is analogous to the memory system 104 illustrated in FIG. 1. The memory system 304 is illustrated as including an operating system page table 316. Although the operating system page table 316 can be stored in the memory array 311, it is illustrated separately for ease of illustration and explanation. Likewise, the computational memory program 342 can be stored in the memory array 311, but is illustrated separately to highlight the functional flows described with respect to FIGS. 3-6. The memory system 304 can include an entropy source 340 as described in more detail below.

[0033] Some embodiments of the present disclosure can keep the CPU 306 and underlying architecture unchanged from what is conventional for CPUs. However, the computational memory system 304 can operate differently, and/or an operating system of a host can operate differently from what is conventional. Conventionally, the operating system can maintain an operating system page table, however according to the present disclosure, the computational memory system 304 can maintain an operating system page table 316 because the computational memory system 304 can encrypt and/or decrypt pages stored in memory and indicate the same in the operating system page table and can generate and store keys in the operating system page table for encrypted pages. The computational memory system 304 can generate a new key for an encrypted page and re-encrypt the page on the fly. The host CPU 306 can include a TLB 320 in its memory hierarchy, but the operating system page table 316 is stored in the memory array 311. On a page miss (e.g., when executables are loaded to the memory array 311) pages can be demand loaded from mass storage 314 and loaded and placed in reserved areas of physical and virtual memory. The reservation can be managed by the operating system and maintained in the operating system page table 316. The operating system page table 316 can be located in a reserved area of the memory array 311. For example, in an ARM architecture, the ARM memory management unit (MMU) can use registers TTB0 and TTB1 to point to the operating system page tables to allow for hardware walking of the tables in the event of a page fault.

[0034] As the operating system page table 316 is located in the memory array 311, the computational memory system 304 has programmatic access to the operating system page table 316 structures, meaning that the computational memory system 304 can make changes to the operating system page table 316. The operating system page table 316 can include a number of fields that indicate information about pages referenced by the operating system page table 316. Such fields can include an encryption indication field 346, a key field 348, a virtual address field 350, a physical address field 352, a page type field 354, and/or a size field 356. The encryption indication field 346 can indicate whether the corresponding page is encrypted (e.g., by a bit value of 1 for yes or a bit value of 0 for no). The key field 348 can store a key for the corresponding page if the corresponding page is encrypted. If the corresponding page is not encrypted, a key may not be stored in the key field 348 for the corresponding page as it would be unnecessary. The virtual address field 350 can store a virtual address corresponding to the page. The physical address field 352 can store a physical address corresponding to the page. The page type field 352 can mark the type of the corresponding page (e.g., read “R”, write “W”, read/write “R/W”, or executable “X”). The type of the page indicates, among other things, whether the page stores data or executables. The size field 356 can indicate a size of the corresponding page (e.g., 4k). An example of a table is shown in Table 1.

TABLE 1
					Page
Encrypted	Key	Virtual	Physical	Type	Size
1	0xA8F01 . . .	0x80010000	0x01000000	X	4k
0	NA	0x40A00000	0x01100000	R	1 MB
1	0xBB16B . . .	0x80080000	0x01080000	X	4k
0	NA	0x60A08000	0x00001000	R/W	4k

[0035] In some embodiments, the operating system page table 316 may not be cached so as to preserve coherence between information in the operating system page table 316, the CPU 306, and the memory array 311. The computational memory system 304 can be configured (e.g., programmed) to traverse the operating system page table 316 in the memory array 311 (e.g., for a page marked as executable). For example, the computational memory system 304 can include a computational memory program 342 that can handle traversing the operating system page table 316. Pages referenced in the operating system page table 316 can store either data or executables. Thus, a page referenced in the operating system page table 316 can be marked as executable by a marking in the page type field 354. Page types read, write, and read/write can mark data pages (a page that stores data) and page type executable can mark a page that is executable (a page that store executable instructions).

[0036] The computational memory system 304 can be configured to encrypt and/or decrypt executables. For example, the computational memory system 304 can include a computational memory program 342 that can handle encryption and/or decryption of executables. In some embodiments the computational memory program 342 can handle encryption and/or decryption of executables as they are populated in the computational memory system 304 during a page fault and/or as they are read from the computational memory system 304 (e.g., during a cache line refill from the CPU 306). An indication of whether a page is encrypted can be stored in the encryption indication field 346. In some embodiments, the host operating system can launch the computational memory program 342 in the computational memory system 304 (e.g., on startup) as indicated by the line between the I/O circuitry 330 and the computational memory program 342. After the computational memory program 342 is running, the responsibility of the host operating system can end with respect to encryption.

[0037] The computational memory system 304 can include an entropy source 340 that can generate a key and/or be used to generate a key for a page marked as executable to encrypt the page with the key. The key can be generated based on a random number or near-random number generated with the entropy source 340. An example of the entropy source 340 is a phase-locked loop (PLL) frequency (e.g., a PLL clock), which can be sampled to generate a number to be used as a key. An example of the entropy source 340 is a serial number associated with the computational memory system 304, which can be sampled to generate a number to be used as a key and/or used as input to an algorithm that generates another value, which can be sampled (or used), to generate a number to be used as a key. An example of the entropy source 340 is a timer, which can be sampled to generate a number to be used as a key. In some embodiments, a key can be generated with a sampled PLL frequency exclusive or (XOR) with a sampled serial number XOR with a sampled timer. The computational memory system 304 can be configured to use unique keys generated with the entropy source 340 to encrypt or re-encrypt pages in the memory array 311. Other entropy sources and/or combinations of entropy sources can be used to generate a random or near-random number.

[0038] As described above, for data read or write operations, encryption, according to the present disclosure, is not necessary. The computational memory program 442 can grant access to a data page (a page marked as read, write, and/or read/write) in the operating system page table 316 without regard to encryption. Accordingly, a data page 358 can be transferred through I/O circuitry 330 between the memory array 311 and the CPU 306 (e.g., via the CPU cache 322) and stored in the memory array 311 or read from the memory array 311. For example, in a read/write operation, a virtual memory address (e.g., “A”) from the TLB 320 can be transmitted from and/or to the computational memory system 304 and retrieved from and/or stored in the virtual address field 350 for the first table entry 344 corresponding to the data page 358 that is being written. A physical address (e.g., “B”) corresponding to the virtual address can be retrieved from and/or stored in the physical address field 352 for the first table entry 344. This is indicated by the line running between the first table entry 344 and the TLB 320. Because what is being transferred is a data page 358 rather than executables, the computational memory program 342 can mark the page as not being encrypted (e.g., “0”) in the encryption indication field 346 of the first table entry 344 as indicated by the line between the computational memory program 342 and the first table entry 344. The computational memory program may not store a key in the key field 348 (e.g., “N/A”) of the first table entry 344 because it corresponds to a data page 358 that is not encrypted. The computational memory program 342 can store an indication that the data page 358 is read/write (e.g., “R/W”) in the page type field 354 and an indication of the page size (e.g., “4k”) in the size field 356.

[0039] FIG. 4 is a block flow diagram illustrating a new page allocation according to a number of embodiments of the present disclosure. FIG. 4 includes an illustration of a mass storage device 414 including executables 461. FIG. 4 includes a CPU 406 including a logic unit 418, TLB 420, and CPU cache 422. FIG. 4 includes a computational memory system 404 including I/O circuitry 430, memory array 411, computational memory system cache 412, operating system page table 416, computational memory program 442, and entropy source 440.

[0040] The mass storage 414 can store executables 461 for the CPU 406. The executables 461 can be loaded into the memory array 411 by direct memory access (DMA) from the mass storage device 414 as indicated by the arrow from the mass storage device 414 through the I/O circuitry 430 to the memory array 411. Initially, the executables 461 from the mass storage device 414 are stored in the memory array 411 as a plaintext executable page 462 because they were not encrypted in the mass storage device 414. The computational memory program 442 can create a second table entry 460 in the operating system page table 416 to correspond to the plaintext executable page 462 in the memory array 411.

[0041] Because the plaintext executable page 462 has not yet been encrypted, the computational memory program 442 can mark the plaintext executable page 462 as not being encrypted (e.g., “0”) in the encryption indication field 446 of the second table entry 460. Likewise, a key is not stored in the key field 448 of the second table entry 460 (e.g., “-”). A virtual memory address (e.g., “C”) from the TLB 420 can be transmitted to the computational memory system 404 and stored in the virtual address field 450 for the second table entry 460. A physical address (e.g., “D”) corresponding to the virtual address can be stored in the physical address field 452 for the second table entry 460. This is indicated by the line running between the second table entry 460 and the TLB 420. The computational memory program can mark the plaintext executable page 462 as executable (e.g., “X”) in the type field 454 of the second table entry 460 as indicated by the line between the computational memory program 442 and the second table entry 460. The correspondence between the plaintext executable page 462 not being encrypted and the indication as such is illustrated by the line between the memory array 411 and the second table entry 460. The computational memory program 442 can store an indication of the page size (e.g., “4k”) in the size field 456.

[0042] FIG. 5 is a block flow diagram illustrating encryption of executables according to a number of embodiments of the present disclosure. FIG. 5 includes an illustration of a mass storage device 514. FIG. 5 includes a CPU 506 including a logic unit 518, TLB 520, and CPU cache 522. FIG. 5 includes a computational memory system 504 including I/O circuitry 530, memory array 511, computational memory system cache 512, operating system page table 516, computational memory program 542, and entropy source 540.

[0043] In FIG. 4, the executable 461 from the mass storage device 414 was initially stored in the memory array 411 as a plaintext executable 462. However, in FIG. 5, the computational memory program 542 can generate a key for the plaintext executable 462 using entropy source 540 and encrypt it to a ciphertext executable 564 and store it back to the memory array 511. Some examples of the encryption included advanced encryption standard (AES), such as AES 128 bit encryption, AES 256 bit encryption, etc., and data encryption standard (DES), among others. The computational memory program 542 can delete the second table entry 460 for the plaintext executable 462 and create a third table entry 563 for the ciphertext executable 564.

[0044] The computational memory program 542 can mark the ciphertext executable page 564 as being encrypted (e.g., “1”) in the encryption indication field 546 of the third table entry 563. This is indicated by the line between the computational memory program 542 and the third table entry 563. The key generated to encrypt the page can be stored in the key field 548 of the third table entry 563 (e.g., “XYZ”). This is indicated by the line from the entropy source 540 through the computational memory program 542 to the key field 548 in the third table entry 563. The virtual memory address (e.g., “C”) in the virtual address field 550, the physical address (e.g., “D”) in the physical address field 552, the type (e.g., “X”) in the type field 554, and the size (e.g., “4k”) in the size field 556 for the third table entry 563 can remain the same as for the second table entry 460, however embodiments are not so limited, as, for example, the physical address could change.

[0045] The computational memory program 542 can copy the plaintext executable 462 (as illustrated in FIG. 4) before encrypting it as the ciphertext executable 564 and store it as plaintext executable 566 in the memory system cache 512. This is indicated by the lines between the computational memory 542, the ciphertext executable 564 and the plaintext executable 566. The computational memory system cache 512 can be a non-addressable (e.g., secure) area of the computational memory (e.g., of the computational memory system 504 and/or the memory array 511). The computational memory system cache 512 being non-addressable (e.g., by a host or DMA device, etc.) can secure the plaintext executable 566 because malevolent software cannot be injected by an external device such as a host or DMA device. The plaintext executable 566 in the computational memory system cache 512 can be used to satisfy additional instruction requests from the host and to hide some of the latency that may be caused by operation of the computational memory program 542. This is illustrated by the line from the plaintext executable 566 to the CPU 506.

[0046] The computational memory program 542 can traverse the operating system page table 516 (e.g., outside of any host operation and/or during idle time of the computational memory system 504 and/or the operating system page table 516) looking for pages marked as executable. In some embodiments, the computational memory program 542 can traverse the operating system page table 516 in response to receiving an instruction from a host in association with a page access (e.g., for a requested page). In response to finding a page marked as executable, the computational memory program 542 can determine whether the page marked as executable has been encrypted. Determining whether the requested page has been encrypted can be by reference to the operating system page table 516 that indicates whether pages are encrypted (e.g., by the encryption indication field 546) and whether pages are executable (e.g., by the type field 554). In response to determining that the page marked as executable is not encrypted, the computational memory program 542 can generate a key for the page marked as executable and encrypt the page using the key. The encrypted page can be stored in place of the unencrypted page (in place of the requested page where the encryption operation is in response to a request from a host). Finding a page marked as executable that has not been encrypted can imply that at some point the computational memory system 504 encountered a page fault and demand loaded a page into the memory array 511. Advantageously, the computational memory program 542 can remedy this by encrypting the page with a uniquely generated key so that it is more resilient to injection attacks.

[0047] In response to determining that the page marked as executable is encrypted, the computational memory program 542 can continue traversing the operating system page table 516 for an additional page marked as executable. In response to finding an additional page marked as executable, the computational memory program 542 can determine whether the additional page marked as executable has been encrypted. If the additional page marked as executable has not been encrypted, the computational memory program 542 can generate a different key and encrypt the additional page marked as executable using the different key. The computational memory program 542 can continue traversing the operating system page table 516 for any page marked as executable and encrypt those executables that are not encrypted. Each encrypted page referenced in the operating system memory table 516 that is encrypted can be encrypted with a unique key, such that each key in the key field 548 of the operating system page table 516 is unique (no two keys are the same).

[0048] In some embodiments, in response to determining that the page marked as executable is encrypted, the computational memory program 542 can generate a new key, re-encrypt the requested page using the new key, and store the re-encrypted page in place of the requested page in the memory array 511. The key field 548 for the requested page can be updated with the new key. The re-encrypted page can be decrypted (using the key) and stored in the memory system cache 512 as plaintext.

[0049] FIG. 6 is a block flow diagram illustrating a subsequent access to an encrypted executable according to a number of embodiments of the present disclosure. FIG. 6 includes an illustration of a mass storage device 614. FIG. 6 includes a CPU 606 including a logic unit 618, TLB 620, and CPU cache 622. FIG. 6 includes a computational memory system 604 including I/O circuitry 630, memory array 611, computational memory system cache 612, operating system page table 616, computational memory program 642, and entropy source 640.

[0050] The memory array 611 is illustrated with the ciphertext executable 644, which corresponds to the ciphertext executable 564 illustrated in FIG. 5. In response to a request for the page marked as executable (e.g., the ciphertext page 664), the computational memory program 642 can generate a new key (with the entropy source 640), re-encrypt the page marked as executable using the new key, and store it in place of the page marked as executable. This is illustrated by the lines between the computational memory program 642 and the ciphertext executable 664 and the ciphertext executable 668, which represents the re-encrypted page marked as executable. The x-out of the ciphertext executable 664 represents the ciphertext executable 668 being stored in its place. The computational memory program 642 can delete the third table entry 563 for the ciphertext executable 564 and create a fourth table entry 665 for the ciphertext executable 668.

[0051] The computational memory program 642 can mark the ciphertext executable page 668 as being encrypted (e.g., “1”) in the encryption indication field 646 of the fourth table entry 665. The new key generated to encrypt the page can be stored in the key field 648 of the fourth table entry 665 (e.g., “PQR”). This is indicated by the line from the entropy source 640 through the computational memory program 642 to the key field 648 in the fourth table entry 665. The virtual memory address (e.g., “C”) in the virtual address field 650, the physical address (e.g., “D”) in the physical address field 652, the type (e.g., “X”) in the type field 654, and the size (e.g., “4k”) in the size field 556 for the fourth table entry 665 can remain the same as for the third table entry 563, however embodiments are not so limited, as, for example, the physical address could change.

[0052] Although not specifically illustrated in FIG. 6, a new page of executables can be received (e.g., from a host or DMA device) and the computational memory program 642 can generate a new key for the new page (with the entropy source 640). The new page can be encrypted with the new key and stored in the memory array 611. The computational memory program 642 can create a new entry in the operating system page table 616 for the new page, including marking the new page as executable and encrypted.

[0053] In some embodiments, the computational memory program 642 can decrypt the re-encrypted page (e.g., the ciphertext executable 668) and store the decrypted page (e.g., as plaintext executable 670) in the computational memory system cache 612 for transfer (e.g., to a host or DMA device) to satisfy a request (to a source of the request). This is illustrated by the lines between the computational memory program 642, the plaintext executable 670, and the ciphertext executable 668 as well as the line between the plaintext executable 670 and the CPU 606. In some embodiments, decrypted executables or unencrypted executables are transferred through the I/O circuitry 630 to a requesting device from the computational memory system cache 612 rather than from the memory array 611 to prevent any injected code from being sent along with the executables as there is no mechanism for injecting code to the computational memory system cache 612. Even if ciphertext executables in the memory array 611 are injected with malicious code, the decryption of the executable will render the injected code meaningless because it would not have been injected in an encrypted form with the same key used to encrypt the executable. Therefore the decryption process would compromise the malicious code. The executable with the compromised malicious code may not function for its intended purpose (it may generate an error), but the malicious code will not execute (e.g., it may cause a halt, prefetch abort, or crowbar the pipeline), but the virus would not spread.

[0054] Although not specifically illustrated as such, a non-transitory computing device readable medium for storing executable instructions can include all forms of volatile and non-volatile memory, including, by way of example, semiconductor memory devices, DRAM, PIM, HMC, EPROM, EEPROM, flash memory devices, magnetic disks such as fixed, floppy, and removable disks, other magnetic media including tape, optical media such as compact discs (CDs), digital versatile discs (DVDs), and Blu-Ray discs (BD). The instructions may be supplemented by, or incorporated in, ASICs. For example, any one or more of the secondary storage 114, the CPU cache 122, and/or the memory array 111 illustrated in FIG. 1, can be a non-transitory computing device readable medium.

[0055] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

[0056] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.