ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR DRIVING THE SAME

[0001] This application claims the benefit of Korea Patent Application No. 10-2014-0194442 filed on Dec. 30, 2014, which is incorporated herein by reference for all purposes as if fully set forth herein.

[0002] 1. Field

[0003] The present disclosure relates to an organic light emitting diode display driven through a digital driving method and a method for driving the same.

[0004] 2. Discussion of Related Art

[0005] Because an organic light emitting diode display (hereinafter, referred to as “OLED display”) is a self-emission display device, the OLED display may be manufactured to have lower power consumption and thinner profile than a liquid crystal display which requires a backlight unit. Further, the OLED display has advantages of a wide viewing angle and a fast response time and thus has expanded its market while competing with the liquid crystal display.

[0006] The OLED display is driven through an analog voltage driving method or a digital driving method and using grayscale values of an input image. The analog voltage driving method adjusts a data voltage applied to pixels based on data gray values of the input image and adjusts a luminance of the pixels based on a magnitude of the data voltage, thereby representing grayscale of the input image. The digital driving method adjusts an emission time of the pixels based on the data gray values of the input image, thereby representing grayscale of the input image.

[0007] As shown in FIGS. 1 and 2, the digital driving method time-divides one frame into a plurality of subframes SF1 to SF6. Each subframe represents one bit of input image data. As shown in FIG. 1, each subframe may include a writing time ADT, during which data is written on pixels, and an emission time EMT, during which the pixels emit light. As shown in FIG. 2, each subframe may further include an erase time ERT, during which the pixels are turned off, in addition to the writing time ADT and the emission time EMT. The emission times of the subframes may have different lengths. However, all of the subframes are the same as one another in a scan direction for writing the data and an erase direction for turning off the pixels. In addition, a writing speed for writing the data and an erase speed for turning off the pixels in each subframe are the same as each other. Therefore, the emission time of the same subframe is uniform irrespective of a position of the display panel.

[0008] Because the emission time of the same subframe is uniform, there should be negligible luminance deviation across pixels irrespective of the position of the pixel within the display panel. However, as shown in FIG. 3, because variations IR drop resulting from varying line resistances occur in the display panel, a high potential power voltage EVDD varies depending on a spatial position of the display panel to thereby generate the luminance deviation. The luminance implemented in the display panel decreases as the display panel is far from an input terminal of the high potential power voltage EVDD.

[0009] In the analog voltage driving method, a driving thin film transistor (TFT) is driven in a saturation region. As shown in FIG. 4, the saturation region is a voltage region, in which a drain-source current Ids does not substantially change as a function of a drain-source voltage Vds of the driving TFT, and is positioned on the right side of the Vds-Ids plane (for values of Vds above a threshold). In other words, in the saturation region, the drain-source current Ids does not change although the high potential power voltage EVDD (i.e., the drain-source voltage Vds of the driving TFT) changes.

[0010] On the other hand, in the digital driving method, the driving TFT is driven in an active region, so as to reduce power consumption. As shown in FIG. 4, the active region indicates a voltage region, in which the drain-source current Ids changes depending on the drain-source voltage Vds of the driving TFT, and is positioned on the left side of the Vds-Ids plane (for values of Vds below a threshold). In other words, in the active region, the drain-source current Ids changes depending on changes in the high potential power voltage EVDD (i.e., the drain-source voltage Vds of the driving TFT).

[0011] For this reason, the luminance deviation resulting from the IR drop is more of a problem in the digital driving method than the analog voltage driving method.

[0012] Accordingly, the present disclosure provides an organic light emitting diode display driven through a digital driving method and a method for driving the same capable of reducing (e.g., minimizing) a luminance deviation resulting from variable IR drops across signal lines.

[0013] An organic light emitting diode display comprises a display panel including a plurality of pixels; a display panel driver configured to drive signal lines of the display panel; and a timing controller configured to divide one frame into a plurality of subframes, divide data of an input image at each bit, map the data of the input image to the plurality of subframes, control an operation of the display panel driver, and differently adjust a writing speed for writing data and an erase speed for turning off the pixels in at least one compensation frame of the plurality of subframes.

[0014] Some embodiments provide a method for driving an organic light emitting diode display that includes a display panel including a plurality of pixels, and a display panel driver driving signal lines of the display panel. The method comprising dividing one frame into a plurality of subframes, dividing data of an input image at each bit, and mapping the data of the input image to the plurality of subframes; and controlling an operation of the display panel driver and differently adjusting a writing speed for writing data and an erase speed for turning off the pixels in at least one compensation frame of the plurality of subframes.

[0030] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the like reference numbers will be used throughout the drawings to refer to the like parts.

[0031] FIGS. 5 to 7 show an organic light emitting diode display (hereinafter, referred to as “OLED display”) according to an embodiment.

[0032] Referring to FIGS. 5 to 7, the OLED display according to an embodiment includes a display panel 10, display panel drivers 12, 13, and 14 for writing pixel data of an input image on a pixel array of the display panel 10, and a timing controller 11 for controlling the display panel drivers 12, 13, and 14.

[0033] On the pixel array of the display panel 10, a plurality of data lines 15 and a plurality of first and second gate lines 16 and 17 cross each other. The pixel array of the display panel 10 includes pixels PIX, that are arranged in a matrix form and display the input image. Each pixel PIX may be one of a red (R) pixel, a green (G) pixel, a blue (B) pixel, and a white (W) pixel. As shown in FIG. 7, each pixel PIX may include a plurality of thin film transistors (TFTs), an organic light emitting diode (OLED), a capacitor, and the like.

[0034] The display panel drivers 12, 13, and 14 include a data driver 12, and first and second gate drivers 13 and 14.

[0035] The data driver 12 generates a data voltage SVdata based on data RGB of the input image received from the timing controller 11 and outputs the data voltage SVdata to the data lines 15. In a digital driving method, an amount of light emitted by the pixels PIX is uniform, and grayscale of the data RGB is represented through an amount of emission time, during which the pixels PIX emit light. Therefore, the data driver 12 selects one of a voltage (hereinafter, referred to as “on-voltage”) satisfying an emission condition of the pixels PIX and a voltage (hereinafter, referred to as “off-voltage”) not satisfying the emission condition of the pixels PIX depending on digital values of the data RGB mapped to the subframe, and generates the data voltage SVdata.

[0036] The first gate driver 13 sequentially supplies a scan pulse (or a gate pulse) SP synchronized with the data voltage SVdata of the data driver 12 to the first gate lines 16 (i.e., 161 to 16n) under the control of the timing controller 11. The first gate driver 13 sequentially shifts the scan pulse SP and sequentially selects the pixels PIX, to which the data voltage SVdata is applied, on a per line basis.

[0037] The second gate driver 14 sequentially supplies an erase pulse EP to the second gate lines 17 (i.e., 171 to 17n) under the control of the timing controller 11. The pixels PIX stop emitting light in response to the erase pulse EP. The timing controller 11 controls application timing of the erase pulse EP and controls an emission time of each subframe.

[0038] The timing controller 11 receives the pixel data RGB of the input image and timing signals synchronized with the pixel data RGB from a host system (not shown). The timing controller 11 controls operation timing of the data driver 12 and operation timing of the gate drivers 13 and 14 based on the timing signals synchronized with the pixel data RGB of the input image. The timing signals include a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE, a dot clock DCLK, and the like. The timing controller 11 generates a source timing control signal DDC controlling the operation timing of the data driver 12, a first gate timing control signal GDC controlling the operation timing of the first gate driver 13, and a second gate timing control signal EDC controlling the operation timing of the second gate driver 14.

[0039] The timing controller 11 controls the display panel drivers 12, 13, and 14 through the digital driving method. The timing controller 11 divides one frame into a plurality of subframes. Lengths of the emission times of the subframes may be differently set depending on a data bit of the input image. For example, the most significant bit (MSB) represents a highest gray level and thus may be mapped to the subframe having the longest emission time, and the least significant bit (LSB) represents a lowest gray level and thus may be mapped to the subframe having the shortest emission time. The timing controller 11 maps the data RGB of the input image to the subframe at each bit and transmits the data RGB to the data driver 12.

[0040] As shown in FIGS. 8, 10, 12, and 14, each subframe may further include an erase time ERT, during which the pixels PIX are turned off, as well as a writing time ADT, during which the data is written on the pixels PIX, and an emission time EMT, during which the pixels PIX emit light. As described above, the emission times EMT of the subframes may have different lengths.

[0041] The timing controller 11 controls operations of the display panel drivers 12, 13, and 14 and differently adjusts a writing speed for the data write (indicating the application of the data voltage) and an erase speed for turning off the pixels PIX in at least one compensation subframe of the plurality of subframes. Hence, the timing controller 11 differently adjusts emission times of upper and lower display lines of the display panel 10 and can suppress a luminance deviation resulting from IR drop depending on a position of the display panel 10. This is described in detail later with reference to FIGS. 8 to 13.

[0042] The timing controller 11 controls the operations of the display panel drivers 12, 13, and 14 and reversely adjusts a scan direction for the data write and an erase direction for turning off the pixels PIX in at least one compensation subframe of the plurality of subframes. Hence, the timing controller 11 differently adjusts emission times of the upper and lower display lines of the display panel 10 and can suppress the luminance deviation resulting from the IR drop depending on the position of the display panel 10. This is described in detail later with reference to FIGS. 14 to 15C.

[0043] The host system may be implemented as one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

[0044] As shown in FIG. 7, each pixel PIX includes an OLED, a driving TFT DT, a first switching TFT ST1, a second switching TFT ST2, a storage capacitor Cst, and the like.

[0045] The OLED has a stack structure of organic compound layers including a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, an electron injection layer EIL, etc. The OLED generates light when electrons and holes combine in the emission layer EML.

[0046] The driving TFT DT operates in the active region shown in FIG. 4 and makes the OLED emit light. The driving TFT DT is connected between a power line, to which a high potential power voltage EVDD is supplied, and the OLED and switches on or off a current flowing in the OLED depending on a voltage state of a gate node Ng. The driving TFT DT is turned on when the gate node Ng is in an on-voltage state, and applies a driving current to the OLED, thereby making the OLED emit light. The driving TFT DT is turned off when the gate node Ng is in an off-voltage state, and cuts off the driving current applied to the OLED, thereby turning off the OLED. Namely, the OLED does not emit light.

[0047] The first switching TFT ST1 is turned on in response to the scan pulse SP from the first gate line 16. The first switching TFT ST1 supplies the data voltage SVdata of the on-voltage or the off-voltage to the gate node Ng in response to the scan pulse SP.

[0048] The second switching TFT ST2 is turned on in response to the erase pulse EP from the second gate line 17. The second switching TFT ST2 makes a voltage of the gate node Ng in an off-voltage state in response to the erase pulse EP.

[0049] The storage capacitor Cst maintains the voltage of the gate node Ng of the driving TFT DT.

[0050] Each pixel PIX of the display panel 10 according to an embodiment is not limited to the structure shown in FIG. 7 and may have any pixel structure capable of performing the digital driving method.

[0051] FIG. 8 shows an example where an erase speed and a writing speed in a specific compensation subframe are differently adjusted as a method for minimizing the luminance deviation resulting from the variable IR drop. FIG. 9 shows that a total application time of the scan signals and a total application time of the erase signals in the specific compensation subframe are differently controlled so as to implement the method shown in FIG. 8.

[0052] As shown in FIG. 8, in the OLED display according to an embodiment, the high potential power voltage EVDD for driving the pixels is applied to the display panel 10 from the upper side UP of the display panel 10, and the data write may be sequentially performed from the upper side UP to the lower side DOWN of the display panel 10 in a sequential line manner. In this instance, a luminance at the lower side DOWN of the display panel 10 may be less than a luminance at the upper side UP of the display panel 10 because of the IR drop.

[0053] To remove the luminance deviation depending on the position of the display panel 10, the timing controller 11 controls the operations of the display panel drivers 12, 13, and 14 such that an erase speed for turning off the pixels is slower than a writing speed for the data write in at least one compensation subframe (for example, SF4) of a plurality of subframes belonging to one frame. Hence, as it goes from the upper side UP to the lower side DOWN of the display panel 10, the emission time EMT may gradually increase.

[0054] The writing speed is determined in inverse proportion to a total application time of the scan signals for writing the data in the compensation subframe SF4, and the erase speed is determined in inverse proportion to a total application time of the erase signals for turning off the pixels in the compensation subframe SF4.

[0055] As shown in FIG. 9, the timing controller 11 may cause a total application time Te of erase signals EP1 to EPn to be longer than a total application time Ts of scan signals SP1 to SPn, so that the erase speed is slower than the writing speed in the compensation subframe SF4. For this, the timing controller 11 may cause a first gate shift clock GSC1, that forms the basis of the generation of the scan signals SP1 to SPn, to have a first pulse period P1 and cause a second gate shift clock GSC2, that forms the basis of the generation of the erase signals EP1 to EPn, to have a second pulse period P2 longer than the first pulse period P1.

[0056] The first gate driver 13 receives the first gate shift clock GSC1, a first gate start pulse GSP1, and a first gate output enable signal GOE1 from the timing controller 11 and generates the scan signals SP1 to SPn in synchronization with a rising edge of the first gate shift clock GSC1. The first gate driver 13 sequentially supplies the scan signals SP1 to SPn to the first gate lines 16 and scans the display lines of the display panel 10 in a forward direction during the total scanning time Ts.

[0057] The second gate driver 14 receives the second gate shift clock GSC2, a second gate start pulse GSP2, and a second gate output enable signal GOE2 from the timing controller 11 and generates the erase signals EP1 to EPn in synchronization with a rising edge of the second gate shift clock GSC2. The second gate driver 14 sequentially supplies the erase signals EP1 to EPn to the second gate lines 17 and erases the display lines of the display panel 10 in the forward direction during the total erase time Te longer than the total scanning time Ts.

[0058] As described above, this causes the erase speed to be slower than the writing speed when the high potential power voltage EVDD is applied to the display panel 10 from the upper side UP of the display panel 10 as shown in FIG. 8, and gradually increases the emission time EMT as it goes from the upper side UP to the lower side DOWN of the display panel 10, thereby removing the luminance deviation resulting from the IR drop depending on the position of the display panel 10.

[0059] FIG. 10 shows another example where an erase speed and a writing speed in a specific compensation subframe are differently adjusted as a method for minimizing the luminance deviation resulting from variations in IR drop across signal lines for pixels of the panel. FIG. 11 shows that a total application time of the scan signals and a total application time of the erase signals in the specific compensation subframe are differently controlled (e.g., varied) so as to implement the method shown in FIG. 10.

[0060] As shown in FIG. 10, in the OLED display according to a further embodiment, the high potential power voltage EVDD for driving the pixels is applied to the display panel 10 from the lower side DOWN of the display panel 10, and the data write may be sequentially performed from the upper side UP to the lower side DOWN of the display panel 10 in the sequential line manner. In this instance, a luminance at the upper side UP of the display panel 10 may be less than a luminance at the lower side DOWN of the display panel 10 because of the IR drop.

[0061] To remove the luminance deviation depending on the position of the display panel 10, the timing controller 11 controls the operations of the display panel drivers 12, 13, and 14 such that an erase speed for turning off the pixels is faster than a writing speed for the data write in at least one compensation subframe (for example, SF4) of a plurality of subframes belonging to one frame. Hence, progressing from the lower side (labeled in FIG. 10 as DOWN) to the upper side (labeled in FIG. 10 as UP) of the display panel 10, the emission time EMT may gradually increase.

[0062] As shown in FIG. 11, the timing controller 11 may cause a total application time Te of the erase signals EP1 to EPn to be shorter than a total application time Ts of the scan signals SP1 to SPn, so that the erase speed is faster than the writing speed in the compensation subframe SF4. For this, the timing controller 11 may cause a first gate shift clock GSC1, that forms the basis of the generation of the scan signals SP1 to SPn, to have a first pulse period P1 and cause a second gate shift clock GSC2, that forms the basis of the generation of the erase signals EP1 to EPn, to have a second pulse period P2 shorter than the first pulse period P1.

[0063] The first gate driver 13 receives the first gate shift clock GSC1, a first gate start pulse GSP1, and a first gate output enable signal GOE1 from the timing controller 11 and generates the scan signals SP1 to SPn in synchronization with a rising edge of the first gate shift clock GSC1. The first gate driver 13 sequentially supplies the scan signals SP1 to SPn to the first gate lines 16 and scans the display lines of the display panel 10 in the forward direction during the total scanning time Ts.

[0064] The second gate driver 14 receives the second gate shift clock GSC2, a second gate start pulse GSP2, and a second gate output enable signal GOE2 from the timing controller 11 and generates the erase signals EP1 to EPn in synchronization with a rising edge of the second gate shift clock GSC2. The second gate driver 14 sequentially supplies the erase signals EP1 to EPn to the second gate lines 17 and erases the display lines of the display panel 10 in the forward direction during the total erase time Te shorter than the total scanning time Ts.

[0065] As described above, this causes the erase speed to be faster than the writing speed when the high potential power voltage EVDD is applied to the display panel 10 from the lower side DOWN of the display panel 10 as shown in FIG. 10, and gradually increases the emission time EMT as it goes from the lower side DOWN to the upper side UP of the display panel 10, thereby removing the luminance deviation resulting from the IR drop depending on the position of the display panel 10.

[0066] FIG. 12 shows an example where an erase speed and a writing speed in a specific compensation subframe are differently adjusted, and an erase speed in a portion of the specific compensation subframe is different from an erase speed in a remaining portion, as a method for minimizing the luminance deviation resulting from variations in the IR drop across signal lines for pixels of the panel. FIG. 13 shows that application times of erase signals in the specific compensation subframe are differently controlled depending on portions divided from the specific compensation subframe, so as to implement the method shown in FIG. 12.

[0067] As shown in FIG. 12, in the OLED display according to a yet further embodiment, the high potential power voltage EVDD for driving the pixels is simultaneously applied to the display panel 10 from both the upper side UP and the lower side DOWN of the display panel 10, and the data write may be sequentially performed from the upper side UP and the lower side DOWN of the display panel 10 in the sequential line manner. In this instance, a luminance at the middle part MIDD of the display panel 10 may be less than a luminance at the upper side UP and the lower side DOWN of the display panel 10 because of the IR drop.

[0068] To remove the luminance deviation depending on the position of the display panel 10, the timing controller 11 controls the operations of the display panel drivers 12, 13, and 14 such that an erase speed is slower than a writing speed in a portion of at least one compensation subframe (for example, SF4) of a plurality of subframes belonging to one frame, and then the erase speed is faster than the writing speed in a remaining portion of the compensation subframe SF4. Hence, proceeding from the upper side UP to the middle part MIDD of the display panel 10 and from the lower side DOWN to the middle part MIDD of the display panel 10, the emission time EMT may gradually increase.

[0069] The erase signals EP1 to EPn include first erase signals EP1 to EPk applied in a portion of the compensation subframe SF4 corresponding to a portion (subregion) of the panel and second erase signals EP(k+1) to EPn applied in a remaining portion of the compensation subframe SF4 corresponding to a remaining portion (subregion) of the panel. In this instance, as shown in FIG. 13, the timing controller 11 may cause a total application time Te of the erase signals EP1 to EPn to be same as a total application time Ts of the scan signals SP1 to SPn. But the total application time Te of the erase signals EP1 to EPn may be divided into a first erase time Te1, during which the first erase signals EP1 to EPk are applied, and a second erase time Te2, during which the second erase signals EP(k+1) to EPn are applied. The timing controller may cause the first erase time Te1 to be longer than the second erase time Te2, so as to differently adjust the erase speed depending on the portions of the divided compensation subframe SF4.

[0070] For this, the timing controller 11 may cause a first gate shift clock GSC1, that forms the basis of the generation of the scan signals SP1 to SPn, to have a first pulse period P1 and cause a second gate shift clock GSC2, that forms the basis of the generation of the erase signals EP1 to EPn, to have a second pulse period P2 longer than the first pulse period P1 during the first erase time Te1 and to have a third pulse period P3 shorter than the first pulse period P1 during the second erase time Te2.

[0071] The first gate driver 13 receives the first gate shift clock GSC1, a first gate start pulse GSP1, and a first gate output enable signal GOE1 from the timing controller 11 and generates the scan signals SP1 to SPn in synchronization with a rising edge of the first gate shift clock GSC1. The first gate driver 13 sequentially supplies the scan signals SP1 to SPn to the first gate lines 16 and scans the display lines of the display panel 10 in the forward direction during the total scanning time Ts.

[0072] The second gate driver 14 receives the second gate shift clock GSC2, a second gate start pulse GSP2, and a second gate output enable signal GOE2 from the timing controller 11 and generates the erase signals EP1 to EPn in synchronization with a rising edge of the second gate shift clock GSC2. The second gate driver 14 sequentially supplies the erase signals EP1 to EPn to the second gate lines 17 and erases the display lines of the display panel 10 in the forward direction at a first erase speed slower than the writing speed during the first erase time Te1 and at a second erase speed faster than the writing speed during the second erase time Te2.

[0073] As described above, this differently adjusts the erase speed depending on the portions of the divided compensation subframe (i.e., causes the erase speed to be slower than the writing speed in the portion of the compensation subframe and to be faster than the writing speed in the remaining portion of the compensation subframe) when the high potential power voltage EVDD is simultaneously applied to the display panel 10 from both the upper side UP and the lower side DOWN of the display panel 10 as shown in FIG. 12. Hence, the embodiment of the invention gradually increases the emission time EMT as it goes from the upper side UP and the lower side DOWN to the middle part MIDD of the display panel 10, thereby removing the luminance deviation resulting from the IR drop depending on the position of the display panel 10.

[0074] FIG. 14 shows an example where a scanning direction and an erase direction in a specific compensation subframe are reversely adjusted as another method for minimizing the luminance deviation resulting from the IR drop. FIGS. 15A to 15C show examples where an erase speed in a compensation subframe is differently controlled depending on a degree of the IR drop.

[0075] As shown in FIG. 14, in the OLED display according to a still further embodiment, the high potential power voltage EVDD for driving the pixels is applied to the display panel 10 from the lower side DOWN of the display panel 10, and the data write may be sequentially performed from the upper side UP to the lower side DOWN of the display panel 10 in the sequential line manner. In this instance, a luminance at the upper side UP of the display panel 10 may be less than a luminance at the lower side DOWN of the display panel 10 because of the IR drop.

[0076] To reduce the luminance deviation along positions of the display panel 10, the timing controller 11 controls the operations of the display panel drivers 12, 13, and 14 such that a scanning direction for the data write and an erase direction for turning off the pixels may be reversed in at least one compensation subframe (for example, SF4) of a plurality of subframes belonging to one frame. For example, the timing controller 11 may define the scanning direction as a forward direction and define the erase direction as a reverse direction. Hence, the timing controller 11 can gradually increase the emission time EMT as it goes from the lower side DOWN to the upper side UP of the display panel 10.

[0077] The erase speed of the reverse direction may be differently determined depending on a degree of the luminance deviation resulting from variations in IR drop on the upper and lower sides of the display panel 10.

[0078] When the luminance deviation is large, the timing controller 11 may cause the erase speed of the reverse direction to be slower than the writing speed of the forward direction in the compensation subframe SF4. For this, as shown in FIG. 15A, the timing controller 11 may cause a total application time Te of the erase signals EP1 to EPn to be longer than a total application time Ts of the scan signals SP1 to SPn. The timing controller 11 may cause a first gate shift clock GSC1, that forms the basis of the generation of the scan signals SP1 to SPn, to have a first pulse period P1 and may cause a second gate shift clock GSC2, that forms the basis of the generation of the erase signals EP1 to EPn, to have a second pulse period P2 longer than the first pulse period P1. The first gate driver 13 sequentially supplies the scan signals SP1 to SPn to the first gate lines 16 in the forward direction and scans the display lines of the display panel 10 in the forward direction during the total scanning time Ts. The second gate driver 14 sequentially supplies the erase signals EP1 to EPn to the second gate lines 17 in the reverse direction and erases the display lines of the display panel 10 in the reverse direction during the total erase time Te longer than the total scanning time Ts.

[0079] Conversely, when the luminance deviation is small, the timing controller 11 may cause the erase speed of the reverse direction to be faster than the writing speed of the forward direction in the compensation subframe SF4. For this, as shown in FIG. 15B, the timing controller 11 may cause a total application time Te of the erase signals EP1 to EPn to be shorter than a total application time Ts of the scan signals SP1 to SPn. The timing controller 11 may set the first gate shift clock GSC1, that forms the basis of the generation of the scan signals SP1 to SPn, to have the first pulse period P1 and may set the second gate shift clock GSC2, that forms the basis of the generation of the erase signals EP1 to EPn, to have the second pulse period P2 shorter than the first pulse period P1. The first gate driver 13 sequentially supplies the scan signals SP1 to SPn to the first gate lines 16 in the forward direction and scans the display lines of the display panel 10 in the forward direction during the total scanning time Ts. The second gate driver 14 sequentially supplies the erase signals EP1 to EPn to the second gate lines 17 in the reverse direction and erases the display lines of the display panel 10 in the reverse direction during the total erase time Te shorter than the total scanning time Ts.

[0080] Alternatively, as shown in FIG. 15C, when the luminance deviation is small, the timing controller 11 may cause the erase speed of the reverse direction to be same as the writing speed of the forward direction in the compensation subframe SF4.

[0081] FIGS. 16 and 17 illustrate comparisons between simulation results for the disclosed embodiments and for related art approaches.

[0082] FIG. 16 illustrates results from an implementation according to the embodiment shown in FIG. 8 and measured luminances depending on the position of the display panel. Referring to FIG. 16, an increase in a value of a vertical line indicates that the position of the display panel is close to the lower side of the display panel.

[0083] As can be seen from the simulation result of FIGS. 16 and 17, according to the embodiment of the invention a deviation between the luminances of the upper and lower sides of the display panel, is reduced in comparison with corresponding results from the related art approach.

[0084] As described above, the disclosed approaches select at least one of the plurality of subframes belonging to one frame as the compensation subframe and cause the erase speed for turning off the pixels to be faster or slower than the writing speed for the data write in the compensation subframe, thereby differently controlling the emission times of the upper and lower display lines of the display panel. This reduces the luminance deviation resulting from varying IR drops across pixel signal lines, across portions of the panel.

[0085] Furthermore, this embodiment selects at least one of the plurality of subframes belonging to one frame as the compensation subframe and reversely controls the scanning direction for the data write and the erase direction for turning off the pixels in the compensation subframe, thereby differently controlling the emission times of the upper and lower display lines of the display panel. This can minimize the luminance deviation resulting from the IR drop.

[0086] Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of the present disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

[0087] An organic light emitting diode display includes: a display panel including a plurality of pixels; a display panel driver configured to drive signal lines of the display panel; and a timing controller configured to divide one frame into a plurality of subframes, divide data of an input image at each bit, map the data of the input image to the plurality of subframes, control an operation of the display panel driver, and differently adjust a writing speed for writing data and an erase speed for turning off the pixels in at least one compensation frame of the plurality of subframes.

[0088] Optionally, when a high potential power voltage for driving the pixels is applied to the display panel from an upper side of the display panel, and the data write is sequentially performed from the upper side of the display panel to a lower side of the display panel opposite the upper side in a sequential line manner, the timing controller controls an operation of the display panel driver such that the erase speed is slower than the writing speed in the compensation subframe.

[0089] Optionally, the timing controller controls a total application time of erase signals for turning off the pixels to be longer than a total application time of scan signals for writing the data in the compensation subframe, and the timing controller controls a first gate shift clock, that forms the basis of the generation of the scan signals, to have a first pulse period and controls a second gate shift clock, that forms the basis of the generation of the erase signals, to have a second pulse period longer than the first pulse period.

[0090] Optionally, when a high potential power voltage for driving the pixels is applied to the display panel from a lower side of the display panel, and the data write is sequentially performed from an upper side opposite the lower side of the display panel to the lower side of the display panel in a sequential line manner, the timing controller controls an operation of the display panel driver such that the erase speed is faster than the writing speed in the compensation subframe.

[0091] Optionally, the timing controller controls a total application time of erase signals for turning off the pixels to be shorter than a total application time of scan signals for writing the data in the compensation subframe, and the timing controller controls a first gate shift clock, that forms the basis of the generation of the scan signals, to have a first pulse period and controls a second gate shift clock, that forms the basis of the generation of the erase signals, to have a second pulse period shorter than the first pulse period.

[0092] Optionally, when a high potential power voltage for driving the pixels is applied to the display panel from an upper side and a lower side of the display panel that are opposite to each other, and the data write is sequentially performed from the upper side to the lower side of the display panel in a sequential line manner, the timing controller controls an operation of the display panel driver such that the erase speed is slower than the writing speed in a portion of the compensation subframe, and then the erase speed is faster than the writing speed in a remaining portion of the compensation subframe.

[0093] Optionally erase signals for turning off the pixels include first erase signals applied in the portion of the compensation subframe and second erase signals applied in the remaining portion of the compensation subframe, and the timing controller controls a total application time of the erase signals to be same as a total application time of scan signals for writing the data in the compensation subframe, divides the total application time of the erase signals into a first erase time, during which the first erase signals are applied, and a second erase time, during which the second erase signals are applied, and controls the first erase time to be longer than the second erase time, and the timing controller controls a first gate shift clock, that forms the basis of the generation of the scan signals, to have a first pulse period and controls a second gate shift clock, that forms the basis of the generation of the erase signals, to have a second pulse period longer than the first pulse period during the first erase time and to have a third pulse period shorter than the first pulse period during the second erase time.

[0094] Optionally, the timing controller reversely adjusts a scanning direction for writing the data and an erase direction for turning off the pixels in the compensation subframe.

[0095] Optionally, an erase speed for turning off the pixels is determined based on a luminance deviation depending on a position of the display panel in the compensation subframe.

[0096] Optionally, each of the plurality of subframes includes a writing time during which the data is written on the pixels, an emission time during which the pixels emit light, and an erase time during which the pixels are turned off.

[0097] There is also provided a method for driving an organic light emitting diode display including a display panel including a plurality of pixels and a display panel driver driving signal lines of the display panel, the method including: dividing one frame into a plurality of subframes, dividing data of an input image at each bit, and mapping the data of the input image to the plurality of subframes; and controlling an operation of the display panel driver and differently adjusting a writing speed for writing data and an erase speed for turning off the pixels in at least one compensation frame of the plurality of subframes.

[0098] Optionally the method further includes reversely adjusting a scanning direction for writing the data and an erase direction for turning off the pixels in the compensation subframe.

[0099] Optionally, an erase speed for turning off the pixels is determined based on a luminance deviation depending on a position of the display panel in the compensation subframe.

[0100] Optionally, each of the plurality of subframes includes a writing time during which the data is written on the pixels, an emission time during which the pixels emit light, and an erase time during which the pixels are turned off.