Intermediate Voltage Bus Converter with Power Saving Modes

[0001] The present application relates to intermediate DC/DC voltage bus converters, in particular entering and exiting power saving modes by intermediate DC/DC voltage bus converters.

[0002] To save power in datacenters and other data-intensive applications, a typical 12V DC distribution bus can be replaced by a higher voltage bus e.g. typically 48V nominal. This higher distribution voltage is stepped down on the motherboard in one or more stages to the low DC voltage required by the CPU (central processing unit), memory, and other electronic components included in the system such as memory, graphics logic, I/O (input/output), etc. For example, a single DC/DC converter conventionally generates an intermediate bus voltage that is fed to all lower-voltage converter stages. The intermediate bus is typically between 5-12V and can therefore use existing infrastructure to be highly scalable. In another example, the CPU has a dedicated converter (e.g. 48V to 1V) that can be a single conversion stage, or two converter stages in series to achieve the step down. The other voltage rails (e.g. memory, graphics logic, etc.) are fed from a common intermediate bus. In still another example, all voltage rails are fed directly from the 48V distribution bus. In this case scalability is limited, and the use of existing infrastructure is not an option. Other architectures employ multiple intermediate bus voltages for feeding different voltage rails, using direct conversion for the CPU and some other voltage rails with the intermediate bus powering the rest, or some combination thereof.

[0003] In each case, the final conversion stage of the DC/DC converter that supplies the CPU is widely known as a voltage regulator. The voltage regulator converts an intermediate voltage e.g. 12V to the CPU voltage e.g. 1V. The CPU communicates with the voltage regulator using a protocol for status, protection, and system optimization. Part of the optimization includes instructing the voltage regulator to enter power saving modes of operation to increase light-load efficiency when the CPU enters low power states. However, a problem occurs with higher-voltage distribution systems such as 48V systems when the converter stage that converts the high distribution bus voltage to an intermediate bus voltage is not privy to the communication between the CPU and the voltage regulator that converts between the intermediate bus voltage and the load voltage. For example in a 48V system, the 48V-to-12V converter stage monitors its output current and adjusts its operating point (e.g. active phases, pulse frequency modulation (PFM) mode, etc.) accordingly. However, if the voltage regulator is still in the most active power state but the 48V-to-12V converter stage enters a low power mode, the slow response of the 48V-to-12V converter stage can feed through to the CPU voltage rail when a transient occurs. Such a condition would result in a CPU hang which is prohibited in a server where high reliability is a fundamental necessity.

[0004] This problem has been solved by increasing the intelligence of the converter stage that converts the high distribution bus voltage to an intermediate bus voltage. For example, this intermediate converter stage can measure its output voltage and current, and make decisions to enter power-saving states based on those measurements. Detection of a transient event may cause the intermediate converter stage to leave the power saving state by adding phases (if applicable) or leaving pulse frequency modulation (PFM) mode and entering PWM (pulse width modulation) mode. However, to maintain high efficiency, converters on a higher-voltage distribution bus such as a 48V bus typically switch at lower frequencies than the downstream lower voltage regulators that feed the CPUs. Further, the filter inductance of these higher-voltage converter stages is significantly larger than that of the downstream voltage regulators, by more than an order of magnitude. As such, their response is significantly slower.

[0005] During low current intervals in the maximum power state, it is possible that a voltage regulator sheds phases to conserve power. The multiple phases, high switching frequency, and low inductance promote fast reaction time to allow the voltage regulator to respond quickly to a load transient without the CPU voltage experiencing undershoot. However, the response of the upstream higher-voltage converter stage is significantly slower than the voltage regulator. Therefore, if the converter stage that converts the high distribution bus voltage to the intermediate bus voltage enters a power saving state while the CPU is still in the maximum power state, the slow response of this intermediate converter stage generates a sag on the intermediate voltage input to the voltage regulator which in turn propagates and manifests itself as undershoot at the CPU.

[0006] According to an embodiment of a DC/DC voltage converter, the DC/DC voltage converter comprises a first stage operable to convert a first DC voltage rail to a second DC voltage rail different than the first DC voltage rail and a second stage operable to convert the second DC voltage rail to a third DC voltage rail lower than the second DC voltage rail and deliver current to a load at the third DC voltage rail, the amount of current delivered to the load corresponding to an operating set point of the second stage. The second stage is operable to change its operating set point responsive to a command received from the load, such that the amount of current delivered to the load is reduced. The first stage is operable to change its operating set point responsive to a command issued by the load, such that the amount of current delivered to the second stage is reduced.

[0007] According to an embodiment of a server, the server comprises a central processing unit (CPU), memory coupled to the CPU, a DC/DC voltage converter for powering the CPU and the memory, a communication bus for coupling the CPU to the memory and the DC/DC voltage converter and a DC voltage distribution bus coupled to the DC/DC voltage converter. The DC/DC voltage converter comprises a first stage operable to convert a first DC voltage rail provided by the DC voltage distribution bus to a second DC voltage rail different than the first DC voltage rail and a second stage operable to convert the second DC voltage rail to a third DC voltage rail lower than the second DC voltage rail and deliver current to the CPU at the third DC voltage rail, the amount of current delivered to the CPU corresponding to an operating set point of the second stage. The second stage is operable to change its operating set point responsive to a command received from the CPU, such that the amount of current delivered to the CPU is reduced. The first stage is operable to change its operating set point responsive to a command issued by the CPU, such that the amount of current delivered to the second stage is reduced.

[0008] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

[0015] Embodiments described herein relate to a DC/DC converter that includes a first stage for converting a high bus voltage to an intermediate bus voltage and a second stage for converting the intermediate bus voltage to a low bus voltage that supplies a load such as a CPU. The load communicates with the DC/DC converter using a protocol for status, protection, and system optimization. Part of the optimization process includes the load instructing the second stage to change its operating set point so that the light-load efficiency of the second stage can be increased when the load enters a lower-power state. The first stage is aware of the power saving intentions of the load, e.g. by monitoring the communication between the load and the second stage, or by receiving communications directly from the load. In response, the first stage changes its operating set point such that the amount of current delivered to the second stage is reduced. In this way, the first stage implements an anticipatory power savings approach as opposed to a reactionary approach that merely relies on observation of system parameters such as bus voltage, output current, etc. The first stage of the DC/DC converter is therefore less likely to hinder operation of the second stage, and hence, load performance.

[0016] FIG. 1 illustrates an embodiment of the DC/DC converter 100. The DC/DC voltage converter 100 comprises a first stage 102 for converting a first DC voltage rail (VR1) to a second DC voltage rail (VR2) different than the first DC voltage rail. The level of the second DC voltage rail VR2 can be lower or higher than the first DC voltage rail VR1. For example, 48V is the nominal voltage for systems that can vary from 35-75V for VR1. So in one embodiment VR1 is at 48V (but can be 35-75V) and VR2 is at 12V. In another embodiment, VR1 again is at 48V but the second rail VR2 can be 54V. In general, the second DC voltage rail VR2 is different than the first DC voltage rail VR1.

[0017] The DC/DC voltage converter 100 further comprises a second stage 104 for converting the second DC voltage rail VR2 to a third DC voltage rail (VR3) lower than the second DC voltage rail VR2. The second stage 104 delivers current to a load 106 such as a CPU at the third DC voltage rail VR3. The amount of current delivered to the load 106 corresponds to the operating set point of the second stage 104, and the operating set point of the second stage 104 in turn corresponds to the amount of current required by the load 106.

[0018] The second stage 104 of the DC/DC converter 100 can change its operating set point responsive to a command received from the load 106 powered by the DC/DC converter 100, such that the amount of current delivered to the load 106 is reduced. For example in the case of a CPU load, the CPU communicates with the second stage 104 over a communication bus 108 using a protocol for status, protection, and system optimization. Part of the optimization process includes the CPU instructing the second stage 104 to change its operating set point so that the light-load efficiency of the second stage 104 is increased when the CPU enters a low power state. This can include, but is not limited to, phase shedding where the second stage 104 deactivates or sheds (drops) one or more previously active phases, dynamic reduction in the output voltage of the second stage 104, transitioning the second stage 104 from PWM to PFM operation, etc. Any standard communication protocol can be used by the load 106 to communicate commands to the second stage 104 of the DC/DC converter 100 which cause the second stage 104 to change its operating set point and correspondingly lower its power output. For example through the SVID (serial VID) interface, the load 106 is a CPU that can dynamically control the output voltage, slew rates and power states of the second stage 104, as well as monitor the second stage 104 for telemetry purposes.

[0019] The first stage 102 of the DC/DC converter 100 also can change its operating set point responsive to a command issued by the load 106, such that the amount of current delivered to the second stage 104 is reduced. The first stage 102 has insight into the power consumption behavior of the downstream load 106. In one embodiment, the load 106 is a CPU that communicates with the second stage 104 by transmitting communication packets over a communication bus 108. The packets are addressed to the second stage 104. The second stage 104 extracts commands from the packets, and takes corresponding action. This can include taking one or more power saving-related actions such as phase shedding, dynamic output voltage reduction, transitioning the second stage 104 from PWM to PFM operation, etc.

[0020] In one embodiment, the first stage 102 of the DC/DC converter 100 monitors the communication bus 108 between the second stage 104 and the load 106 for a command addressed to the second stage 104 that instructs the second stage 104 to change its operating set point. The load 106 actively controls the power state of second stage 104, and the first stage 102 decides whether to change its operating point based on power state instructions to the second stage 104. The load 106 does not directly communicate with the first stage 102 according to this embodiment.

[0021] The first stage 102 can change its operating set point responsive to commands addressed to the second stage 104, when the amount of current required by the second stage 104 is reduced. If the first stage 102 has more than one phase, this can include phase shedding where the first stage 102 deactivates or sheds (drops) one or more previously active phases. Alternatively or in addition, the first stage 102 can dynamically reduce its output voltage, transition from PWM to PFM operation, etc. For example, if the load 106 issues a command to enter a lower power state that results in the second stage 104 shedding phases, the first stage 102 can then know what its maximum load is limited to and could potentially shed phases as well if it were safe to do so. If the load 106 issues a command to put the second stage 104 to sleep, the first stage 102 can also enter its most efficient mode of operation where the term ‘most efficient mode of operation’ is not limited to phase shedding or PFM operation. From a system perspective, this could include the first stage 102 adjusting the second DC voltage rail (VR2) to minimize losses. To maintain the highest level of load power quality, when the load 106 instructs the second stage 104 to leave a power saving mode of operation and return to the maximum power state, the first stage 102 of the DC/DC converter 100 is aware of the command and can enter its own maximum power state in response.

[0022] In another embodiment, the first stage 102 of the DC/DC converter 100 can be coupled to the load 106 via the same or different communication bus 108 as the second stage 104 and receive packets with commands addressed to the first stage 102. According to this embodiment, the load 106 can send messages independently to both the second stage 104 and first stage 102 of the DC/DC converter 100. This way, the first stage 102 need not necessarily monitor for commands addressed to the second stage 104 which instruct the second stage 104 to take power saving action. Instead, the load 106 can communicate directly with the first stage 102 by addressing power saving commands to the first stage 102. The first stage 102 can change its operating set point responsive to a power saving command received over the communication bus 108 and addressed to the first stage 102 e.g. by phase shedding, entering PFM operation, adjusting the second DC voltage rail (VR2) to minimize losses, etc. The dashed line in FIG. 1 indicates that the first stage 102 can monitor the communication bus 108 between the load 106 and the second stage 104 or receive packets from the load 106 uniquely addressed to the first stage 102, in order to gain insight into the power consumption behavior of the downstream load 106.

[0023] FIG. 2 illustrates an embodiment of the first stage 102 of the DC/DC converter 100. The first stage 102 comprises a plurality of power stages (phases) 110 and a controller 112 such as a microcontroller, microprocessor, ASIC (application-specific integrated-circuit), etc. for controlling operation of the power stages 110. Each power stage 110 is operable to deliver a phase current (i_Ln) through a separate inductor (L_n) to yield the second DC voltage rail VR2. In the case of a multiphase buck converter for implementing the first stage 102 as shown in FIG. 2, the first stage 102 produces a DC voltage rail VR2 less than VR1. In general, the first stage 102 can be implemented using any standard DC/DC converter architecture such as buck-boost converter, flyback converter, etc. such that the second DC voltage rail VR2 can be lower or higher than the first DC voltage rail VR1.

[0024] Each power stage 102 of the multiphase buck converter shown in FIG. 2 has a high-side transistor (HSn) and a low-side transistor (LSn) for coupling to the second DC voltage rail VR2 through the corresponding inductor. The high-side transistor of each power stage 110 switchably connects the second DC voltage rail VR2 to the first DC voltage rail VR1, and the corresponding low-side transistor switchably connects the second DC voltage rail VR2 to ground at different periods. N power stages 110 are shown in FIG. 2. The first stage 102 can include any number of power stages 110 including a single power stage (phase) or more than one power stage (i.e. multi-phase where each power stage is one phase of the multi-phase regulator). In many cases, the first stage 102 switches at a lower frequency than the second stage 104 of the DC/DC converter 100. The first stage 102 can have a lower phase count than the second stage 104, and larger inductors. As a result, the first stage 102 typically has a slower inherent response time to transient conditions as compared to the second stage 104. The second stage 104 of the DC/DC converter 100 can have the same or similar construction as the first stage 102.

[0025] The controller 112 of the DC/DC converter 100 regulates the second DC voltage rail VR2 delivered by the power stage(s) 110, by adjusting the phase currents delivered by the power stage(s) 110. Each phase 110 is configured to output a maximum rated current at the second DC voltage rail. The controller 112 includes a pulse width modulator (PWM) unit 114 for switching each power stage 110 via a corresponding PWM control signal (pwm). The controller 112 also includes a pulse frequency modulator (PFM) unit 116 for switching one of the power stages 110 via a corresponding PFM (pfm) control signal e.g. during light-load operation. Drivers 118 for the power stage(s) 110 provide gate drive signals (Vdrive) to the gates of the corresponding high-side and low-side transistors in response to the PWM or PFM control signals provided by the controller 112.

[0026] The controller 112 can manage changes from one reference voltage to another. The controller 112 also can determine errors between the second DC voltage rail VR2 and a reference voltage, and convert the error voltage into a digital representation provided to the PWM and PFM units 114, 116 for modifying the switching cycle of each power stage 110 e.g. by adjusting the PWM duty cycle in PWM mode or switching frequency in PFM mode.

[0027] FIG. 3 illustrates examples of different operating set point changes that can be made by the first stage 102 of the DC/DC converter 100 in response to commands issued by the load 106 which indicate a change in power demand at the load 106. The operating set point changes available at the first stage 102 depend on the architecture of the first stage 102. For example, if the first stage 102 has more than one phase (power stage) 110, the first stage 102 can shed (deactivate) one or more phases 110 in response to a command from the load 106 indicating a reduced power state at the load 106. With only one phase 110 active, the first stage 102 can transition from PWM mode to PFM mode for that phase 110. The PWM-to-PFM mode change option is available even if the first stage 110 has only one phase (i.e. is a single-phase stage).

[0028] In addition or alternatively, the first stage 102 can change the gate drive signals (Vdrive) applied to the gates of the high-side and low-side transistor of each active phase 110 from a higher voltage (Vdrive,high) to a lower voltage (Vdrive,low) in response to a command from the load 106 indicating a reduced power state at the load 106.

[0029] In yet another embodiment, the first stage 102 can change the level of the second DC voltage rail VR2 from a higher voltage (Vbus,high) to a lower voltage (Vbus,low) in response to a command from the load 106 indicating a reduced power state at the load 106. For example, the first stage 102 can increase or decrease the level of the second DC voltage rail VR2 responsive to the second stage 104 being instructed by the load 106 to shed one or more phases, each phase of the second stage 104 configured to output a maximum rated current at the third DC voltage rail VR3. The first stage 102 can change the level of the second DC voltage rail VR2 for each active phase 110, and can perform this level adjustment to VR2 each time a phase 110 is shed.

[0030] Each of the operating set point changes shown in FIG. 3, alone or in any combination, allows the first stage 102 of the DC/DC converter 100 to adjust its operating set point when the current required by the second stage 104 is reduced in response to power saving commands issued by the load 106. The commands can be addressed to the second stage 104 and monitored by the first stage 102, or addressed directly to the first stage 102 as explained above. In either case, the overall efficiency of the DC/DC converter 100 can be increased under light-load conditions.

[0031] FIGS. 4 through 6 illustrate the variables that affect each operating point variable shown in FIG. 3.

[0032] According to FIG. 4, the first stage 102 of the DC/DC converter 100 has a plurality of phases (power stages) 110 each of which has a programmed phase current limit for protection. The controller 112 of the first stage 102 can monitor commands addressed to the second stage 104 that affect the number of active phases Nφ for the second stage 104, or receive the same or similar commands directly from the load 106. The controller 112 can optimize efficiency while assuming safe operation by measuring input voltage, input current and output current of the first stage 102. For example, two phases 110 of the first stage 102 may be active at some operating point, but one phase 110 can handle the load current demand. In this case the controller 112 can switch to one phase 110 if safe and more efficient than two phases 110, based on the input power and output current measurements.

[0033] According to FIG. 5, the output voltage (VR2) of the first stage 102 can be adjusted and its impact on efficiency determined by measuring the input power and output current of the first stage 102. The controller 112 of the first stage 102 can monitor output current for protection and the possibility of phase count increase. For a given power level, reduction of the output voltage VR2 may increase the efficiency of the downstream second stage 104 but lower the efficiency of the first stage 102. Or reduction of the output voltage VR2 may increase both efficiencies, or decrease both. Output voltage adjustments are very dependent on the converter implementation, but in general the controller 112 can adjust the output voltage VR2 of first stage 102 to increase overall efficiency of the DC/DC converter 100.

[0034] According to FIG. 6, the voltage of the signals (Vdrive) used to drive the gates of the power transistors of the first stage 102 can be adjusted to improve overall system efficiency. For example, it may be beneficial to reduce the gate drive voltage under lower load power conditions as indicated by measuring the input power and output current of the first stage 102. However, the first stage 102 output current need not necessarily be measured or sensed.

[0035] The way in which the first stage 102 of the DC/DC converter 100 implements operating set point changes depends on the architecture of the first stage 102. In one embodiment, the first stage 102 is hard-wired with different operating set point options. Each of the hard-wired operating set point options corresponds to a different power mode of the first stage 102. According to this embodiment, the first stage 102 selects the operating set point option associated with a corresponding command issued by the load 106. The command can be addressed to the second stage 104 and monitored by the first stage 102, or addressed directly to the first stage 102 as explained above.

[0036] In another embodiment, the different operating set point options available to the first stage 102 of the DC/DC converter 100 are stored in registers 200 of the system in which the DC/DC converter 100 is included e.g. as shown in FIG. 2. The first stage 102 changes its operating set point responsive to a command issued by the load 106, in accordance with the register settings 200 which are accessible by the first stage 102.

[0037] In yet another embodiment, the first stage 102 develops a history of power mode behavior by monitoring prior activity on the second DC voltage rail VR2 in response to different commands issued by the load 106. The first stage 102 then determines whether to change its operating set point based at least partly on the history of power mode behavior.

[0038] The DC/DC converter 100 can use its current monitoring pin (IMON) with knowledge of the load power state to implement an adaptive filter that determines the threshold and delays required for the first stage 102 of the DC/DC converter 100 to safely enter and exit a power saving state. Then the power state commands for the second stage 104 of the DC/DC converter 100 need only be required for a few power state transitions until the controller 112 of the first stage 102 learns the behavior of the load 106 during each power state via the current monitoring pin.

[0039] The DC/DC voltage converter 100 can communicate with electronic components other than a CPU, e.g. including memory, graphics, I/O, and other electronic components. For example in a server environment, there can be as many as six voltage rails or more which are controlled by a CPU on a single board.

[0040] FIG. 7 illustrates an embodiment of a server 300 that includes a first DC/DC converter 100 of the kind previously described herein that provides an intermediate voltage rail VR2a for powering all voltage rails VR3a, VR3b, VR3c that supply electronic components in communication with the CPU 106. For example, the server 300 can include memory 302 such as volatile and/or nonvolatile memory and graphics logic 304 such as a graphics processor coupled to the CPU 106. The first DC/DC voltage converter 100 powers the CPU 106 and each electronic component 302, 304 that communicates with the CPU 106. A communication bus 108 couples the CPU 106 to the first DC/DC converter 100, memory 302, graphics logic 304, etc. A DC voltage distribution bus (rail) VR1 is coupled to the first DC/DC voltage converter 100.

[0041] The first DC/DC voltage converter 100 also includes an additional stage 306, 308 for converting the second DC voltage rail VR2a to an additional DC voltage rail VR3b, VR3c lower than the second DC voltage rail VR2a and different than the third DC voltage rail VR3a. Each additional stage 306, 308 delivers current to an electronic component 302, 304 other than the CPU 106 at the corresponding additional DC voltage rail VR3b, VR3c, where the amount of current delivered to each of these electronic component(s) 302, 304 corresponds to an operating set point of the corresponding additional stage 306, 308 of the first DC/DC converter 100. Each additional stage 306, 308 of the first DC/DC converter 100 can change its operating set point responsive to a command received from the load 106 and addressed to that stage 306, 308, such that the amount of current delivered to the corresponding electronic component 302, 304 is reduced.

[0042] The first stage 102 of the first DC/DC converter 100 can be responsible for multiple voltage rails VR3a, VR3b, VR3c, and therefore the decision making process of the first stage 102 becomes more complex. For example, the first stage 102 can monitor for multiple addresses (one for each rail/component) and make a decision for all downstream voltage rails VR3a, VR3b, VR3c. The first stage 102 should be able to support the worst operating point for each voltage rail VR3a, VR3b, VR3c. The electronic components 106, 302, 304 supplied by the first DC/DC converter 100 may not all be at same power levels. For example, the CPU 106 can be in a lower power state than the graphics processor 304.

[0043] In general, the first stage 102 of the first DC/DC converter 100 can change its operating set point responsive to commands issued by the CPU 106 to the downstream stages 104, 306, 308, or responsive to a command issued by the CPU 106 directly to the first stage 102. For example, the first stage 102 of the first DC/DC converter 100 can monitor communication between the CPU 106 and each stage 104, 306, 308 of the first DC/DC converter 100 downstream of the first stage 102, or the first stage 102 can communicate directly with the CPU 106. The dashed lines in FIG. 7 indicate that the first stage 102 of the first DC/DC converter 100 can monitor the communication bus 108 between the CPU 106 and each downstream stage 104, 306, 308 of the first DC/DC converter 100, or receive packets from the CPU 106 over the communication bus 108 that are uniquely addressed to the first stage 102, in order to gain insight into the power consumption behavior of the CPU 106. In either case, the ability to enter a power saving mode is then calculated by the first stage controller 112 of the first DC/DC converter 100 based on knowledge of the rated power of the different downstream voltage rails VR3a, VR3b, VR3c.

[0044] Exiting to the maximum power state depends on the capability of the first stage 102 of the first DC/DC converter 100 and capabilities of the voltage rail(s) VR3a, VR3b, VR3c that have also been instructed to leave power saving modes. For example, the first stage 102 can change its operating set point by shedding one or more phases 110, each phase 110 configured to output a maximum rated current at VR2a, based on the operating set point of one or more downstream converter stages 104, 306, 308. In another embodiment, the first stage 102 of the first DC/DC converter 100 can change its operating set point by changing from a PWM operating mode to a PFM mode for one or more of the phases 110. In yet another embodiment, the first stage 102 of the first DC/DC converter 100 can change its operating set point by changing the gate drive signal (Vdrive) applied to the power transistors of one or more phases 110 of the first stage 102. In still another embodiment, the first stage 102 of the first DC/DC converter 100 can change its operating set point by changing the level of the second DC voltage rail VR2a provided by the first stage 102 to the downstream stages 104, 306, 308.

[0045] The server 300 also includes a second DC/DC converter 310 that provides an intermediate voltage rail VR2b for powering the voltage rails VR3d, VR3e that supply electronic components that are not in direct communication with the CPU 106. The same or different DC voltage distribution bus (rail) VR1 is coupled to both the first and second DC/DC voltage converters 100, 310. The second DC/DC converter 310 can have one or more stages 312, 314 in series. Any standard converter can be used as the second DC/DC converter 310.

[0046] The way in which the first stage 102 of the first DC/DC converter 100 implements operating set point changes depend on the architecture of the first stage 102 as previously described herein. For example, the first stage 102 can be hard-wired with different operating set point options each of which corresponds to a different power mode of the first stage 102. The first stage 102 selects the operating set point option associated with a corresponding command issued by the load 106. In another example, the different operating set point options available to the first stage 102 of the first DC/DC converter 100 are stored in registers 200 of the server 300. The first stage 102 changes its operating set point responsive to a command issued by the load 106, in accordance with the register settings 200 which are accessible by the first stage 102. In yet another example, the first stage 102 of the first DC/DC converter 100 develops a history of power mode behavior by monitoring prior activity on the second DC voltage rail VR2a in response to different commands issued by the load 106. The first stage 102 then determines whether to change its operating set point based at least partly on the history of power mode behavior. The observed power mode behavior can include power mode behavior for all electronic components 302, 304 that are in communication with the CPU 106.

[0047] Terms such as “first”, “second”, and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0048] As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0049] It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

[0050] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.