SWITCH DRIVING CIRCUIT AND SWITCHING POWER DEVICE USING THE SAME

[0001] This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-212705, filed on Oct. 17, 2014, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a switch driving circuit and a switching power device using the same.

[0003] A phase shift full-bridge zero-volt switching (ZVS) operation has been proposed as an effective scheme for supporting mutual compatibility between enhancement of efficiency of a switching power device and noise reduction, compared with the related arts.

[0004] In the switching power device of the related art, a simultaneous OFF time (also known as a dead time) of an upper switch and a lower switch is set to be long in order not to interrupt the soft switching operation (ZVS operation) even when a load is light or a device delay is great.

[0005] However, when the long simultaneous OFF time is fixedly set, a high enough efficiency may not be achieved when a load is heavy or a device delay is small.

[0006] In addition, an optimal value of the simultaneous OFF time for achieving the highest efficiency is significantly changed by manufacturing deviations of upper and lower switches, transformers, or the like, and is also significantly changed by the magnitude of current flowing in such components.

[0007] The present disclosure provides some embodiments of a switch driving circuit capable of always performing an optimal soft switching operation (ZVS operation) in consideration of the foregoing problems discovered by the inventors of the present application, and a switching power device using the same.

[0008] According to one embodiment of the present disclosure, there is provided a switch driving circuit, wherein the switch driving circuit has a function of periodically updating a simultaneous OFF time prepared to soft-switch an upper switch and a lower switch of a switching output circuit, and is configured to monitor how an output power or an input power of the switching output circuit is changed depending on previous updating of the simultaneous OFF time to determine new updated contents (hereinafter, referred to as the “first feature”).

[0009] Further, in the switch driving circuit having the first configuration, in a case in which the output power is increased or the input power is decreased depending on previous updating of the simultaneous OFF time, the simultaneous OFF time may be changed in a direction of a change that is the same as that of the previous updating, and in a case in which the output power is decreased or the input power is increased depending on previous updating of the simultaneous OFF time, the simultaneous OFF time may be changed in a direction of a change that is opposite to that of the previous updating (hereinafter, referred to as the “second feature”).

[0010] Also, in the switch driving circuit having the first or second configuration, the switch driving circuit may be configured to monitor at least one of an output current, an output voltage, an input current, and an input voltage of the switching output circuit (hereinafter, referred to as the “third feature”).

[0011] In addition, the switching power device disclosed herein includes the switch driving circuit having any one of the first to third configurations; and a switching output circuit configured to generate an output voltage from an input voltage depending on ON/OFF control of the upper switch and the lower switch (hereinafter, referred to as the “fourth feature”).

[0012] Further, in the switching power device having the forth configuration, the switching output circuit may include: a transformer including electronically coupled primary winding and secondary winding; a first upper switch and a first lower switch connected in series between an application terminal of the input voltage and a first ground terminal and in which a connection node therebetween is connected to a first terminal of the primary winding through an inductor; a first upper switch and a first lower switch connected in series between the application terminal of the input voltage and the first ground terminal and in which a connection node therebetween is connected to a second terminal of the primary winding; and a rectifying part configured to generate the output voltage from an inductive voltage that appears in the secondary winding (hereinafter, referred to as the “fifth feature”).

[0013] Also, in the switching power device having the fifth configuration, the rectifying part may include: a first rectifying diode, in which a cathode is connected to a first terminal of the secondary winding and an anode is connected to a second ground terminal; a second rectifying diode, in which a cathode is connected to a second terminal of the secondary winding and an anode is connected to the second ground terminal; a choke coil, in which a first terminal is connected to an intermediate tap of the second winding and a second terminal is connected to an application terminal of the output voltage; a smoothing capacitor, in which a first terminal is connected to the application terminal of the output voltage and a second terminal is connected to the second ground terminal (hereinafter, referred to as the “sixth feature”).

[0014] Also, in the switching power device having the fifth or sixth configuration, the switch driving circuit may be configured to periodically update a first simultaneous OFF time prepared to soft-switch the first upper switch and the first lower switch and a second simultaneous OFF time prepared to soft-switch the second upper switch and the second lower switch (hereinafter, referred to as the “seventh feature”).

[0015] Also, in the switching power device having the seventh configuration, the switch driving circuit may be configured to set the first simultaneous OFF time and the second simultaneous OFF time to have different lengths (hereinafter, referred to as the “eighth feature”).

[0016] Also, in the switching power device having the eighth configuration, the switch driving circuit may be configured to update the first simultaneous OFF time and the second simultaneous OFF time at different timings (hereinafter, referred to as the “ninth feature”).

[0017] Also, in the switching power device having the ninth configuration, the switch driving circuit may be configured to continuously update the first simultaneous OFF time and the second simultaneous OFF time at a plurality of periods (hereinafter, referred to as the “tenth feature”).

[0027] FIG. 1 is a circuit diagram illustrating a configuration example of a switching power device 1. The switching power device 1 of this exemplary configuration is an insulating DC/DC converter for generating a desired output voltage Vo from an input voltage Vi and supplying the generated voltage Vo to a load 2, and includes a switch driving circuit 10 and a switching output circuit 20.

[0028] The switch driving circuit 10 pulse-drives each of gate signals G1H and G1L and gate signals G2H and G2L such that the output voltage Vo is equal to a target value, thereby driving the switching output circuit 20 (more specifically, the upper switches SW1H and SW2H and the lower switches SW1L and SW2L). A configuration and an operation of the switch driving circuit 10 will be described in detail later.

[0029] The switching output circuit 20 includes a transformer TR1, the upper switches SW1H and SW2H, the lower switches SW1L and SW2L, an inductor L3, a choke coil L4, rectifying diodes D1 and D2, and a smoothing capacitor C3, and generates the output voltage Vo from the input voltage Vi depending on the ON/OFF control of the upper switches SW1H and SW2H, and the lower switches SW1L and SW2L.

[0030] The transformer TR1 includes electronically coupled primary winding L1 and secondary winding L2, and transfers an alternating current (AC) power from a primary circuit system 1p (GND1 system) to a secondary circuit system is (GND2 system), while electrically insulating the primary circuit system 1p and the secondary circuit system 1s.

[0031] The upper switch SW1H and the lower switch SW1L, which are first arms of a full-bridge type output stage, are connected in series between an application terminal of the input voltage Vin and an application terminal (which corresponds to a first ground terminal) of a ground voltage GND1. A connection node (i.e., an application terminal of a node voltage V1) between the upper switch SW1H and the lower switch SW1L is connected to a first terminal of the primary winding L1 through the inductor L3. As the inductor L3, the leakage inductance of the transformer TR1 may be appropriately used. Parasitic capacitors C1H and C1L are positioned between both ends of the upper switch SW1H and the lower switch SW1L, respectively.

[0032] The upper switch SW2H and the lower switch SW2L, which are second arms of the full-bridge type output stage, are connected in series between the application terminal of the input voltage Vin and the application terminal of the ground voltage GND1. A connection node (i.e., an application terminal of a node voltage V2) between the upper switch SW2H and the lower switch SW2L is connected to a second terminal of the primary winding L1. Parasitic capacitors C2H and C2L are positioned between both ends of the upper switch SW2H and the lower switch SW2L, respectively.

[0033] In addition, in a case in which a high voltage is applied to the upper switches SW1H and SW2H and the lower switches SW1L and SW2L, high voltage switch devices such as a power metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and an SiC transistor are used as switch devices.

[0034] A cathode of the rectifying diode D1 is connected to the first terminal of the secondary winding L2. A cathode of the rectifying diode D2 is connected to a second terminal of the secondary winding L2. Both anodes of the rectifying diodes D1 and D2 are connected to an application terminal (which corresponds to a second ground terminal) of a ground voltage GND2. A first terminal of the choke coil L4 is connected to an intermediate tap of the secondary winding L2. Both a second terminal of the choke coil L4 and a first terminal of the smoothing capacitor C3 are connected to an application terminal of the output voltage Vo. A second terminal of the smoothing capacitor C3 is connected to an application terminal of the ground voltage GND2.

[0035] The rectifying diodes D1 and D2, the choke coil L4, and the smoothing capacitor C3 connected in this manner serve as a full-wave rectifying type rectifying/smoothing part for generating the output voltage Vo from an inductive voltage that appears in the secondary winding L2. However, the configuration of the rectifying/smoothing part is not necessarily limited thereto, and for example, a half-wave rectifying type may also be employed.

[0036] The upper switch SW1H and the lower switch SW1L are complementarily turned on and off depending on the gate signals G1H and G1L, respectively. Also, the upper switch SW2H and the lower switch SW2L are complementarily turned on and off depending on the gate signals G2H and G2L, respectively. In this present disclosure, the term “complementary” includes a case in which a predetermined delay is given to a transition timing of ON/OFF of the upper switch and the lower switch (a simultaneous OFF time Td (dead time) of the upper switch and the lower switch is provided), as well as including a case in which an ON/OFF state of the upper switch and the lower switch are completely reversed.

[0037] Further, the simultaneous OFF time Td of the upper switch and the lower switch is provided to prevent an excessive through current flowing through the two switches, implement a soft switching operation (ZVS operation), and reduce switching loss and switching noise.

[0038] FIG. 2 is a timing chart illustrating an example of a soft switching operation (phase shift full-bridge ZVS operation) by the switch driving circuit 10, and the gate signals G1H, G1L, G2H, and G2L, and the node voltages V1 and V2 are illustrated sequentially from top to bottom of the figure. Further, as for the node voltages V1 and V2, behaviors thereof (a) in a case in which the simultaneous OFF time Td is smaller than an optimal value, (b) in a case in which the simultaneous OFF time Td is identical to the optimal value, and (c) in a case in which the simultaneous OFF time Td is greater than an optimal value are illustrated.

[0039] First, before describing the soft switching operation (ZVS operation), a basic operation of phase shift full-bridge pulse width modulation (PWM) control will be briefly described. In the phase shift full-bridge PWM control, the gate signals G1H, G1L, G2H, and G2L are pulse-driven at a predetermined duty rate (for example, at 50%). Further, a shift time Ts (phase difference) is set between the gate signals G1H and G1L of the first arm side and the gate signals G2H and G2L of the second arm side. By variably controlling the shift time Ts, an application time (duty) of the input voltage Vi with respect to the primary winding L1 is changed. Thus, in the phase shift full-bridge PWM control, a feedback control of the output voltage Vo may be performed, while uniformly fixing a switching frequency, unlike an LLC resonance control of a half-bridge configuration.

[0040] Next, a soft switching operation (ZVS operation) of the upper switches SW1H and SW2H and the lower switches SW1L and SW2L will be described.

[0041] For example, as illustrated in the time duration of t1 to t2, in a state where the lower switches SW1L and SW2L are turned on and the upper switches SW1H and SW2H are turned off, when the lower switch SW1L is switched to be turned off, the node voltage V1 gently increases due to LC resonance. Thus, when the upper switch SW1H is turned on at a timing at which the node voltage V1 is equal to the input voltage Vi (that is, at a timing at which a voltage across the upper switch SW1H is 0 V), the soft switching operation (ZVS operation) may be realized.

[0042] Further, as illustrated in the time duration of t3 to t4, in a state where the upper switches SW1H and SW2H are turned on and the lower switches SW1L and SW2L are turned off, when the upper switch SW1H is switched to be turned off, the node voltage V1 gently decreases due to LC resonance. Thus, when the lower switch SW1L is turned on at a timing at which the node voltage V1 is equal to the ground voltage GND1 (that is, at a timing at which a voltage across the lower switch SW1L is 0 V), the soft switching operation (ZVS operation) may be realized.

[0043] Also, as illustrated in the time duration of t5 to t6, in a state where the upper switch SW1H and the lower switch SW2L are turned on and the upper switch SW2H and the lower switch SW1L are turned off, when the lower switch SW2L is switched to be turned off, the node voltage V2 gently increases due to LC resonance. Thus, when the upper switch SW2H is turned on at a timing at which the node voltage V2 is equal to the input voltage Vi (that is, at a timing at which a voltage across the upper switch SW2H is 0 V), the soft switching operation (ZVS operation) may be realized.

[0044] Also, as illustrated in the time duration of t7 to t8, in a state where the upper switch SW2H and the lower switch SW1L are turned on and the upper switch SW1H and the lower switch SW2L are turned off, when the upper switch SW2H is switched to be turned off, the node voltage V2 gently decreases due to LC resonance. Thus, when the lower switch SW2L is turned on at a timing at which the node voltage V2 is equal to the ground voltage GND1 (that is, at a timing at which a voltage across the lower switch SW2L is 0 V), the soft switching operation (ZVS operation) may be realized.

[0045] Further, like patterns (b) of the node voltages V1 and V2, in a case in which the simultaneous OFF time Td of the upper switch and the lower switch is equal to an optimal value that satisfies the timing condition, an ideal soft switching operation (ZVS operation) may be realized, dramatically reducing switching loss and switching noise.

[0046] However, like patterns (a) of the node voltages V1 and V2, in a case in which the simultaneous OFF time Td is shorter than the optimal value, the simultaneous OFF time Td expires before the node voltages V1 and V2 increase to the input voltage Vi or before the node voltages V1 and V2 decrease to the ground voltage GND1.

[0047] Also, like patterns (c) of the node voltages V1 and V2, in a case in which the simultaneous OFF time Td is longer than the optimal value, the simultaneous OFF time Td expires after the node voltages V1 and V2 increase to the input voltage Vi and turn to decrease or after the node voltages V1 and V2 decrease to the ground voltage GND1 and turn to increase.

[0048] Thus, when the simultaneous OFF time Td is not identical to the optimal value, since the switch having a potential difference between both ends thereof is turned on, the effect of reducing switching loss and switching noise is damaged, compared with the ideal case.

[0049] However, the optimal value of the simultaneous OFF time Td is varied due to a state of the load 2, a manufacturing deviation of the switching output circuit 20 or the like, rather than being uniformly determined. For example, when an output current Io flowing in the load 2 is great, a current flowing in the transformer TR1 is also increased in turn. Accordingly, a charge/discharge time of parasitic capacitances C1H and C1L and parasitic capacitances C2H and C2L is reduced, reducing the optimal value of the simultaneous OFF time Td. Conversely, when the output current Io is small, the current flowing in the transformer TR1 is also decreased in turn. Thus, since the charge/discharge time of the parasitic capacitances C1H and C1L and the parasitic capacitances C2H and C2L is increased, the optimal time of the simultaneous OFF time Td is increased.

[0050] Thus, in order to always perform an optimal soft switching operation (ZVS operation), the switch driving circuit 10 has a function of periodically updating the simultaneous OFF time Td prepared to soft-switch the upper switches SW1H and SW2H and the lower switches SW1L and SW2L of the switching output circuit 20. This will be described in more detail hereinafter.

[0051] FIGS. 3A, 3B, 3C, 3D, 3E, and 3F are block diagrams illustrating an example of an input/output monitoring operation required to optimize the simultaneous OFF time Td. The switch driving circuit 10 monitors an output power Po or an input power Pi of the switching output circuit 20 and optimizes the simultaneous OFF time Td depending on the monitoring result.

[0052] Further, in case of monitoring the output power Po, an output current Io and an output voltage Vo of the switching output circuit 20 may be individually monitored as illustrated in the column (FIG. 3A). However, when the output voltage Vo may be regarded as being constant, only the output current Io may be monitored as illustrated in the column (FIG. 3B). Also, when the output current Io may be regarded as being constant, only the output voltage Vo may be monitored as illustrated in the column (FIG. 3C).

[0053] Meanwhile, in case of monitoring the input power Pi, an input current Ii and an input voltage Vi of the switching output circuit 20 may be individually monitored as illustrated in the column (FIG. 3D). However, when the input voltage Vi may be regarded as being constant, only the input current Ii may be monitored as illustrated in the column (FIG. 3E). Also, when the input current Ii may be regarded as being constant, only the input voltage Vi may be monitored as illustrated in the column (FIG. 3F).

[0054] That is, in optimizing the simultaneous OFF time Td, the switch driving circuit 10 may monitor at least one of the output current Io, the output voltage Vo, the input current Ii, and the input voltage Vi of the switching output circuit 20, as a monitoring target.

[0055] Hereinafter, the simultaneous OFF time updating operation that depends on the monitoring results will be described in detail by way of specific embodiments.

[0056] FIG. 4 is a timing chart illustrating a first example of the simultaneous OFF time updating operation, in which the gate signals G1H, G1L, G2H, and G2L, the output current Io, a simultaneous OFF time Td1 of the upper switch SW1H and the lower switch SW1L and a simultaneous OFF time Td2 of the upper switch SW2H and the lower switch SW2L are illustrated sequentially from above. Further, in the following description, it may be regarded that the output voltage Vo is constant. Thus, the output power Po is increased as the output current Io is greater, and decreased as the output current Io is smaller.

[0057] In the operation of updating the simultaneous OFF times Td1 and Td2, the switch driving circuit 10 measures magnitudes (“Io1” to “Io5” in the exemplary drawing) of the output current Io at each timing of t11 to t15. Further, the switch driving circuit 10 monitors how the output current Io is changed depending on previous updating of the simultaneous OFF times Td1 and Td2 to determine new updated contents. Also, in the first example of the drawing, the magnitude of the output current Io is measured at every rising timing of the gate signal G2H arriving at a predetermined period, but the measurement timing is not limited thereto.

[0058] Hereinafter, a method for updating the simultaneous OFF times Td1 and Td2 based on a change behavior of the output current Io will be described in detail. In a case in which the output current Io is increased depending on previous updating of the simultaneous OFF times Td1 and Td2, the switch driving circuit 10 changes the simultaneous OFF times Td1 and Td2 in a direction of a change that is the same as that of the previous updating. Meanwhile, in a case in which the output current Io is decreased depending on previous updating of the simultaneous OFF times Td1 and Td2, the switch driving circuit 10 changes the simultaneous OFF times Td1 and Td2 in a direction of a change that is opposite to that of the previous updating.

[0059] As an example, a case in which, when the simultaneous OFF times Td1 and Td2 are prolonged from “Td10” to “Td11” at a time t11, the output current Io is increased from “Io1” to “Io2” by comparing the times t11 and t12 will be considered. In this case, since the efficiency of the switching output circuit 20 is increased due to the prolongation of the simultaneous OFF times Td1 and Td2, the switch driving circuit 10 further prolongs the simultaneous OFF times Td1 and Td2 from “Td11” to “Td12” at the time t12.

[0060] Next, a case when the simultaneous OFF times Td1 and Td2 are prolonged from “Td11” to “Td12” at time t12, the output current Io is decreased from “Io2” to “Io3” by comparing times t12 and t13 will be considered. In this case, since the efficiency of the switching output circuit 20 is decreased due to the prolongation of the simultaneous OFF times Td1 and Td2, the switch driving circuit 10 shortens the simultaneous OFF times Td1 and Td2 from “Td12” to “Td13” at the time t13.

[0061] Next, a case when the simultaneous OFF times Td1 and Td2 are shortened from “Td12” to “Td13” at time t13, the output current Io is increased from “Io3” to “Io4” by comparing times t13 and t14 will be considered. In this case, since the efficiency of the switching output circuit 20 is increased due to the shortening of the simultaneous OFF times Td1 and Td2, the switch driving circuit 10 further shortens the simultaneous OFF times Td1 and Td2 from “Td13” to “Td14” at the time t14.

[0062] Next, a case in which, when the simultaneous OFF times Td1 and Td2 are shortened from “Td13” to “Td14” at time t14, the output current Io is decreased from “Io4” to “Io5” by comparing times t14 and t15 will be considered. In this case, since the efficiency of the switching output circuit 20 is decreased due to the shortening of the simultaneous OFF times Td1 and Td2, the switch driving circuit 10 prolongs the simultaneous OFF times Td1 and Td2 from “Td14” to “Td15” at time t15.

[0063] Such a simultaneous OFF time updating operation allows for automatically optimizing the simultaneous OFF times Td1 and Td2 such that the efficiency of the switching output circuit 20 is always enhanced, without relying on a state of the load 2, a manufacturing deviation of the switching output circuit 20, or the like.

[0064] In addition, in the first example of the drawing, an example in which the output voltage Vo is regarded as being constant and only the output current Io being monitored is taken as an example, but as illustrated in FIGS. 3A, 3B, 3C, 3D, 3E and 3F, even when the output current Io is regarded as being constant and the output voltage Vo is monitored or even when the output power Po (both the output current Io and the output voltage Vo) is monitored, the simultaneous OFF times Td1 and Td2 may be updated such that the output power Po is as large as possible.

[0065] Meanwhile, in a case in which the input power Pi (or any one of the input current Ii and the input voltage Vi) is monitored, the simultaneous OFF times Td1 and Td2 need to be updated such that input power Pi is as low as possible. Thus, in the switch driving circuit 10, in a case in which the input power Pi is decreased depending on previous updating of the simultaneous OFF times Td1 and Td2, the simultaneous OFF times Td1 and Td2 may be changed in a direction of a change that is the same as that of the previous updating, and in a case in which the input power Pi is increased depending on previous updating of the simultaneous OFF times Td1 and Td2, the simultaneous OFF times Td1 and Td2 may be changed in a direction of a change that is opposite to that of the previous updating.

[0066] Further, in the first example of the drawing, the switch driving circuit 10 sets the simultaneous OFF time Td1 of the upper switch SW1H and the lower switch SW1L and the simultaneous OFF time Td2 of the upper switch SW2H and the lower switch SW2L to have the same length, and periodically updates each of those at the same timing. With this configuration, the switch driving circuit 10 can be simplified.

[0067] FIG. 5 is a timing chart illustrating a second example of the simultaneous OFF time updating operation, in which the gate signals G1H, G1L, G2H, and G2L, the output current Io, and the simultaneous OFF times Td1 and Td2 are illustrated sequentially from above, like the foregoing case. In the second example of the drawing, the switch driving circuit 10 sets the simultaneous OFF times Td1 and Td2 to have different lengths, and periodically updates the simultaneous OFF times Td1 and Td2 at the same timing, unlike the first example.

[0068] For example, a case when the simultaneous OFF time Td1 is prolonged from “Td10” to “Td11” and the simultaneous OFF time Td2 is prolonged from “Td20” to “Td21” at a time t21, the output current Io is increased from “Io1” to “Io2” by comparing the times t21 and t22 will be considered. In this case, since the efficiency of the switching output circuit 20 is increased due to the prolongation of the simultaneous OFF times Td1 and Td2, the switch driving circuit 10 further prolongs the simultaneous OFF time Td1 from “Td11” to “Td12” and the simultaneous OFF time Td2 from “Td21” to “Td22” at the time t22.

[0069] Cases after time t22 are similar, and when the simultaneous OFF time Td1 is prolonged, the simultaneous OFF time Td2 is also prolonged at the same timing, and when the simultaneous OFF time Td2 is shortened, the simultaneous OFF time Td2 is also shortened at the same timing. However, each of the absolute values is not necessarily the same.

[0070] FIG. 6 is a timing chart illustrating a third example of the simultaneous OFF time updating operation, in which the gate signals G1H, G1L, G2H, and G2L, the output current Io, and the simultaneous OFF times Td1 and Td2 are illustrated sequentially from top to bottom, like the foregoing case. In the third example of the drawing, the switch driving circuit 10 periodically updates the simultaneous OFF times Td1 and Td2 at different timings, unlike the second example.

[0071] Further, in the third example of the drawing, times t31, t33, and t35 are updating timings of the simultaneous OFF time Td1, and times t32 and t34 are updating timings of the simultaneous OFF time Td2. That is, the simultaneous OFF times Td1 and Td2 are alternately updated at different timings.

[0072] First, an operation of updating the simultaneous OFF time Td1 will be described. For example, a case in which, while fixing the simultaneous OFF time Td2 at time t31, when the simultaneous OFF time Td1 is prolonged from “Td10” to “Td11”, the output current Io is increased from “Io1” to “Io2” by comparing times t31 and t32 will be considered. In this case, since the efficiency of the switching output circuit 20 is increased due to the prolongation of the simultaneous OFF time Td1, the switch driving circuit 10 further prolongs the simultaneous OFF time Td1 from “Td11” to “Td12” at time t33, while fixing the simultaneous OFF time Td2.

[0073] Further, a case in which, while fixing the simultaneous OFF time Td2 at time t33, when the simultaneous OFF time Td1 is prolonged from “Td11” to “Td12”, the output current Io is decreased from “Io3” to “Io4” by comparing times t33 and t34 will be considered. In this case, since the efficiency of the switching output circuit 20 is decreased due to the prolongation of the simultaneous OFF time Td1, the switch driving circuit 10 shortens the simultaneous OFF time Td1 from “Td12” to “Td13” at the time t35, while fixing the simultaneous OFF time Td2.

[0074] Next, an operation of updating the simultaneous OFF time Td2 will be described. For example, a case in which, while fixing the simultaneous OFF time Td1 at time t32, when the simultaneous OFF time Td2 is prolonged from “Td20” to “Td21”, the output current Io is decreased from “Io2” to “Io3” by comparing times t32 and t33 will be considered. In this case, since the efficiency of the switching output circuit 20 is decreased due to the prolongation of the simultaneous OFF time Td2, the switch driving circuit 10 shortens the simultaneous OFF time Td2 from “Td21” to “Td22” at time t34, while fixing the simultaneous OFF time Td1.

[0075] In this manner, when the simultaneous OFF times Td1 and Td2 are updated at different timings, the corresponding scheme may also be applied to a case in which the optimal values of the simultaneous OFF times Td1 and Td2 are different. Thus, a more optimal soft switching operation (ZVS operation) may be implemented to increase the effect of reducing switching loss and switching noise.

[0076] FIG. 7 is a timing chart illustrating a fourth example of the simultaneous OFF time updating operation, in which the gate signals G1H, G1L, G2H, and G2L, the output current Io, and the simultaneous OFF times Td1 and Td2 are illustrated sequentially from top to bottom, like the foregoing cases. In the fourth example of the drawing, the switch driving circuit 10 continuously updates the simultaneous OFF times Td1 and Td2 at a plurality of periods, unlike the third example.

[0077] Further, in the fourth example of the drawing, times t41, t42, and t45 are updating timings of the simultaneous OFF time Td1, and times t43 and t44 are updating timings of the simultaneous OFF time Td2.

[0078] First, an operation of updating the simultaneous OFF time Td1 will be described. For example, a case in which, while fixing the simultaneous OFF time Td2 at the time t41, when the simultaneous OFF time Td1 is prolonged from “Td10” to “Td11”, the output current Io is increased from “Io1” to “Io2” by comparing the times t41 and t42 will be considered. In this case, since the efficiency of the switching output circuit 20 is increased due to the prolongation of the simultaneous OFF time Td1, the switch driving circuit 10 further prolongs the simultaneous OFF time Td1 from “Td11” to “Td12” at the time t42, while fixing the simultaneous OFF time Td2.

[0079] Further, a case in which, while fixing the simultaneous OFF time Td2 at time t42, when the simultaneous OFF time Td1 is prolonged from “Td11” to “Td12”, the output current Io is decreased from “Io2” to “Io3” by comparing times t42 and t43 will be considered. In this case, since the efficiency of the switching output circuit 20 is decreased due to the prolongation of the simultaneous OFF time Td1, the switch driving circuit 10 shortens the simultaneous OFF time Td1 from “Td12” to “Td13” at the time t45, while fixing the simultaneous OFF time Td2.

[0080] Next, an operation of updating the simultaneous OFF time Td2 will be described. For example, a case in which, while fixing the simultaneous OFF time Td1 at time t43, when the simultaneous OFF time Td2 is prolonged from “Td20” to “Td21”, the output current Io is increased from “Io3” to “Io4” by comparing times t43 and t44 will be considered. In this case, since the efficiency of the switching output circuit 20 is increased due to the prolongation of the simultaneous OFF time Td2, the switch driving circuit 10 further prolongs the simultaneous OFF time Td2 from “Td21” to “Td22” at time t44, while fixing the simultaneous OFF time Td1.

[0081] FIG. 8 is a timing chart illustrating a fifth example of the simultaneous OFF time updating operation, in which the gate signals G1H, G1L, G2H, and G2L, the output current Io, and the simultaneous OFF times Td1 and Td2 are illustrated sequentially from top to bottom, like the foregoing cases. In the fifth example of the drawing, the switch driving circuit 10 sets updating periods of the simultaneous OFF times Td1 and Td2 to ½, unlike the fourth example. Specifically, the simultaneous OFF times Td1 and Td2 are updated even at a rising timing of the gate signal G2L, as well as at a rising timing of the gate signal G2H.

[0082] With this configuration, since the responsiveness to a fluctuation in the load 2 can be enhanced, a more optimal soft switching operation (ZVS operation) can be implemented to increase the effect of reducing switching loss and switching noise.

[0083] FIG. 9 is a block diagram illustrating a configuration example of the switch driving circuit 10. The switch driving circuit 10 of this configuration example includes a feedback control part 110, a gate driving part 120, an analog/digital conversion part 130, and a digital signal processing part 140.

[0084] Upon receipt of a feedback signal S1 corresponding to the output voltage Vo, the feedback control part 110 generates a pulse signal S2 [a pulse width modulation (PWM) signal or a pulse frequency modulation (PFM) signal].

[0085] Upon receipt of the pulse signal S2, the gate driving part 120 generates gate signals G1H, G1L, G2H, and G2L for complementarily turning on and off the upper switches SW1H and SW2H and the lower switches SW1L and SW2L. In addition, the gate driving part 120 has a function of setting a simultaneous OFF time Td of the upper switches SW1H and SW2H and the lower switches SW1L and SW2L depending on a simultaneous OFF time setting signal S8. For example, as a data value of the simultaneous OFF time setting signal S8 is greater, the gate driving part 120 lengthens the simultaneous OFF time Td, and as the data value of the simultaneous OFF time setting signal S8 is smaller, the gate driving part 120 shortens the simultaneous OFF time Td.

[0086] The analog/digital conversion part 130 converts an analog monitoring signal S3 (at least one of an output current Io, an output voltage Vo, an input current Io, and an input voltage Vo) into a digital monitoring signal S4.

[0087] The digital signal processing part 140 monitors an output power Po or an input power Pi of the switching output circuit 20 and updates the simultaneous OFF time Td, and includes a power monitoring part 141, a storage part 142, a comparing part 143, and a simultaneous OFF time setting part 144.

[0088] The power monitoring part 141 samples/holds the digital monitoring signal S4at an updating timing of a predetermined period (for example, see time duration of t11 to t15 illustrated in FIG. 4), and sequentially outputs the hold value as new data S5.

[0089] The storage part 142 stores the new data S5 input at a certain updating timing, and outputs the stored value as old data S6 at a next updating timing.

[0090] The comparing part 143 compares the new data S5 and the old data S6 to generate a comparison signal S7. For example, the comparison signal S7 has a high level when the output power Po is increased or when the input power Io is reduced depending on previous updating of the simultaneous OFF time Td, and conversely, has a low level when the output power Po is reduced or when the input power Io is increased depending on previous updating of the simultaneous OFF time Td.

[0091] The simultaneous OFF time setting part 144 updates the simultaneous OFF time setting signal S8 depending on the comparison signal S7. For example, when the comparison signal S7 has a high level at the present updating timing depending on a result of prolonging the simultaneous OFF time Td at a previous updating time, the simultaneous OFF time setting part 144 increases a data value of the simultaneous OFF time setting signal S8 such that the simultaneous OFF time Td may be additionally prolonged. Conversely, when the comparison signal S7 has a low level at the present updating timing depending on a result of prolonging the simultaneous OFF time Td at a previous updating time, the simultaneous OFF time setting part 144 decreases the data value of the simultaneous OFF time setting signal S8such that the simultaneous OFF time Td may be reduced.

[0092] Further, when the comparison signal S7 has a high level at the present updating timing depending on a result of shortening the simultaneous OFF time Td at a previous updating time, the simultaneous OFF time setting part 144 decreases the data value of the simultaneous OFF time setting signal S8 such that the simultaneous OFF time Td may be further shortened. Conversely, when the comparison signal S7 has a low level at the present updating timing depending on a result of shortening the simultaneous OFF time Td at a previous updating timing, the simultaneous OFF time setting part 144 increases the data value of the simultaneous OFF time setting signal S8 such that the simultaneous OFF time Td may be prolonged.

[0093] In addition, various technical features disclosed in the present disclosure may be variously modified, without departing from the spirit of the present disclosure, in addition to the foregoing embodiments. That is, it should be considered that the foregoing embodiments are illustrative in every respect and not intended to be limited, and it should be understood that the technical scope of the present disclosure is not the description of the foregoing embodiments but defined by claims and is intended to encompass all the modifications that are within the meanings or scope equivalent to those claims.

[0094] According to the present disclosure in some embodiments, it is possible to provide a switch driving circuit capable of always performing an optimal soft switching operation (ZVS operation), and a switching power device using the same.

[0095] The present disclosure can be employed throughout the switching power device (particularly, a power source for vehicle to industrial equipment that requires a large power, and thus has industrial applicability.

[0096] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the novel methods and apparatuses described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.