MULTIDIMENSIONAL CONTIGUOUS MEMORY ALLOCATION

[0001] This application is a Non-Provisional of U.S. Provisional Patent Application 62/059,488 filed on Oct. 3, 2014, which is incorporated herein by reference.

[0002] The present disclosure relates generally to semiconductor memory and methods, and more particularly, to multidimensional contiguous virtual memory allocation.

[0003] Memory devices are typically provided as internal, semiconductor, integrated circuits in computing systems or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., user data, error data, etc.) and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include non-volatile random access memory (NVRAM), NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

[0004] Computing systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processing resource can comprise a number of functional units (e.g., herein referred to as functional unit circuitry (FUC)) such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can execute instructions to perform logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on data (e.g., one or more operands).

[0005] A number of components in a computing system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be generated, for instance, by a processing resource such as a controller and/or host processing resource. Data (e.g., the operands on which the instructions will be executed to perform the logical operations) may be stored in a memory array that is accessible by the FUC. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the FUC begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the FUC, intermediate results of the operations and/or data may also be sequenced and/or buffered. In many instances, the processing resources (e.g., processor and/or associated FUC) may be external to the memory array, and data can be accessed (e.g., via a bus between the processing resources and the memory array to execute instructions). Data can be moved from the memory array to registers external to the memory array via a bus.

[0006] Virtual memory is a memory mapping technique that is implemented using both hardware and software. It maps memory addresses used by a program, called virtual addresses, into physical addresses in physical memory. The memory space, as seen by a process or task, appears as contiguous address space or a collection of contiguous segments. An operating system manages virtual address spaces and the assignment of physical memory to virtual memory. Software within the operating system may extent these capabilities to provide a virtual address space that can exceed the capacity of real memory and thus reference more than is physically present. Some benefits of virtual memory include freeing applications from having to manage a shared memory space, increased security due to memory isolation, and being able to conceptually use more memory than might be physically available.

[0020] In some approaches to managing virtual memory, the virtual address space may appear to address physical memory as a collection of contiguous segments (e.g., one segment for each allocation of memory) that is one-dimensional, even if the physical memory is organized as a series of hierarchical multidimensional units. As such, virtual allocations can be fulfilled in virtually contiguous, physically disjoint strips of one-dimensional space. The physical memory may become fragmented, which inefficiently utilizes the memory and does not facilitate effective use of contiguous regions of the memory, particularly in more than one dimension of the memory. The more the physical memory becomes fragmented, the more difficult it may be to allocate larger contiguous portions of the memory. However, it may not be advantageous to have a direct correlation between the virtual address space and the physical address space. This can allow the operating system to work with different types of memory, different sizes of memory, and different memory protocols without having to significantly (or at all) change the way the virtual address space operates. For example, this can allow an application that is using virtual memory space to be assigned different physical memory space without having to change the virtual memory space assigned to the application (e.g., the application can be physically “relocated” without the knowledge of and/or action from the application).

[0021] Recent advances in memory technology, for example, related to processing in memory, which can benefit from multidimensional bit contiguity, may make it advantageous to allocate physically bit contiguous blocks of virtual memory. However, the notions of multidimensional physical bit contiguity do not fit current models of one-dimensional virtual allocation. Multidimensional bit contiguity is described in more detail with respect to FIGS. 8-9. Expanding the current use of one-dimensional memory allocation may increase the amount of memory (e.g., large data constructs) that are scanned for candidate unallocated memory in more than one dimension of the physical memory space. Given the statistical potential for significant fragmentation, especially in dense memory devices, an NP search complexity problem can arise that is not useful for applications.

[0022] The present disclosure is related to multidimensional contiguous memory allocation. Multidimensional contiguous memory allocation can include receiving an allocation request for an amount of memory that is contiguous in multiple dimensions of the memory and determining whether the memory includes a region corresponding to the requested amount that is a candidate as being unallocated based on information indicating a maximum number of contiguous unallocated allocable portions of the memory. In response to determining that the memory includes the candidate region, the method can include determining whether the candidate region is unallocated based on a subset of information indicating whether each allocable portion of the memory is allocated. The subset of information corresponds to the candidate region only.

[0023] A number of embodiments of the present disclosure can provide the ability to explicitly allocate virtual memory in well-defined, contiguous multidimensional bit patterns without traversing all possible bits of the target physical memory to determine where space is available. Some embodiments can reduce the search space for a given allocation to be significantly less than the total number of bits in the target memory. A number of embodiments can reduce relative memory fragmentation in multiple dimensions across multiple devices when allocating virtual memory of different shapes and complexity.

[0024] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “A”, “B”, “C”, “M”, “N”, “S”, and “X”, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory devices can refer to one or more memory devices). As used herein, the terms “first” and “second” are used to differentiate between one feature from another and do not necessarily imply an order between the features so designated.

[0025] The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 662 may reference element “62” in FIG. 6, and a similar element may be referenced as 762 in FIG. 7. Multiple analogous elements within one figure may be referenced with a reference numeral followed by a hyphen and another numeral or a letter. For example, 440-1 may reference element 40-1 in FIGS. 4 and 440-X may reference element 40-X, which can be analogous to element 440-1. Such analogous elements may be generally referenced without the hyphen and extra numeral or letter. For example, elements 440-1, . . . , 440-X may be generally referenced as 440. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

[0026] FIG. 1 is a block diagram of an apparatus in the form of a computing system 100 including at least one memory system 104 in accordance with a number of embodiments of the present disclosure. As used herein, a host 102, a memory system 104, a memory device 110, a memory array 111, and/or sensing circuitry 124 might also be separately considered an “apparatus.”

[0027] The computing system 100 can include a host 102 coupled to memory system 104, which includes a memory device 110 (e.g., including a memory array 111 and/or sensing circuitry 124). The host 102 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. In some embodiments, the host 102 can be or include a memory management unit. A memory management unit is a hardware component that performs translation between virtual memory addresses and physical memory addresses. The host 102 can store and/or access a multidimensional matrix 116 (e.g., “ALLOC MATRIX”) and a number of vectors 114 such as “VECTOR 1” 114-1 and “VECTOR 2” 114-2. The host 102 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The computing system 100 can include separate integrated circuits or both the host 102 and the memory system 104 can be on the same integrated circuit. The computing system 100 can be, for instance, a server system and/or a high performance computing system and/or a portion thereof. Although the example shown in FIG. 1 illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures (e.g., a Turing machine), which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

[0028] For clarity, the computing system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 111 can be a hybrid memory cube (HMC), processing in memory random access memory (PIMRAM) array, DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NVRAM array, NAND flash array, and/or NOR flash array, for instance. The memory array 111 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although a single memory device 110 is shown in FIG. 1, embodiments are not so limited. For instance, memory system 104 may include a number of memory devices 110 (e.g., a number of banks of DRAM cells).

[0029] The memory device 110 can be a multidimensional random access memory. A dimension of memory is a coordinate that can be used to specify a location within the memory (e.g., the location of a memory cell or allocable portion of memory). Examples of dimensions of a memory include rows, columns, layers (e.g., in the case of a hybrid memory cube), banks, chips, etc. A memory can have more than three dimensions in terms of coordinates. For example, a memory device 110 can include multiple memory channels (a first dimension of the memory device is a channel), each channel including multiple memory dies (a second dimension of the memory device 110 is a die), each die including multiple subarrays (a third dimension of the memory device 110 is a subarray), and each subarray including multiple rows (a fourth dimension of the memory is a row). Some embodiments are described herein with respect to a two-dimensional memory device for ease of illustration and explanation however embodiments are not so limited. One of ordinary skill in the art, having read and understood the present disclosure can apply the teachings to a memory device 110 having more than two dimensions.

[0030] The memory system 104 can include address circuitry 126 to latch address signals provided over an I/O bus 138 (e.g., a data bus) through I/O circuitry 130. Address signals can be received and decoded by a row decoder 128 and a column decoder 134 to access the memory device 110. Data can be read from the memory array 111 by sensing voltage and/or current changes on the sense lines using sensing circuitry 124. The sensing circuitry 124 can read and latch a page (e.g., row) of data from the memory array 111. The I/O circuitry 130 can be used for bi-directional data communication with host 102 over the I/O bus 138. The write circuitry 132 can be used to write data to the memory device 110.

[0031] Controller 108 can decode signals provided by control bus 136 from the host 102. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory device 110, including data read, data write, and data erase operations. In various embodiments, the controller 108 is responsible for executing instructions from the host 102. The controller 108 can be a state machine, a sequencer, a processor, and/or other control circuitry.

[0032] An example of the sensing circuitry 124 is described further below in association with FIG. 3. For instance, in a number of embodiments, the sensing circuitry 124 can comprise a number of sense amplifiers and a number of compute components, which may comprise latch serving as an accumulator and can be used to perform logical operations (e.g., on data associated with complementary sense lines). Logical operations can include Boolean operations (e.g., AND, OR, NOR, XOR, etc.) as well as combinations of Boolean operations to perform other mathematical operations. In a number of embodiments, the sensing circuitry 124 can be used to perform logical operations using data stored in the memory array 111 as inputs and store the results of the logical operations back to the memory array 111 without transferring via a sense line address access (e.g., without firing a column decode signal). As such, a logical operation can be performed using sensing circuitry 124 rather than and/or in addition to being performed by processing resources external to the sensing circuitry 124 (e.g., by a processor associated with host 102 and/or other processing circuitry, such as ALU circuitry, located on the memory system 104, such as on the controller 108, or elsewhere).

[0033] In various previous approaches, data associated with a logical operation, for instance, would be read from memory via sensing circuitry and provided to an external ALU. The external ALU circuitry would perform the logical operations using the elements (which may be referred to as operands or inputs) and the result could be transferred back to the array via the local I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry 124 can be configured to perform a logical operation on data stored in memory cells in memory array 111 and store the result back to the array 111 without enabling a local I/O line coupled to the sensing circuitry.

[0034] As such, in a number of embodiments, registers and/or an ALU external to the memory array 111 and sensing circuitry 124 may not be needed to perform the logical operation as the sensing circuitry 124 can be operated to perform the logical operation using the address space of memory array 111. Additionally, the logical operation can be performed without the use of an external processing resource.

[0035] The host 102 can be configured with an operating system “OS” 112. The host 102 can be coupled to the memory device 110 (e.g., via the control bus 136 and/or the I/O bus 138. The OS 112 is executable instructions (software) that manages hardware resources and provides services other executable instructions (programs) that run on the OS 112. The OS 112 can implement a virtual memory (VM) system 123. The VM system 123 can control the vectors 114 and the matrix 116. The VM system 123 can implement a search algorithm 118 to search the vectors 114 and/or scan the matrix 116. For example, the OS 112 can include instructions to search a number of vectors 114, each corresponding to a dimension of the memory device 110, instructions to scan the matrix 116 indicating whether respective allocable portions of the memory device 110 are allocated, instructions to allocate 122-1 and/or deallocate 122-2 memory, and/or instructions to manage the virtual memory system 123, among other instructions. The OS 112 can store and/or access a multidimensional matrix 116 and a number of vectors 114. In some embodiments, a vector can be a one-dimensional array.

[0036] The OS 112 can include instructions to respond to a received memory allocation request. The memory allocation request can be a request for an amount of memory that is contiguous in a plurality of dimensions of the memory, as described herein. Memory allocation requests can originate from the host 102 (e.g., from a program running on the host 102) among other originations (e.g., from a direct memory access (DMA) device). The memory allocation requests can be for virtual memory and the OS 112 can include the instructions to manage the virtual memory 123 by mapping memory addresses (e.g., virtual addresses) used by a program to physical addresses in the memory device 110 and vice versa. Additional detail regarding such instructions is provided with respect to FIGS. 4A-7C.

[0037] FIG. 2 is a block diagram of an apparatus in the form of a memory device 210 in accordance with a number of embodiments of the present disclosure. The memory device 210 can be analogous to the memory device 110 illustrated in FIG. 1. The memory device 210 illustrated in FIG. 2 is two-dimensional. A first dimension is the subarrays 258-1, 258-2, 258-3, 258-4, 258-5, 258-6, 258-7, . . . , 258-S. A second dimension is the rows 260. The specific example illustrated in FIG. 2 includes 8 rows 260 and 1024 columns per subarray 258, however embodiments are not limited to any particular number of rows, columns, subarrays, or dimensions. In the example of FIG. 2, an allocable portion of the memory is one row 260, which would include any column within a particular subarray 258 intersecting the row 260. Embodiments are not limited to a particular allocable portion of the memory. In some examples, a portion of a row could be allocable. The specifics of what is considered to be an allocable portion of memory can be specific to particular memory devices 210.

[0038] As described in more detail herein, a multidimensional matrix that includes a respective plurality of units per dimension can be stored, where each unit indicates whether a respective allocable portion of the memory is allocated. Each dimension of the matrix can correspond to a respective dimension of the memory. An n-dimensional matrix corresponds to an n-dimensional memory. For example with respect to FIG. 2, a matrix for the memory device 210 would include a first dimension corresponding to the subarrays 258 and a second dimension corresponding to the rows 260. To facilitate understanding of a number of embodiments of the present disclosure, more detail of an array (e.g., a subarray 258) is given with respect to FIG. 3.

[0039] FIG. 3 is a schematic diagram of a portion of a memory device 310 in accordance with a number of embodiments of the present disclosure. The memory device 310 can include a memory array 311 that includes memory cells 340-1, 340-2, 340-3, 340-4, 340-5, 340-6, 340-7, 340-8, . . . , 340-N coupled to rows of access lines 342-1, 342-2, 342-3, 342-4, 342-5, 342-6, 342-7, . . . , 342-M and columns of sense lines 344-1, 344-2, 344-3, 344-4, 344-5, 344-6, 344-7, 344-8, . . . , 344-N. The memory array 311 is not limited to a particular number of access lines and/or sense lines, and use of the terms “rows” and “columns” does not intend a particular physical structure and/or orientation of the access lines and/or sense lines. Although not pictured, each column of memory cells can be associated with a corresponding pair of complementary sense lines.

[0040] Each column of memory cells can be coupled to sensing circuitry 324, which can be analogous to sensing circuitry 124 illustrated in FIG. 1. In this example, the sensing circuitry includes a number of sense amplifiers 346-1, 346-2, 346-3, 346-4, 346-5, 346-6, 346-7, 346-8, . . . , 346-N coupled to the respective sense lines 344. The sense amplifiers 346 are coupled to input/output (I/O) line 354 (e.g., a local I/O line) via access devices (e.g., transistors) 350-1, 350-2, 350-3, 350-4, 350-5, 350-6, 350-7, 350-8, . . . , 350-N. In this example, the sensing circuitry also includes a number of compute components 348-1, 348-2, 348-3, 348-4, 348-5, 348-6, 348-7, 348-8, . . . , 348-N coupled to the respective sense lines 344. Column decode lines 352-1, 352-2, 352-3, 352-4, 352-5, 352-6, 352-7, 352-8, . . . , 352-N are coupled to the gates of transistors 350 respectively, and can be selectively activated to transfer data sensed by respective sense amps 346 and/or stored in respective compute components 348 to a secondary sense amplifier 356. In a number of embodiments, the compute components 348 can be formed on pitch with the memory cells of their corresponding columns and/or with the corresponding sense amplifiers 346.

[0041] In a number of embodiments, the sensing circuitry (e.g., compute components 348 and sense amplifiers 346) is configured to perform a number of logical operations on elements stored in array 311. As an example, a first plurality of elements can be stored in a first group of memory cells coupled to a particular access line (e.g., access line 342-1) and to a number of sense lines 344, and a second plurality of elements can be stored in a second group of memory cells coupled to a different access line (e.g., access line 342-2) and the respective number of sense lines 344. Each element of the first plurality of elements can have a logical operation performed thereon with a respective one of the second plurality of elements, and the result of the logical operation can be stored (e.g., as a bit-vector) in a third group of memory cells coupled to a particular access line (e.g., access line 342-3) and to the number of sense lines 344.

[0042] A number of embodiments of the present disclosure can include allocating a region of memory that is contiguous in a plurality of dimensions. In the example described above, and as illustrated in more detail with respect to FIGS. 8-9, some advantages of the present disclosure include providing an ability to perform such logical operations on multiple allocable portions of the memory without an intermediate step of moving data that is stored in memory and/or allocating a temporary allocable portion of memory, among others. Some memory devices 310 may include many (e.g., thousands) of columns 344. According to the present disclosure, a logical operation can be performed on the many memory elements associated with the many (e.g., thousands) of columns 344 in parallel in memory (e.g., without transferring the data out of the array, such as to a processing resource). Such embodiments can save a significant amount of time that would otherwise be required if the data was transferred to a processing resource to perform the logical operations (e.g., at 64 bits per clock cycle). As noted above, further advantages can be realized by allocating an amount of memory that is contiguous in multiple dimensions before the logical operation is performed so that there is no stall in the performance of the logical operation in memory in order to align data and/or allocate a temporary allocable portion of memory (e.g., allocate a temporary row of memory).

[0043] FIG. 4A is a diagram of a matrix 416 and a number of vectors 414-1, 414-2 in accordance with a number of embodiments of the present disclosure. The matrix 416 is a multidimensional matrix that stores information indicating whether each allocable portion of the memory is allocated. The matrix 416 includes a respective plurality of units per dimension. Each unit (e.g., unit 466) of the matrix 416 indicates whether a respective allocable portion of memory is allocated. As illustrated, a unit of “1” indicates that the respective allocable portion is allocated and a unit of “0” indicates that the respective allocable portion is unallocated however embodiments are not limited to this convention. In the example of FIG. 4A, the matrix 416 includes information for a first dimension 461-1 (e.g., rows) and a second dimension 461-2 (e.g., subarrays). Each dimension 461 of the matrix 416 corresponds to a respective dimension of the memory. The matrix 416 can be an n-dimensional matrix corresponding to n-dimensions of the memory. At each intersection of the n-dimensions, the matrix 416 can include a respective indication of whether a corresponding allocable portion of the memory is allocated. Each intersection of the matrix 416 represents one allocable portion of the memory.

[0044] Each vector 414 corresponds to a respective one of the dimensions 461 (e.g., vector 414-1 corresponds to dimension 416-1 and vector 414-2 corresponds to dimension 416-2). Each vector 414 includes a respective plurality of entries 468. Each entry 468 represents a maximum number of contiguous unallocated allocable portions 470 of the memory in the corresponding dimension that correspond to a particular element of a different dimension. For example, vector 414-1 includes a plurality of entries including entry 468-1 (e.g., “5”), which represents the maximum number of contiguous unallocated allocable portions 470-1 of the memory in the corresponding first dimension 461-1 that correspond to a particular element of the second dimension 461-2. The entry 468-1 (“5”) indicates that there are a maximum of 5 contiguous unallocated allocable portions (the units that are equal to “0” in the column of units above entry 468-1, which includes, in order, from top-to-bottom, units 0, 1, 1, 0, 0, 0, 0, 0, thus including a maximum of 5 consecutive zeroes). That column of units also includes a single zero by itself, but five is greater than one, which is why the entry 468-1 indicates “5”. Likewise, for example, the vector 414-2 includes a plurality of entries including entry 468-2 (e.g., “3”), which represents the maximum number of contiguous unallocated allocable portions 470-2 of the memory in the corresponding second dimension 461-2 that correspond to a particular element of the first dimension 461-1. The entry 468-2 (“3”) indicates that there are a maximum of 3 contiguous unallocated allocable portions (the units that are equal to “0” in the row of units to the left of entry 468-2, which includes, in order, from left-to-right, units 1, 1, 1, 0, 0, 0, 1, 1, thus including a maximum of 3 consecutive zeroes).

[0045] An operating system of a host and/or a controller can be configured to search the vectors 414 to determine whether the memory includes a candidate region corresponding to an amount of memory that is contiguous in the plurality of dimensions 461. The amount of memory can be defined by a received memory allocation request that specifies an amount of memory that is contiguous in more than one dimension 461. The operating system of the host and/or the controller can search the vectors 414 to determine whether the maximum number of contiguous unallocated allocable portions 470 of the memory per corresponding dimension 461 is sufficient in the dimensions 461 to fulfill the memory allocation request. FIGS. 4B-4C illustrate examples of such candidate regions.

[0046] An operating system of a host (e.g., operating system 112 of host 102 illustrated in FIG. 1) and/or a controller can be configured to store and/or update the matrix 416. For example, the matrix 416 can be updated after memory is allocated. The total memory space used to represent the virtual allocations for any given n-dimensional memory is the sum of the space used to represent the matrix 416 and the vectors 414.

[0047] FIG. 4B is a diagram of the matrix 416 and the number of vectors 414-1, 414-2 illustrated in FIG. 4A, highlighting a candidate region 472-1 in accordance with a number of embodiments of the present disclosure. As described herein, a memory allocation request for an amount of memory that is contiguous in a plurality of dimensions 461 of the memory can be received. In some embodiments, the memory allocation request can be for an amount of virtual memory that also specifies dimensions of the physical memory to be allocated to fulfill the request for virtual memory. For example, a memory allocation request can be for an amount of memory comprising a region of memory that includes four contiguous allocable units in a first dimension 461-1 of the memory by five contiguous allocable units in a second dimension of the memory 461-2 (e.g., a region that measures 4×5 allocable units), which is a request for a region of memory that includes total of 20 allocable units.

[0048] An operating system of a host and/or a controller can be configured to determine whether the first dimension 461-1 includes a first number of contiguous unallocated allocable portions sufficient to fulfill the memory allocation request. For example, this can be accomplished by searching a vector 414-1 corresponding to the first dimension 461-1 for information indicating a maximum number of contiguous unallocated allocable portions of the physical memory in the first dimension 461-1. Each entry in the vector 414-1 indicates the maximum number of contiguous unallocated allocable portions of the physical memory in the first dimension 461-1. Because the memory allocation request specifies four contiguous allocable portions in the first dimension 461-1 and five contiguous allocable portions in the second dimension 461-2, the vector 414-1 can be searched for five consecutive entries that indicate at least four consecutive allocable portions are unallocated. The first three entries in the vector 414-1 are 3, 3, 3, so these will not be sufficient to fulfill the memory allocation request. However the remaining five entries are 8, 5, 5, 5, 5, which means that there are at least five consecutive entries greater than or equal to four, so the memory should have sufficient availability in the first dimension 461-1. These consecutive sufficient entries are labeled as 474-1 in FIG. 4B.

[0049] An operating system of a host and/or a controller can be configured to determine whether the second dimension 461-2 includes a second number of contiguous unallocated allocable portions sufficient to fulfill the memory allocation request. For example, this can be accomplished by searching a vector 414-2 corresponding to the second dimension 461-2 for information indicating a maximum number of contiguous unallocated allocable portions of the physical memory in the first dimension 461-2. Because the memory allocation request specifies four contiguous allocable portions in the first dimension 461-1 and five contiguous allocable portions in the second dimension 461-2, the vector 414-2 can be searched for four consecutive entries that indicate at least five consecutive allocable portions are unallocated. The first three entries in the vector 414-1 are 3, 1, 1, so these will not be sufficient to fulfill the memory allocation request. However the next four entries are 5, 5, 8, 8, which means that there are at least four consecutive entries greater than or equal to five, so the memory should have sufficient availability in the second dimension 461-2. These consecutive sufficient entries are labeled as 474-2 in FIG. 4B. Thus, it has been determined that the memory includes a region 472-1 corresponding to the requested amount that is contiguous in the dimensions 461-1, 461-2 that is a candidate as being unallocated based on information (e.g., information stored in the vectors 414-1, 414-2) indicating a maximum number of contiguous unallocated allocable portions of the memory. Although not specifically illustrated, the operating system of a host and/or a controller can be configured to search additional vectors, if such vectors exist (e.g., for a multidimensional memory that includes more than two dimensions).

[0050] However, the candidate region 472-1 may be partially allocated (see the example illustrated in FIG. 7B). In response to determining that the memory includes the candidate region 472-1, the operating system of a host and/or a controller can be configured to determine whether the candidate region 472-1 is unallocated based on a subset (e.g., the portion of the matrix 416 indicated as the candidate region 472-1) of information (e.g., the matrix 416) indicating whether each allocable portion of the memory is allocated. The subset corresponds to the candidate region 472-1 only. The candidate region 472-1 is illustrated in the matrix 416 even though the matrix 416 is not the memory itself because the matrix 416 includes a plurality of units per dimension 461 that each indicate whether a respective allocable portion of memory is allocated. Thus, the candidate region 472-1 is highlighted within the matrix 416 as a representation of the corresponding region of physical memory. The portion of the matrix 416 includes a number of units equal to a number of allocable portions of the memory needed to fulfill the memory allocation request. The operating system of a host and/or a controller can be configured to scan only the portion of the matrix 416 (e.g., the candidate region 472-1) based on a result of searching the vectors 414. As described herein, the unit “0” indicates that that a corresponding allocable portion of memory is unallocated and the unit “1” indicates that a corresponding allocable portion of memory is allocated. As illustrated in FIG. 4B, the candidate region 472-1 includes all 0s, thus, scanning the portion of the matrix would result in a confirmation that the portion of the matrix included all 0's, providing a determination that the candidate region 472-1 is unallocated. Searching the vectors 414 and scanning a respective portion 472 of the matrix 416 reduces the search space for finding available multidimensional memory versus an alternative of searching a bit for every allocable portion of the memory.

[0051] FIG. 4C is a diagram of the matrix 416 and the number of vectors 414-1, 414-2 illustrated in FIG. 4A, highlighting a candidate region 472-2 in accordance with a number of embodiments of the present disclosure. Returning to the discussion of searching the vectors 414, the first vector 414-1 included only one set 474-1 of consecutive entries sufficient to fulfill the memory allocation request in the first dimension 461-1 (e.g., the entries 8, 5, 5, 5, 5, were the only set of at least five consecutive entries that indicate at least four consecutive allocable portions are unallocated in the first dimension 461-1). In FIG. 4B, the set 474-2 of consecutive entries sufficient to fulfill the memory allocation request in the second dimension 461-2 (e.g., the entries 5, 5, 8, 8, were a set of at least four consecutive entries that indicate at least five consecutive allocable portions are unallocated in the second dimension 461-2) was identified. However, as illustrated in FIG. 4C, the second vector 414-2 includes another set 474-3 of consecutive entries sufficient to fulfill the memory allocation request in the second dimension 461-2 (e.g., the entries 5, 8, 8, 8, are a set of at least five consecutive entries that indicate at least four consecutive allocable portions are unallocated in the second dimension 461-2). Thus, the operating system of a host and/or a controller can determine that the memory includes another region 472-2 corresponding to the requested amount that is contiguous in the dimensions 461-1, 461-2 that is a candidate as being unallocated based on information (e.g., information stored in the vectors 414-1, 414-2) indicating a maximum number of contiguous unallocated allocable portions of the memory.

[0052] FIG. 5 is a diagram of the matrix and the number of vectors illustrated in FIG. 4A after allocation of the candidate region highlighted in FIG. 4B in accordance with a number of embodiments of the present disclosure. The operating system of a host and/or a controller can be configured to allocate a candidate region 572-1, which is analogous to candidate region 472-1 illustrated in FIG. 4B, in response to determining that the candidate region 572-1 is unallocated. The allocation of the candidate region 572-1 can fulfill the memory allocation request. After allocation, the operating system of a host and/or a controller can be configured to update the multidimensional matrix 516 and the vectors 514-1, 514-2. For example, updating the matrix 516 can include changing the units within the candidate region 572-1 from 0 to 1 (e.g., as illustrated at unit 566, which has changed from a 0 in FIG. 4B to a 1 in FIG. 5).

[0053] Updating the vectors 514 can include calculating new entries for the sets (e.g., sets 474-1, 474-2 illustrated in FIG. 4B) of consecutive entries that were sufficient to fulfill the memory allocation request and that correspond to the allocated region 572-1. For example, in vector 514-1, the set of entries 569-1 have been updated from 8, 5, 5, 5, 5, in FIG. 4B to 3, 1, 1, 1, 1, in FIG. 5 because with the allocation of the region 572-1, the maximum number of consecutive unallocated allocable portions of memory have changed in the first dimension 561-1 for that region 572-1. Likewise, in vector 514-2, the set of entries 569-2 have been updated from 5, 5, 8, 8, in FIG. 4B to 0, 0, 3, 3, in FIG. 5 because with the allocation of the region 572-1, the maximum number of consecutive unallocated allocable portions of memory have changed in the second dimension 561-2 for that region 572-1.

[0054] FIG. 6 is a diagram of the matrix and the number of vectors illustrated in FIG. 4A after allocation of the candidate region highlighted in FIG. 4C in accordance with a number of embodiments of the present disclosure. The operating system of a host and/or a controller can be configured to allocate a candidate region 672-2, which is analogous to candidate region 472-2 illustrated in FIG. 4C, in response to determining that the candidate region 672-2 is unallocated. The allocation of the candidate region 672-2 can fulfill the memory allocation request. After allocation, the operating system of a host and/or a controller can be configured to update the multidimensional matrix 616 and the vectors 614-1, 614-2. For example, updating the matrix 616 can include changing the units within the candidate region 672-1 from 0 to 1 (e.g., as illustrated at unit 666, which has changed from a 0 in FIG. 4C to a 1 in FIG. 6).

[0055] Updating the vectors 614 can include calculating new entries for the sets (e.g., sets 474-1, 474-3 illustrated in FIG. 4C) of consecutive entries that were sufficient to fulfill the memory allocation request and that correspond to the allocated region 672-2. For example, in vector 614-1, the set of entries 669-1 have been updated from 8, 5, 5, 5, 5, in FIG. 4C to 4, 1, 1, 1, 1, in FIG. 6 because with the allocation of the region 672-2, the maximum number of consecutive unallocated allocable portions of memory have changed in the first dimension 661-1 for that region 672-2. Likewise, in vector 614-2, the set of entries 669-3 have been updated from 5, 8, 8, 8, in FIG. 4C to 0, 3, 3, 3, in FIG. 6 because with the allocation of the region 672-2, the maximum number of consecutive unallocated allocable portions of memory have changed in the second dimension 661-2 for that region 672-2.

[0056] Comparing the result of the allocation illustrated in FIG. 5 to the allocation illustrated in FIG. 6, FIG. 5 results in a larger maximum consecutive unallocated allocable portion in the second dimension 561-2. The vector 514-2 includes an 8, whereas the largest maximum consecutive unallocated allocable portion in FIG. 6 is 5, as illustrated by the vector 614-2. However, FIG. 6 results in a larger maximum consecutive unallocated allocable portion in the first dimension 661-1. The vector 614-1 includes a 4, whereas the largest maximum consecutive unallocated allocable portion in FIG. 5 is 3, as illustrated by the vector 514-1. In some embodiments, when more than one allocation is possible to satisfy a memory allocation request, the operating system of a host and/or a controller can be configured to choose between the possibilities based on which dimension of memory is more frequently allocated in larger consecutive allocable portions or based on a configurable operating parameter.

[0057] FIG. 7A is a diagram of a matrix 716 and a number of vectors 714-1, 714-2 in accordance with a number of embodiments of the present disclosure. The matrix 716 can be analogous to the matrix 416 illustrated in FIG. 4A, but with different entries. Likewise, the vectors 714 can be analogous to the vectors 414 illustrated in FIG. 4A, but with different entries. In the example of FIG. 7A, the matrix 716 includes information for a first dimension 761-1 and a second dimension 761-2. Each dimension 761 of the matrix 716 corresponds to a respective dimension of the memory.

[0058] FIG. 7B is a diagram of the matrix and the number of vectors illustrated in FIG. 7A, highlighting a candidate region 772-1 that is partially allocated in accordance with a number of embodiments of the present disclosure. The operating system of a host and/or a controller can be configured to determine whether a first region 772-1 of memory that is contiguous in more than one dimension 761-1, 761-2 and that is a candidate as being unallocated exists. The candidate region 772-1 is an amount of memory sufficient to fulfill the memory allocation request. For example, a memory allocation request can be for an amount of memory comprising a region of memory that includes three contiguous allocable units in a first dimension 761-1 of the memory by four contiguous allocable units in a second dimension of the memory 761-2 (e.g., a region that measures 3×4 allocable units), which is a request for a region of memory that includes total of 12 allocable units.

[0059] Because the memory allocation request specifies three contiguous allocable portions in the first dimension 761-1 and four contiguous allocable portions in the second dimension 761-2, the vector 714-1 can be searched for four consecutive entries that indicate at least three consecutive allocable portions are unallocated. The first four entries in the vector 714-1 are 3, 4, 3, 5, which means that there are at least four consecutive entries greater than or equal to three, so the memory should have sufficient availability in the first dimension 761-1. These consecutive sufficient entries are labeled as 774-1 in FIG. 7B.

[0060] Because the memory allocation request specifies three contiguous allocable portions in the first dimension 761-1 and four contiguous allocable portions in the second dimension 761-2, the vector 714-2 can be searched for three consecutive entries that indicate at least four consecutive allocable portions are unallocated. The first three entries in the vector 714-1 are 4, 1, 1, so these will not be sufficient to fulfill the memory allocation request. However, skipping down, the last three entries are 4, 4, 8, which means that there are at least three consecutive entries greater than or equal to four, so the memory should have sufficient availability in the second dimension 761-2. These consecutive sufficient entries are labeled as 774-2 in FIG. 7B. Thus, it has been determined that the memory includes a region 772-1 corresponding to the requested amount that is contiguous in the dimensions 761-1, 761-2 that is a candidate as being unallocated.

[0061] The operating system of a host and/or a controller can be configured to scan a subset of information indicating whether each allocable portion of the memory is unallocated in response to determining that the first candidate region 772-1 exists. The subset corresponds to the first candidate region 772-1 only. The subset of information can be the information indicated in the matrix 716 within the area highlighted as the first candidate region 772-1. This information can be used to determine whether the first number of contiguous unallocated allocable portions (e.g., the at least three contiguous allocable portions searched for in the first vector 714-1) and the second number of contiguous unallocated allocable portions (e.g., the at least four contiguous allocable portions searched for in the second vector 714-2) are aligned in the first dimension 761-1 and the second dimension 761-2 to form a region of physical memory that is contiguous in the first dimension 761-1 and the second dimension 761-2. If they are aligned in the first dimension 761-1 and the second dimension 761-2, then the region can be allocated. However, as illustrated in FIG. 7B, they are not aligned (at least three of the five consecutive 0s indicated by the entry “5” in the set of consecutive sufficient entries 774-1 are not aligned with the three consecutive 0s indicated by the entries 3, 4, 3 is the set 774-1). This lack of alignment is also indicated by the fact that candidate region 772-1, as illustrated in FIG. 7B includes some 1s, (e.g., unit 766-1 is a 1 and unit 766-2 is a 1).

[0062] This is an example of an instance where the information in the vectors 714 is insufficient on its own to provide certainty whether the candidate region 772-1 is unallocated, which is why the subset of the matrix 716 is scanned after a candidate region 772-1 is identified. The candidate region 772-1 is partially allocated and thus not unallocated. If the candidate region 772-1 had been unallocated, it could have been allocated to fulfill the memory allocation request. In response to the subset of information indicating the first candidate region 772-1 as being allocated (at least partially allocated), the operating system of a host and/or a controller can be configured to determine whether a second region of the memory that is sufficient to fulfill the memory request and that is contiguous in more than one dimension and that is a candidate as being unallocated exists. A determination can be made as to whether the memory includes a second region that is contiguous in the plurality of dimensions 761 corresponding to the requested amount that is a second candidate, as illustrated in more detail in FIG. 7C.

[0063] FIG. 7C is a diagram of the matrix and the number of vectors illustrated in FIG. 7A, highlighting a candidate region 772-2 that is unallocated in accordance with a number of embodiments of the present disclosure. The operating system of a host and/or a controller can be configured to determine whether a second region 772-2 of memory that is contiguous in more than one dimension 761-1, 761-2 and that is a candidate as being unallocated exists.

[0064] As was previously described with respect to FIG. 7B, the last three entries of the second vector 714-2 are 4, 4, 8, which means that there are at least three consecutive entries greater than or equal to four, so the memory should have sufficient availability in the second dimension 761-2. These consecutive sufficient entries are labeled as 774-2 in FIG. 7B, and are the only set of entries in the second vector 714-2 sufficient to fulfill the memory allocation request in the second dimension 761-2. Therefore, the first vector 714-1 can be searched for another set of entries sufficient to fulfill the memory allocation request in response to the subset of information indicating that the first candidate region 772-1 (illustrated in FIG. 7B) is not unallocated.

[0065] The last four entries in the vector 714-1 are 3, 3, 3, 3, which means that there are at least four consecutive entries greater than or equal to three, so the memory should have sufficient availability in the first dimension 761-1. These consecutive sufficient entries are labeled as 774-3 in FIG. 7C. Other than the set 774-1 illustrated and discussed with respect to FIG. 7B, any group of four consecutive entries in the vector 714-1 would include values greater than or equal to three, so any group of four consecutive entries would indicate that the memory should have sufficient availability in the first dimension 761-1 based on searching the vector 714-1 alone. However, as was observed previously from scanning the portion 772-1 of the matrix 716 in FIG. 7B, the entries 766-1, 766-2 are 1, and these entries are in the fourth column of the matrix 716, therefore only that last four columns of the matrix are capable of actually having sufficient availability in the first dimension 761-1 given the set of entries 774-2 already being known as the only viable option in the second dimension 761-2.

[0066] The set of entries 774-2 and the set of entries 774-3 collectively define the second candidate region 772-2. The operating system of a host and/or a controller can be configured to scan a different subset of the information (different than the subset described with respect to FIG. 7B) indicating whether each allocable portion of the memory is unallocated in response to determining that the second candidate region 772-2 exists. The different subset of information corresponds to the second candidate region 772-2 only. The second candidate region 772-2 can be allocated in response to the different subset of the information indicating the second candidate region as being unallocated. In the example illustrated in FIG. 7C, the subset of information corresponding to the second candidate region 772-2 does indicate that it is unallocated because all of the units therein are 0, thus the second candidate region 772-2 can be allocated to fulfill the memory allocation request. The different subset of information corresponding to the second candidate region 772-2 can be updated to indicate that the second candidate region is allocated (e.g., the 0s can be changed to is in the matrix 716). Likewise, the vectors 714-1, 714-2 can be updated (e.g., as described with respect to FIGS. 5-6).

[0067] If the different subset of information corresponding to the second candidate region 772-2 had not indicated that it was unallocated, then the operating system of a host and/or a controller can be configured to determine whether a third region of the memory that is contiguous in more than one dimension 761 and that is a candidate as being unallocated exists in response thereto. The vectors 714 can be searched and respective portions of the matrix 716 can be scanned, as described herein, for each iteration of this process. This process can be repeated until all possibilities have been eliminated or until the memory allocation request has been fulfilled. If a region that is contiguous in the plurality of dimension 761 of the memory and that is unallocated is not converged on (e.g., if all possibilities are eliminated without fulfilling the memory allocation request) a null point can be returned in response. The null point can indicate to the operating system, for example, that there is not sufficient memory available to fulfill the memory allocation request.

[0068] FIG. 8 is a block diagram illustrating a memory operation for memory that is not contiguous in a plurality of dimensions. The instance illustrated in FIG. 8 includes a first array portion 811-1 and a second array portion 811-2. Each array portion 811 includes a respective sensing circuitry portion 824-1, 824-2. The memory, including the array portion 811 and the sensing circuitry portion 824 can be analogous to the memory device 410 illustrated in FIG. 3. The first array portion 811-1 can be a first subarray 858-1 and the second array portion 811-2 can be a second subarray 858-2. The subarrays 858 can be a first dimension of the memory. Three rows 860-1, 860-2, 860-3 are illustrated. The first row 860-1 and the third row 860-3 are in the first subarray 858-1 and the second row 860-2 is in the second subarray 858-2. The rows 860 can be a second dimension of the memory.

[0069] A, B, and C can be considered as variables that each include a number of elements (e.g., bits) from 0 to n. Variable A in row 860-1, variable B in row 860-2, and variable C in row 860-3 are bit contiguous in one dimension (e.g., along each row) because the elements are arranged in order and are all contained in the same dimension (e.g., row). Variables A and C are also contiguous in a second dimension (e.g., column) because corresponding elements of each variable are located in the same column. For example A[0] is in the same column as C[0], A[1] is in the same column as C[1], etc. This second dimension of contiguity may also be referred to as locality. However, variable B is not contiguous in a plurality of dimensions with variables A and C because the corresponding elements are not located in the same columns. It can be said that variables A, B, and C are bit contiguous in one dimension, but not bit local.

[0070] As an example of a logical operation that can be performed in memory in order to illustrate some advantages of the present disclosure, consider an operation that uses the first row 860-1 and the second row 860-2 as input and stores a result of the logical operation performed on the first row 860-1 and the second row 860-2 in the third row 860-3. By way of example, each i^th element of the first row 860-1 and the second row 860-2 can be added. An example of code for this operation is:

	int i;
	uint64_t A[N];
	uint64_t B[N];
	uint64_t C[N];
	for ( i=0; i<N; i++ ){
	C[i] = A[i] + B[i]
	}

where A is the first row 860-1, B is the second row 860-2, C is the third row 860-3, and each row 860 contains elements from 0 to N, individually referred to as i.

[0071] In order to perform the logical operation in memory, each i^th element should be physically aligned in memory. If they are not aligned, then the software runtime allocates a temporary row 878 and preemptively moves the data (e.g., the second row 860-2 from array portion 811-2 to array portion 811-1) in order to perform the alignment prior to performing the logical operation. Thus, the additional operations of creating a temporary row and moving the data (reading and writing) must be performed. This adds latency to the logical operation that is dependent on the amount of data to be moved and the bandwidth of the respective subarrays 858.

[0072] FIG. 9 is a block diagram illustrating a memory operation for memory that is contiguous in a plurality of dimensions in accordance with a number of embodiments of the present disclosure. Following on the example illustrated in FIG. 8, according to the present disclosure, this latency can be avoided. The ability to allocate contiguous memory in more than one dimension, as described herein, can provide a layout as illustrated in FIG. 9 in the first instance. The first row 960-1, the second row 960-2, and the third row 960-3 can all be allocated in one subarray 958 that includes array portion 911 and sensing circuitry portion 924. As such, no data movement or temporary row allocation operations are required to perform the desired logical operation in memory. This allows the performance gains provided by processing in memory (e.g., massively parallel logical operations without transferring data out of the array as described herein) to be realized without the additional latency described above.

[0073] Although not specifically illustrated as such, a non-transitory computing system readable medium for storing executable instructions can include all forms of volatile and non-volatile memory, including, by way of example, semiconductor memory devices, DRAM, HMC, EPROM, EEPROM, flash memory devices, magnetic disks such as fixed, floppy, and removable disks, other magnetic media including tape, optical media such as compact discs (CDs), digital versatile discs (DVDs), and Blu-Ray discs (BD). The instructions may be supplemented by, or incorporated in, ASICs.

[0074] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

[0075] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.