METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

[0001] This U.S. non-provisional patent application claims the benefit of priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0104581, filed on Aug. 12, 2014, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

[0002] 1. Field

[0003] The inventive concepts relate to semiconductor devices and/or methods for manufacturing the same. More particularly, the inventive concepts relate to semiconductor devices including a field effect transistor and/or methods for manufacturing the same.

[0004] 2. Description of Related Art

[0005] Semiconductor devices are widely used in the electronic industry because of their small size, multi-function, and/or lower manufacturing costs. Semiconductor devices may be classified into semiconductor memory devices storing logical data, semiconductor logic devices processing logical data, and hybrid semiconductor devices having both the function of the semiconductor memory devices and the function of the semiconductor logic devices. Semiconductor devices with improved characteristics have been demanded with the development of the electronic industry. For example, high-reliable, high-speed, and/or multi-functional semiconductor devices have been increasingly demanded. To satisfy these demands, structures of semiconductor devices become more complicated and integration degrees of semiconductor devices are increasing.

[0006] Example embodiments of the inventive concepts may provide semiconductor devices including field effect transistors having threshold voltages different from each other.

[0007] Example embodiments of the inventive concepts may also provide methods for manufacturing a semiconductor device including field effect transistors having threshold voltages different from each other.

[0008] In some example embodiments, a method for manufacturing a semiconductor device includes forming first fins protruding from a substrate, the substrate including a first region and a second region, and the first fins including silicon-germanium (SiGe); forming a first mask pattern to expose the first fins disposed in the second region, the first mask pattern covering the first fins disposed in the first region; oxidizing the first fins in the second region to form second fins in the second region; and forming germanium (Ge)-rich layers, each of the Ge-rich layers disposed on a surface of a respective one of the second fins.

[0009] In some example embodiments, a Ge concentration of the second fins may be substantially equal to a Ge concentration of the first fins.

[0010] In some example embodiments, the oxidizing selectively oxidizes the first fins in the second region using the first mask pattern as an oxidation prevention layer.

[0011] In some example embodiments, the oxidizing reduces widths of the first fins in the second region.

[0012] In some embodiments, the method may further include forming a device isolation layer covering sidewalls of the first fins in the first and second regions. In this case, the first fins may include protruding portions protruding from the device isolation layer and including SiGe.

[0013] In some example embodiments, the substrate may include silicon (Si). The forming the first fins may include forming buried portions on the substrate; and forming protruding portions including SiGe on the buried portions. In this case, the buried portions may include buffer layers that reduce a difference between a lattice constant of the substrate and a lattice constant of the protruding portions.

[0014] In some example embodiments, the forming the first fins may include forming an epitaxial layer including SiGe on the substrate; forming second mask patterns on the epitaxial layer; and etching the epitaxial layer using the second mask patterns as etch masks.

[0015] In some example embodiments, the forming the first fins may include forming a device isolation layer on the substrate, forming trenches in the device isolation layer, the trenches exposing a top surface of the substrate, and growing epitaxial layers from the top surface of the substrate exposed by the trenches, the epitaxial layers filling the trenches and including SiGe.

[0016] In some example embodiments, the oxidizing oxidizes surfaces of the first fins in the second region to form the second fins and oxide layers covering the second fins. The Ge-rich layers may be formed along with the oxide layers at the same time and between the second fins and the oxide layers.

[0017] In some example embodiments, the method may further include removing the oxide layers disposed on the second fins and the first mask pattern disposed in the first region; and forming a gate dielectric pattern and a gate electrode pattern that cover the second fins of the second region and the first fins of the first regions.

[0018] In some example embodiments, the method may further include forming source/drain regions on the first fins at both sides of the gate electrode pattern; and forming source/drain regions on the second fins at both sides of the gate electrode pattern.

[0019] In other example embodiments, a method for manufacturing a semiconductor device includes forming a first fin protruding from a first region of a substrate and including silicon-germanium (SiGe); and forming a second fin protruding from a second region of the substrate and including SiGe, the second fin including a germanium (Ge)-rich layer disposed on a surface of the second fin. A Ge concentration of the Ge-rich layer may be greater than Ge concentrations of the first and second fins.

[0020] In some example embodiments, the forming the second fin includes forming an oxide layer covering the Ge-rich layer by an oxidizing process. A width of an upper portion of a structure including the oxide layer and the second fin may be greater than a width of an upper portion of the first fin.

[0021] In some example embodiments, a Ge concentration of the second fin may be substantially equal to that of the first fin.

[0022] In some example embodiments, the method may further include forming a device isolation layer covering sidewalls of the first and second fins. In this case, the formation of the first fin may include forming a first buried portion surrounded by the device isolation layer; and forming a first protruding portion protruding from the first buried portion. The formation of the second fin may include forming a second buried portion surrounded by the device isolation layer; and a second protruding portion protruding from the second buried portion. The Ge-rich layer may cover the second protruding portion.

[0023] In some example embodiments, the substrate may include silicon (Si). The first and second buried portions may include buffer layers that reduce a difference between a lattice constant of the substrate and a lattice constant of the first and second protruding portions.

[0024] In some example embodiments, the method may further include a gate dielectric pattern and a gate electrode pattern that cover the first and second fins. In this case, the Ge-rich layer may be in contact with the second fin and the gate dielectric pattern.

[0025] In some example embodiments, the method may further include first source/drain regions disposed on the first fin at both sides of the gate electrode pattern; and second source/drain regions disposed on the second fin at both sides of the gate electrode pattern.

[0026] In further example embodiments, a method of manufacturing a semiconductor device, includes forming a first fin and a second fin extending over a first region and a second region of a substrate, respectively, the first and the second fins including silicon germanium (SiGe), forming a mask pattern over the first fin to expose the second fin, and oxidizing the second fin so as to form a third fin including a SiGe layer and a germanium (Ge)-rich layer covering surfaces of the SiGe layer.

[0027] In some example embodiments, the third fin may further include an oxide layer covering surfaces of the SiGe layer, the oxide layer being formed during the oxidizing.

[0028] The method may further include forming a device isolation pattern having trenches therein over the first and the second regions of the substrate. The forming the first fin and the second fin may include forming a buried portion of the first fin and a buried portion of the second fin filling the trench over a respective one of the first and second regions, and forming a protruding portion of the first fin and a protruding portion of the second fin such that the protruding portions protrude from a respective one of the buried portions. The buried portions of the first and second fins may include a semiconductor element having a lattice constant different than a lattice constant of SiGe. The protruding portions of the first and second fins may include SiGe.

[0029] The forming the first fin and the second fin may include growing a semiconductor layer over the substrate, forming a mask pattern over the semiconductor layer, and etching the semiconductor layer using the mask pattern as an etching mask to form the first and second fins. A Ge concentration of the first fin may be substantially equal to a Ge concentration of the SiGe layer.

[0030] The oxidizing may include removing Si from the SiGe in the second fin to form the Ge-rich layer so that a Ge concentration of the Ge-rich layer is substantially higher than that of the SiGe layer of the third fin.

[0031] In some example embodiments, a threshold voltage of a first transistor using the first fin as a channel region may be different from a threshold voltage of a second transistor using the second fin as a channel region.

[0032] In some example embodiments, the first fin and the second fin may be doped with dopants of the same conductivity type or different conductivity types from each other.

[0039] Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Thus, the invention may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein. Therefore, it should be understood that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope.

[0040] In the drawings, the thicknesses of layers and regions may be exaggerated for clarity, and like numbers refer to like elements throughout the description of the figures.

[0041] Although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0042] It will be understood that, if an element is referred to as being “connected” or “coupled” to another element, it can be directly connected, or coupled, to the other element or intervening elements may be present. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” if used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

[0044] Spatially relative terms (e.g., “beneath,” “below,” “lower,” “above,” “upper” and the like) may be used herein for ease of description to describe one element or a relationship between a feature and another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0045] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.

[0046] It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0048] As appreciated by the present inventive entity, devices and methods of forming devices according to various embodiments described herein may be embodied in microelectronic devices such as integrated circuits, wherein a plurality of devices according to various embodiments described herein are integrated in the same microelectronic device. Accordingly, the cross-sectional view(s) illustrated herein may be replicated in two different directions, which need not be orthogonal, in the microelectronic device. Thus, a plan view of the microelectronic device that embodies devices according to various embodiments described herein may include a plurality of the devices in an array and/or in a two-dimensional pattern that is based on the functionality of the microelectronic device.

[0049] The devices according to various embodiments described herein may be interspersed among other devices depending on the functionality of the microelectronic device. Moreover, microelectronic devices according to various embodiments described herein may be replicated in a third direction that may be orthogonal to the two different directions, to provide three-dimensional integrated circuits.

[0050] Accordingly, the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. The plurality of device structures may be integrated in a same electronic device. For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include a plurality of active regions and transistor structures (or memory cell structures, gate structures, etc., as appropriate to the case) thereon, as would be illustrated by a plan view of the device/structure. The plurality of device structures may be arranged in an array and/or in a two-dimensional pattern.

[0051] In order to more specifically describe example embodiments, various features will be described in detail with reference to the attached drawings. However, example embodiments described are not limited thereto.

[0052] A method for manufacturing a semiconductor device according to some example embodiments will be described with reference to FIGS. 1A to 6A and 1B to 6B. FIGS. 1A to 6A are perspective views illustrating a method for manufacturing a semiconductor device according to some example embodiments of the inventive concepts. FIGS. 1B to 6B are cross-sectional views taken along lines A-A′ of FIGS. 1A to 6A, respectively.

[0053] Referring to FIGS. 1A and 1B, a substrate 100 including a first region RG1 and a second region RG2 may be provided. The substrate 100 may include a semiconductor-based structure. In some example embodiments, the substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. The first region RG1 and the second region RG2 may correspond to different regions of the substrate 100. For example, the first and second regions RG1 and RG2 may be regions in which different threshold voltages from each other are required. In some embodiments, all of the first and second regions RG1 and RG2 may be N-type metal-oxide-semiconductor (NMOS) transistor regions, or P-type MOS (PMOS) transistor regions. In other example embodiments, one of the first and second regions RG1 and RG2 may be the NMOS transistor region, and the other of the first and second regions RG1 and RG2 may be the PMOS transistor region. However, example embodiments of the inventive concepts are not limited thereto.

[0054] A buffer layer 110 and a semiconductor layer 120 may be sequentially formed on the substrate 100. The buffer layer 110 may be formed by a selective epitaxial growth (SEG) process using the substrate 100 as a seed layer. The buffer layer 110 may relax (or, alternatively, reduce) a difference between a lattice constant of the substrate 100 and a lattice constant of the semiconductor layer 120. In other words, the buffer layer 110 may relax (or, alternatively, reduce) a stress that may be caused by the difference between the lattice constants of the substrate 100 and the semiconductor layer 120. For example, if the semiconductor layer 120 including silicon-germanium (SiGe) is epitaxially grown directly on the substrate 100 including silicon (Si), crystal defects may occur in the semiconductor layer 120 by the stress caused by the difference between lattice constants of silicon (Si) and silicon-germanium (SiGe). However, according to example embodiments of the inventive concepts, the semiconductor layer 120 may not be in contact with the substrate 100 due to the buffer layer 110, so crystal defects of the semiconductor layer 120 may be reduced. The semiconductor layer 120 may be formed by a SEG process using the substrate 100 or the buffer layer 110 as a seed layer. For example, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0055] The semiconductor layer 120 and the buffer layer 110 may include SiGe. In addition, the buffer layer 110 may further include a semiconductor element of which a lattice constant is greater or smaller than that of SiGe. Because the buffer layer 110 includes the semiconductor element different from the semiconductor layer 120, a compressive force or a tensile force may be provided to a channel region defined in the semiconductor layer 120. The channel region will be described in more detail later.

[0056] In other example embodiments, the buffer layer 110 may be omitted. In this case, the semiconductor layer 120 may be formed directly on the substrate 100, and the semiconductor layer 120 may be etched or patterned to form first fins F1.

[0057] Referring to FIGS. 2A and 2B, first fins F1 protruding from the substrate 100 may be formed on the substrate 100 in the first and second regions RG1 and RG2. In more detail, a first mask layer (not shown) may be formed on the semiconductor layer 120, and the first mask layer may be patterned to form first mask patterns 206 defining the first fins F1. For example, the first mask layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, photoresist, spin-on-glass (SOG), or spin-on-hardmask (SOH). The first mask layer may be formed by at least one of a physical vapor deposition (PVD) process, a CVD process, an atomic layer deposition (ALD) process, or a spin-coating process.

[0058] The semiconductor layer 120 and the buffer layer 110 may be sequentially etched using the first mask patterns 206 as etch masks to form the first fins F1 having a first width T1. Hereinafter, a width of a fin means a width of an upper portion of the fin in the present embodiments. First trenches 102 may be formed between the first fins F1 by the etching process performed on the semiconductor and buffer layers 120 and 110. Upper portions of the first mask patterns 206 may also be etched by the etching process, so the first mask patterns 206 may have rounded surfaces. Even though not shown in the drawings, the substrate 100 under the first trenches 102 may be recessed by over-etching during the etching process.

[0059] Each of the first fins F1 may have the first width T1 in a first direction X and a length in a second direction Y. The length in the second direction Y may be greater than the first width T1 in the first direction X, so the first fin F1 may have a line shape extending in the second direction Y. The first direction X may be parallel to the top surface of the substrate 100. The second direction Y may be parallel to the top surface of the substrate 100 and may intersect the first direction X. Each of the first fins F1 may include a buried portion 115 protruding from the top surface of the substrate in a third direction Z and a first protruding portion 125 disposed on the buried portion 115. The third direction Z may be perpendicular to the top surface of the substrate 100 and may also be perpendicular to the first and second directions X and Y. The buried portion 115 may be formed by etching the buffer layer 110, and the first protruding portion 125 may be formed by etching the semiconductor layer 120. The first fins F1 may be doped with dopants for controlling a threshold voltage. In some example embodiments, a doping process for controlling the threshold voltage may be performed on the semiconductor layer 120 before the formation of the first mask layer.

[0060] In FIGS. 2A and 2B, a plurality of first fins F1 may be provided on the substrate 100 in each of the first and second regions RG1 and RG2. Alternatively, a single first fin F1 may be provided on the substrate 100 in each of the first and second regions RG1 and RG2. The plurality of first fins F1 in the first region RG1 may form individual transistors, respectively. Alternatively, the plurality of first fins F1 in the first region RG1 may form one transistor. Likewise, the plurality of first fins F1 in the second region RG2 may form individual transistors, respectively, or may form one transistor.

[0061] Referring to FIGS. 3A and 3B, a device isolation layer 130 may be formed to cover sidewalls of lower portions of the first fins F1. In some example embodiments, an insulating layer (not shown) may be formed on the substrate 100 in the first and second regions RG1 and RG2, and the insulating layer may be etched until upper portions of the first fins F1 are exposed, thereby forming the device isolation layer 130. In other example embodiments, the first mask patterns 206 may be removed before forming the insulating layer for the device isolation layer 130 or after forming the device isolation layer 130. The exposed portions of the first fins F1 may correspond to the first protruding portions 125. The device isolation layer 130 may include at least one of a high-density plasma (HDP) oxide layer, a SOG layer, or a CVD oxide layer.

[0062] Referring to FIGS. 4A and 4B, a second mask pattern 210 may be formed on the substrate 100 having the device isolation layer 130 thereon. The second mask pattern 210 may cover the first region RG1 and may expose the second region RG2. The second mask pattern 210 may serve as an oxidation prevention layer that prevents the first fins F1 in the first region RG1 from being oxidized. In some example embodiments, the second mask pattern 210 may be formed of a material having an etch selectivity with respect to the device isolation layer 130. For example, the second mask pattern 210 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a photoresist layer, a SOG layer, or a SOH layer. Here, the second mask pattern 210 may include a different material from the device isolation layer 130.

[0063] Referring to FIGS. 5A and 5B, the first fins Fl in the second region RG2 may be oxidized to form second fins F2 having a second width T2. In more detail, the first fins F1 in the second region RG2 exposed by the second mask pattern 210 may be selectively oxidized by the oxidation process, but the first fins Fl in the first region RG1 covered with the second mask pattern 210 may not be oxidized.

[0064] The first fins F1 in the second region RG2 may be oxidized, so the width of the first fins Fl may be reduced. In more detail, the first protruding portions 125 exposed by the second mask pattern 210 and the device isolation layer 130 may be oxidized to form the second protruding portions 126. The second width T2 of the second protruding portions 126 may be smaller than the first width T1 of the first fins F1. Oxide layers 129, which cover surfaces of the second protruding portions 126, respectively, may be formed simultaneously with the formation of the second protruding portions 126. In addition, germanium (Ge)-rich layers 127 may be formed at interfaces between the second protruding portions 126 and the oxide layers 129, respectively, when the oxide layers 129 are formed. In other words, the second protruding portions 126, the oxide layers 129, and the Ge-rich layers 127 may be formed at the same time by the oxidation process. Each of the second fins F2 may include the buried portion 115, the second protruding portion 126 disposed on the buried portion 115 and the germanium (Ge)-rich layer 127 covering the second protruding portion 126.

[0065] Silicon (Si) may be more easily oxidized than germanium (Ge). Thus, if the first fins F1 including SiGe are oxidized, the oxide layers 129 may be rich with silicon oxide (SiO₂). The surfaces of the first fins F1 in the second region RG2 may be oxidized, so the widths of the first fins F1 may be reduced to form the second fins F2 and the oxide layers 129 may be formed on the surfaces of the second fins F2. At the same time, germanium (Ge) (not oxidized) may be concentrated under the oxide layers 129 to form the interfaces relatively rich in germanium (Ge) (i.e., the Ge-rich layers 127). The terminology “Ge-rich layer” as used in this disclosure refers to a layer having germanium where a germanium (Ge) concentration of the Ge-rich layer is higher than a Ge concentration of the second protruding portions 126. As such, the Ge-rich layers 127 have a Ge concentration higher than the Ge concentration of the second protruding portions 126. Because the oxide layers 129 are formed on only the surfaces of the second protruding portions 126, a Ge concentration of the insides of the second protruding portions 126 may be substantially equal to a Ge concentration of the first protruding portion 125 in the first region RG1.

[0066] A structure including the second protruding portion 126 and the oxide layer 129 disposed thereon may have a third width T3, and the third width T3 may be greater than the first width T1.

[0067] The oxidation process may be, but not limited to, a general oxidation process (e.g., a thermal oxidation process, or a plasma oxidation process).

[0068] For example, the oxidation process may be performed using an oxygen gas at a temperature of about 200° C. to about 1500° C.

[0069] Because a fin field effect transistor uses a fin protruding from a substrate as a body, a short channel effect of the fin field effect transistor may be reduced than that of a planar transistor. However, because the body of the fin field effect transistor is narrower than that of the planar transistor, it may be difficult that a threshold voltage of the fin field effect transistor is controlled by an ion implantation process. According to example embodiments of the inventive concepts, an energy band gap, a strain, and/or a surface charge concentration of the fin including SiGe may be varied depending on a Ge concentration of the surface of the fin. Thus, the threshold voltage of the fin field effect transistor may be varied on depending on the Ge concentration of the surface of the fin. According to some example embodiments of the inventive concepts, the Ge concentration of the surface of the first fin F1 in the first region RG1 may be different from that of the surface of the second fin F2 including the Ge-rich layer 127 in the second region RG2, so the fin field effect transistors having different threshold voltages from each other may be formed in the first region RG1 and the second region RG2, respectively. In other words, according to example embodiments of the inventive concepts, the fins of which surface Ge concentration are different from each other may be easily formed in the first region RG1 and the second region RG2, respectively. Thus, the transistors having the different threshold voltages may be respectively formed in the first and second regions RG1 and RG2 at the same time. In addition, because the Ge concentrations of only the surfaces of the fins are changed, defects of the fins may be reduced.

[0070] Referring to FIGS. 6A and 6B, the oxide layers 129 in the second region RG2 and the second mask pattern 210 in the first region RG1 may be removed. The oxide layers 129 and the second mask pattern 210 may be removed by a single etching process or a plurality of selective etching process.

[0071] Next, a gate dielectric layer (not shown) may be formed on the substrate 100 in the first and second regions RG1 and RG2, and a gate electrode layer (not shown) may be then formed to cover the gate dielectric layer. The gate dielectric layer may include at least one of a silicon oxide layer, a silicon oxynitride layer, or a high-k dielectric layer. For example, the high-k dielectric layer may include at least one of a hafnium oxide layer, a hafnium-silicon oxide, a lanthanum oxide layer, a zirconium oxide layer, a zirconium-silicon oxide layer, a tantalum oxide layer, a titanium oxide layer, a barium-strontium-titanium oxide layer, a barium-titanium oxide layer, a strontium-titanium oxide layer, a lithium oxide layer, an aluminum oxide layer, a lead-scandium-tantalum oxide layer, or a lead-zinc niobate layer. The gate electrode layer may include at least one of a doped semiconductor material, a metal, a conductive metal nitride, or a metal-semiconductor compound (e.g., a metal silicide). In some example embodiments, each of the gate dielectric layer and the gate electrode layer may be formed by at least one of a CVD process, a sputtering process, or an ALD process.

[0072] The gate electrode layer and the gate dielectric layer may be etched using an etch mask to form a gate dielectric pattern 141 and a gate electrode pattern 143. In some embodiments, the gate electrode pattern 143 may be formed using a replacement gate process. For example, the replacement gate process may include forming a sacrificial gate structure including a sacrificial gate dielectric layer and a sacrificial gate electrode, removing the sacrificial gate structure, and replacing the removed sacrificial gate structure with a gate structure including a gate dielectric pattern and a gate electrode pattern. The gate electrode pattern 143 may have a line shape that extends in the first direction X to cross over the first and second fins F1 and F2. The gate dielectric pattern 141 may extend along a bottom surface of the gate electrode pattern 143, so the gate dielectric pattern 141 may cover a top surface and sidewalls of the first protruding portion 125 and a top surface and sidewalls of the second protruding portion 126 having the Ge-rich layer 127 thereon. The gate dielectric pattern 141 may be in contact with the Ge-rich layers 127. In addition, the gate dielectric pattern 141 may horizontally extend from the first and second fins F1 and F2 to partially cover a top surface of the device isolation layer 130.

[0073] Generally, a gate dielectric pattern and a gate electrode pattern may have complex multi-layered structures to control threshold voltages of a fin field effect transistor. However, according to example embodiments of the inventive concepts, because the threshold voltages of the fin field effect transistors are controlled using the Ge-rich layers 127 selectively formed, structures of the gate dielectric pattern 141 and the gate electrode pattern 143 may be simplified. In some example embodiments, each of the gate dielectric pattern 141 and the gate electrode pattern 143 may be formed of a single layer. In some example embodiments, the gate electrode pattern 143 may include a same work function layer in the first and second regions RG1 and RG2.

[0074] In some example embodiments, the source/drain regions may be formed on the first and second fins F1 and F2 at both sides of the gate electrode pattern 143. In some example embodiments, upper portions of the first and second fins F1 and F2 at both sides of the gate electrode pattern 143 may be etched, and a SEG process may be performed on the etched first and second fins F1 and F2 to form the source/drain regions. Portions of the first and second fins F1 and F2, which are surrounded by the source/drain regions and the gate electrode pattern 143, may be defined as the channel regions.

[0075] Like the buried portion 115 (e.g., buffer layer 110 of FIGS. 1A and 1B), the source/drain regions may include a different semiconductor element from the first and second protruding portions 125 and 126) (e.g., the semiconductor layer 120 of FIGS. 1A and 1B). Thus, the source/drain regions may provide a compressive force or a tensile force to the channel regions. If the fin field effect transistors including the first and second fins F1 and F2 are PMOS field effect transistors, the compressive force may be provided to the channel regions. Alternatively, if the fin field effect transistors including the first and second fins F1 and F2 are NMOS field effect transistors, the tensile force may be provided to the channel regions. A conductivity type of the source/drain regions may be different from that of the first and second fins F1 and F2.

[0076] The semiconductor device according to some example embodiments of the inventive concepts will be described with reference to FIGS. 6A and 6B.

[0077] Referring again to FIGS. 6A and 6B, the substrate 100 including the first and second regions RG1 and RG2 may be provided. The substrate 100 may include a semiconductor-based structure. For example, the substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. The first region RG1 and the second region RG2 may correspond to different regions from each other of the substrate 100. For example, the first and second regions RG1 and RG2 may be regions in which different threshold voltages from each other are required. In some example embodiments, all of the first and second regions RG1 and RG2 may be NMOS transistor regions, or PMOS transistor regions. In other example embodiments, one of the first and second regions RG1 and RG2 may be the NMOS transistor region, and the other of the first and second regions RG1 and RG2 may be the PMOS transistor region. However, example embodiments of the inventive concepts are not limited thereto.

[0078] The second fins F2 protruding in the third direction Z may be disposed on the substrate 100 of the second region RG2, and the first fins F1 protruding in the third direction Z may be disposed on the substrate of the first region RG1. The third direction Z may be perpendicular to the top surface of the substrate 100. The first and second fins F1 and F2 may have widths in the first direction X and lengths in the second direction Y. Here, the lengths may be greater than the widths. In other words, the first and second fins F1 and F2 may have line shapes extending in the second direction Y. The first direction X may be parallel to the top surface of the substrate 100. The second direction Y may be parallel to the top surface of the substrate 100 and may intersect the first direction X.

[0079] Each of the first fins F1 may include a buried portion 115 protruding from the top surface of the substrate 100 in the third direction Z and a first protruding portion 125 disposed on the buried portion 115. Each of the second fins F2 may include a buried portion 115 protruding from the top surface of the substrate 100 in the third direction Z, a second protruding portion 126 disposed on the buried portion 115, and a Ge-rich layer 127 disposed on the surface of the second protruding portion 126.

[0080] The first and second protruding portions 125 and 126 may include silicon-germanium (SiGe). If the substrate 100 includes silicon (Si), each of the buried portions 115 may include a buffer layer (110 of FIGS. 1A and 1B) capable of relaxing (or, alternatively, reducing) the difference between the lattice constant of the substrate 100 and the lattice constant of the first and second protruding portions 125 and 126. The buffer layers may further include a semiconductor element of which a lattice constant is greater or smaller than that of SiGe. Because the buffer layers may include the different semiconductor element from the first and second protruding portions 125 and 126, the compressive force or the tensile force may be provided to the channel regions defined in the first and second protruding portions 125 and 126. In other example embodiments, the buffer layers may be omitted. In this case, the buried portion 115 and the first protruding portion 125 which are stacked in the first region RG1 may constitute the first fin F1 of one united body, and the buried portion 115 and the second protruding portion 126 which are stacked in the second region RG2 may constitute the second fin F2 of one united body.

[0081] The first protruding portions 125 may have a first width T1 (see FIG. 2B), and the second protruding portions 126 may have a second width T2 (see FIG. 5B). Here, the second width T2 may be smaller than the first width T1.

[0082] The device isolation layer 130 may be disposed on the substrate 100 to cover the sidewalls of the buried portions 115 of the first and second fins F1 and F2. In other words, the buried portions 115 may be surrounded by the substrate 100, the device isolation layer 130, and the first and second protruding portions 125 and 126. The first and second protruding portions 125 and 126 may protrude upwardly from the device isolation layer 130. For example, top surfaces of the first and second protruding portions 125 and 126 may be higher than a top surface of the device isolation layer 130. The device isolation layer 130 may include at least one of a high-density plasma (HDP) oxide layer, a SOG layer, or a CVD oxide layer.

[0083] The Ge-rich layers 127 may be disposed on the surfaces of the second protruding portions 126, respectively. For example, the Ge-rich layers 127 may cover the surfaces of the second protruding portions 126, respectively. The Ge-rich layers 127 may be in contact with the gate dielectric pattern 141. For example, the Ge-rich layers 127 may be disposed between the gate dielectric pattern 141 and the second protruding portions 126. The Ge concentration of the Ge-rich layers 127 may be greater than the Ge concentration of the second protruding portions 126. Meanwhile, the Ge concentration of the insides of the second protruding portions 126 may be substantially equal to the Ge concentration of the first protruding portions 125. The surfaces of the first protruding portions 125 may not be covered with the Ge-rich layers 127.

[0084] The gate dielectric pattern 141 and the gate electrode pattern 143 may be sequentially stacked on the first and second fins F1 and F2. The gate electrode pattern 143 may have a line shape which extends in the first direction X to cross over the first and second fins F1 and F2. The gate dielectric pattern 141 may extend along the bottom surface of the gate electrode pattern 143, so the gate dielectric pattern 141 may cover the top surfaces and sidewalls of the first and second protruding portions 125 and 126. In addition, the gate dielectric pattern 141 may horizontally extend from the first and second fins F1 and F2 to partially cover the top surface of the device isolation layer 130.

[0085] The gate dielectric pattern 141 may include at least one of a silicon oxide layer, a silicon oxynitride layer, or a high-k dielectric layer. For example, the high-k dielectric layer may include at least one of a hafnium oxide layer, a hafnium-silicon oxide, a lanthanum oxide layer, a zirconium oxide layer, a zirconium-silicon oxide layer, a tantalum oxide layer, a titanium oxide layer, a barium-strontium-titanium oxide layer, a barium-titanium oxide layer, a strontium-titanium oxide layer, a lithium oxide layer, an aluminum oxide layer, a lead-scandium-tantalum oxide layer, or a lead-zinc niobate layer. The gate electrode pattern 143 may include at least one of a doped semiconductor material, a metal, a conductive metal nitride, or a metal-semiconductor compound.

[0086] Even though not shown in the drawings, source/drain regions (not shown) may be disposed on the first and second fins F1 and F2 at both sides of the gate electrode pattern 143. Portions of the first and second fins F1 and F2, which are surrounded by the source/drain regions and the gate electrode pattern 143, may be defined as the channel regions. The source/drain regions may include a different semiconductor element from the semiconductor layer 120 (see FIGS. 1A and 1B), like the buffer layer 110 (see FIGS. 1A and 1B). Thus, the source/drain regions may provide a compressive force or a tensile force to the channel regions. If the fin field effect transistors including the first and second fins F1 and F2 are PMOS field effect transistors, the compressive force may be provided to the channel regions. Alternatively, if the fin field effect transistors including the first and second fins F1 and F2 are NMOS field effect transistors, the tensile force may be provided to the channel regions. A conductivity type of the source/drain regions may be different from that of the first and second fins F1 and F2.

[0087] According to example embodiments of the inventive concepts, the second fins F2 of the second region RG2 may include the Ge-rich layers 127 disposed on the second protruding portions 126, unlike the first fins F1 of the first region RG1. For example, the surface Ge concentration of the first fins F1 including SiGe in the first region RG1 may be different from that of the second fins F2 including SiGe in the second region RG2, so the energy band gap, the strain, and/or the surface charge concentration of the first fins F1 may be different from those of the second fins F2.

[0088] In other words, a threshold voltage of a first transistor using the first fin F1 as a channel region may be different from a threshold voltage of a second transistor using the second fin F2 as a channel region.

[0089] A method for manufacturing a semiconductor device according to other example embodiments will be described with reference to FIGS. 7A, 7B, 8A, and 8B. FIGS. 7A and 8A are perspective views illustrating a method for manufacturing a semiconductor device according to other example embodiments of the inventive concepts. FIGS. 7B and 8B are cross-sectional views taken along lines A-A′ of FIGS. 7A and 8A, respectively.

[0090] In the present example embodiments, the same elements as described in the embodiment of FIGS. 1A to 6A and 1B to 6B will be indicated by the same reference numerals or the same reference designators. Hereinafter, the descriptions to the same element as in the embodiment of FIGS. 1A to 6A and 1B to 6B will be omitted or mentioned briefly for the purpose of ease and convenience in explanation.

[0091] Referring to FIGS. 7A and 7B, a device isolation layer 130 may be formed on a substrate 100. The device isolation layer 130 may be patterned to form second trenches 135. The second trenches 135 may expose the top surface of the substrate 100. The second trenches 135 may extend in the second direction Y parallel to the top surface of the substrate 100 and may be spaced apart from each other in the first direction X intersecting the second direction Y. In other words, the device isolation layer 130 may be patterned to define regions in which first fins F1 will be formed.

[0092] Referring to FIGS. 8A and 8B, first fins F1 may be formed to fill the second trenches 135, respectively. In more detail, buried portions 115 may be first formed to fill the second trenches 135, respectively. Each of the buried portions 115 may include the buffer layer 110 (see FIGS. 1A and 1B). The buried portions 115 may be formed by a selective epitaxial growth (SEG) process using the substrate 100 exposed by the second trenches 135 as a seed layer. Subsequently, first protruding portions 125 which protrude in the third direction Z may be formed on the buried portions 115, respectively. The third direction Z may be perpendicular to the top surface of the substrate 100 and may also be perpendicular to the first and second directions X and Y. The first protruding portions 125 may be formed by a SEG process using the buried portions 115 as a seed layer. Each of the first protruding portions 125 may include the semiconductor layer 120 (see FIGS. 1A and 1B).

[0093] The buried portions 115 and the first protruding portions 125 may constitute first fins F1. In other example embodiments, the buffer layers may be omitted. In this case, the buried portion 115 and the first protruding portion 125 which are sequentially stacked may constitute the first fin F1 of one united body.

[0094] The same subsequent processes as described with reference to FIGS. 4A to 6A and 4B to 6B may be performed to manufacture a semiconductor device.

[0095] FIG. 9 is a schematic block diagram illustrating an electronic system including a semiconductor device according to example embodiments of the inventive concepts.

[0096] Referring to FIG. 9, an electronic system 1100 according to example embodiments of the inventive concepts may include a controller 1110, an input/output (I/O) unit 1120, a memory device 1130, an interface unit 1140, and a data bus 1150. At least two of the controller 1110, the I/O unit 1120, the memory device 1130, and the interface unit 1140 may communicate with each other through the data bus 1150. The data bus 1150 may correspond to a path through which electrical signals are transmitted.

[0097] The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, or other logic devices having a similar function to any one thereof. The I/O unit 1120 may include a keypad, a keyboard and/or a display unit. The memory device 1130 may store data and/or commands. The interface unit 1140 may transmit electrical data to a communication network or may receive electrical data from a communication network. The interface unit 1140 may operate by wireless or cable. For example, the interface unit 1140 may include an antenna a wireless/cable transceiver. Although not shown in the drawings, the electronic system 1100 may further include a fast dynamic random access memory (DRAM) device and/or a fast static random access memory (SRAM) device which acts as a cache memory for improving an operation of the controller 1110. At least one of the semiconductor devices according to the aforementioned example embodiments of the inventive concepts may be provided into at least one of the memory device 1130, the controller 1110, or the I/O unit 1120.

[0098] The electronic system 1100 may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card or other electronic products. The other electronic products may receive or transmit information data by wireless.

[0099] According to example embodiments of the inventive concepts, the field effect transistors may have the different threshold voltages from each other by means of the different surface Ge concentrations of the SiGe fins. In addition, the SiGe fins having the different surface Ge concentrations may be easily formed, and the field effect transistors having the different threshold voltages may be formed at the same time.

[0100] While the inventive concepts have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirits and scopes of the inventive concepts. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scopes of the inventive concepts are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.