SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE AND DISPLAY DEVICE

[0001] The present invention relates to a semiconductor device and a display device provided with thin film transistors, and production method of a semiconductor device and a display device provided with thin film transistors.

[0002] An active matrix liquid crystal display device or an organic EL (Electro Luminescence) display device generally includes: a substrate on which a thin film transistor (Thin Film Transistor; hereinafter referred to as “TFT”) is formed as a switching element for each pixel (hereinafter referred to as “a TFT substrate”; a counter substrate on which a counter electrode, a color filter, and the like are formed; and an optical modulation layer such as a liquid crystal layer disposed between the TFT substrate and the counter substrate.

[0003] On the TFT substrate, a plurality of source lines, a plurality of gate lines, a plurality of TFTs respectively disposed at the crossings thereof, a pixel electrode for applying a voltage across the optical modulation layer such as the liquid crystal layer, a storage capacitor line and a storage capacitor electrode, and the like are formed.

[0004] The configuration of the TFT substrate is disclosed, for example, in Patent Document 1. Hereinafter, with reference to the drawings, the configuration of the TFT substrate disclosed in Patent Document 1 will be described.

[0005] FIG. 29(a) is a schematic plan view generally showing the TFT substrate, and FIG. 29(b) is an enlarged plan view showing one of the pixels in the TFT substrate. FIG. 30 is a sectional view of a TFT and a terminal portion in a semiconductor device shown in FIG. 29.

[0006] As shown in FIG. 29(a), the TFT substrate has a plurality of gate lines 2016 and a plurality of source lines 2017. Respective regions enclosed by these lines 2016 and 2017 constitute “pixels”. In an area 2040 excluding the area in which the pixels are formed (a display area) of the TFT substrate, a plurality of connecting portions 2041 for connecting the plurality of gate lines 2016 and source lines 2017 to a driving circuit, respectively, are disposed. Each connecting portion 2041 constitutes a terminal portion for the connection to external lines.

[0007] As shown in FIG. 29(b) and FIG. 30, a pixel electrode 2020 is provided so as to cover respective regions 2021 which will be pixels. In each region 2021, a TFT is formed. The TFT includes a gate electrode G, gate insulating films 2025 and 2026 which covers the gate electrode G, a semiconductor layer 2019 disposed on the gate insulating film 2026, and a source electrode S and a drain electrode D connected respectively to end portions of the semiconductor layer 2019. The TFT is covered with a protecting film 2028. An interlayer insulating film 2029 is formed between the protecting film 2028 and the pixel electrode 2020. The source electrode S of the TFT is connected to a source line 2017, and the gate electrode G is connected to a gate line 2016. The drain electrode D is connected to the pixel electrode 2020 in a contact hole 2030.

[0008] A storage capacitor line 2018 is formed in parallel to the gate line 2016. The storage capacitor line 2018 is connected to a storage capacitor. Herein the storage capacitor is constituted by a storage capacitor electrode 2018b formed from the same conductive film as the drain electrode, a storage capacitor electrode 2018a formed from the same conductive film as the gate line, and a gate insulating film 2026 positioned between them.

[0009] On the connecting portion 2041 extending from each of the gate lines 2016 and the source lines 2017, the gate insulating films 2025 and 2026 and the protecting film 2028 are not formed, but a connecting line 2044 is formed so as to be in contact with the upper surface of the connecting portion 2041. With such a configuration, electric connection between the connecting portion 2041 and the connecting line 2044 is ensured.

[0010] As shown in FIG. 30, in a liquid crystal display device, a TFT substrate is disposed so as to be opposed to a substrate 2014 on which a counter electrode and a color filter are formed with a liquid crystal layer 2015 interposed therebetween.

[0011] When such a TFT substrate is produced, it is preferred that a region 2021 which will be a pixel (also referred to as “a pixel portion”) and a terminal portion are formed by a common process, so as to suppress the increases in the number of masks and in the number of process steps.

[0012] In order to produce the above-mentioned TFT substrate, it is necessary to perform the etching of a portion positioned in a terminal arranging area 2040 of the gate insulating films 2025 and 2026 and the protecting film 2028 and a portion positioned in a region in which the storage capacitor is formed of the gate insulating film 2025 and the insulating film 2028. Patent Document 1 discloses that an interlayer insulating film 2029 is formed by using an organic insulating film, and by using the film as a mask, these insulating films 2025, 2026, and 2028 are etched.

[0013] Recently, it is proposed that, instead of the silicon semiconductor film, an oxide semiconductor film such as zinc oxide is used for forming a channel layer of a TFT. Such a TFT is referred to as “an oxide semiconductor TFT”. Since the oxide semiconductor has higher mobility than amorphous silicon, the oxide semiconductor TFT can operate at higher speed than the amorphous silicon TFT. The oxide semiconductor film is formed by a process which is simpler and easier than a polycrystalline silicon film, so that it can be applied to a device which is required to have a larger area.

[0014] Patent Document 2 discloses an example of a semiconductor device provided with an oxide semiconductor TFT of inverted stagger type. FIG. 22 of this document depicts that, on the source and drain electrodes of the oxide semiconductor TFT, an insulating layer is formed by sputtering, SOG, spin coating, or other techniques.

[0015] Patent Document 3 discloses an example of an oxide semiconductor TFT of inverted staggered type. The document describes that the semiconductor is oxidized by forming a liquid oxidizer material “self-assembled monolayer (SAM)” on the channel layer of the oxide semiconductor.

[0016] Patent Document 4 discloses an example of an oxide semiconductor TFT of staggered type. In this example, the channel layer and the source and drain electrodes are covered with a protecting layer of SiN_x, SiO₂, or an organic matter.

• [0017] Patent Document 1: Japanese Laid-Open patent Publication No. 2008-170664
• [0018] Patent Document 2: Japanese Laid-Open Patent Publication No. 2010-171406
• [0019] Patent Document 3: U.S. Patent Application Publication No. 2009/0140243
• [0020] Patent Document 4: Japanese Laid-Open Patent Publication No. 2007-73705

[0021] However, in the oxide semiconductor TFT, during the production process of the TFT, for example, in the step of thermal treatment or the like, carrier electrons are created due to oxygen defect, thereby disadvantageously degrading the resistance. In addition, in the etching step of the source and drain electrodes, or the step of forming an insulating layer thereon, there exists a problem that the oxide semiconductor film positioned below may be damaged by reduction or the like.

[0022] In recent years, as the material for oxide semiconductors, IGZO (InGaZnO_x) receives much attention. As the result of the study by the inventors of the present invention, it was found that in the case where IGZO or the like was used for the oxide semiconductor, when a metal layer functioning as the source and drain electrodes was layered on the oxide semiconductor layer, the channel layer was damaged by plasma CVD or other processes, thereby degrading the characteristics of the TFT. In addition, it was found that due to the damage by photolithography in the shaping of the metal layer, or due to the damage in the annealing of an insulating layer or the like on the channel layer, the composition changes of the TFT and the deterioration in characteristics of the TFT were caused. It was considered that the deterioration in characteristics of the TFT was caused by excessive oxygen deficiency generated in the channel layer due to the damage, so as to increase the leakage current. Accordingly, it was considered that the ON-OFF current ratio of the TFT was deviated from predetermined values, so as not to obtain desired characteristics.

[0023] Patent Document 2 describes that in the semiconductor device, two insulating layers are formed for protecting the TFT. However, since the insulating layers are formed on the source and drain electrodes, the damage to the channel portion by dry etching in the step of forming the source and drain electrodes, the damage caused by a residue in the channel portion after the wet etching, or other damages cannot be prevented by the insulating layers.

[0024] In the production process of the semiconductor device in Patent Document 3, after the source and drain electrodes are formed on the gate insulating layer, the channel layer is formed, and thereafter an SAM layer is formed only on the channel layer for oxidizing the channel layer. On the channel layer on which the SAM layer is formed, and on the source and drain electrodes, an active layer is formed. However, this document does not describe a special method for protecting the channel layer from the above-described damages after forming the channel layer.

[0025] In the semiconductor device of stagger type in Patent Document 4, a source electrode and a drain electrode are formed on a plastic substrate, and a channel layer is formed between the source electrode and the drain electrode. On the channel layer, a gate insulating film and a gate electrode are formed in this order. In addition, a protecting film is formed so as to cover the TFT. The protecting film is formed after the gate insulating layer and the gate electrode are formed on the channel layer. The protecting film will not reduce the damage to the channel layer when the gate insulating layer and the gate electrode are formed.

[0026] The present invention has been conducted in view of the above-described prior art, and the objective of the present invention is to produce a semiconductor device having excellent TFT characteristics with good production efficiency by reducing the damage to a channel layer caused in the production of an oxide semiconductor TFT. In addition, another objective of the present invention is to produce a display device provided with such a semiconductor device as a TFT substrate with high performance and high production efficiency.

[0027] The production method of a semiconductor device according to the present invention is a production method of a semiconductor device provided with a thin film transistor, including the steps of:

[0028] (A1) forming a gate electrode of the thin film transistor on a substrate;

[0029] (B1) forming a gate insulating layer so as to cover the gate electrode;

[0030] (C1) forming an oxide semiconductor layer of the thin film transistor on the gate insulating layer;

[0031] (D1) forming a protecting layer by a spin-on-glass technique so as to cover the oxide semiconductor layer;

[0032] (E1) forming a first and a second contact holes in the protecting layer; and

[0033] (F1) forming a source electrode and a drain electrode of the thin film transistor on the protecting layer, wherein

[0034] the source electrode is formed to be electrically connected to the oxide semiconductor layer via the first contact hole, and the drain electrode is formed to be electrically connected to the oxide semiconductor layer via the second contact hole.

[0035] In one embodiment, the step (D1) of forming the protecting layer includes: a step of applying a spin-on-glass material on the oxide semiconductor layer and the gate insulating layer by the spin-on-glass technique; and a step of sintering the applied spin-on-glass material.

[0036] In one embodiment, in the sintering step, the protecting layer of silicon oxide is obtained due to dehydration polymerization reaction of the spin-on-glass material.

[0037] In one embodiment, the spin-on-glass material includes silanol, alkoxysilane, or an organic siloxane resin.

[0038] In one embodiment, the sintering temperature in the sintering step is 200 to 450° C.

[0039] In one embodiment, the production method further includes the steps of: forming an interlayer insulating layer so as to cover the source electrode and the drain electrode; forming a third contact hole in the interlayer insulating layer; and forming a transparent electrode on the interlayer insulating layer so as to be connected to the drain electrode via the third contact hole.

[0040] In one embodiment, the production method further includes the steps of: forming a second protecting layer so as to cover the source electrode and the drain electrode; forming the interlayer insulating layer on the second protecting layer; forming a third contact hole in the second protecting layer and the interlayer insulating layer; and forming a transparent electrode on the interlayer insulating layer so as to be connected to the drain electrode via the third contact hole.

[0041] In one embodiment, the production method includes, after the step (F1), a step of forming a second transparent electrode on the source electrode and the drain electrode and in the first and second contact holes, wherein the source electrode and the drain electrode are electrically connected to the oxide semiconductor layer via the second transparent electrode in the first and second contact holes, respectively.

[0042] In one embodiment, the production method further includes a step of forming a transparent electrode so as to be directly in contact with the drain electrode.

[0043] In one embodiment, the production method includes, after the step (F1), a step of forming a transparent electrode on the source electrode and the drain electrode and in the first and second contact holes, wherein the source electrode and the drain electrode are electrically connected to the oxide semiconductor layer via the transparent electrode in the first and second contact holes, respectively.

[0044] The production method of a display device according to the present invention is a production method of a display device including a transistor portion having a thin film transistor, a Cs portion having a pixel electrode and a storage capacitor, and a terminal portion having a connecting portion for connecting an upper layer wiring and a lower layer wiring, including the steps of:

[0045] (A2) forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer of the thin film transistor, the storage capacitor of the Cs portion, and the lower layer wiring of the terminal portion, on a substrate;

[0046] (B2) forming a protecting layer by a spin-on-glass technique so as to cover the oxide semiconductor layer, the storage capacitor, and the lower layer wiring;

[0047] (C2) forming a source electrode and a drain electrode of the thin film transistor, and the upper layer wiring of the terminal portion, on the protecting layer;

[0048] (D2) forming a first and a second contact holes in the protecting layer in the transistor portion, forming a third contact hole in the protecting layer on the storage capacitor, and removing the protecting layer on at least part of the lower layer wiring of the terminal portion; and

[0049] (E2) forming a transparent electrode on the first, second, and third contact holes, and in the terminal portion, wherein

[0050] the source electrode and the drain electrode, and the oxide semiconductor layer are electrically connected via the transparent electrode, the transparent electrode and a counter electrode of the storage capacitor are electrically connected in the Cs portion, and the lower layer wiring and the upper layer wiring are electrically connected via the transparent electrode in the terminal portion.

[0051] In one embodiment, the step (B2) of forming the protecting layer includes: a step of applying a spin-on-glass material onto the oxide semiconductor layer and the gate insulating layer by a spin-on-glass technique; and a step of sintering the applied spin-on-glass material.

[0052] In one embodiment, in the sintering step, the protecting layer of silicon oxide is obtained due to dehydration polymerization reaction of the spin-on-glass material.

[0053] In one embodiment, the spin-on-glass material includes silanol, alkoxysilane, or an organic siloxane resin.

[0054] The sintering temperature in the sintering step is 200 to 450° C.

[0055] In one embodiment, the production method includes, between steps (C2) and (D2): a step of forming an interlayer insulating layer so as to cover the source electrode, the drain electrode, and the upper layer wiring; a step of forming a second protecting layer on the interlayer insulating layer; and a step of forming a plurality of contact holes in the second protecting layer, wherein in the step (D2), the interlayer insulating layer and the protecting layer under the plurality of contact holes are removed, thereby forming the first, second and third contact holes.

[0056] In one embodiment, in the step (E2), the transparent electrode is formed so as to be directly in contact with the source electrode and the drain electrode of the thin film transistor, the counter electrode of the storage capacitor, and the lower layer wiring and the upper layer wiring of the terminal portion.

[0057] In one embodiment, the step (C2) is performed after the steps (D2) and (E2), thereby forming the source electrode, the drain electrode, and the upper layer wiring of the terminal portion on the transparent electrode.

[0058] The semiconductor device of the present invention is a semiconductor device provided with a thin film transistor, including: a gate electrode of the thin film transistor; a gate insulating layer formed on the gate electrode; an oxide semiconductor layer of the thin film transistor formed on the gate insulating layer; a protecting layer formed on the oxide semiconductor layer by a spin-on-glass technique; and a source electrode and a drain electrode of the thin film transistor disposed on the protecting layer, wherein in the protecting layer, a first contact hole and a second contact hole are formed, the source electrode is electrically connected to the oxide semiconductor layer via the first contact hole, and the drain electrode is electrically connected to the oxide semiconductor layer via the second contact hole.

[0059] In one embodiment, the protecting layer is a layer obtained by applying a spin-on-glass material onto the oxide semiconductor layer and the gate insulating layer by a spin-on-glass technique, and by sintering the applied spin-on-glass material.

[0060] In one embodiment, the protecting layer is a silicon oxide film obtained by dehydration polymerization reaction of the spin-on-glass material.

[0061] In one embodiment, the protecting layer is a layer obtained by the sintering at temperatures of 200 to 450° C.

[0062] The display device according to the present invention is a display device including the above-mentioned semiconductor device.

[0063] In one embodiment, the display device is provided with a transistor portion including the thin film transistor, a Cs portion including a pixel electrode and a storage capacitor, and a terminal portion including a connecting portion for connecting an upper layer wiring and a lower layer wiring, wherein a third contact hole is formed in the protecting layer on the storage capacitor, and a transparent electrode is formed on the first, second, and third contact holes and in the terminal potion, the source electrode and the drain electrode, and the oxide semiconductor layer being electrically connected via the transparent electrode, the transparent electrode and a counter electrode of the storage capacitor being electrically connected in the Cs portion, and the lower layer wiring and the upper layer wiring being electrically connected via the transparent electrode in the terminal portion.

[0064] According to the present invention, the protecting layer is formed on the oxide semiconductor layer by the spin-on-glass technique, so that the damage to the oxide semiconductor layer by sputtering, etching, annealing, or other processes in forming the upper layers such as the source and drain electrodes can be prevented or reduced. Accordingly, the deterioration in characteristics of the semiconductor device and the display device having the oxide semiconductor TFT can be prevented, and it is possible to provide a semiconductor device and a display device with high quality and high reliability.

[0065] According to the present invention, the protecting layer of the spin-on-glass material is formed so as to be in contact with the oxide semiconductor layer, so that H₂O or —OH radical is diffused from the spin-on-glass material into the oxide semiconductor layer in the production, whereby the defect of the oxide semiconductor is restored. Accordingly, the deterioration in characteristics of the semiconductor device and the display device having the oxide semiconductor TFT can be prevented, and it is possible to provide a semiconductor device and a display device with high quality and high reliability.

[0066] According to the present invention, the configuration in which the spin-on-glass material layer is formed on the oxide semiconductor layer, and the source electrode and the drain electrode are connected to the oxide semiconductor layer via the contact hole can be adopted. Thus, the damage to the channel layer due to the etching when the source electrode and the drain electrode are formed, or the plasma damage due to CVD caused after the forming of the oxide semiconductor layer can be prevented.

[0067] According to the present invention, when the oxide semiconductor TFT with high quality is formed, the storage capacitor or the terminal portion of the display device is simultaneously formed. Accordingly, it is possible to provide a display device with high quality and high reliability with good production efficiency.

[0098] Hereinafter with reference to the drawings, a semiconductor device, a display device, and production methods of the semiconductor device and the display device in the embodiments of the present invention will be described. It should be noted that the scope of the present invention is not limited to the embodiments described below. The semiconductor device of the present invention is a TFT substrate in which an oxide semiconductor TFT is formed, and widely includes TFT substrates of various display devices, electronic equipment, and the like. In the following description of the embodiments, the semiconductor device is a TFT substrate for a display device which includes an oxide semiconductor TFT as a switching element.

[0099] FIG. 1 is a sectional view schematically showing the configuration of a semiconductor device 100 (sometimes referred to as “a TFT substrate 100”) in Embodiment 1 of the present invention.

[0100] The semiconductor device 100 includes a thin film transistor 10. The thin film transistor 10 includes a gate electrode 102 formed on a substrate 101 such as a glass substrate, a gate insulating layer 103 (sometimes referred to simply as “an insulating layer 103”) formed on the gate electrode 102, an oxide semiconductor layer 104 formed on the gate insulating layer 103, a protecting layer (an SOG layer) 107 disposed on the gate insulating layer 103 so as to cover the oxide semiconductor layer 104, a source electrode 105 and a drain electrode 106 formed on the protecting layer 107, an interlayer insulating layer 108 (sometimes referred to simply as “an insulating layer 108”) formed on the source electrode 105 and the drain electrode 106, and a transparent electrode 109 formed on the interlayer insulating layer 108.

[0101] In the protecting layer 107, a contact hole (a first contact hole) 131 and a contact hole (a second contact hole) 132 are formed. The source electrode 105 is in contact with the oxide semiconductor layer 104 at the bottom of the contact hole 131. The drain electrode 106 is in contact with the oxide semiconductor layer 104 at the bottom of the contact hole 132. In other words, the source electrode 105 and the drain electrode 106 are electrically connected to the oxide semiconductor layer 104 via the contact holes 131 and 132, respectively.

[0102] The transparent electrode 109 can function as a pixel electrode, so that the transparent electrode 109 is sometimes referred to as “a pixel electrode 109”. In the interlayer insulating layer 108 under the transparent electrode 109, a contact hole (a third contact hole) 133 is formed. The transparent electrode 109 is in contact with the drain electrode 106 at the bottom of the contact hole 133.

[0103] The protecting layer 107 is a silicon oxide film obtained by dehydration polymerization reaction in which a spin-on-glass (SOG) material containing silanol (Si(OH)₄), for example, is applied by spin coating, and the applied spin-on-glass material is sintered (an SOG technique). As the spin-on-glass material, a material containing alkoxysilane, organic siloxane resin, or the like can be used, instead of silanol.

[0104] The source electrode 105 has a two-layer structure in which on a lower layer source electrode 105b of e.g. titan (Ti), an upper layer source electrode 105a of e.g. copper (Cu) is formed. The drain electrode 106 also has a two-layer structure in which on a lower layer drain electrode 106b of e.g. titan an upper layer drain electrode 106a of e.g. copper is formed. The transparent electrode 109 is connected to the upper layer drain electrode 106a via the contact hole 133.

[0105] The gate electrode 102 may also have a two-layer structure in which on a lower layer gate electrode of e.g. titan, an upper layer gate electrode of e.g. copper is formed. The gate electrode 102 may alternatively have a three-layer structure of Ti/Al(aluminum)/Ti, or the like.

[0106] FIG. 2 is a perspective view schematically showing the configuration of a liquid crystal display device 1000 in one embodiment of the present invention. In this embodiment, the liquid crystal display device 1000 includes the above-described semiconductor device 100 as its TFT substrate. The liquid crystal display device 1000 may alternatively include semiconductor devices of Embodiments 2 to 12 which will be described below as its TFT substrate.

[0107] As shown in FIG. 2, the liquid crystal display device 1000 includes the semiconductor device (the TFT substrate) 100 and a counter substrate 200 which are opposed to each other with a liquid crystal layer interposed therebetween, polarizing plates 210 and 220 disposed on the respective outer sides of the TFT substrate 100 and the counter substrate 200, and a backlight unit 230 for emitting light for display to the TFT substrate 100. On the TFT substrate 100, a scanning line driving circuit 240 for driving a plurality of scanning lines (gate bus lines) and a signal line driving circuit 250 for driving a plurality of signal lines (data bus lines) are disposed. The scanning line driving circuit 240 and the signal line driving circuit 250 are connected to a control circuit 260 which is disposed on the inner side or on the outer side of the TFT substrate 100. In accordance with the control by the control circuit 260, a scanning signal for switching the on-off of the TFTs is supplied from the scanning line driving circuit 240 to the plurality of scanning lines, and a display signal (an applied voltage to the pixel electrode 109) is supplied from the signal line driving circuit 250 to a plurality of signal lines.

[0108] The counter substrate 200 is provided with color filters and a common electrode. In the case of three primary color display, the color filters include R (red) filters, G (green) filters, and B (blue) filters disposed in a corresponding manner to the pixels, respectively. The common electrode is formed so as to cover the plurality of pixel electrodes 109 with the liquid crystal layer interposed therebetween. In accordance with the potential difference applied across the common electrode and the respective pixel electrodes 109, liquid crystal molecules between the electrodes are aligned for each pixel, thereby performing display.

[0109] FIG. 3 is a plan view schematically showing the configuration of the TFT substrate 100, and FIG. 4 is a plan view schematically showing the configuration of a display area DA of the TFT substrate 100.

[0110] As shown in FIG. 3, the TFT substrate 100 has a display area DA and a fringe area FA positioned on the outer side of the display area. In the fringe area FA, the scanning line driving circuit 240, the signal line driving circuit 250, and electric elements 25 such as a voltage supplying circuit are disposed by a COG (Chip on Glass) technology. In the vicinity of an outer edge portion of the fringe area FA, terminal portions 30 for attaching external elements such as FPC (Flexible Printed Circuits) are provided.

[0111] In the display area DA, as shown in FIG. 4, a plurality of pixels 50 are disposed in a matrix, and a plurality of scanning lines 160 and a plurality of signal lines 152 are disposed so as to be orthogonal to each other. In the vicinity of respective intersections of the plurality of scanning lines 160 and the plurality of signal lines 152, thin film transistors (TFTs) 10 as active elements are formed for pixels 50, respectively. In each of the pixels 50, a pixel electrode 109 of e.g. ITO (Indium Tin Oxide) is disposed. The pixel electrode 109 is electrically connected to the drain electrode 106 of the TFT 10. Between two scanning lines 160 which are adjacent to each other, a storage capacitor line (also referred to as a Cs line) 162 extends in parallel to the scanning lines 160. In each pixel 10, a storage capacitor (Cs) is formed. Part of the storage capacitor line 162 functions as a storage capacitor electrode (a lower electrode) of the storage capacitor. Part of the scanning line 160 functions as the gate electrode 102. The gate electrode 102, the scanning line 160, the storage capacitor electrode, and the storage capacitor electrode are formed from the same material and by the same process.

[0112] Although not shown in the figure, on the boundary between the display area DA and the fringe area FA, a plurality of connecting lines are formed. Each signal line 152 is electrically connected to a connecting line via a connecting portion formed correspondingly to the signal line. By the connecting portion, the signal line 152 as an upper layer wiring is connected to a connecting line as a lower layer wiring. The drain electrode 106 of the TFT 10 is connected to a storage capacitor counter electrode as an upper electrode of the storage capacitor. The storage capacitor counter electrode is connected to the pixel electrode 109 via a contact hole formed in the interlayer insulating layer 108.

[0113] On the side of the fringe area FA, another connecting portion is disposed. In the connecting portion of the fringe area FA, the connecting line is connected to the upper layer wiring of the fringe area FA, and the upper layer wiring is connected to the electric element 25. The scanning line 160 as the lower layer wiring is connected to the upper layer wiring of the fringe area FA by the connecting portion, and then connected to the electric element 25. The electric element 25 and the terminal portion 30 are connected via a plurality of wirings.

[0114] Next, with reference to FIG. 5, the production method of the TFT substrate 100 will be described.

[0115] In FIG. 5, (a) to (g) are schematic sectional views showing the production process steps of the TFT substrate 100.

[0116] Step (A1):

[0117] First, a Ti layer and a Cu layer are layered in this order on a substrate 101 by sputtering or other techniques. The thickness of the Ti layer is 30 to 150 nm, and the thickness of the Cu layer is 200 to 500 nm. Next, the layered two layers are patterned by known photolithography and wet etching (the first mask process), thereby obtaining a gate electrode 102 shown in FIG. 5(a). At this time, scanning lines 160 and storage capacitor electrodes which are not shown are simultaneously formed. Thereafter, the remaining resist is peeled off and the substrate is cleaned.

[0118] Step (B1):

[0119] Next, on the substrate 101, a gate insulating layer 103 is formed so as to cover the gate electrode 102. The gate insulating layer 103 has a two layer configuration including a silicon nitride (SiNx) film layered to the thickness of 100 to 500 nm by CVD and a silicon oxide (SiO₂) film layered thereof to the thickness of 10 to 200 nm by CVD. The gate insulating layer 103 may be a single layer film of silicon nitride or silicon oxide.

[0120] Step (C1):

[0121] Next, an oxide semiconductor is layered on the gate insulating layer 103. The oxide semiconductor is formed by layering In—Ga—Zn—O semiconductor (IGZO), for example, to the thickness of 10 to 100 nm by sputtering. Thereafter, the layered oxide semiconductor is patterned by photolithography and wet etching (the second mask process), thereby obtaining an oxide semiconductor layer 104 functioning as a channel layer of a thin film transistor 10 as shown in FIG. 5(b). Thereafter, the remaining resist is peeled off and the substrate is cleaned. As the oxide semiconductor, instead of IGZO, another kind of oxide semiconductor film may be utilized.

[0122] Step (D1):

[0123] Next, as shown in FIG. 5(c), on the gate insulating layer 103, an SOG material is applied by spin coating so as to cover the oxide semiconductor layer 104, and the applied SOG material is sintered. Instead of the spin coating, an applying technique which utilizes a slit coater may be adopted. Preferably, the sintering temperature is 200 to 450 degrees. In this embodiment, the sintering is performed at 350 degrees. As the result of the sintering, the dehydration polymerization reaction of the SOG material is performed, and a protecting layer 107 of silicon oxide having the thickness of 100 to 3000 nm is formed (the formation of the protecting layer 107 by SOG). As the SOG material, for example, a material containing silanol, alkoxysilane, or an organic siloxane resin as a base material is used.

[0124] At this time, H₂O or —OH radical generated by the sintering of the SOG material is diffused into the oxide semiconductor from the upper surface and the side face of the oxide semiconductor layer, so that the defect of the oxide semiconductor is uniformly restored. In addition, the SOG material is applied by spin coating, so that the damage to the oxide semiconductor layer which may be caused by the use of sputtering, photolithography, etching, or other techniques can be prevented.

[0125] By the provision of the protecting layer 107, the damage to the oxide semiconductor layer from the sputtering, the photolithography, the etching, the heat treatment, and the like in the succeeding steps for forming layers can be prevented or reduced. In addition, when the SOG material is sintered, the oxide semiconductor layer can be annealed, so that it is unnecessary to add another annealing step. Thus, the production efficiency can be improved.

[0126] Step (E1):

[0127] Next, as shown in FIG. 5(d), by using photolithography and dry etching, contact holes 131 and 132 are formed in the protecting layer 107 (the third mask process).

[0128] Step (F1):

[0129] Next, by sputtering, Ti and Cu are layered in this order on the protecting layer 107 so as to bury the contact holes 131 and 132. The thickness of the Ti layer is 20 to 150 nm, and the thickness of the Cu layer is 100 to 600 nm. Next, by photolithography and wet etching, the two layers of Cu/Ti are patterned, thereby obtaining a source electrode 105 and a drain electrode 106 as shown in FIG. 5(e) (the fourth mask process). Thereafter, the remaining resist is removed, and the substrate is cleaned.

[0130] The source electrode 105 is constituted by a lower layer source electrode 105b of Ti, and an upper layer source electrode 105a of Cu. The drain electrode 106 is constituted by a lower layer source electrode 106b of Ti, and an upper layer source electrode 106a of Cu. Herein, the upper layer source electrode 105a is formed so that the width thereof is narrower than that of the lower layer source electrode 105b, and the upper layer drain electrode 106a is formed so that the width thereof is narrower than that of the lower layer drain electrode 106b. The source electrode 105 and the drain electrode 106 are electrically connected to the oxide semiconductor layer at the bottoms of the contact holes 131 and 132, respectively. In this step, a signal line 152 is formed simultaneously.

[0131] Step (G1):

[0132] Next, as shown in FIG. 5(f), an interlayer insulating layer 108 of a photosensitive material is formed on the protecting layer 107 so as to cover the source electrode 105 and the drain electrode 106 by SOG technique utilizing a spin coater or a slit coater, for example. Thereafter, by photolithography and dry etching, the interlayer insulating layer 108 is patterned (the fifth mask process), thereby forming a contact hole (a third contact hole) 133 in the interlayer insulating layer 108.

[0133] Step (H1):

[0134] Next, on the interlayer insulating layer 108, a transparent conductive material is deposited by sputtering, for example. At this time, the transparent conductive material is deposited so as to be in contact with the drain electrode 106 in the contact hole 133. As the transparent conductive material, for example, ITO (the thickness: 50 to 200 nm) is used. Then, the transparent electrode layer is patterned by known photolithography (the sixth mask process). As a result, as shown in FIG. 5(g), a transparent electrode (a pixel electrode in a pixel 50) 109 is formed.

[0135] Next, with reference to FIG. 6, the production method of a counter substrate of the liquid crystal display device 1000 will be described.

[0136] In FIG. 6, (a) to (c) are sectional views schematically showing the production process steps of a counter substrate 200 in the liquid crystal display device 1000 shown in FIG. 2.

[0137] First, on a substrate 201 such as a glass substrate, as shown in FIG. 6(a), a black matrix (BM) 202 and color filters 203 are formed by photolithography. The black matrix 202 is formed in a lattice-like manner so as to cover the boundaries of the pixels 50. In a region surrounded by the black matrix 202, a color filter 203 of red, green, or blue is formed so as to cover each pixel.

[0138] Next, as shown in FIG. 6(b), a counter electrode 204 is formed on the black matrix 202 and the color filters 203. The counter electrode is obtained by depositing ITO to the thickness of 50 to 200 nm by sputtering, and then patterning it by photolithography and wet etching.

[0139] Next, a photosensitive material is applied on the counter electrode 204, and the material is patterned by photolithography, thereby forming a photo spacer 205 having a shape as shown in FIG. 6(c) above the black matrix 202.

[0140] Thereafter, the TFT substrate 100 and the counter substrate 200 which are formed as described above are stuck together with a liquid crystal layer interposed therebetween, thereby completing the liquid crystal display device 1000. Before the sticking, on respective surfaces on the sides of the electrodes of the TFT substrate 100 and the counter substrate 200 (i.e. on the sides of the liquid crystal layer), alignment films are formed. The alignment film is obtained by forming a film of polyimide by printing. Before the sticking, a sealing member is formed by printing in a fringe region of one of the substrates, and a liquid crystal material is dropped onto the area enclosed by the sealing member. In general, a plurality of TFT substrates 100 and a plurality of counter substrates 200 corresponding to a plurality of liquid crystal display devices 1000 are formed as a large TFT substrate and a large counter substrate. After the large substrates are stuck together, they are diced and separated, thereby obtaining a plurality of liquid crystal display device 100.

[0141] According to this embodiment, the protecting layer 107 is formed on the oxide semiconductor layer 104 by a spin-on-glass technique, so that the damage to the oxide semiconductor layer from the sputtering, the etching, the annealing, and other treatments during the formation of upper layers can be prevented or reduced. In addition, according to this embodiment, when the protecting layer 107 is formed, H₂O or —OH radical are diffused from the SOG material to the oxide semiconductor layer. Thus, the defect of the oxide semiconductor can be restored. Moreover, according to this embodiment, the oxide semiconductor can be annealed by the sintering of the protecting layer 107, so that the production process steps can be simplified.

[0142] Next, other embodiments (Embodiments 2 to 13) according to the present invention will be described. Through these embodiments, the effects which are fundamentally obtained from the above-described embodiment can be obtained.

[0143] Next, with reference to FIG. 7 and FIG. 8, a semiconductor device 100b in Embodiment 2 of the present invention will be described.

[0144] FIG. 7 is a sectional view schematically showing the configuration of the semiconductor device 100b. The fundamental configuration of the semiconductor device 100b except for the configuration which will be described below is the same as that of the semiconductor device 100 in Embodiment 1. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0145] The semiconductor device 100b includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a source electrode 105, a drain electrode 106, a protecting layer (a second protecting layer) 110, an interlayer insulating layer 109 and a transparent electrode 109, formed on a substrate 101. Unlike the semiconductor device 100 shown in FIG. 1, on the oxide semiconductor layer 104, the protecting layer 110 is provided so as to cover the source electrode 105 and the drain electrode 106, and an interlayer insulating layer 108 is formed on the protecting layer 110. A contact hole 133 is formed so as to reach the drain electrode 106 through the interlayer insulating layer 108 and the protecting layer 110.

[0146] Next, with reference to FIG. 8, the production method of the semiconductor device 100b will be described.

[0147] In FIG. 8, (a) to (g) are schematic sectional views showing the production process steps of the semiconductor device 100b.

[0148] First, as shown in (a) to (e) in FIG. 8, the same steps as the steps (A1) to (F1) described above with reference to FIG. 5 are performed, so that the gate electrode 102, the gate insulating layer 103, the oxide semiconductor layer 104, the protecting layer 107, the source electrode 105, and the drain electrode 106 are formed on the substrate 101.

[0149] Next, so as to cover the source electrode 105 and the drain electrode 106, on the protecting layer 107, an oxide layer is layered by CVD, thereby forming a protecting layer (a second protecting layer) 110. The thickness of the protecting layer 110 is 50 to 300 nm. As the material for the protecting layer 110, silicon dioxide (SiO₂) is used. Instead of the silicon dioxide, silicon nitride (SiN_x) may be used. Alternatively, a layered structure of a silicon dioxide layer and a silicon nitride layer can be applied to the protecting layer 110.

[0150] Next, an interlayer insulating layer 108 is formed on the protecting layer 110. Thereafter, the interlayer insulating layer 108 and the protecting layer 110 are patterned by photolithography and dry etching (the fifth mask process), thereby forming the contact hole 133 in the interlayer insulating layer 108 and the protecting layer 110, as shown in FIG. 8(f).

[0151] Thereafter, by the same method as in the above-described step (H1), a transparent electrode 109 is formed as shown in FIG. 8(g). The transparent electrode 109 is electrically connected to the drain electrode 106 via the contact hole 133.

[0152] Next, with reference to FIG. 9 and FIG. 10, a semiconductor device 100c in Embodiment 3 of the present invention will be described.

[0153] FIG. 9 is a sectional view schematically showing the configuration of the semiconductor device 100c. The fundamental configuration of the semiconductor device 100c except for the configuration which will be described below is the same as that of the semiconductor device 100 in Embodiment 1. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0154] The semiconductor device 100c includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a source electrode 105, a drain electrode 106, a transparent electrode (a second transparent electrode) 111, an interlayer insulating layer 108, and a transparent electrode 109, formed on a substrate 101. Unlike the semiconductor device 100 shown in FIG. 1, the source electrode 105 and the drain electrode 106 are formed in the positions slightly away from the contact holes 131 and 132, respectively, so as not to cover the contact holes 131 and 132.

[0155] On the contact holes 131 and 132, and on the protecting layer 107 around them, two transparent electrodes 111 which are separated from each other are formed. One of the transparent electrodes 111 buries the contact hole 131, and extends onto a part of the source electrode 105. With such a configuration, the source electrode 105 and the oxide semiconductor layer 104 are electrically connected via the transparent electrode 111. The other transparent electrode 111 buries the contact hole 132, and extends onto a part of the drain electrode 106. With such a configuration, the drain electrode 106 and the oxide semiconductor layer 104 are electrically connected via the transparent electrode 111.

[0156] Next, with reference to FIG. 10, the production method of the semiconductor device 100c will be described.

[0157] In FIG. 10, (a) to (g) are schematic sectional view showing the production process steps of the semiconductor device 100c.

[0158] First, as shown in (a) to (d) of FIG. 10, the same steps as the steps (A1) to (E1) which are described above with reference to FIG. 5 are performed, so that the gate electrode 102, the gate insulating layer 103, the oxide semiconductor layer 104, the protecting layer 107, and the contact holes 131 and 132 are formed on the substrate 101.

[0159] Next, similarly to the step (F1), by sputtering, on the protecting layer 107, Ti and Cu are layered in this order, and they are patterned by photolithography and wet etching, thereby obtaining the source electrode 105 and the drain electrode 106 (the fourth mask process). It is understood that, as shown in FIG. 10(e), the source electrode 105 and the drain electrode 106 are formed not in the positions which cover the contact holes 131 and 132, but in the positions away from the contact holes.

[0160] Next, by sputtering, ITO is deposited to the thickness of 50 to 200 nm. Thereafter, the ITO is patterned by photolithography and wet etching, so as to be left only in the positions in the vicinities of the contact holes 131 and 132 (the fifth mask process), thereby obtaining two transparent electrodes 111 which are separated from each other.

[0161] Thereafter, the same step as the step (G1) is performed, thereby forming the interlayer insulating layer 108 having the contact hole 133, as shown in FIG. 10(f) (the sixth mask process).

[0162] Next, the same step as the step (H1) is performed (the seventh mask process), thereby forming the transparent electrode 109 as shown in FIG. 10(g).

[0163] Next, with reference to FIG. 11 and FIG. 12, a semiconductor device 100d in Embodiment 4 of the present invention will be described.

[0164] FIG. 11 is a sectional view schematically showing the configuration of the semiconductor device 100d. The fundamental configuration of the semiconductor device 100d except for the configuration which will be described below is the same as that of the semiconductor device 100c in Embodiment 3. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0165] The semiconductor device 100d includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a source electrode 105, a drain electrode 106, a transparent electrode 111, a protecting layer (a second protecting layer) 110, an interlayer insulating layer 108, and a transparent electrode 109, formed on a substrate 101. Unlike the semiconductor device 100c in Embodiment 3, on the oxide semiconductor layer 104, so as to cover the source electrode 105, the drain electrode 106, and the transparent electrode 111, the protecting layer 110 is provided, and the interlayer insulating layer 108 is formed on the protecting layer 110. A contact hole 133 is formed so as to reach the drain electrode 106 through the interlayer insulting layer 108 and the protecting layer 110.

[0166] Next, with reference to FIG. 12, the production method of the semiconductor device 100d will be described.

[0167] In FIG. 12, (a) to (g) are schematic sectional views showing the production process steps of the semiconductor device 100d.

[0168] First, as shown in (a) to (e) in FIG. 12, the same steps as the steps (a) to (e) in FIG. 10 are performed, so that on the substrate 101, the gate electrode 102, the gate insulating layer 103, the oxide semiconductor layer 104, the protecting layer 107, the source electrode 105, the drain electrode 106, and the transparent electrode 111 are formed.

[0169] Next, so as to cover the source electrode 105, the drain electrode 106, and the transparent electrode 111, an oxide layer is layered by CVD on the protecting layer 107, thereby forming the protecting layer (a second protecting layer) 110.

[0170] Next, the interlayer insulating layer 108 is formed on the protecting layer 110. Thereafter, the interlayer insulating layer 108 and the protecting layer 110 are patterned by photolithography and dry etching (the sixth mask process), thereby forming the contact hole 133 in the interlayer insulating layer 108 and the protecting layer 110, as shown in FIG. 12(f).

[0171] Thereafter, by the same method as in the above-described step (H1), the transparent electrode 109 is formed as shown in FIG. 12(g). The transparent electrode 109 is electrically connected to the drain electrode 106 via the contact hole 133.

[0172] Next, with reference to FIG. 13 and FIG. 14, a semiconductor device 100e in Embodiment 5 of the present invention will be described.

[0173] FIG. 13 is a sectional view schematically showing the configuration of the semiconductor device 100e. The fundamental configuration of the semiconductor device 100e except for the configuration which will be described below is the same as that of the semiconductor device 100 in Embodiment 1. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0174] The semiconductor device 100e includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a source electrode 105, a drain electrode 106, and a transparent electrode 109, formed on a substrate 101. Unlike the semiconductor device 100 shown in FIG. 1, the interlayer insulating layer 108 is not formed, and the transparent electrode 109 is formed so as to be directly in contact with the drain electrode 106 and the protecting layer 107.

[0175] Next, with reference to FIG. 14, the production method of the semiconductor device 100e will be described.

[0176] In FIG. 14, (a) to (f) are schematic sectional views showing the production process steps of the semiconductor device 100e.

[0177] As shown in (a) to (e) in FIG. 14, the same steps as the steps (A1) to (F1) described above with reference to FIG. are performed, so that the gate electrode 102, the gate insulating layer 103, the oxide semiconductor layer 104, the protecting layer 107, contact holes 131 and 132, the source electrode 105, and the drain electrode 106 are formed on the substrate 101.

[0178] Next, without forming the interlayer insulating layer 108, the same step as the step (H1) is performed (the fifth mask process), thereby forming the transparent electrode 109 which is directly in contact with the drain electrode 106 on the protecting layer 107.

[0179] Next, with reference to FIG. 15 and FIG. 16, a semiconductor device 100f in Embodiment 6 of the present invention will be described.

[0180] FIG. 15 is a sectional view schematically showing the configuration of the semiconductor device 100f. The fundamental configuration of the semiconductor device 100f except for the configuration which will be described below is the same as that of the semiconductor device 100c in Embodiment 3. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0181] The semiconductor device 100f includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a source electrode 105, a drain electrode 106, and a transparent electrode 109, formed on a substrate 101. Unlike the semiconductor device 100c in Embodiment 3, the interlayer insulating layer 108 is not formed, and the transparent electrode 109 is formed so as to be directly in contact with the drain electrode 106 and the protecting layer 107. A transparent electrode 111 is formed via the same process and from the same material as those for the transparent electrode 109.

[0182] Next, with reference to FIG. 16, the production method of the semiconductor device 100f will be described.

[0183] In FIG. 16, (a) to (e) are schematic sectional views showing the production process steps of the semiconductor device 100f.

[0184] As shown in (a) to (d) in FIG. 16, the same steps as those shown in (a) to (d) in FIG. 10 are performed, so that the gate electrode 102, the gate insulating layer 103, the oxide semiconductor layer 104, the protecting layer 107, and the contact holes 131 and 132 are formed on the substrate 101.

[0185] Next, without forming the interlayer insulating layer 108, the same step as that in FIG. 10(e) is performed (the fifth and sixth mask processes), thereby forming the source electrode 105, the drain electrode 106, and the transparent electrode 111, as shown in FIG. 16(e). In this step, simultaneously with the transparent electrode 111, the transparent electrode 109 is formed so as to be directly in contact with the drain electrode 106.

[0186] Next, with reference to FIG. 17 and FIG. 18, a semiconductor device 100g in Embodiment 7 of the present invention will be described.

[0187] The semiconductor device 100g is a semiconductor device obtained as a TFT substrate of the liquid crystal display device 1000. The semiconductor device 100g includes a TFT portion 60 including a TFT 10, a Cs portion 70 including a pixel electrode 109 and a storage capacitor, and a terminal portion 30.

[0188] FIG. 17 is a sectional view schematically showing the configurations of the TFT portion 60, the Cs portion 70, and the terminal portion 30 in the semiconductor device 100g. The fundamental configuration of the semiconductor device 100g except for the configuration which will be described below is the same as that of the semiconductor device 100 in Embodiment 1. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0189] The TFT portion 60 in the semiconductor device 100g includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a source electrode 105, a drain electrode 106, a protecting layer 110, an interlayer insulating layer 108, and a transparent electrode 109, formed on a substrate 101.

[0190] In the protecting layer 107, contact holes 131 and 132 are formed. In the interlayer insulating layer 108 and the protecting layer 110 on the contact hole 131 and part of the source electrode 105, a contact hole 135 is formed. In the interlayer insulating layer 108 and the protecting layer 110 on the contact hole 132 and part of the drain electrode 106, another contact hole 136 is formed. The transparent electrode 109 is formed so as to cover the upper surface of the interlayer insulating layer 108, the side faces of the contact holes 135 and 136, part of the source electrode 105, and part of the drain electrode 106, and to bury the contact holes 131 and 132. By means of a part of the transparent electrode 109, via the contact hole 131, the source electrode 105 and the oxide semiconductor layer 104 in the TFT portion 60 are electrically connected. By means of another part of the transparent electrode 109, via the contact hole 132, the drain electrode 106 and the oxide semiconductor layer 104 are electrically connected.

[0191] The Cs portion 70 in the semiconductor device 100g includes a storage capacitor electrode (a Cs electrode) 102b, the gate insulating layer 103, an oxide semiconductor layer 104b, the protecting layer 107, the protecting layer 110, the interlayer insulating layer 108, and the transparent electrode (the pixel electrode) 109, formed on the substrate 101. The gate insulating layer 103 is formed on the substrate 101 so as to cover the storage capacitor electrode 102b. The oxide semiconductor layer 104b is formed above the storage capacitor electrode 102b with the gate insulating layer 103 sandwiched therebetween. The oxide semiconductor layer 104b functions as a storage capacitor counter electrode. A storage capacitor is constituted by the storage capacitor electrode 102b and the storage capacitor counter electrode, and the gate insulating layer 103 sandwiched between the electrodes.

[0192] In the protecting layer 107, a contact hole (a third contact hole) 134 is formed. In the interlayer insulating layer 108 and the protecting layer 110 on the contact hole 134, a contact hole 137 is formed. The transparent electrode 109 is formed so as to cover the upper surface of the interlayer insulating layer 108, the side face of the contact hole 137, and the bottom portion of the contact hole 134. In the bottom of the contact hole 134, the transparent electrode 109 is connected to the oxide semiconductor layer 104b.

[0193] The terminal portion 30 of the semiconductor device 100g includes a lower layer wiring 102c, the gate insulating layer 103, the protecting layer 107, an upper layer wiring 117, the protecting layer 110, the interlayer insulating layer 108, and the transparent electrode 109, formed on the substrate 101. The gate insulating layer 103 and the protecting layer 107 are formed only on part of the lower layer wiring 102c. The protecting layer 110 and the interlayer insulating layer 108 are formed only on part of the upper layer wiring 117. A portion of the lower layer wiring 102c which is not covered with the gate insulating layer 103 and the protecting layer 107, the side faces of the gate insulating layer 103 and the protecting layer 107, a portion of the upper layer wiring 117 which is not covered with the protecting layer 110 and the interlayer insulating layer 108, the side faces of the protecting layer 110 and the interlayer insulating layer 108, and the upper surface of the interlayer insulating layer 108 are covered with the transparent electrode 109. By the transparent electrode 109, the upper layer wiring 117 and the lower layer wiring 102c are electrically connected.

[0194] Next, with reference to FIG. 18, the production method of the semiconductor device 100g will be described.

[0195] In FIG. 18, (a) to (g) are schematic sectional views showing the production process steps of the semiconductor device 100g.

[0196] Step (A2):

[0197] First, on the substrate 101, a Ti layer and a Cu layer are layered in this order by sputtering or the like. The thickness of the Ti layer is 30 to 150 nm, and the thickness of the Cu layer is 200 to 500 nm. Next, these two layers are patterned by known photolithography and wet etching (the first mask process), thereby obtaining the gate electrode 102, the storage capacitor electrode 102b, and the lower layer wiring 102c, as shown in FIG. 18(a). At this time, a scanning line 160 and a storage capacitor line which are not shown are simultaneously formed. Thereafter, the remaining resist is peeled off and the substrate is cleaned.

[0198] Step (B2-1):

[0199] Next, on the substrate 101, the gate insulating layer 103 is formed so as to cover the gate electrode 102, the storage capacitor electrode 102b, and the lower layer wiring 102c. The gate insulating layer 103 has a two layer structure of a silicon nitride (SiNx) film layered by CVD to the thickness of 100 to 500 nm and a silicon oxide (SiO₂) film layered thereon by CVD to the thickness of 10 to 200 nm. Alternatively, the gate insulating layer 103 may be a single layer film of silicon nitride or silicon oxide.

[0200] Step (B2-2):

[0201] Next, an oxide semiconductor is layered on the gate insulating layer 103. The oxide semiconductor is formed by layering e.g. IGZO by sputtering to the thickness of 10 to 100 nm. Thereafter, the layered oxide semiconductor is patterned by photolithography and wet etching (the second mask process), thereby obtaining the oxide semiconductor layer 104 as the channel layer of the TFT and the storage capacitor electrode 102b of the Cs portion 70, as shown in FIG. 18(b). Thereafter, the remaining resist is peeled off and the substrate is cleaned. As the oxide semiconductor, instead of IGZO, another kind of oxide semiconductor film may be used.

[0202] Step (B2-3):

[0203] Next, as shown in FIG. 18(c), on the gate insulating layer 103, an SOG material is applied by spin coating so as to cover the oxide semiconductor layer 104 and the storage capacitor electrode 102b, and the applied SOG material is sintered. The sintering temperature is 200 to 450 degrees. In this embodiment, the sintering is performed at 350 degrees. As the result of the sintering, dehydration polymerization reaction of the SOG material is caused, thereby forming the protecting layer 107 of silicon oxide having the thickness of 100 to 3000 nm (the formation of the protecting layer 107 by SOG technique).

[0204] Step (C2):

[0205] Next, by sputtering, on the protecting layer 107, Ti and Cu are layered in this order. The thickness of the Ti layer is 20 to 150 nm, and the thickness of the Cu layer is 100 to 600 nm. Next, the two layers of Cu/Ti are patterned by photolithography and wet etching, thereby obtaining the source electrode 105, the drain electrode 106, and the upper layer wiring 117 of the terminal portion 30, as shown in FIG. 18(d) (the third mask process). Thereafter, the remaining resist is removed, and the substrate is cleaned.

[0206] In each of the source electrode 105, the drain electrode 106, and the upper layer wiring, the width of the Cu layer as the upper layer is formed so as to be narrower than that of the Ti layer as the lower layer. In this process step, a signal line 152 shown in FIG. 4 is simultaneously formed.

[0207] Step (D2-1):

[0208] Next, so as to cover the source electrode 105, the drain electrode 106, and the upper layer wiring 117, on the protecting layer 107, an oxide layer is layered by CVD, thereby forming the protecting layer (the second protecting layer) 110. The thickness of the protecting layer 110 is 50 to 300 nm.

[0209] Next, on the protecting layer 110, the interlayer insulating layer 108 of a photosensitive material is formed. Thereafter, the interlayer insulating layer 108 is patterned by photolithography and dry etching (the fourth mask process), thereby forming contact holes 135 to 137 in the interlayer insulating layer 108 as shown in FIG. 18(e). At this time, in the terminal portion 30, the interlayer insulating layer 108 on the lower layer wiring 102c, and on part of the upper layer wiring 117 is removed.

[0210] Step (D2-2):

[0211] Next, as shown in FIG. 18(f), by using the interlayer insulating layer 108 as a mask, dry etching is performed, thereby forming the contact holes 131, 132, and 134 in the protecting layers 110 and 107 at the bottoms of the contact holes 135 to 137. At the bottoms of the contact holes 131 and 132, the oxide semiconductor layer 104 is exposed, and at the bottom of the contact hole 134, the oxide semiconductor layer 104b is exposed. At this time, in the terminal portion 30, the gate insulating layer 103, the protecting layer 107, and the protecting layer 110 on the lower layer wiring 102c, and the protecting layer 110 on part of the upper layer wiring 117 are also removed.

[0212] Step (E2):

[0213] Next, on the interlayer insulating layer 108, a transparent conductive material is deposited to the thickness of 50 to 200 nm by sputtering, for example. As the transparent conductive material, ITO is used, for example. At this time, the transparent conductive material is also deposited on the side faces of the contact holes 135 to 137, the side faces and the bottom faces of the contact holes 131, 132 and 134, and the exposed surface of the terminal portion 30. Then, by known photolithography, the transparent electrode layer is patterned (the fifth mask process). Accordingly, the transparent electrode 109 is formed as shown in FIG. 18(g).

[0214] By the transparent electrode 109 in the contact holes 131 and 135, the source electrode 105 and the oxide semiconductor layer 104 are electrically connected. By the transparent electrode 109 in the contact holes 132 and 136, the drain electrode 106 and the oxide semiconductor layer 104 are electrically connected. At the bottom of the contact hole 134, the transparent electrode 109 in the Cs portion 70 is electrically connected to the oxide semiconductor layer 104b. In the terminal portion 30, by the transparent electrode 109, the upper layer wiring 117 and the lower layer wiring 102c are electrically connected.

[0215] According to this embodiment, the effects by the protecting layer 107 described above in Embodiment 1 can be attained, and the TFT substrate for a display device including the TFT portion 60, the Cs portion 70, and the terminal portion 30 can be formed by five mask processes. Accordingly, the production efficiency of the display device can be improved, and the cost can be reduced. In the case where the TFT substrate includes a connecting portion for connecting the upper layer wiring 117 and the lower layer wiring 102c, the structure of the connecting portion and the production method thereof are the same as those of the terminal portion 30. The TFT substrate or the semiconductor device having such a connecting portion is also included in this embodiment and embodiments which are described below.

[0216] Next, with reference to FIG. 19 and FIG. 20, a semiconductor device 100h in Embodiment 8 of the present invention will be described.

[0217] FIG. 19 is a sectional view schematically showing the configuration of the semiconductor device 100h. The fundamental configuration of the semiconductor device 100h except for the configuration which will be described below is the same as that of the semiconductor device 100g in Embodiment 7. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0218] The TFT portion 60 of the semiconductor device 100h includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a source electrode 105, a drain electrode 106, a protecting layer 110, an interlayer insulating layer 108, and a transparent electrode 109, formed on a substrate 101. Unlike Embodiment 7, the gate insulating layer 103 is substantially formed only between the gate electrode 102 and the oxide semiconductor layer 104.

[0219] The Cs portion 70 includes a storage capacitor electrode 102b, the gate insulating layer 103, an oxide semiconductor layer 104b, the protecting layer 107, the protecting layer 110, the interlayer insulating layer 108, and the transparent electrode 109, formed on the substrate 101. The gate insulating layer 103 is substantially formed only between the storage capacitor electrode 102b and the oxide semiconductor layer 104b.

[0220] The terminal portion 30 includes a lower layer wiring 102c, the gate insulating layer 103, the protecting layer 107, an upper layer wiring 117, the protecting layer 110, the interlayer insulating layer 108, and the transparent electrode 109, formed on the substrate 101. The gate insulating layer 103 is substantially formed only on part of the lower layer wiring 102c.

[0221] Next, with reference to FIG. 20, the production method of the semiconductor device 100h will be described.

[0222] In FIG. 20, (a) to (h) are schematic sectional views showing the production process steps of the semiconductor device 100h.

[0223] First, by sputtering or the like, on the substrate 101, a Ti layer and a Cu layer are layered in this order, thereby obtaining a metal layer 122 of two layer configuration. The thickness of the Ti layer is 30 to 150 nm, and the thickness of the Cu layer is 200 to 500 nm. In addition, on the metal layer 122, the gate insulating layer 103 and the oxide semiconductor layer 104 are layered by the same method as that in Embodiment 7. Next, on the oxide semiconductor layer 104, e.g. a photosensitive resist is applied. The applied resist is selectively removed, thereby forming a resist 112 in the TFT portion 60 and the Cs portion 70, and a resist 113 in the terminal portion 30, as shown in FIG. 20(a). The resist 113 is formed so as to be thinner than the resist 112 by half-tone exposure or gray-tone exposure.

[0224] Next, by using the resists 112 and 113 as masks, wet etching is performed to the gate insulating layer 103 and the oxide semiconductor layer 104, thereby obtaining a layered structure shown in FIG. 20(b). Herein, in the TFT portion 60 and the Cs portion 70, on the metal layer 122, the gate insulating layer 103, the oxide semiconductor layer 104, and the resist 112 are left in an island-like shape. In the terminal portion 30, the gate insulating layer 103 and the oxide semiconductor layer 104 are left in an island-like shape.

[0225] Next, dry etching is performed so as to pattern the metal layer 112, and then the resist 112 is removed. As a result, as shown in FIG. 20(c), in the TFT portion 60, an island-like structure including the gate electrode 102, the gate insulating layer 103, and the oxide semiconductor layer 104 is formed. In the Cs portion 70, an island-like structure including the storage capacitor electrode 102b, the gate insulating layer 103, and the oxide semiconductor layer 104b is formed. In the terminal portion 30, an island-like structure including the lower layer wiring 102c and the gate insulating layer 103 is formed.

[0226] Next, as shown in (d) to (h) in FIG. 20, the same method as that shown in (c) to (h) of FIG. 18 in Embodiment 7 is performed, thereby completing the semiconductor device 100h. Herein, similarly to Embodiment 7, by the transparent electrode 109 in the contact holes 131 and 135, the source electrode 105 and the oxide semiconductor layer 104 are electrically connected. By the transparent electrode 109 in the contact holes 132 and 136, the drain electrode 106 and the oxide semiconductor layer 104 are electrically connected. In addition, at the bottom of the contact hole 134, the transparent electrode 109 in the Cs portion 70 is electrically connected to the oxide semiconductor layer 104b. In the terminal portion 30, by the transparent electrode 109, the upper layer wiring 117 and the lower layer wiring 102c are electrically connected.

[0227] According to this embodiment, the effects by the protecting layer 107 described above in Embodiment 1 can be attained, and the TFT substrate for a display device including the TFT portion 60, the Cs portion 70, and the terminal portion 30 can be formed by four mask processes. Accordingly, the production efficiency of the display device can be improved, and the cost can be reduced.

[0228] Next, with reference to FIG. 21 and FIG. 22, a semiconductor device 100i in Embodiment 9 of the present invention will be described.

[0229] FIG. 21 is a sectional view schematically showing the configuration of the semiconductor device 100i. The fundamental configuration of the semiconductor device 100i except for the configuration that the protecting layer 110 and the interlayer insulating layer 108 are not formed is the same as that of the semiconductor device 100g in Embodiment 7. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0230] A TFT portion 60 of the semiconductor device 100i includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a source electrode 105, a drain electrode 106, and a transparent electrode 109, formed on a substrate 101. A Cs portion 70 includes a storage capacitor electrode 102b, the gate insulating layer 103, an oxide semiconductor layer 104b, the protecting layer 107, and the transparent electrode 109, formed on the substrate 101. A terminal portion 30 includes a lower layer wiring 102c, the gate insulating layer 103, the protecting layer 107, an upper layer wiring 117, and the transparent electrode 109, formed on the substrate 101.

[0231] Next, with reference to FIG. 22, the production method of the semiconductor device 100i will be described.

[0232] In FIG. 22, (a) to (f) are schematic sectional views showing the production process steps of the semiconductor device 100i.

[0233] First, as shown in (a) to (d) of FIG. 22, by the same method as that shown in (a) to (d) of FIG. 18, the gate electrode 102, the storage capacitor electrode 102b, the lower layer wiring 102c, the gate insulating layer 103, the oxide semiconductor layers 104 and 104b, the protecting layer 107, the source electrode 105, the drain electrode 106, the upper layer wiring 117, and the transparent electrode 109 are formed on the substrate 101.

[0234] Next, as shown in FIG. 22(e), by photolithography and etching, contact holes 131, 132, and 134 are formed in the protecting layer 107. At the bottoms of the contact holes 131 and 132, the oxide semiconductor layer 104 is exposed. At the bottom of the contact hole 134, the oxide semiconductor layer 104b is exposed. At this time, in the terminal portion 30, the gate insulating layer 103 and the protecting layer 107 on part of the lower layer wiring 102c are removed.

[0235] Next, on the protecting layer 107, so as to cover the source electrode 105, the drain electrode 106, and the upper layer wiring 117, e.g. ITO is deposited by sputtering to the thickness of 50 to 200 nm. At this time, the ITO is also deposited on the side faces and the bottom faces of the contact holes 131, 132, and 134, and the exposed face of the terminal portion 30. Next, by photolithography, the transparent electrode layer is patterned. Accordingly, the transparent electrode 109 is formed as shown in FIG. 22(f).

[0236] By the transparent electrode 109 in the contact hole 131, the source electrode 105 and the oxide semiconductor layer 104 are electrically connected. By the transparent electrode 109 in the contact hole 132, the drain electrode 106 and the oxide semiconductor layer 104 are electrically connected. At the bottom of the contact hole 134, the transparent electrode 109 of the Cs portion 70 is electrically connected to the oxide semiconductor layer 104b. In the terminal portion 30, by the transparent electrode 109, the upper layer wiring 117 and the lower layer wiring 102c are electrically connected.

[0237] According to this embodiment, the effects by the protecting layer 107 which are described above in Embodiment 1 can be attained, and the TFT substrate for a display device including the TFT portion 60, the Cs portion 70, and the terminal portion 30 can be formed by five mask processes. Accordingly, the production efficiency of the display device is improved, and the cost can be reduced.

[0238] Next, with reference to FIG. 23 and FIG. 24, a semiconductor device 100j in Embodiment 10 of the present invention will be described.

[0239] FIG. 23 is a sectional view schematically showing the configuration of the semiconductor device 100j. The fundamental configuration of the semiconductor device 100j except for the configuration that the protecting layer 110 and the interlayer insulating layer 108 are not formed is the same as that of the semiconductor device 100h in Embodiment 8. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0240] A TFT portion 60 of the semiconductor device 100j includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a source electrode 105, a drain electrode 106, and a transparent electrode 109, formed on a substrate 101. A Cs portion 70 includes a storage capacitor electrode 102b, the gate insulating layer 103, an oxide semiconductor layer 104b, the protecting layer 107, and the transparent electrode 109, formed on the substrate 101. A terminal portion 30 includes a lower layer wiring 102c, the gate insulating layer 103, the protecting layer 107, an upper layer wiring 117, and the transparent electrode 109, formed on the substrate 101.

[0241] Next, with reference to FIG. 24, the production method of the semiconductor device 100j will be described.

[0242] In FIG. 24, (a) to (g) are schematic sectional views showing the production process steps of the semiconductor device 100j.

[0243] First, as shown in (a) to (e) of FIG. 24, by the same method as that shown in (a) to (e) of FIG. 20, the gate electrode 102, the storage capacitor electrode 102b, the lower layer wiring 102c, the gate insulating layer 103, the oxide semiconductor layers 104 and 104b, the protecting layer 107, the source electrode 105, the drain electrode 106, the upper layer wiring 117, and the transparent electrode 109 are formed on the substrate 101.

[0244] Next, as shown in FIG. 24(f), by photolithography and etching, contact holes 131, 132, and 134 are formed in the protecting layer 107. At the bottoms of the contact holes 131 and 132, the oxide semiconductor layer 104 is exposed. At the bottom of the contact hole 134, the oxide semiconductor layer 104b is exposed. At this time, in the terminal portion 30, the gate insulating layer 103 and the protecting layer 107 on part of the lower layer wiring 102c are removed.

[0245] Next, on the protecting layer 107, so as to cover the source electrode 105, the drain electrode 106, and the upper layer wiring 117, ITO is deposited by sputtering, for example, to the thickness of 50 to 200 nm. At this time, the ITO is also deposited on the side faces and the bottom faces of the contact holes 131, 132, and 134, and the exposed face of the terminal portion 30. Next, by photolithography, the transparent electrode layer is patterned. Accordingly, the transparent electrode 109 is formed as shown in FIG. 24(g).

[0246] By the transparent electrode 109 in the contact hole 131, the source electrode 105 and the oxide semiconductor layer 104 are electrically connected. By the transparent electrode 109 in the contact hole 132, the drain electrode 106 and the oxide semiconductor layer 104 are electrically connected. At the bottom of the contact hole 134, the transparent electrode 109 of the Cs portion 70 is electrically connected to the oxide semiconductor layer 104b. In the terminal portion 30, by the transparent electrode 109, the upper layer wiring 117 and the lower layer wiring 102c are electrically connected.

[0247] According to this embodiment, the effects by the protecting layer 107 which are described above in Embodiment 1 can be attained, and the TFT substrate for a display device including the TFT portion 60, the Cs portion 70, and the terminal portion 30 can be formed by four mask processes. Accordingly, the production efficiency of the display device is improved, and the cost can be reduced.

[0248] Next, with reference to FIG. 25 to FIG. 27, a semiconductor device 100k in Embodiment 11 of the present invention will be described.

[0249] FIG. 25 is a sectional view schematically showing the configuration of the semiconductor device 100k. The fundamental configuration of the semiconductor device 100k except for the configuration which will be described below is the same as that of the semiconductor device 100h in Embodiment 8. The components having the same functions are designated by the same reference numerals, and the detailed descriptions thereof are omitted.

[0250] A TFT portion 60 of the semiconductor device 100k includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107, a protecting layer 110, a transparent electrode 109, a source electrode 105, a drain electrode 106, and a resist 112, formed on a substrate 101. Unlike Embodiment 8, the source electrode 105 and the drain electrode 106 are formed on the transparent electrode 109 and covered with the resist 112. The transparent electrode 109 buries contact holes 131 and 132 formed in the protecting layers 107 and 110.

[0251] A Cs portion 70 includes a storage capacitor electrode 102b, the gate insulating layer 103, an oxide semiconductor layer 104b, the protecting layer 107, the protecting layer 110, and the transparent electrode 109, formed on the substrate 101. Under the transparent electrode 109, the interlayer insulating layer 108 is not formed.

[0252] A terminal portion 30 includes a lower layer wiring 102c, the gate insulating layer 103, the protecting layer 107, the protecting layer 110, an upper layer wiring 117, the transparent electrode 109, and the resist 112, formed on the substrate 101. Part of the transparent electrode 109 is formed on the protecting layer 110, and another part is formed on the protecting layer 107. The upper layer wiring 117 is formed on the transparent electrode 109 and covered with the resist 112.

[0253] Next, with reference to FIG. 26 and FIG. 27, the production method of the semiconductor device 100k will be described.

[0254] In FIG. 26, (a) to (g), and in FIG. 27, (h) to (m) are schematic sectional views showing the production process steps of the semiconductor device 100k.

[0255] First, as shown in (a) to (c) of FIG. 26, by the same method as that shown in (a) to (c) of FIG. 20, on the substrate 101 of the TFT portion 60, a layered structure of the gate electrode 102, the gate insulating layer 103, and the oxide semiconductor layer 104 is formed. On the substrate 101 of the Cs portion 70, a layered structure of the storage capacitor electrode 102b, the gate insulating layer 103, and the oxide semiconductor layer 104b is formed. On the substrate 101 of the terminal portion 30, a layered structure of the lower layer wiring 102c and the gate insulating layer 103 is formed (the first mask process).

[0256] Next, so as to cover the above-described three layered structures, on the substrate 101, an SOG material is applied by spin coating, and the applied SOG material is sintered. The sintering temperature is 200 to 450 degrees. In this embodiment, the sintering is performed at 350 degrees. As the result of the sintering, dehydration polymerization reaction of the SOG material is caused, thereby forming the protecting layer 107 of silicon oxide having the thickness of 100 to 3000 nm (the formation of the protecting layer 107 by SOG technique).

[0257] Next, on the protecting layer 107, an oxide layer is layered by CVD, thereby forming the protecting layer 110. The thickness of the protecting layer 110 is 50 to 300 nm. Accordingly, the layered structure shown in FIG. 26(d) is obtained.

[0258] next, a photosensitive resist applied on the protecting layer 110 is selectively removed, thereby forming the resist 112 having contact holes 135, 136, and 137, as shown in FIG. 26(e). The resist located above the terminal portion 30 is removed.

[0259] Next, by using the resist 112 as a mask, the protecting layers 110 and 107 are patterned by dry etching (the second mask process), thereby forming the contact holes 131, 132, and 134, as shown in FIG. 26(f). At this time, in the terminal portion 30, the protecting layers 110 and 107 on the lower layer wiring 102c and on part of the upper layer wiring 117 are also removed.

[0260] Thereafter, as shown in FIG. 26(g), the remaining resist 112 is removed. Herein, at the bottoms of the contact holes 131 and 132, the oxide semiconductor layer 104 is exposed. At the bottom of the contact hole 134, the oxide semiconductor layer 104b is exposed. In the terminal portion 30, the lower layer wiring 102c is exposed.

[0261] Next, by sputtering, as shown in FIG. 27(h), the transparent electrode 109 of e.g. ITO is deposited to the thickness of 50 to 200 nm. In addition, a metal layer 124 of e.g. Cu is deposited to the thickness of 100 to 600 nm. Herein the contact holes 131, 132, and 134 are buried by the transparent electrode 109, or by the transparent electrode 109 and the metal layer 124.

[0262] Next, as shown in FIG. 27(i), on the metal layer 124, the resists 112 and 113 are selectively formed. The resist 113 is formed so as to be thinner than the resist 112 by half-tone exposure or gray-tone exposure (the third mask process).

[0263] Then, by wet etching, as shown in FIG. 27(j), part of the metal layer 124 and part the transparent electrode 109 are removed.

[0264] Next, the resist 112 is partially withdrawn by ashing, thereby removing the resist 112 on the metal layer 124 to be removed, as shown in FIG. 27(k).

[0265] Next, by wet etching, the exposed metal layer 124 is removed. Accordingly, as shown in FIG. 27(1), the source electrode 105, the drain electrode 106, and the upper layer wiring 117 are formed. Herein, the transparent electrode 109 remains without being removed.

[0266] Next, the remaining resist 112 is not peeled off, but exposed to a solvent atmosphere, heated, and caused to reflow. Accordingly, as shown in FIG. 27(m), the source electrode 105, the drain electrode 106, and the upper layer wiring 117 are not exposed but covered with the resist 112.

[0267] It is understood that the process step is not necessarily performed, but in the case where leakage current from the source electrode 105, the drain electrode 106, and the upper layer wiring 117 to the counter electrode is not seriously considered, the resist 112 is not caused to reflow, but may be removed.

[0268] In this way, the semiconductor device 100k is completed. Herein, by the transparent electrode 109 in the contact hole 131, the source electrode 105 and the oxide semiconductor layer 104 are electrically connected. By the transparent electrode 109 in the contact hole 132, the drain electrode 106 and the oxide semiconductor layer 104 are electrically connected. At the bottom of the contact hole 134, the transparent electrode 109 of the Cs portion 70 is electrically connected to the oxide semiconductor layer 104b. In the terminal portion 30, by the transparent electrode 109, the upper layer wiring 117 and the lower layer wiring 102c are electrically connected.

[0269] According to this embodiment, the effects by the protecting layer 107 described above in Embodiment 1 can be attained, and the TFT substrate for a display device including the TFT portion 60, the Cs portion 70, and the terminal portion 30 can be formed by three mask processes. Thus, the production efficiency of the display device can be further improved, and the cost can be further reduced.

[0270] Next, a semiconductor device in Embodiment 12 of the present invention will be described.

[0271] The semiconductor device in Embodiment 12 has the configuration of the semiconductor device 100k in Embodiment 11 shown in FIG. 25 excluding the protecting layer 110. The other configurations are the same as those of the semiconductor device 100k, so that the descriptions thereof by way of the figures are omitted. The production method of the semiconductor device in Embodiment 12 is the same as that of the semiconductor device 100k excluding the production process step of forming the protecting layer 110 shown in FIG. 26(d), so that the description by way of figures is omitted.

[0272] According to this embodiment, the effects of the protecting layer 107 described above in Embodiment 1 can be attained, and the TFT substrate for a display device including the TFT portion 60, the Cs portion 70, and the terminal portion 30 can be formed by three mask processes. Accordingly, the production efficiency of the display device can be further improved, and the cost can be further reduced.

[0273] Next, an organic EL display device 1002 in Embodiment 13 of the present invention will be described.

[0274] FIG. 28 is a sectional view schematically showing the configuration of the organic EL display device 1002 (sometimes referred to simply as “a display device 1002”). As shown in the figure, the display device 1002 includes a TFT substrate 140, a hole transporting layer 144 disposed on the TFT substrate 140, a light emitting layer 146 disposed on the hole transporting layer 144, and a counter electrode 148 disposed on the light emitting layer 146. The hole transporting layer 144 and the light emitting layer 146 constitute an organic EL layer. The organic EL layer is segmented by insulating projections 147. The segmented organic EL layer corresponds to an organic EL layer for one pixel.

[0275] The TFT substrate 140 may have fundamentally the same configuration as those of the semiconductor devices in Embodiments 1 to 12. The TFT substrate 140 has a TFT 10 formed on a substrate 101. The TFT substrate 140 may include a Cs portion 70, a terminal portion 30, and the like. In one example of the TFT substrate 140 shown in FIG. 28, the TFT 10 includes a gate electrode 102, a gate insulating layer 103, an oxide semiconductor layer 104, a protecting layer 107 (herein not shown in the figure), a source electrode 105, and a drain electrode 106, formed on the substrate 101. In addition, the TFT substrate 140 includes an interlayer insulating layer 108 layered so as to cover the TFT 10, and a pixel electrode 109 formed on the interlayer insulating layer 108. The pixel electrode 109 is connected to the drain electrode 106 in a contact hole formed in the interlayer insulating layer 108.

[0276] A planar construction of the TFT substrate 140 is fundamentally the same as that shown in FIG. 3 and FIG. 4, so that the same components are designated by the same reference numerals and the descriptions thereof are omitted. It is understood that as the TFT substrate 140, a configuration in which a storage capacitor 162 is not provided may be used.

[0277] When a voltage is applied across the organic EL layer by the pixel electrode 109 and the counter electrode 148, holes generated from the pixel electrode 109 are transported to the light emitting layer 146 via the hole transporting layer 144. At the same time, electrons generated from the counter electrode 148 are moved to the light emitting layer 146. Such holes and electrons are combined again, so that light emission occurs in the light emitting layer 146. The light emitted from the light emitting layer 146 is controlled for respective pixels by the TFT substrate 140 as the active matrix substrate, thereby performing desired display.

[0278] As the materials of the hole transporting layer 144, the light emitting layer 146, and the counter electrode 148, and their layered structure, the known materials and structure may be used. In order to increase the hole injection efficiency, a hole injection layer may be provided between the hole transporting layer 144 and the light emitting layer 146. In order to increase the light emission efficiency, and to attain high electron injection efficiency to the organic EL layer, for the counter electrode 148, a material with high transmittance and small work function may preferably be used.

[0279] The organic EL display device 1002 in this embodiment utilizes the semiconductor device described in any one of Embodiments 1 to 12 as its TFT substrate, so that the effects described in Embodiments 1 to 12 can be attained. According to this embodiment, the organic EL display device 1002 which can perform display with high performance can be provided with good production efficiency.

[0280] In the production methods of the semiconductor device and the display device according to the present invention, the protecting layer is formed on the oxide semiconductor layer by the spin-on-glass technique, so that the damage to the oxide semiconductor layer when an upper layer such as the source and drain electrodes is formed can be prevented or reduced. Thus, it is possible to provide a semiconductor device and a display device having high quality and high reliability.

[0281] In addition, in the semiconductor device and the display device according to the present invention, the protecting layer of spin-on-glass material is disposed so as to be in contact with the oxide semiconductor layer, so that the damage to the oxide semiconductor layer occurring in the production can be prevented. Accordingly, a semiconductor device and a display device having high quality and high reliability can be obtained.

[0282] In addition, according to the production method of the present invention, H₂O or —OH radical is diffused from the spin-on-glass material to the oxide semiconductor layer, so that the defect of the oxide semiconductor can be restored. Accordingly, it is possible to provide a semiconductor device and a display device having high quality and high reliability.

[0283] According to the present invention, it is possible to provide a display device including a semiconductor TFT of high quality, a storage capacitor, and a terminal portion with good production efficiency.

[0284] The present invention is suitably utilized for a semiconductor device having a thin film transistor, and a display device such as a liquid crystal display device or an organic EL display device provided with a thin film transistor in a TFT substrate.

• • [0285] 10 TFT (Thin Film Transistor)
  • [0286] 25 electric element
  • [0287] 30 terminal portion
  • [0288] 50 pixel
  • [0289] 60 TFT portion
  • [0290] 70 Cs portion (storage capacitor portion)
  • [0291] 100, 100b to 100k, 140 TFT substrate (semiconductor device)
  • [0292] 101 substrate
  • [0293] 102 gate electrode
  • [0294] 102b storage capacitor electrode
  • [0295] 102c lower layer wiring
  • [0296] 103 insulating layer (gate insulating layer)
  • [0297] 104, 104b oxide semiconductor layer
  • [0298] 105 source electrode
  • [0299] 105a upper layer source electrode
  • [0300] 105b lower layer source electrode
  • [0301] 106 drain electrode
  • [0302] 106a upper layer drain electrode
  • [0303] 106b lower layer drain electrode
  • [0304] 107 protecting layer (SOG layer)
  • [0305] 108 interlayer insulating layer
  • [0306] 109 transparent electrode (pixel electrode)
  • [0307] 110 protecting layer (second protecting layer)
  • [0308] 112, 113 resist
  • [0309] 114 oxide layer (conductive layer)
  • [0310] 117 upper layer wiring
  • [0311] 122 metal layer
  • [0312] 122a upper metal layer
  • [0313] 122b lower metal layer
  • [0314] 124 metal layer
  • [0315] 131 to 137 contact holes
  • [0316] 152 signal line
  • [0317] 160 scanning line
  • [0318] 162 storage capacitor line
  • [0319] 200 counter substrate
  • [0320] 201 substrate (glass substrate)
  • [0321] 202 black matrix
  • [0322] 203 color filter
  • [0323] 204 counter electrode
  • [0324] 205 photo spacer
  • [0325] 210, 220 polarizing plate
  • [0326] 230 backlight unit
  • [0327] 240 scanning line driving circuit
  • [0328] 250 signal line driving circuit
  • [0329] 260 control circuit
  • [0330] 1000 liquid crystal display device
  • [0331] 1002 organic EL display device