Optoelectronic Semiconductor Chip

[0001] This patent application is a national phase filing under section 371 of PCT/EP2012/054601, filed Mar. 15, 2012, which claims the priority of German patent application 10 2011 016 302.6, filed Apr. 7, 2011, each of which is incorporated herein by reference in its entirety.

[0002] The invention relates to an optoelectronic semiconductor chip.

[0003] International Patent Publication No. WO 2009/106069 A1 discloses an optoelectronic semiconductor chip in which a first and a second electrical contact layer are arranged between the semiconductor layer sequence and the carrier substrate. In this case, the first and second electrical contact layers are insulated from one another by means of an electrically insulating layer. In the case of a semiconductor chip of this type, a mirror layer can adjoin the semiconductor layer sequence at a side facing the carrier substrate in order to deflect the radiation emitted by the active zone in the direction of the carrier substrate to a radiation coupling-out surface situated opposite the carrier substrate.

[0004] In the case of a semiconductor chip of this type, there may be the risk of moisture being transported from the edges of the semiconductor chip through the electrically insulating layer right into the region of the minor layer, which would result in a degradation of the minor layer and hence a reduction of the radiation efficiency.

[0005] Embodiments of the invention specify an improved optoelectronic semiconductor chip in which the minor layer is effectively protected against ingress of moisture and at the same time an efficient electrical contact-connection of the semiconductor chip is obtained with comparatively low production outlay.

[0006] In accordance with one configuration, the optoelectronic semiconductor chip comprises a semiconductor layer sequence having a first semiconductor region of a first conduction type, a second semiconductor region of a second conduction type, and an active zone arranged between the first semiconductor region and the second semiconductor region.

[0007] Furthermore, the optoelectronic semiconductor chip comprises a carrier substrate, wherein the semiconductor layer sequence has a first main surface facing the carrier substrate, and an opposite second main surface. A first electrical contact layer and a second electrical contact layer are arranged at least regionally between the carrier substrate and the first main surface of the semiconductor layer sequence, wherein the second electrical contact layer is led through a perforation in the first semiconductor region and the active zone into the second semiconductor region. The first electrical contact layer and the second electrical contact layer are insulated from one another by an electrically insulating layer.

[0008] A mirror layer is arranged between the semiconductor layer sequence and the carrier substrate. The minor layer can adjoin the semiconductor layer sequence in particular at the first main surface. The minor layer advantageously reflects radiation emitted by the active zone in the direction of the carrier substrate to the second main surface of the semiconductor layer sequence, said second main surface serving as a radiation coupling-out surface. The minor layer adjoins in particular partial regions of the first electrical contact layer and partial regions of the electrically insulating layer, wherein the interface of the mirror layer that faces the carrier substrate is covered by the first electrical contact layer.

[0009] The optoelectronic semiconductor chip comprises a transparent encapsulation layer, which covers the side surfaces of the semiconductor layer sequence and the side surfaces of the minor layer. Furthermore, the transparent encapsulation layer also covers side surfaces of the electrically insulating layer which face the side surfaces of the semiconductor chip.

[0010] By virtue of the fact that the transparent encapsulation layer covers the side surfaces of the semiconductor layer sequence and of the minor layer, the mirror layer is protected against ingress of moisture. This protective effect of the transparent encapsulation layer is further improved by the transparent encapsulation layer also covering the side surfaces of the electrically insulating layer which face the side surfaces of the semiconductor chip. In this way, in particular, ingress of moisture into the electrically insulating layer is prevented and the risk of moisture propagating through the electrically insulating layer as far as the minor layer is thus reduced.

[0011] Preferably, the electrically insulating layer at no point adjoins a surrounding medium of the optoelectronic semiconductor chip. This advantageously ensures that moisture cannot penetrate from outside into the electrically insulating layer and propagate in the layer system of the semiconductor chip.

[0012] The transparent encapsulation layer preferably contains an aluminum oxide such as Al₂O₃, for example, or a silicon oxide such as SiO₂, for example, or consists thereof.

[0013] Particularly preferably, the transparent encapsulation layer comprises an ALD layer, i.e., a layer produced by means of atomic layer deposition (ALD). In a further advantageous configuration, the transparent encapsulation layer comprises a spin-on glass. An ALD layer or a spin-on glass is advantageously distinguished by a low defect density and affords good protection against ingress of moisture. Applying the transparent encapsulation layer by means of ALD or as spin-on glass furthermore has the advantage that the transparent encapsulation layer can be introduced into small interspaces.

[0014] In particular, it is advantageous if the mirror layer has a smaller lateral extent than the semiconductor layer sequence, and partial regions of the transparent encapsulation layer extend below the semiconductor layer sequence. Particularly, good protection of the mirror layer against oxidation and/or ingress of moisture is obtained in this way. Preferably, the semiconductor layer sequence has an overhang over the minor layer at all side surfaces. The side surfaces of the mirror layer are advantageously adjoined by an interspace formed between the semiconductor layer sequence and a layer sequence applied to the carrier substrate. The interspace is advantageously filled by the transparent encapsulation layer.

[0015] In one preferred configuration, the second main surface of the semiconductor chip, which serves in particular as a radiation exit surface, is covered by the transparent encapsulation layer.

[0016] The semiconductor layer sequence is preferably covered by the transparent encapsulation layer completely, i.e., including the side surfaces.

[0017] In one advantageous configuration, the semiconductor layer sequence has a mesa structure, wherein the first electrical contact layer and the second electrical contact layer extend right into regions of the semiconductor chip that are arranged laterally alongside the mesa structure.

[0018] The transparent encapsulation layer preferably has alongside the mesa structure an opening in which a connection contact for the first electrical contact layer is arranged. In this case, the connection contact is advantageously arranged alongside the semiconductor layer sequence, such that, in particular, a second main surface of the semiconductor layer sequence functioning as radiation exit surface is free of connection contacts. This has the advantage that the radiation exit surface is not shaded by the connection contact and, consequently the efficiency of the semiconductor chip increases. The connection contact is preferably arranged outside the center of the semiconductor chip, in particular, in a corner of the semiconductor chip.

[0019] The first electrical contact layer advantageously serves firstly for making electrical contact with the semiconductor chip and secondly for protecting the mirror layer against corrosion. In particular, at least one part of the interface of the minor layer facing the carrier substrate is covered by the first electrical contact layer.

[0020] The first electrical contact layer preferably contains gold, titanium, chromium, platinum, titanium nitride, titanium tungsten nitride or nickel or consists thereof. These materials are advantageously distinguished firstly by a good electrical conductivity and secondly by their suitability as a diffusion barrier. The first electrical contact layer can comprise a plurality of sublayers which preferably each contain at least one of the materials.

[0021] The minor layer preferably contains silver, aluminum or a silver or aluminum alloy or consists thereof. Silver and aluminum are distinguished by high reflection in the visible spectral range. Furthermore, these materials have a good electrical conductivity and form a metal-semiconductor contact having a low contact resistance. This is advantageous since the minor layer advantageously adjoins the semiconductor layer sequence and in this way electrically conductively connects the first semiconductor region to the first electrical contact layer.

[0022] The second electrical contact layer, like the mirror layer, preferably contains silver, aluminum or a silver or aluminum alloy, or consists thereof. High reflection in the visible spectral range and a good electrical conductivity are advantageous for the second electrical contact layer, since the second electrical contact layer also adjoins the semiconductor layer sequence at least regionally and in this way makes electrical contact with the second semiconductor region.

[0023] The electrically insulating layer, which insulates the first electrical contact layer and the second electrical contact layer from one another, preferably contains a silicon oxide, a silicon nitride, a silicon oxynitride or an aluminum oxide.

[0024] In one preferred embodiment, the first semiconductor region is a p-type semiconductor region and the second semiconductor region is an n-type semiconductor region. In this configuration, therefore, the minor layer adjoins the p-type semiconductor region, and the second electrical contact layer is led through the perforation into the n-type semiconductor region. The p-type semiconductor region faces the carrier substrate and the n-type semiconductor region faces the second main surface of the semiconductor layer sequence serving as radiation exit surface.

[0025] In a further advantageous configuration, the semiconductor layer sequence of the optoelectronic semiconductor chip has no growth substrate. In this case, the semiconductor chip is a so-called thin-film light-emitting diode chip, in which the growth substrate used for the epitaxial growth of the semiconductor layer sequence was detached after the connection of the semiconductor layer sequence to the carrier substrate.

[0026] The semiconductor chip is preferably connected to the carrier substrate by means of a solder layer. In particular, the semiconductor chip can be connected to the carrier substrate at the side situated opposite the original growth substrate.

[0030] Identical or identically acting component parts are provided with the same reference signs in each case in the figures. The illustrated component parts and the size relationships of the component parts among one another should not be regarded as true to scale.

[0031] The optoelectronic semiconductor chip 1 illustrated schematically in cross section in FIG. 1 contains a semiconductor layer sequence 2 having a first semiconductor region 3 of a first conduction type and a second semiconductor region 5 of a second conduction type. Preferably, the first semiconductor region 3 is a p-type semiconductor region and the second semiconductor region 5 is an n-type semiconductor region. An active zone 4 is arranged between the first semiconductor region 3 and the second semiconductor region 5.

[0032] The active zone 4 of the optoelectronic semiconductor chip 1 can be, in particular, an active zone suitable for emitting radiation. In this case, the optoelectronic semiconductor chip 1 is a luminescence diode, in particular an LED. Alternatively, it would also be conceivable for the active zone 4 to be a radiation-detecting layer, wherein the optoelectronic semiconductor chip 1 in this case is a detector component. The active zone 4 can be embodied, for example, as a pn junction, as a double heterostructure, as a single quantum well structure or multiple quantum well structure.

[0033] The semiconductor layer sequence 2 of the semiconductor chip 1 is preferably based on a III-V compound semiconductor material, in particular on an arsenide, nitride or phosphide compound semiconductor material. By way of example, the semiconductor layer sequence 2 can contain In_xAl_yGa_1-x-yN, In_xAl_yGa_1-x-yP or In_xAl_yGa_1-x-yAs, in each case where 0≦1 x≦1, 0≦y≦1 and x+y≦1. In this case, the III-V compound semiconductor material need not necessarily have a mathematically exact composition according to one of the above formulae. Rather, it can comprise one or more dopants and additional constituents which substantially do not change the physical properties of the material. For the sake of simplicity, however, the above formulae only include the essential constituents of the crystal lattice, even if these can be replaced in part by small amounts of further substances.

[0034] The semiconductor chip 1 is connected to a carrier substrate 10 by a connecting layer 21, which can be, in particular, a solder layer composed of a metal or a metal alloy.

[0035] For electrical contact-connection, the semiconductor chip 1 has a first electrical contact layer 7 and a second electrical contact layer 8. The first electrical contact layer 7 is electrically conductively connected to the first semiconductor region 3, and the second electrical contact layer 8 is electrically conductively connected to the second semiconductor region 5.

[0036] Both the first electrical contact layer 7 and the second electrical contact layer 8 are arranged at least regionally between a first main surface 11 of the semiconductor layer sequence 2 facing the carrier substrate 10 and the carrier substrate 10. The first electrical contact layer 7 and the second electrical contact layer 8 are electrically insulated from one another by means of an electrically insulating layer 9. The electrically insulating layer 9 preferably contains a silicon oxide, a silicon nitride, a silicon oxynitride, an aluminum oxide or consists thereof. Alternatively, the electrically insulating layer 9 can also contain other oxides or nitrides.

[0037] The second main surface 12 of the semiconductor layer sequence 2 situated opposite the carrier substrate 10 serves as a radiation coupling-out surface of the optoelectronic semiconductor chip 1 and is advantageously free of electrical contact layers. In order to improve the coupling-out of radiation, the second main surface 12 can be provided with a coupling-out structure 23 or a roughening.

[0038] In order to improve the radiation efficiency of the optoelectronic semiconductor chip 1, a mirror layer 6 is arranged between the semiconductor layer sequence 2 and the carrier substrate 10. The mirror layer 6 is disposed downstream of the first semiconductor region 3 at the side facing the carrier substrate 10 and can adjoin, in particular, the first main surface 11 of the semiconductor layer sequence 2. It is also possible for an intermediate layer, for example, a thin adhesion promoter layer, to be arranged between the first semiconductor region 3 and the minor layer 6. The minor layer 6 contains, in particular, silver, aluminum or a metal alloy comprising silver or aluminum. These materials are distinguished by a high reflectivity in the visible spectral range and a good electrical conductivity. The mirror layer 6 firstly has the function of reflecting radiation emitted by the active zone 4 in the direction of the carrier substrate 10 to the radiation coupling-out surface 12. Furthermore, the mirror layer 6 also serves for making electrical contact with the first semiconductor region 3. In particular, the mirror layer 6 adjoins the first electrical contact layer 7 at the side facing the carrier substrate 10 and is therefore electrically conductively connected to the first electrical contact layer 7.

[0039] The first electrical contact layer 7 preferably covers the interface of the mirror layer facing the carrier substrate 10. The first electrical contact layer 7 preferably contains gold, titanium, chromium, platinum, titanium nitride, titanium tungsten nitride or nickel or consists thereof. These materials are distinguished by the fact that they are electrically conductive and additionally chemically inert. In this way, the mirror layer 6 is advantageously protected against corrosion in the regions in which it is covered by the first electrical contact layer 7.

[0040] The second electrical contact layer 8 is electrically conductively connected to the second semiconductor region 5 through a perforation 18 running through the first semiconductor region 3 and the active zone 4. In the region of the perforation 18, the active zone 4, the first semiconductor region 3, the mirror layer 6 and the first electrical contact layer 7 are insulated from the second electrical contact layer 8 by means of the electrically insulating layer 9 or passivated regions 20 of the semiconductor layer sequence 2.

[0041] The second electrical contact layer 8, in the regions in which it directly adjoins the semiconductor layer sequence 2, advantageously functions not only as a contact layer, but also as a reflective layer that reflects radiation toward the second main surface 12 of the semiconductor layer sequence 2 serving as radiation exit surface. The second electrical contact layer 8 therefore advantageously comprises a metal or a metal alloy having a high reflectivity, in particular silver, aluminum or an alloy comprising silver or aluminum.

[0042] In the semiconductor chip 1, the side surfaces 26 of the semiconductor layer sequence 2 and the side surfaces 16 of the mirror layer 6 are covered by an electrically insulating transparent encapsulation layer 13. The encapsulation layer 13 firstly has the function of protecting the mirror layer 6 against corrosion. In particular, the mirror layer 6 is protected against oxidation or ingress of moisture by the encapsulation layer 13. The side surfaces 16 of the mirror layer 6 are preferably surrounded by the encapsulation layer 13 on all sides, such that the mirror layer 6 at no point directly adjoins the surrounding medium.

[0043] The transparent encapsulation layer 13 furthermore also covers the side surfaces 17 of the first contact layer 7 and the side surfaces 19 of the electrically insulating layer 9 facing the side surfaces 15 of the semiconductor chip 1. In particular, ingress of moisture into the electrically insulating layer 9 is prevented in this way. Particularly preferably, the electrically insulating layer 9 at no point adjoins a surrounding medium of the semiconductor chip 1.

[0044] The transparent encapsulation layer 13 is preferably an aluminum oxide layer, in particular an Al₂O₃ layer, or a silicon oxide layer, in particular a SiO₂ layer. The transparent encapsulation layer is advantageously deposited by means of atomic layer deposition or as spin-on glass. Such a silicon oxide layer deposited by means of ALD or as spin-on glass advantageously has a high resistance to corrosion and ingress of moisture.

[0045] In one particularly preferred configuration, the minor layer 6 has a smaller lateral extent than the semiconductor layer sequence 2, such that partial regions of the transparent encapsulation layer 13 extend below the semiconductor layer sequence 2. In this configuration, the side surfaces 16 of the minor layer 6 are advantageously spaced apart from the side surfaces 26 of the semiconductor layer sequence 2. The distance between the side surfaces 26 of the semiconductor layer sequence 2 and the side surfaces 16 of the minor layer 6 is preferably between 0.5 μm and 5 μm, particularly preferably approximately 3 μm. The mirror layer 6 is protected particularly effectively in this way. Particularly, by producing the transparent encapsulation layer 13 by means of atomic layer deposition, it is possible to deposit the transparent encapsulation layer 13 in such a way that it fills the interspace between the semiconductor layer sequence 2 and the mirror layer 6.

[0046] The transparent encapsulation layer 13 advantageously also covers the side surfaces 26 and the second main surface 12 of the semiconductor layer sequence 2 serving as radiation exit surface. The semiconductor layer sequence 2 is therefore advantageously completely covered by the transparent encapsulation layer 13. Advantageously, fine cracks possibly present at the surfaces of the semiconductor layer sequence 2 can be closed by the transparent encapsulation layer 13. The complete encapsulation of the semiconductor layer sequence 2 is therefore advantageous for the long-term stability of the semiconductor chip.

[0047] The semiconductor layer sequence 2 has a mesa structure, wherein the first electrical contact layer 7 and the second electrical contact layer 8 extend laterally alongside the mesa structure. The transparent encapsulation layer 13 has alongside the mesa structure an opening in which a connection contact 14 is arranged, said connection contact being connected to the first electrical contact layer. The connection contact 14 can be, in particular, a bonding pad provided for the connection of a bonding wire.

[0048] The connection contact 14 is preferably arranged outside the center of the semiconductor chip 1, in particular in the region of a corner of the semiconductor chip 1.

[0049] When the semiconductor chip 1 is viewed from above, advantageously essentially only the second electrical contact layer 8 is visible through the transparent encapsulation layer 13 alongside the semiconductor layer sequence 2 structured as a mesa, said second electrical contact layer advantageously containing a highly reflective metal such as a Ag or Al, for example. Regions of the first electrical contact layer 7, which can contain a less reflective material such as platinum, for example, are visible only in a small region around the connection contact 14.

[0050] The second electrical contact layer 8 can be electrically connected externally, for example, via the rear side of the semiconductor chip 1, in particular via an electrically conductive carrier substrate 10 and the solder layer 21. A barrier layer 22 can be arranged between the solder layer 21 and the second electrical contact layer 8, said barrier layer preventing in particular a diffusion of constituents of the solder layer 21 into the second electrical contact layer 8, and vice versa.

[0051] One exemplary embodiment of a method for producing the optoelectronic semiconductor chip is described in the following FIGS. 2A to 2O. The above-described advantageous configurations of individual component parts of the optoelectronic semiconductor chip apply in the same way to the method described below, and vice versa.

[0052] In the intermediate step of the method as illustrated in FIG. 2A, the semiconductor layer sequence 2 comprising the first semiconductor region 3, the active zone 4 and the second semiconductor region 5 has been grown onto a growth substrate 24. The growth is preferably effected epitaxially, in particular by means of MOVPE. The semiconductor layer sequence 2 can contain nitride compound semiconductor materials, for example, and the growth substrate 24 can be a sapphire substrate. The first semiconductor region 3 is preferably a p-type semiconductor region, and the second semiconductor region 5 is preferably an n-type semiconductor region.

[0053] In the method step illustrated in FIG. 2B, an oxide layer 25, for example, a silicon oxide layer, was applied to the second semiconductor region 5. The oxide layer 25 serves for protecting the first semiconductor region 3 during subsequent photolithography and etching processes.

[0054] In the intermediate step illustrated in FIG. 2C, the oxide layer was patterned photolithographically, for example. Furthermore, the mirror layer 6 and the first electrical contact layer 7 were applied and lifted off from the regions still covered with the oxide layer 25 by means of lift-off technology. Advantageously, therefore, the minor layer 6 and the first electrical contact layer are patterned in the same method step. The minor layer 6 contains, in particular, silver, aluminum or a metal alloy comprising silver or aluminum. The first electrical contact layer 7 covers the surface of the mirror layer 6 and in this way firstly produces the electrical connection to the first semiconductor region 3, and secondly serves as encapsulation for the material of the minor layer 6. The first electrical contact layer 7 can contain, in particular, gold, titanium, chromium, platinum, titanium nitride, titanium tungsten nitride or nickel or consist thereof. It is also possible for the first electrical contact layer 7 to comprise a plurality of sublayers. By way of example, the first electrical contact layer 7 can comprise a Ti/Pt/Au/Cr layer sequence.

[0055] In the method step illustrated in FIG. 2D, the oxide layer applied previously has been removed again, for example, by etching by means of buffered hydrofluoric acid (BOE—Buffered Oxide Etch).

[0056] In the intermediate step illustrated in FIG. 2E, the p-doped semiconductor region 3 has been passivated in regions 20 arranged between and outside the regions of the semiconductor layer sequence 2 that are covered by the minor layer 6 and the first electrical contact layer 7. The passivated regions 20 can be produced for example by bombardment of the p-doped semiconductor material 3 with argon ions. Preferably, the passivated regions 20 extend right into the active layer 4, such that the pn junction is severed by the electrically insulating passivated regions 20. Instead of passivating the regions 20, it is alternatively also possible to remove them by sputtering.

[0057] In the intermediate step illustrated in FIG. 2F, an electrically insulating layer 9 was applied to the structure produced in this way. The electrically insulating layer 9 can be, in particular, a silicon oxide layer or a silicon nitride layer.

[0058] In the intermediate step illustrated in FIG. 2G, a perforation 18 was produced in the electrically insulating layer 9 and the semiconductor layer sequence 2. The perforation 18 is produced by means of photolithography and reactive ion etching, for example. The perforation 18 extends through the passivated regions 20 of the first semiconductor region 3 and of the active layer 4 right into the second semiconductor region 5.

[0059] In the intermediate step illustrated in FIG. 2H, the entire layer structure produced previously was covered with the second electrical contact layer 8. The second electrical contact layer 8 preferably contains silver, aluminum or an alloy comprising silver or aluminum. The second electrical contact layer 8 serves for making electrical contact with the second semiconductor region 5, which can be an n-type semiconductor region, in particular. The second electrical contact layer 8 extends through the perforation 18 right into the second semiconductor region 5.

[0060] In the intermediate step illustrated in FIG. 2I, the semiconductor chip has been connected to a carrier substrate 10 at a side facing away from the growth substrate 24 by means of a solder layer 21. Before the connection of the carrier substrate 10 to the semiconductor chip, a barrier layer 22 is preferably applied to the second electrical contact layer 8 in order to protect the second electrical contact layer 8, preferably containing silver or aluminum, against a diffusion of constituents of the solder layer 21. The solder layer 21 can contain AuSn, in particular. The barrier layer 22 can contain TiWN, for example.

[0061] The carrier substrate 10 is preferably an electrically conductive substrate, for example, a doped semiconductor wafer composed of silicon or germanium. Alternatively, the carrier substrate 10 can also be formed by an electrodeposited metal layer.

[0062] In the intermediate step illustrated in FIG. 2J, the growth substrate 24 has been detached from the semiconductor chip. The semiconductor chip is illustrated in a manner rotated by 180° in comparison with the previous figures, since now the carrier substrate 10 situated opposite the original growth substrate functions as the sole carrier of the semiconductor chip. The growth substrate, in particular a sapphire substrate, can be detached from the semiconductor layer sequence 2 by means of a laser lift-off process, for example.

[0063] In the intermediate step illustrated in FIG. 2K, the main surface 12 of the semiconductor layer sequence 2 from which the growth substrate 24 was detached was provided with a coupling-out structure 23, for example by etching using KOH. This is advantageous since the second main surface 12 of the semiconductor layer sequence 2 serves as the radiation coupling-out surface in the finished optoelectronic semiconductor chip.

[0064] In the intermediate step illustrated in FIG. 2L, the semiconductor layer sequence 2 was provided with a mesa structure. For this purpose, the semiconductor layer sequence 2 was completely removed in the edge regions of the semiconductor chip in order to produce a semiconductor layer sequence 2 having a desired form and size. The structuring is preferably effected photolithographically, wherein for example, H₃PO₄ can be used as etchant and SiO₂ can be used as mask. In particular, the semiconductor layer sequence 2 was removed in such a way that a part of the mirror layer 6 and of the electrically insulating layer 9 are exposed alongside the semiconductor layer sequence 2. The semiconductor layer sequence 2 provided with the mesa structure can have oblique side flanks 26. The first electrical contact layer 7 and the second electrical contact layer 8 extend right into regions of the semiconductor chip that are situated laterally alongside the mesa structure.

[0065] In the method step illustrated in FIG. 2M, a part of the minor layer 6 was removed using an etchant suitable for selectively etching the mirror layer 6. In this case, the semiconductor layer sequence 2 and the electrically insulating layer 9 function as etching mask. The semiconductor layer sequence is advantageously undercut during the etching process, with the result that an interspace forms between the semiconductor layer sequence 2 and the first electrical contact layer 7. The mirror layer 6 therefore has a smaller lateral extent than the adjoining semiconductor layer sequence 2. In particular, the side flanks 16 of the minor layer 6 are at a distance from the side flanks 26 of the semiconductor layer sequence 2. The distance is preferably between 0.5 μm and 5 μm.

[0066] In the intermediate step illustrated in FIG. 2N, the regions of the electrically insulating layer 9 not covered by the first electrical contact layer 7 were removed. This can be effected, for example, by etching by means of buffered hydrofluoric acid. What is achieved in this way, in particular, is that the electrically insulating layer 9 no longer extends as far as the side surfaces 15 of the semiconductor chip. The side surfaces 17 of the first electrical contact layer 7 that were previously covered by the electrically insulating layer 9 are exposed by the etching process. Furthermore, exposed side surfaces 19 of the electrically insulating layer 9 are produced below the first electrical contact layer 7. In this case, the first electrical contact layer 7 is preferably partly undercut, with the result that the side surfaces 19 of the electrically insulating layer 9 are laterally spaced apart from the side surfaces 17 of the first electrical contact layer 7.

[0067] In the intermediate step illustrated in FIG. 2O, an electrically insulating transparent encapsulation layer 13 has been applied to the layer structure produced in this way. The transparent encapsulation layer 13 preferably contains Al₂O₃ or SiO₂ or consists thereof. The transparent encapsulation layer 13 is preferably produced at least partly by means of atomic layer deposition (ALD). Alternatively, the transparent encapsulation layer 13 can be applied at least partly as spin-on glass. Particularly, pure and impermeable layers can advantageously be deposited with these methods for layer deposition. Furthermore, these methods have the advantage that layer deposition is also possible in comparatively small interspaces. In particular, the transparent encapsulation layer 13 is deposited in such a way that it completely fills the interspaces adjoining the side surfaces 16 of the mirror layer 6 and the side surfaces 19 of the electrically insulating layer 9.

[0068] It is possible that firstly a first sublayer of the transparent encapsulation layer 13 is applied by means of atomic layer deposition or as spin-on glass, in order to fill the cavities produced in the layer structure. The first sublayer produced in this way can subsequently be reinforced by a second sublayer, applied by means of CVD, for example. The transparent encapsulation layer 13 advantageously completely covers the semiconductor layer sequence 2, i.e., both the side surfaces 26 and the second main surface 12 serving as the radiation exit surface. It has been found that fine cracks possibly present at the surfaces of the semiconductor layer sequence 2 can be closed by the transparent encapsulation layer 13, thereby reducing the risk of corrosion or ingress of moisture.

[0069] In order to complete the optoelectronic semiconductor chip 1 illustrated in FIG. 1, subsequently alongside the semiconductor layer sequence 2 structured as a mesa an opening is produced in the transparent encapsulation layer 13, the first electrical contact layer 7 being exposed in said opening. The opening is produced, for example, by photolithography and reactive ion etching. A connection contact 14 is applied in said opening. The connection contact 14 can contain gold and/or platinum, for example. The connection contact 14 can be, in particular, a bonding pad provided for the connection of a bonding wire. The connection contact 14 is preferably arranged outside the center of the semiconductor chip 1, in particular in the region of a corner of the semiconductor chip 1. A further electrical connection for the semiconductor chip 1 can be provided at the rear side of the preferably electrically conductive carrier substrate 10, in order to electrically connect the second electrical contact layer 8 in this way.

[0070] The exemplary embodiment of an optoelectronic semiconductor chip 1 as illustrated in FIG. 1 was produced in this way. The production method is distinguished, in particular, by the fact that only four photolithography steps are necessary, such that the production outlay is comparatively low despite the complex encapsulation of the semiconductor chip.

[0071] The invention is not restricted by the description on the basis of the exemplary embodiments. Rather, the invention encompasses any novel feature and also any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.