Command Aware Partial Page Programming

[0001] Non-volatile memory systems, such as flash memory, have been widely adopted for use in consumer products. Flash memory may be found in different forms, for example in the form of a portable memory card that can be carried between host devices or as a solid state disk (SSD) embedded in a host device.

[0002] Flash memory can be organized in different ways, including segmenting the memory into blocks and pages, with the blocks being composed of multiple pages. For example, a single 4 MB memory block may be composed of multiple pages. The total number of pages and blocks may vary depending on the actual capacity of the device.

[0003] The basic programming unit of the flash memory is typically a page. For example, in flash memories using a binary cache (BC), the atomic unit of programming is the physical page. However, there are instances in which the flash memory may program in smaller portions of a page, such as by using partial page programming. For example, partial page programming programs may program the flash memory in granularity as small as an Error Correction coding (ECC) page. In particular, partial page programming uses the concept of a “write step”, which is the maximum programming step size as a multiple of ECC page. This allows for partial page programming to program an amount that is a multiple of the ECC page, but is less than an entire page.

[0004] A method and system for partial page programming is disclosed.

[0005] In one aspect, a storage device is provided. The storage device comprises: a memory and a controller in communication with the memory. The controller is configured to: determine an amount to write by partial page programming; dynamically set a write step based on the determined amount; and perform the partial page programming in the memory with the dynamically set write step.

[0006] There are different types of data that may be written using partial page programming, such as host data that is received from a host device, and binary cache index data. The controller may determine the amount to write by partial page programming by receiving the host data from the host device and determining an amount of the host data (such as by examining a host command from the host device that includes the host data). The controller may also determine the amount to write by partial page programming by determining whether the binary cache index data needs to be written to the memory.

[0007] The controller may select the write step from a plurality of predetermined write steps based on the amount to write by partial page programming. The predetermined write steps may be multiples of the Error Correction coding (ECC) page. The controller may select a single write step to program the entire amount to write by partial page programming. For example, the controller may select the predetermined write step that is closest to but not less than the amount to write by partial page programming. Or, the controller may select multiple write steps to program the amount to write by partial page programming (such as one write step to program the host data and another write step to program the binary cache index data).

[0008] In another aspect, a method for partial page programming in a memory of a storage device is disclosed. The method comprises: determining an amount to write by the partial page programming; dynamically setting a write step based on the determined amount; and performing the partial page programming in the memory with the dynamically set write step.

[0009] Embodiments of the present invention are defined by the claims, and nothing in this section should be taken as a limitation on those claims. Other features and advantages will become apparent upon review of the following drawings, detailed description and claims. Additionally, other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. The embodiments will now be described with reference to the attached drawings.

[0019] A flash memory system suitable for use in implementing aspects of the invention is shown in FIG. 1. A host system 10 stores data into, and retrieves data from, a storage device 12. The storage device 12 may be embedded in the host system 10 or may exist in the form of a card or other removable drive that is removably connected to the host system 10 through a mechanical and electrical connector. The host system 10 may be any of a number of data generating devices, such as a personal computer, a mobile telephone, a personal digital assistant (PDA), or the like. The host system 10 communicates with the storage device over a communication channel 14.

[0020] The storage device 12 contains a controller 16 and a memory 26. As shown in FIG. 1, the controller 16 includes a processor 18 and a controller memory 20. The processor 18 may comprise a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array, a logical digital circuit, or other now known or later developed logical processing capability. The controller memory 20 may include volatile and/or non-volatile memory and instructions 24.

[0021] The memory 26 may include non-volatile memory (such as flash memory). The flash memory may be composed of memory cells. The memory cells may be operated to store two levels of charge so that a single bit of data is stored in each cell. This is typically referred to as a binary or single level cell (SLC) memory. Alternatively or in addition, the memory cells may be operated to store more than two detectable levels of charge in each charge storage element or region, thereby to store more than one bit of data in each. This latter configuration is referred to as multi-level cell (MLC) memory. As illustrated in FIG. 1, memory 26 may include binary cache 28 (which may include SLC type of flash configuration) and main storage 30 (which may include MLC type of flash configuration).

[0022] The storage device 12 may include the functions for a memory management. In operation, the processor 18 may execute memory management instructions 23 (which may be resident in instructions 24) for operation of the partial page programming functions, such as detailed in FIG. 5. One example of memory management instructions 23 may comprise Media Management Layer (MML) firmware. The MML firmware may implement functionality, such as described in FIGS. 5-6, discussed in more detail below.

[0023] The memory 26 may comprise one or more integrated circuit chips, where each chip may contain an array of memory cells. Data are transferred into and out of the chip through respective data input/output circuits that are connected with a system bus. Circuitry on the chip may provide for both programming data into the memory cells and for reading data from the memory cells of their respective planes. Each memory chip may contain some controlling circuitry that executes commands from the controller 16 to perform such functions. For example, the controller 16, executing the memory management instructions 23, may generate commands for the chip to perform the functionality described in FIGS. 5-6.

[0024] One or more types of data may be cached in storage device 12. One type of data that may be cached in the storage device 12 is host data, which is data sent to and/or received from the host device 10. Another type of data that may be cached in the storage device 12 is control data. Other types of data for caching are contemplated.

[0025] Control data may include data related to managing and/or controlling access to data stored in memory 26. The binary cache 28 may store up-to-date fragments of the logical groups (LGs). The main storage may comprise the data storage for the LGs. Control data may be used to manage the entries in memory, such as entries in binary cache 28 and main storage 30, as shown in FIG. 2. For example, a binary cache index (BCI) may receive a Logical Block Address (LBA), and may map/point to the most up to date fragment(s) of the LG in binary cache 28. The GAT may receive the LBA address and map to the physical location of the LG in the main storage 30.

[0026] In flash memories employing a binary cache (such as binary cache 28), the atomic unit of programming in the binary cache is a physical page. The restriction of programming a full physical is overcome by partial page programming, as discussed above. Partial page programming enables programming of less than the physical page, such as a programming granularity as small as an Error Correction Coding (ECC) page.

[0027] Partial page programming uses the notion of a “write step”, which is the maximum programming step size as a multiple of a predetermined amount. In one embodiment, the predetermined amount is the ECC page so that the write step may be multiples of the ECC page. Typically, the write step is selected as a fixed size (and is not changeable during the operation of the storage device). A smaller fixed size for the write step has certain benefits and drawbacks, as does a larger fixed size for the write step. Depending on the usage and the fragment length, a smaller fixed size for the write step results in more programming steps for a single command. Conversely, a larger fixed size for the write step potentially results in more invalid data and frequent compactions. So, there is a trade-off between command latency, performance and endurance with a fixed write step size. This problem is magnified with larger physical page sizes. Since the media manager does not have knowledge of the physical page size, it operates purely on the write step.

[0028] FIGS. 3A-C illustrate prior art partial page programming with a fixed size for the write step. FIG. 3A is an example of a physical page size of 16 kB, with random 8 kB writes with 4 kB BCI (with every write is to a different BCI in the same zone). Thus, FIG. 3A illustrates 8 kB of host data (data sent by the host system 10 and received by the storage system 12 for writing in memory 26). The controller 16 of the storage system 12 may determine that the BCI be written to cache. The BCI may be written before the new fragment, hence the name ‘BCI pre-pad’. BCI pre-pad may reduce one fragment write to 4 KB program. Further, the data (fragment and BCI) may be held without programming (transfer and program, or program only) unless there is more to program. The storage device can wait to obtain a full page. In the case of the physical page being 16 KB in size, there will be one program per 2 fragments, if nothing else changes.

[0029] FIG. 3A further shows that the fixed size for the write step is 4K. Partial page programming with the 4K write step size requires 3 separate programming steps: 4K of host data; 4K of host data; and 4K of BCI.

[0030] Similar to FIG. 3A, FIG. 3B includes 8K of host data and 4K of BCI. However, FIG. 3B has a fixed size for the write step of 8K. This fixed write step size results in fewer programming steps (two versus three); however, one of the programming steps is pre-padded with 4K of data. The padded 4K of data is wasted space. Thus, the reduction in the number of programming steps is offset by the potential for the need to store wasted space.

[0031] FIG. 3C illustrates mixed mode command lengths, with 4 kB, 1 sector, and 4 kB, in that order. Similar to FIG. 3A, the fixed size for the write step is 4K. The writes illustrated in FIG. 3C will have: (4 kB Data+4 kB BCI)+(1-sector+4 kB BCI)+(4 kB+4 kB BCI). There are a total number of six programming steps, with 3.5 kB padded for the 1-sector case.

[0032] In one aspect of the invention, the selection of the size of the write step is variable. The selection may be based on at least one aspect of the storage device (such as being based on at least one dynamic aspect of the storage device). For example, the selection may be based on how much data to store using partial page programming (e.g., how much host data to store using partial page programming and/or how much BCI to store using partial page programming).

[0033] The media management layer (MML) firmware of the storage device 12 may identify how much data is to be stored using partial page programming. As discussed above, there are different types of data that may be stored using partial page programming, such as host data and BCI. The media management layer firmware may identify how much host data and/or BCI is to be stored. In particular, certain protocols, such as Small Computer System Interface (SCSI) and Serial Advanced Technology Attachment (SATA), provide the command length of the host data beforehand (such as in a field of the command). So that, the media management layer firmware may be aware of the amount of host data in the command for partial page programming. Given that the media management layer is command aware of the amount of host data for partial page programming, the media management layer may select the write step size based on the amount of host data. As another example, the media management layer firmware may identify how much BCI data is to be stored.

[0034] Given the ability to vary the write step size, the media management layer firmware may reduce or optimize the number of programming steps. In this way, the media management layer firmware may maintain knowledge of the physical page size in relation to how many write steps are required for the current command received from the host. With this knowledge, the media management layer firmware may reduce or optimize the number of programming steps required to complete the current command. Reducing the number of programming steps for any given command may improve performance of the memory system. Moreover, varying the write step size may reduce the padding necessary when partial page programming, as discussed in more detail below. Reduced padding may leave less invalid data inside a block, so that compactions will be more efficient and will improve endurance.

[0035] FIGS. 4A-C illustrate partial page programming with a variable size for the write step. Similar to FIGS. 3A-B, 8K of host data and 4K of BCI are written. The MML firmware may select one of multiple write step sizes. The selection by the MML firmware may attempt to reduce or optimize the number of programming steps and/or reduce the amount of wasted space written. The selection may be based on the amount of data to write to the binary cache 28 (including the amount of host data and/or BCI) and the location of where the data is written (including whether the data is being written in the same zone or different zones). FIGS. 4A-B illustrate two different selections of the write step. In FIG. 4A, there are two selections for the write step: a first selection of 8K for the write step (in order to write the 8K of host data); and a second selection of 4K for the write step (in order to write the 4K of BCI). FIGS. 4A-B are provided merely for illustration purposes. Selections of other variable write steps are contemplated.

[0036] In one embodiment, different write step sizes may be selected for different types of data. For example, the MML firmware of the storage device 12 may store the host data in the binary cache 28 in one programming step and store the BCI in the binary cache 28 in a separate programming step. In this example, the MML firmware may select one size of the write step based on the amount of data received from the host system. As illustrated in FIG. 4A, the write step size selected to store the host data into the binary cache 28 is 8 kB (so that only one programming step is needed to store the 8 kB of host data). Moreover, the MML firmware may select another size of the write step based on the amount of BCI to be written to binary cache 28. As illustrated in FIG. 4A, the write step size selected to store the BCI into the binary cache 28 is 4 kB (so that only one programming step is needed to store the 4 kB of BCI).

[0037] In an alternate embodiment, a single write step size is selected for different types of data. For example, FIG. 4B illustrates a single selection for the write step: a selection of 12K for the write step (in order to write the 8K of host data and the 4K of BCI).

[0038] FIG. 4C illustrates mixed mode command lengths similar to FIG. 3C with 4 kB, 1 sector, and 4 kB, in that order. For the first and second write, the size of the variable write step is selected to be 8 kB. For the third write, the size of the variable write step may be selected to be 6 kB. For the 2 kB tail at the end of the page, the size of the variable write step may be 2 kB. In total, the number of programming steps is 4, with 1.5 kB padded for 1-sector data. Comparing FIG. 3C (using a fixed write step size) with FIG. 4C (using a variable write step size), FIG. 4C illustrates that using the variable write step size reduces the number of programming steps and the amount of padding (invalid data), thereby making for a more efficient use of binary cache block space.

[0039] Referring to FIG. 5, there is shown a flow chart 500 for performing partial page programming with a variable write step. At 505, it is determined whether partial page programming is to be performed. If it is determined to perform partial page programming, at 510, an amount to program via partial page programming is determined. At 515, the write step is set based on the determined amount. As discussed above, the write step may be variable based on one or more factors, including the amount to program using partial page programming. Finally, at 520, the partial page programming is performed at the set write step. Performing the partial page programming may include, on the controller side, the controller generating commands, and sending the commands and data to the memory in order for the memory to program the data via the partial page programming, and on the memory side, the memory receiving the commands and data and performing the partial page programming of the data.

[0040] FIG. 6 is an expansion of blocks 510, 515 and 520 of the flow chart 500 depicted in FIG. 5. At 605, the amount of host data to write to binary cache is determined. At 610, it is determined whether a BCI write to binary cache is necessary. If the BCI write to binary cache is necessary, at 615, the amount to write to binary cache is the amount of host data plus the BCI. If the BCI write to binary cache is not necessary, at 620, the amount to write to binary cache is the amount of host data.

[0041] At 625, it is determined how to minimize the number of programming steps. If the write to the binary cache is in different zones, multiple writes may be necessary (such as, for example, the two programming steps illustrated at 650 and 660). If multiple writes are necessary, the size of the write step is set multiple times. FIG. 6 shows setting two different write steps and two programming steps merely for illustration purposes. At 645, the first write step is set to the amount of BCI. At 650, the first programming step is performed using the first write step. At 655, the second write step is set to the amount of host data. At 660, the second programming step is performed using the second write step. If a single write may be performed, at 630, the write step is set to the amount of the partial page programming, and at 640, the programming step is performed using the write step set.

[0042] FIG. 7A illustrates a graph of Input/Output Operations per Second (IOPs) versus write step for a single sector of data. FIG. 7B illustrates a graph of Input/Output Operations per Second (IOPs) versus write step for 4 kB of data. FIGS. 7A-B are for is for a 24 nM feature length of a 64 Gb single die memory device. 24 nM is merely an example of the feature length; other feature lengths are contemplated. Likewise, other size memory devices are contemplated. Further, FIGS. 7A-B use write step sizes of 4 kB, 8 kB and 16 kB, and illustrate with command aware partial page programming that the best write step may be dynamically selected so that the number of programming steps are optimized. That is, for the single sector case illustrated in FIG. 7A, command aware partial page programming may result in the curve corresponding to write step 4 kB.

[0043] FIG. 8 is a table illustrating sustained random write performance for 8 kB and 4 kB fixed write step sizes (measurements taken on a 24 nm 64 Gb single die product). In high performance products, sustained write performance (measured in a localized logical range) may be governed by the frequency of compactions and the burst speed at which binary cache can be written to. FIG. 8 illustrates input/output operations per second (lops) for different random writes, such as Single Sector (SS) random write, a 1 kB random write, a 2 kB random write, and a 4 kB random write. Iops is a method by which to test improvement of operations of a memory device. As shown in FIG. 8, command aware partial page programming reduces both the number of programming steps and the number of compactions.

[0044] Accordingly, the method and system may be realized in hardware, software, or a combination of hardware and software. The method and system may be realized in a centralized fashion in at least one electronic device (such as illustrated in storage device 12 in FIG. 1) or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein. Such a programmed computer may be considered a special-purpose computer.

[0045] The method and system may also be embedded in a computer program product, which includes all the features enabling the implementation of the operations described herein and which, when loaded in a computer system, is able to carry out these operations. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function, either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.

[0046] The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present embodiments are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description. While various embodiments have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the above detailed description. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents.