SWITCH MODE POWER SUPPLY SYSTEM, ASSOCIATED CONTROLLER AND METHOD

[0001] This application claims the benefit of CN application No. 201110397881.1, filed on Dec. 5, 2011, and incorporated herein by reference.

[0002] The present invention generally relates to electronic circuit, and more particularly but not exclusively relates to a switch mode power supply system, associated controller and control method.

[0003] Constant on-time control is widely applied in the area of power supply because of its excellent load transient response, simple circuitry structure and smooth operation mode switching.

[0004] FIG. 1 illustrates a constant on-time switch mode power supply 100 as a prior art. The power supply 100 comprises constant on-time signal generator 101, a logic circuit 102, a driver circuit 103, a comparator 104, a feedback circuit 106 and a switch circuit 105. The switch circuit 105 comprises at least a power switch configured to convert an input signal VIN to an output signal VOUT by turning the power switch on and off. The feedback circuit 106 is coupled between an output terminal of the switch circuit 105 and an inverting terminal of the comparator 104, configured to generate a feedback signal VFB to reflect the output signal VOUT. The feedback signal is provided to the inverting terminal of the comparator 104. A non-inverting terminal of the comparator 104 receives a reference signal VREF. The comparator 104 compares the feedback signal VFB with the reference signal VREF. The constant on-time signal generator generates a constant on-time signal to a reset terminal of the logic circuit 102. A set terminal of the logic circuit 102 is coupled to an output terminal of the comparator 104. A control signal is generated according to the constant on-time signal and a comparative result of the comparator 104. The control signal is provided to an input terminal of the driver circuit 103. A driver signal of the driver circuit 103 drives the power switch in switch circuit 105 on and off.

[0005] When the switch mode power supply is operating in steady state, the output signal VOUT has a ripple. The control of the power switch in switch circuit 105 depends on the ripple of the output signal VOUT. When the equivalent series resistance (ESR) of an output capacitor in switch circuit 105 is relatively large, the output ripple of the output signal VOUT is also relatively large, which results that the average voltage of the output signal VOUT is larger than a desired value. However, if the ESR of the output capacitor is relatively small, the output ripple of VOUT is also very small. The switch mode power supply is tended to be disturbed, and thereby the output stability is affected.

[0006] One embodiment of the present invention discloses a switch mode power supply system, wherein the switch mode power supply system comprises a switch circuit that comprises a power switch and a controller, wherein the controller comprises a feedback circuit, coupled to an output of the switch mode power supply, configured to generate a feedback signal that is based on an output signal of the switch mode power supply; a first ramp signal generator, coupled to the switch circuit, configured to generate a first ramp signal, the first ramp signal generator compensating the feedback signal with the first ramp signal to generate a compensated feedback signal; a comparator, having an inverting input terminal receiving the compensated feedback signal, and a non-inverting terminal coupled to a reference signal, and an output terminal generating a comparative result; a constant on-time signal generator, generating a constant on-time signal; and a logic circuit, coupled to the constant on-time signal generator and the output terminal of the comparator, configured to generate a control signal to control the power switch turning ON and OFF.

[0018] Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

[0019] FIG. 2 illustrates a block diagram of a switch-mode power supply system 200 according to an embodiment of the present invention. Power supply system 200 comprises a constant on-time (COT) signal generator 201, a logic circuit 202, a driver circuit 203, a comparator 204, a feedback circuit 206, a first ramp (RAMP1) signal generator 207 and a switch circuit 205.

[0020] Feedback circuit 206 generates a feedback signal VFB. The feedback signal VFB is compensated by first ramp signal generator 207 and then a compensated feedback signal V′FB is obtained and provided to an inverting terminal of comparator 204. In one embodiment, first ramp signal generator 207 generates a first ramp signal VRAMP1 according to an output signal of a power switch in switch circuit 205, configured to compensate the feedback signal VFB. The comparator 204 compares the compensated feedback signal V′FB with a reference signal VREF, and obtains a comparative result accordingly. Then the comparative result is sent to a set terminal S of the logic circuit 202.

[0021] The constant on-time signal generator 201 generates a constant on-time signal and sends it to a reset terminal R of the logic circuit 202. The logic circuit 202 generates a control signal PWM according to the constant on-time signal and the comparative result of the comparator 204. The control signal SW is provided to an input terminal of the driver circuit 203. A driver signal of the driver circuit 203 is configured to drive the power switch of switch circuit 205 turning ON and OFF.

[0022] The first ramp signal VRAMP1 in switch-mode power supply system 20 may enhance the stability of switch-mode power supply system. However, with the first ramp signal VRAMP1, the inverting input of comparator 204 receives a compensated feedback signal V′FB, for example, a sum of the feedback signal VFB and the first ramp signal VRAMP1. The average voltage level of this sum is larger than the reference signal VREF, which may results the actual value of the output signal VOUT higher than the desired value.

[0023] FIG. 3 illustrates a schematic block diagram of a switch-mode power supply system 300 according to an embodiment of the present invention. Power supply system 300 comprises a switch circuit 305 and a controller. Switch circuit 305 at least comprises a power switch, through turning on and off of which an input signal VIN is converted to an output signal VOUT. Switch circuit 305 may be applied a direct current to direct current (DC-DC) topology, e.g. synchronous or non-synchronous buck converter, synchronous or non-synchronous boost converter, fly-back converter, forward converter, and etc.

[0024] The controller comprises a constant on-time (COT) signal generator 301, a logic circuit 302, a driver circuit 303, a comparator 304, a feedback circuit 306, a first ramp (RAMP1) signal generator 307 and a second ramp signal generator 308. Feedback signal 306 generates a feedback signal VFB. The feedback signal VFB is compensated by the first ramp signal generator 307 so that a compensated feedback signal V′FB is obtained. The compensated feedback signal V′FB is provided to an inverting input terminal of the comparator 304. In one embodiment, the first ramp signal generator 307 generates a first ramp signal VRAMP1. The first ramp signal VRAMP1 compensates the feedback signal VFB to obtain a compensated feedback signal V′FB, and then the V′FB is send to an inverting terminal of comparator 304.

[0025] Second ramp (RAMP2) signal generator 308 generates a second ramp signal VRAMP2 according to a driver signal SW which is generated from the driver circuit 303 and drives the power switch, configured to compensate a reference signal VREF to obtain a compensated reference signal V′REF. In another embodiment, the second ramp signal VRAMP2 may be according to a control signal PWM which is generated by the logic circuit 302. The compensated reference signal V′REF is then sent to a non-inverting terminal of the comparator 304. In one embodiment, the comparator 304 compares the sum of the feedback signal VFB and the first ramp signal VRAMP1, i.e. the compensated feedback signal V′FB, with the sum of the reference signal V′FB and the second ramp signal VRAMP2, i.e. the compensated reference signal V′REF. A comparative result is consequently generated and provided to a set terminal S of the logic circuit 302.

[0026] Constant on-time signal generator 301 generates a constant on-time signal and sends it to a reset terminal R of the logic circuit 302. Logic circuit 302 generates the control signal PWM according to the comparative result and the constant on-time signal. The control signal PWM is provided to an input terminal of driver circuit 303. The driver signal SW of driver circuit 303 is configured to drive the power switch in switch circuit 305 turning ON and OFF.

[0027] FIG. 4 illustrates a schematic circuitry diagram of a switch-mode power supply system 400 according to an embodiment of the present invention. In the illustrated embodiment, a switch circuit 405 utilizes a topology of synchronous buck converter, comprising a high side power switch M1, a low side switch M2, an inductor L and a capacitor C1. Through operating switches M1 and M2 in complementary, the switch circuit 405 converts an input signal VIN into an output signal VOUT. A first terminal of the high side switch M1 receives the input signal VIN and a second terminal is coupled to a first terminal of the low side switch M2. A second terminal of the low side switch M2 is connected to a reference ground. The high side switch M1 receives a first driver signal SW1 from a driver circuit 403, while the low side switch M2 receives an second driver signal SW2 from the driver circuit 403, wherein the driver signals SW1 and SW2 are complementary signals, configured to respectively control the high side switch M1 and the low side switch M2 alternatively turning ON and OFF. A first terminal of the inductor L is coupled to the common node of the high side switch M1 and the low side switch M2. The capacitor C1 is coupled between a second terminal of the inductor L and the reference ground. In certain embodiments, the high side switch M1 and the low side M2 may be bipolar junction transistor (BJT), or metal oxide semiconductor field effect transistor (MOSFET). In other embodiments, a non-synchronous buck converter which comprise a may be applied, and the low side switch M2 may be replaced by a diode.

[0028] A feedback circuit 406 receives the output signal VOUT, and accordingly generates a feedback signal VFB configured based on the output signal VOUT. The feedback signal VFB is compensated by a first ramp signal generator 407, and then sent to an inverting terminal of a comparator 404.

[0029] Feedback circuit 406 comprises a voltage divider composed by two resistors R1 and R2. A first terminal of the resistor R1 is coupled to an output terminal of the switch circuit 405, while a second terminal of R1 is coupled to a first terminal of the resistor R2. A second terminal of R2 is connected to the reference ground. The common node of the resistors R1 and R2 forms a feedback node FB, configured to generate the feedback signal VFB.

[0030] Comparator 404 receives a compensated feedback signal V′FB which is equal to a sum of the feedback signal VFB and a first ramp signal VRAMP1 generated from the first ramp signal generator 407. A non-inverting terminal of the comparator 404 receives a reference signal V′REF compensated by the second ramp signal VRAMP2, e.g. a sum of the reference signal VREF and the second ramp signal VRAMP2. Comparator 404 further compares the compensated feedback signal V′FB with the compensated reference signal V′REF.

[0031] In one embodiment, when the output signal VOUT is lower than a given value, i.e. the sum of the feedback signal VFB and the first ramp signal VRAMP1, i.e. V′FB, is no larger than the sum of the reference signal VREF and the second ramp signal VRAMP2, comparator 404 generates a high level comparative result to set a logic circuit 402. Consequently by means of the driver circuit 403, a high level output of logic circuit 402 turns on the high side switch M1 on and turns off the low side switch M2, so that the output signal VOUT rises. Therefore, the compensated feedback signal V′FB correspondingly rises. As the high side switch M1 keeps turning on for a constant time, the compensated feedback signal V′FB reaches a peak point. By this time a constant on-time signal generator 401 generates a constant on-time signal to reset the logic circuit 402. Thus the logic circuit 402 is reset to provide a low level output. The low level output of logic circuit 402 turns off the high side switch M1 and turns off the low side switch M2 through the driver circuit 403. Thereby the output signal VOUT begins to decline, which makes the sum of the feedback signal VFB and the first ramp signal VRAMP1 also decline. Once the sum of the feedback signal VFB and the first ramp signal VRAMP1 touches the sum of the reference signal VREF and the second ramp signal VRAMP2 again, the high side switch M1 will be turned on again. This process is repeated configured to regulate the output signal VOUT.

[0032] The first ramp signal generator 407 provides a first ramp signal VRAMP1 with relatively large amplitude on the inverting terminal of comparator 404 which serves as an equivalent series resistor (ESR) of the capacitor C1. In one embodiment, the first ramp signal is a voltage signal, having the same phase with and proportional to the ripple of the inductor current.

[0033] In the illustrated embodiments shown in FIG. 4, the first ramp signal generator 407 comprises a resistor R3, a capacitor C2 and a current source I1. The resistor R3 is coupled between the common node of the high side switch M1 and the low side switch M2, and the feedback node FB. The capacitor C2 is coupled between the feedback node FB and the reference ground. The current source I1 is coupled with the capacitor C2 in parallel. The operation of the resistor R3 and the capacitor C2 generates an alternating component with relative large amplitude as the first ramp signal VRAMP1 on the feedback node FB. Simultaneously, the resistor R3 also introduces a new DC current on the node FB, the value of this current is:

$\begin{array}{cc}\frac{VOUT-VFB}{R3}& \left(1\right)\end{array}$

[0034] Hence the output current of the current source I1 is

$\begin{array}{cc}I1=\frac{VOUT-VFB}{R3}& \left(2\right)\end{array}$

[0035] The current source I1 is configured to neutralize the newly added DC current on the node FB.

[0036] With the first ramp signal VRAMP1, the inverting terminal of comparator 404 receives the compensated feedback signal V′FB, the average value of which are increased larger than the given reference signal VREF. It leads that the actual output signal VOUT is larger than desired result. Therefore, one feature of the illustrated embodiment is that a second ramp signal is utilized to compensate the reference signal.

[0037] Second ramp signal generator 408 is coupled to the non-inverting input terminal of the comparator 404, configured to generate a second ramp signal VRAMP2 to compensate the reference signal VREF, e.g. coupling the second ramp signal VRAMP2 into the reference signal VREF. In one embodiment, the signal on the non-inverting input terminal of the comparator 404 is the compensated reference signal V′REF which is equal to VREF+VRAMP2. As a result, the average value of the compensated feedback signal V′FB on the inverting input terminal of comparator 404 is pulled back. In some embodiments, a various types of ramp signal generators may be applied as second ramp signal generator 408 configure to generate a suitable second ramp signal VRAMP2 to make the average value of the compensated signal V′FB substantially equal to the given reference signal VREF, and further to regulate the voltage converter to obtain an accurate output signal VOUT.

[0038] One skilled in relevant art may understand that in other embodiments, the second ramp signal VRAMP2 may compensate the reference signal VREF according to other suitable regulations. For example, in another embodiment, V′REF=k×VRAMP2+m×VREF, wherein k and m are constant factors.

[0039] FIG. 5 is a schematic wave-form diagram of the voltage converter 400 with the second ramp signal generator 408 disabled. When the high side switch M1 is on and the low side switch M2 is off, the current flowing through the inductor L rises gradually, and the feedback signal VFB and the compensated feedback signal V′FB (VFB+VRAMP1) correspondingly rise. When the high side switch M1 is on for a constant time DT, the value of VFB+VRAMP1 reaches a maximum point, and the increment OVFB of the compensated feedback signal V′FB is shown as formula (3)

$\begin{array}{cc}\Delta VFB=\frac{I\times t}{C2}=\frac{\left(\frac{VIN-VFB}{R3}-\frac{VOUT-VFB}{R3}\right)\times \mathrm{DT}}{C3}=\frac{VOUT\times \left(1-D\right)T}{R3\times C2}& \left(3\right)\end{array}$

Wherein, D is the duty-cycle of the high side switch M1, and T is the switching cycle of the high side switch M1.

[0040] The high side switch M1 is turned off and the low side switch M2 is turned on when the constant on time DT has past. After then, the current flowing through the inductor L, as well as the feedback signal VFB and the compensated feedback signal V′FB (VFB+VRAMP1) is gradually decreased. Once the V′FB falls to the reference signal VFB, the high side switch M1 is turned on again and the low side switch M2 is turned off. The inductor current increases again. The above operational process is repeated to realize the regulation of the output signal VOUT.

[0041] With the introduction of the first ramp signal VRAMP1, the average value VAVG of the voltage on the inverting terminal of comparator 404 is larger than the reference signal VREF, resulting that the actual output signal VOUT is larger than the desired value. The average value VAVG is illustrated in formula (4)

$\begin{array}{cc}VAVG=\frac{1}{2}\Delta VFB+VREF=\frac{VOUT\times \left(1-D\right)T}{2\times R3\times C2}+VREF& \left(4\right)\end{array}$

[0042] FIG. 6 illustrates a schematic wave-form diagram of the voltage converter 400 with the second ramp signal generator 408 enabled. When the average value VAVG is equal to the reference signal VREF, the actual output signal VOUT will be equal to the desired value. According to formula (4), if a second ramp signal VRAMP2 has an amplitude equal to

$-\frac{1}{2}\Delta VFB,$

the VAVG=VREF. Supposing that the slope of the second ramp signal VRAMP2 is ramp2, then ramp2 is:

$\begin{array}{cc}\mathrm{ramp}2=\frac{\frac{1}{2}\Delta VFB}{t}=-\frac{VOUT}{2\times R3\times C2}\times \frac{\left(1-D\right)T}{t}\left(t\le T\right)& \left(5\right)\end{array}$

[0043] Wherein, t is the enabled time of the second ramp signal VRAMP2 in a single operation cycle. In one embodiment, t=(1−D)X T, the second ramp signal VRAMP2 is enabled during the off-time of the high side switch M. Therefore the slope ramp2 is constant. At this condition, the slope ramp2 is shown as formula (6)

$\begin{array}{cc}\mathrm{ramp}2=\frac{VOUT}{2\times R3\times C2}& \left(6\right)\end{array}$

[0044] According to formula (6), the slope ramp2 of the second ramp signal VRAMP2 depends on the output signal VOUT of the power supply system 400, the resistance of resistor R3 in the first ramp signal generator 407, and the capacitance of the capacitor C2. Once the second ramp signal VRAMP2 with a slope ramp2 is added to the non-inverting input terminal of the comparator 404, the actual output signal VOUT may be equal to the desired value.

[0045] FIG. 7 illustrates a schematic circuitry diagram of a second ramp signal generator 700 according to an embodiment of the present invention. As shown in FIG. 7, second ramp signal generator 700 comprises switches M3 and M4, an inverter INV, a resistor R4 and a capacitor C3. A first terminal of the switch M3 receives the reference signal VREF, and a second terminal of M3 is coupled to the non-inverting input terminal of comparator 404. A first terminal of the switch M4 is coupled to a first terminal of the resistor R4, and a second terminal of the switch M4 is connected to the reference ground. A first terminal of the capacitor C3 is coupled to a second terminal of the resistor R4. A second terminal of the capacitor C3 is coupled to the reference ground. A control terminal of the switch M3 receives the first driver signal SW1, and a control terminal of the switch M4 is coupled to an output terminal of the inverter INV. An input terminal of the inverter INV is coupled to the first driver signal SW1. Thus the switches M3 and M4 are complementarily turned on and off, and the switch M3 is synchronous to the switch M1 in switch circuit 405.

[0046] When the first driver signal SW1 is at high level, the output of the inverter INV is at low level. As a result the switch M3 is turned on and the switch M4 is turned off, and V′REF=VREF. Meanwhile, the capacitor C3 is charged and the voltage across the capacitor C3 is VREF. Once the first driver signal SW1 drops to low level, the inverter INV generates a high level output. The switch M3 is turned off and the switch M4 is turned on. The switch M4 is discharged through a loop comprised by the switch M4 and the resistor R4, and generates the compensated reference signal V′REF. The discharging current Ic3 of the capacitor C3 is:

$\begin{array}{cc}\mathrm{Ic}3=\frac{VREF}{R4}& \left(7\right)\end{array}$

[0047] Accordingly, a ramp signal is obtain on the first terminal of capacitor C3. The slope of this ramp signal is:

$\begin{array}{cc}-\frac{VREF}{R4\times C3}& \left(8\right)\end{array}$

[0048] By choosing proper values of the resistor R4 and the capacitor C3 to satisfy the formula (9) in the following, the slope of this ramp signal may be equal to the required slope ramp2 of the second ramp signal VRAMP2.

$\begin{array}{cc}\frac{VREF}{R4\times C3}=\frac{VOUT}{2\times R3\times C2}& \left(9\right)\end{array}$

[0049] FIG. 8 illustrates a schematic circuitry diagram of another second ramp signal generator 800 according to another embodiment of the present invention. The illustrated second ramp signal generator 800 comprises a switch M5, a MOSFET M6, a current source 12, a capacitor C4, three resistors R5, R6 and R7, and a buffer comparator BUF. The capacitor C4 is coupled between an output terminal of the current source 12 and the reference ground. The switch M5 is coupled to the capacitor C4 in parallel. The output terminal of the current source 12 is further coupled to a non-inverting terminal of the buffer comparator BUF. A control terminal of the switch M5 receives the control signal SW1. A drain terminal of the MOSFET M6 is coupled to a power supply voltage VCC through the resistor R6, and meanwhile coupled to the reference signal VREF through the resistor R5. The compensated reference signal V′REF is also generated on the drain terminal of the MOSFET M6. A source terminal of the MOSFET M6 is coupled to an inverting terminal of the buffer comparator BUF, and further coupled to the reference ground through the resistor R7. A control terminal of the MOSFET M6 is coupled to an output terminal of the buffer comparator BUF.

[0050] In other embodiments, MOSFET M6 may be replaced by other suitable devices, e.g. bipolar junction transistor (BJT), junction field effect transistor (JFET), and etc.

[0051] The operation of the switch M5 is synchronous to the switch M1 in switch circuit 405. When the switch M5 is turned off, the current source 12 charges the capacitor C4, the voltage on the non-inverting terminal of the buffer comparator BUF is

$\begin{array}{cc}\mathrm{Vc}=\frac{I2\times t}{C4}& \left(10\right)\end{array}$

[0052] The MOSFET M6 is operating at linear region. The current flowing through the resistor R7 is

$\begin{array}{cc}{I}_{R7}=\frac{I2\times t}{C4\times R7}& \left(11\right)\end{array}$

[0053] The voltage on the drain terminal of the MOSFET M6 is

$\begin{array}{cc}{V}_{\mathrm{CC}}-\frac{I2\times t\times R6}{C4\times R7}& \left(12\right)\end{array}$

[0054] When the switch M5 is turned on, the current source 12 is shorted. The capacitor C4 is discharged through the switch M5. The MOFET M6 is off.

[0055] By choosing proper resistance values of the resistors, the capacitor and the current source could satisfy the formula (13) in the following, and the ramp slope of the compensated reference signal V′REF may be equal to the required slope ramp2.

$\begin{array}{cc}\frac{I2\times R6}{C4\times R7}=\frac{VOUT}{2\times R3\times C2}& \left(13\right)\end{array}$

[0056] One with ordinary skill in relevant art should understand that in certain embodiments, the switches M3, M4 and M5 shown in FIG. 7 and FIG. 8 may be BJT or MOSFET or other suitable switching device.

[0057] FIG. 9 illustrates a process flow diagram of a method for controlling a switch mode power supply system according to an embodiment of the present invention. The power supply system comprises a switch circuit. The switch circuit comprises at least a power switch. The method in the illustrated embodiment comprises steps 910-960 which are listed as following:

[0058] Step 910, generating a feedback signal which is based on the output signal of the power supply system;

[0059] Step 920, generating a first ramp signal by means of a first ramp signal generator, and compensating the feedback signal configured to generate a compensated feedback signal;

[0060] Step 930, generating a second ramp signal by means of a second ramp signal generator, and compensating a reference signal configured to generate a compensated reference signal;

[0061] Step 940, comparing the compensated feedback signal with the compensated reference signal to obtain a comparative result;

[0062] Step 950, generating a constant on-time signal by a constant on-time controller; and

[0063] Step 960, controlling the power switch in the switch circuit turning ON and OFF according to the constant on-time signal and the comparative result.

[0064] In one embodiment, the compensated feedback signal is the sum of the feedback signal and the first ramp signal. And in one embodiment, the compensated reference signal is the sum of the reference signal and the second ramp signal.

[0065] In the embodiment shown in FIG. 9, the generation of the on-time signal in Step 950 is later than the Step 940. However, one with ordinary skill in relevant art should understand that the Step 950 may be placed before any step of the Steps 910-940 in other embodiments.

[0066] In one embodiment, the slope of the second ramp signal may depend on the output signal of the power supply system.

[0067] The above description and discussion about specific embodiments of the present invention is for purposes of illustration. However, one with ordinary skill in the relevant art should know that the invention is not limited by the specific examples disclosed herein. Variations and modifications can be made on the apparatus, methods and technical design described above. Accordingly, the invention should be viewed as limited solely by the scope and spirit of the appended claims.