CLOCK SIGNAL GENERATION CIRCUIT

[0001] The present invention relates to a clock signal generation circuit. In particular, the present invention relates to a clock signal generation circuit capable of generating a plurality of clock signals having frequencies different to each other.

[0002] In general, a signal processing circuit disposed in a semiconductor integrated device (referred to as an LSI) is operated at a clock signal with a high frequency when the signal processing circuit needs to perform a high speed processing. On the other hand, when the signal processing circuit does not need to perform a high speed processing, the signal processing circuit is operated at a clock signal with a low frequency. Accordingly, it is possible to perform the high speed processing or reduce power consumption.

[0003] Further, an oscillation circuit is disposed in the LSI for generating the clock signal described above. The oscillation circuit may include a crystal ceramic oscillation circuit, a PLL (Phase Locked Loop) oscillation circuit, and a CR (Capacitor Resistor) oscillation circuit formed of a capacitor and a resistor. The CR oscillation circuit is characterized to have a shorter waiting period, from when the CR oscillation circuit is turned on to when the oscillation frequency of the CR oscillation circuit is stabilized, as compared to the crystal ceramic oscillation circuit or the PLL oscillation circuit.

[0004] Although the PLL oscillation circuit has a longer waiting period as compared with the CR oscillation circuit, the PLL oscillation circuit is characterized to be capable of generating a clock signal with a higher frequency. In the crystal ceramic oscillation circuit, the characteristics of a crystal determines the oscillation frequency thereof. Accordingly, it is difficult to change the oscillation frequency. However, the crystal ceramic oscillation circuit is characterized to be capable of generating a clock signal with a higher frequency.

[0005] Patent Reference has disclosed a conventional clock signal generation circuit. In the conventional clock signal generation circuit, the CR oscillation circuit, the PLL oscillation circuit, and the crystal ceramic oscillation circuit described above are combined, so that the characteristics thereof are effectively utilized. Accordingly, it is possible to reduce the waiting period and power consumption.

• [0006] Patent Reference Japanese Patent Publication No. 2001-344039

[0007] In the conventional clock signal generation circuit disclosed in Patent Reference, the crystal oscillation circuit is provided for generating a clock signal CLK1 with a low frequency, so that the clock signal CLK1 is supplied to the signal processing circuit described above. The CR oscillation circuit is provided for generating a first clock signal CLK11 with a high frequency. Further, the PLL oscillation circuit is provided for generating a second clock signal CLK12 with a high frequency according to the clock signal CLK1 with the low frequency generated with the crystal oscillation circuit.

[0008] When the conventional clock signal generation circuit disclosed in Patent Reference starts operating, it is configured such that the first clock signal CLK11 generated by the CR oscillation circuit with the relatively short waiting period is supplied to the signal processing circuit. After the oscillation state of the PLL oscillation circuit is stabilized, instead of the first clock signal CLK11, the second clock signal CLK12 generated by the PLL oscillation circuit is supplied to the signal processing circuit.

[0009] In the conventional clock signal generation circuit disclosed in Patent Reference, the crystal oscillation circuit has the long waiting period of the long oscillation stabilization period of about a few hundreds ms, from when the crystal oscillation circuit is turned on to when the oscillation operation of the crystal oscillation circuit is stabilized. Accordingly, it is necessary to provide a long startup time to a circuit block that is operated with the clock signal CLK1 with the low frequency.

[0010] In the conventional clock signal generation circuit disclosed in Patent Reference, the crystal oscillation circuit includes a crystal oscillation element externally connected to the LSI for operating the crystal oscillation circuit. It has been known that the crystal oscillation element tends to be susceptible to an external noise such as an electromagnetic wave, vibration, and the like, or an external disturbance effect such as moisture, dust, a foreign matter, and the like. When the crystal oscillation element stops operating due to the external noise or the external disturbance, the PLL oscillation circuit stops generating the second clock signal CLK12. As a result, when the clock signal to be supplied to the signal processing circuit is switched from the first clock signal SLK11 to the second clock signal SLK12, the signal processing circuit stops operating.

[0011] In view of the problems described above, an object of the present invention is to provide a clock signal generation circuit capable of solving the problems of the conventional clock signal generation circuit. In the present invention, it is possible to quickly startup after the clock signal generation circuit is turned on, and to continuously generate a clock signal even when the external noise or the external disturbance occurs.

[0012] Further objects and advantages of the invention will be apparent from the following description of the invention.

[0013] In order to attain the objects described above, according to an aspect of the present invention, a clock signal generation circuit is configured to generate a high speed clock signal having a first frequency and a low speed clock signal having a second frequency lower than the first frequency.

[0014] According to the aspect of the present invention, the clock signal generation circuit includes a first oscillation circuit for generating a first oscillation clock signal having the first frequency; a second oscillation circuit for generating a second oscillation clock signal having the second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as the high speed clock signal.

[0015] According to the aspect of the present invention, the clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal. Further, the clock selection circuit is configured to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.

[0016] As described above, in the aspect of the present invention, the clock selection circuit is configured to output the first oscillation clock signal as the high speed clock signal, and to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal. Further, the clock selection circuit is configured to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.

[0017] In the aspect of the present invention, the first oscillation circuit may be formed of the CR oscillation circuit, and the second oscillation circuit may be formed of the crystal oscillation circuit or the ceramic oscillation circuit. Accordingly, an oscillation state of the first oscillation circuit is stabilized in a shorter period of time as compared with the second oscillation circuit.

[0018] In this case, immediately after the clock selection circuit is turned on, the clock selection circuit is configured to output the frequency division clock signal, which is obtained through dividing the first oscillation clock signal generated with the first oscillation circuit, as the low speed clock signal.

[0019] Accordingly, after the clock selection circuit is turned on, before the oscillation state of the second oscillation circuit formed of the crystal oscillation circuit of the ceramic oscillation circuit is stabilized, it is possible to supply the low speed clock signal. As a result, it is possible to quickly startup a signal processing circuit operated with the low speed clock signal. After the oscillation state of the second oscillation circuit formed of the crystal oscillation circuit or the ceramic oscillation circuit is stabilized, instead of the frequency division clock signal, the second oscillation clock signal accurately generated with the second oscillation circuit is supplied as the low speed clock signal to the signal processing circuit.

[0020] After the oscillation state of the second oscillation circuit is stabilized, even when the crystal oscillation circuit or the ceramic oscillation circuit becomes malfunction due to the external disturbance effect, instead of the second oscillation clock signal, the frequency division clock signal is supplied as the low speed clock signal to the signal processing circuit. Accordingly, it is possible to continuously operate the signal processing circuit with the low speed clock signal.

[0025] Hereunder, preferred embodiments of the present invention will be explained with reference to the accompanying drawings.

[0026] In the present invention, a clock signal generation circuit is configured to generate a high speed clock signal having a first frequency and a low speed clock signal having a second frequency lower than the first frequency.

[0027] According to the present invention, a clock selection circuit is configured to output a first oscillation clock signal generated with a first oscillation circuit as the high speed clock signal. The clock selection circuit is configured to output a second oscillation clock signal generated with a second oscillation circuit as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal. Further, the clock selection circuit is configured to output a frequency division clock signal obtained through dividing the first oscillation clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.

[0028] A first embodiment of the present invention will be explained. FIG. 1 is a block diagram showing an internal configuration of an LSI with a clock signal generation circuit disposed therein according to a first embodiment of the present invention.

[0029] As shown in FIG. 1, the LSI includes a logic circuit unit 1 for performing various signal processing as a primary operation of the LSI, and a clock signal generation unit 2. The clock signal generation unit 2 is configured to generate a high speed clock signal HCLK for operating the logic circuit unit 1 and a low speed clock signal LSCLK having a frequency lower than that of the high speed clock signal HCLK. Further, the clock signal generation unit 2 is configured to supply the high speed clock signal HCLK and the low speed clock signal LSCLK to the logic circuit unit 1.

[0030] Further, the LSI includes a first crystal oscillator 3 and a second crystal oscillator 4. The first crystal oscillator 3 is configured to generate an oscillation signal having a low frequency as an oscillation source of the low speed clock signal LSCLK. The second crystal oscillator 4 is configured to generate an oscillation signal having a frequency higher than that of the low speed clock signal LSCLK.

[0031] In the embodiment, the clock signal generation unit 2 includes a startup control circuit 20; a low speed crystal oscillation circuit 21; a high speed crystal oscillation circuit 22; and a high speed PLL (Phase Locked Loop) oscillation circuit 23. When the low speed crystal oscillation circuit 21, the high speed crystal oscillation circuit 22, and the high speed PLL oscillation circuit 23 perform the oscillation operation, the startup control circuit 20 is configured to supply oscillation enable signals EN1, EN2, and EN3 with a logic level “1” to the low speed crystal oscillation circuit 21, the high speed crystal oscillation circuit 22, and the high speed PLL oscillation circuit 23, respectively. When the low speed crystal oscillation circuit 21, the high speed crystal oscillation circuit 22, and the high speed PLL oscillation circuit 23 stop the oscillation operation, the startup control circuit 20 is configured to supply the oscillation enable signals EN1, EN2, and EN3 with a logic level “0” to the low speed crystal oscillation circuit 21, the high speed crystal oscillation circuit 22, and the high speed PLL oscillation circuit 23, respectively.

[0032] In the embodiment, the clock signal generation unit 2 further includes a low speed clock control circuit 24 and a high speed clock control circuit 25. When the power is turned on, the startup control circuit 20 is configured to generate a reset pulse signal RS, so that the startup control circuit 20 supplies the reset pulse signal RS to the low speed clock control circuit 24 and the high speed clock control circuit 25, respectively.

[0033] In the embodiment, the low speed crystal oscillation circuit 21 is configured to generate an oscillation clock signal LCLK having a low frequency according to an oscillation signal supplied from the first crystal oscillator 3 when the startup control circuit 20 supplies the oscillation enable signal EN1 with the logic level “1” to the low speed crystal oscillation circuit 21. Further, the low speed crystal oscillation circuit 21 is configured to supply the oscillation clock signal LCLK to the high speed PLL oscillation circuit 23, the low speed clock control circuit 24, and the high speed clock control circuit 25, respectively. It is noted that the low speed crystal oscillation circuit 21 is configured to stop the oscillation operation thereof so as to stop generating the oscillation clock signal LCLK when the startup control circuit 20 supplies the oscillation enable signal EN1 with the logic level “0” to the low speed crystal oscillation circuit 21.

[0034] In the embodiment, when the oscillation enable signal EN1 is switched from the logic level “0” to the logic level “1” to initiate a startup instruction, the low speed crystal oscillation circuit 21 starts the oscillation operation according to the startup instruction. After the startup instruction is initiated, the low speed crystal oscillation circuit 21 becomes a state capable of stably generating the oscillation clock signal LCLK after an oscillation stabilization period TA (described later).

[0035] In the embodiment, the high speed crystal oscillation circuit 22 is configured to generate an oscillation clock signal HOCLK having a high frequency according to an oscillation signal supplied from the second crystal oscillator 4 when the startup control circuit 20 supplies the oscillation enable signal EN2 with the logic level “1” to the high speed crystal oscillation circuit 22.

[0036] Further, in the embodiment, the clock signal generation unit 2 includes a high speed clock selection circuit 27. The high speed crystal oscillation circuit 22 is configured to supply the oscillation clock signal HOCLK to the high speed clock selection circuit 27. It is noted that the high speed crystal oscillation circuit 22 is configured to stop the oscillation operation thereof so as to stop generating the oscillation clock signal HOCLK when the startup control circuit 20 supplies the oscillation enable signal EN2 with the logic level “0” to the high speed crystal oscillation circuit 22.

[0037] In the embodiment, with the oscillation clock signal LCLK as the reference clock, the high speed PLL oscillation circuit 23 is configured to generate an oscillation clock signal PLLCLK having a frequency higher than that of the oscillation clock signal LCLK and a phase synchronized with that of the oscillation clock signal LCLK when the startup control circuit 20 supplies the oscillation enable signal EN3 with the logic level “1” to the high speed PLL oscillation circuit 23. Further, the high speed PLL oscillation circuit 23 is configured to supply the oscillation clock signal PLLCLK to the high speed clock selection circuit 27. It is noted that the high speed PLL oscillation circuit 23 is configured to stop the oscillation operation thereof so as to stop generating the oscillation clock signal PLLCLK when the startup control circuit 20 supplies the oscillation enable signal EN3 with the logic level “0” to the high speed PLL oscillation circuit 23.

[0038] In the embodiment, when the oscillation enable signal EN3 is switched from the logic level “0” to the logic level “1” to initiate the startup instruction, the high speed PLL oscillation circuit 23 starts the oscillation operation according to the startup instruction. After the startup instruction is initiated, the high speed PLL oscillation circuit 23 becomes a state capable of stably generating the oscillation clock signal PLLCLK after an oscillation stabilization period TC (described later).

[0039] In the embodiment, the clock signal generation unit 2 further includes a low speed clock selection circuit 26. The low speed clock control circuit 24 is configured to supply a low speed clock selection control signal LSS with the logic level “1” to the low speed clock selection circuit 26 according to the reset pulse signal RS, so that the low speed clock selection circuit 26 selects a frequency division clock signal DIVC (described later).

[0040] In the next step, the low speed clock control circuit 24 determines whether the low speed crystal oscillation circuit 21 supplies the oscillation clock signal LCLK. When the low speed clock control circuit 24 determines that the low speed crystal oscillation circuit 21 supplies the oscillation clock signal LCLK, the low speed clock control circuit 24 supplies the low speed clock selection control signal LSS with the logic level “0” to the low speed clock selection circuit 26, so that the low speed clock selection circuit 26 selects the oscillation clock signal LCLK. When the low speed clock control circuit 24 determines that the low speed crystal oscillation circuit 21 does not supply the oscillation clock signal LCLK, the low speed clock control circuit 24 switches the logic level “0” of the low speed clock selection control signal LSS to the logic level “1”, so that the low speed clock selection circuit 26 selects the frequency division clock signal DIVC.

[0041] In the embodiment, the clock signal generation unit 2 further includes a high speed CR (Capacitor Resistor) oscillation circuit 28. The low speed clock control circuit 24 is also configured to supply the low speed clock selection control signal LSS to the high speed clock control circuit 25. When the low speed crystal oscillation circuit 21 does not supply the oscillation clock signal LCLK, the low speed clock control circuit 24 is configured to supply an oscillation enable signal EN4 with the logic level “1” to the high speed CR oscillation circuit 28, so that the high speed CR oscillation circuit 28 performs the oscillation operation.

[0042] In the embodiment, the high speed CR oscillation circuit 28 is configured to perform the oscillation operation using a resistor and a capacitor only when the low speed clock control circuit 24 supplies the oscillation enable signal EN4 with the logic level “1” to the high speed CR oscillation circuit 28, or the high speed clock control circuit 25 supplies an oscillation enable signal EN5 with the logic level “1” to the high speed CR oscillation circuit 28. Further, the high speed PLL oscillation circuit 23 is configured to supply the oscillation clock signal PLLCLK to the high speed clock selection circuit 27.

[0043] In the embodiment, the clock signal generation unit 2 further includes a frequency division circuit 29. When the high speed CR oscillation circuit 28 performs the oscillation operation, the high speed CR oscillation circuit 28 generates an oscillation clock signal CRCLK having a frequency higher than that of the oscillation clock signal LCLK, so that the high speed CR oscillation circuit 28 supplies the oscillation clock signal CRCLK to the high speed clock selection circuit 27 and the frequency division circuit 29, respectively.

[0044] In the embodiment, when the oscillation enable signal EN4 is switched from the logic level “0” to the logic level “1” to initiate the startup instruction, the high speed CR oscillation circuit 28 starts the oscillation operation according to the startup instruction. After the startup instruction is initiated, the high speed CR oscillation circuit 28 becomes a state capable of stably generating the oscillation clock signal CRCLK after an oscillation stabilization period TB (described later).

[0045] In the embodiment, the high speed clock control circuit 25 is configured to supply a high speed clock selection control signal HCS to the high speed clock selection circuit 27 according to the reset pulse signal RS, so that the high speed clock selection circuit 27 selects the oscillation clock signal CRCLK supplied from the high speed CR oscillation circuit 28. Further, the high speed clock control circuit 25 is configured to generate and supply the high speed clock selection control signal HCS to the high speed clock selection circuit 27 according to a clock selection control process, so that the high speed clock selection circuit 27 selects one of the oscillation clock signal HOCLK, the oscillation clock signal PLLCLK, and the oscillation clock signal CRCLK.

[0046] During the period of time, when the low speed clock control circuit 24 supplies the low speed clock selection control signal LSS with the logic level “1” to the high speed clock control circuit 25 to select the frequency division clock signal DIVC, that is, the low speed crystal oscillation circuit 21 does not supply the oscillation clock signal LCLK, the high speed clock control circuit 25 supplies the high speed clock selection control signal HCS to S27, so that the high speed clock selection circuit 27 selects the oscillation clock signal CRCLK.

[0047] Further, according to the clock selection control process, the high speed clock control circuit 25 supplies the oscillation enable signal EN5 with the logic level “1” to the high speed CR oscillation circuit 28, so that the high speed CR oscillation circuit 28 performs the oscillation operation. On the other hand, the high speed clock control circuit 25 supplies the oscillation enable signal EN5 with the logic level “0” to the high speed CR oscillation circuit 28, so that the high speed CR oscillation circuit 28 stops the oscillation operation.

[0048] In the embodiment, the high speed clock selection circuit 27 is configured to select one of the oscillation clock signal HOCLK, the oscillation clock signal PLLCLK, and the oscillation clock signal CRCLK as indicated with the high speed clock selection control signal HCS. Then, the high speed clock selection circuit 27 is configured to supply the selected one to the logic circuit unit 1 as the high speed clock signal HCLK.

[0049] In the embodiment, the frequency division circuit 29 is configured to divide the oscillation clock signal CRCLK supplied from the high speed CR oscillation circuit 28 by N (N is a natural integer) to generate the frequency division clock signal DIVC, so that the frequency division circuit 29 supplies the frequency division clock signal DIVC to the low speed clock selection circuit 26.

[0050] More specifically, the frequency division circuit 29 is configured to divide the oscillation clock signal CRCLK such that the frequency of the frequency division clock signal DIVC matches to the frequency of the oscillation clock signal LCLK or becomes closer to a closest frequency of the oscillation clock signal LCLK. For example, when the oscillation clock signal CRCLK has the frequency of 500 kHz, and the oscillation clock signal LCLK has the frequency of 32.768 kHz, the frequency division circuit 29 sets N to sixteen. Accordingly, the frequency of the frequency division clock signal DIVC becomes 31.25 kHz (500/16=31.25).

[0051] In the embodiment, the low speed clock selection circuit 26 is configured to select one of the frequency division clock signal DIVC and the oscillation clock signal LCLK supplied from the low speed crystal oscillation circuit 21 according to the low speed clock selection control signal LSS. Then, the low speed clock selection circuit 26 supplies the selected one to the logic circuit unit 1 as the low speed clock signal LSCLK.

[0052] An operation of the clock signal generation unit 2 shown in FIG. 1 will be explained with reference to FIG. 2. FIG. 2 is a time chart showing the operation of the clock signal generation circuit according to the first embodiment of the present invention.

[0053] As shown in FIG. 2, when the power is turned on at a timing T0, the startup control circuit 20 supplies the oscillation enable signal EN1 with the logic level “1” to the low speed crystal oscillation circuit 21, so that the low speed crystal oscillation circuit 21 starts the oscillation operation. Further, the startup control circuit 20 supplies the oscillation enable signal EN1 with the logic level “0” to the high speed crystal oscillation circuit 22 and the high speed PLL oscillation circuit 23, so that the high speed crystal oscillation circuit 22 and the high speed PLL oscillation circuit 23 stop the oscillation operation.

[0054] According to the oscillation enable signal EN1 with the logic level “1” supplied at the timing T0, the low speed crystal oscillation circuit 21 starts the oscillation operation. At a timing T2 after the oscillation stabilization period TA (for example, a few hundreds ms), the low speed crystal oscillation circuit 21 becomes the state of transmitting the oscillation clock signal LCLK. Accordingly, during the period between the timing T0 and the timing T2, the low speed crystal oscillation circuit 21 does not generate the oscillation clock signal LCLK.

[0055] Accordingly, during the period, the low speed clock control circuit 24 supplies the oscillation enable signal EN4 with the logic level “1” to the high speed CR oscillation circuit 28, so that the high speed CR oscillation circuit 28 starts the oscillation operation. As a result, the high speed CR oscillation circuit 28 starts the oscillation operation. At a timing T1 after the oscillation stabilization period TB (for example, a few tens ms), the high speed CR oscillation circuit 28 becomes the state of transmitting the oscillation clock signal CRCLK. At this moment, the frequency division circuit 29 supplies the frequency division clock signal DIVC obtained through dividing the oscillation clock signal CRCLK by N to the low speed clock selection circuit 26.

[0056] Further, in the embodiment, when the power is turned on at the timing T0, the startup control circuit 20 supplies the reset pulse signal RS to the low speed clock control circuit 24 and the high speed clock control circuit 25, respectively. According to the reset pulse signal RS, the high speed clock control circuit 25 supplies the high speed clock selection control signal HCS to the high speed clock selection circuit 27, so that the high speed clock selection circuit 27 selects the oscillation clock signal CRCLK, and the low speed clock control circuit 24 supplies the low speed clock selection control signal LSS with the logic level “1” to the low speed clock selection circuit 26, so that the low speed clock selection circuit 26 selects the frequency division clock signal DIVC.

[0057] Accordingly, as shown in FIG. 2, after the timing T1, the oscillation clock signal CRCLK generated with the high speed CR oscillation circuit 28 is supplied to the logic circuit unit 1 as the high speed clock signal HCLK, and the frequency division clock signal DIVC generated with the frequency division circuit 29 is supplied to the logic circuit unit 1 as the low speed clock signal LSCLK.

[0058] In the embodiment, at the timing T2 shown in FIG. 2, after the low speed crystal oscillation circuit 21 becomes the state of transmitting the oscillation clock signal LCLK, the low speed clock control circuit 24 changes the state of the low speed clock selection control signal LSS to be supplied to the low speed clock selection circuit 26 to the logic level “0”, so that the low speed clock selection circuit 26 selects the oscillation clock signal LCLK. Further, at this moment, the low speed clock control circuit 24 changes the state of the oscillation enable signal EN4 to the logic level “0”, so that the high speed CR oscillation circuit 28 stops the oscillation operation. Accordingly, instead of the frequency division clock signal DIVC, the oscillation clock signal LCLK generated with the low speed crystal oscillation circuit 21 is supplied to the logic circuit unit 1 as the low speed clock signal LSCLK.

[0059] Further, when the state of the low speed clock selection control signal LSS is switched from the logic level “1” to the logic level “0” at the timing T2, the high speed clock control circuit 25 supplies the oscillation enable signal EN5 with the logic level “1” to the high speed CR oscillation circuit 28, so that the high speed CR oscillation circuit 28 starts the oscillation operation. It is noted that the high speed CR oscillation circuit 28 continues the oscillation operation for generating the oscillation clock signal CRCLK after the timing T2.

[0060] After the state of the low speed clock selection control signal LSS is switched from the logic level “1” to the logic level “0” at the timing T2, when a specific period of time TQ is elapsed at a timing T3, the high speed clock control circuit 25 switches the state of the oscillation enable signal EN5 supplied to the high speed CR oscillation circuit 28 from the logic level “1” to the logic level “0”, so that the high speed CR oscillation circuit 28 stops the oscillation operation. Accordingly, the high speed CR oscillation circuit 28 stops generating the oscillation clock signal CRCLK, and the frequency division circuit 29 stops generating the frequency division clock signal DIVC.

[0061] Further, at the timing T3, the startup control circuit 20 supplies the oscillation enable signal EN3 with the logic level “1” to the high speed PLL oscillation circuit 23, so that the high speed PLL oscillation circuit 23 starts the oscillation operation. Accordingly, the high speed PLL oscillation circuit 23 starts the oscillation operation. At a timing T4 after the oscillation stabilization period TC (for example, a few ms) is elapsed from the timing T3, the high speed PLL oscillation circuit 23 becomes the state of transmitting the oscillation clock signal PLLCLK.

[0062] Further, at the timing T3, the high speed clock control circuit 25 supplies the high speed clock selection control signal HCS to the high speed clock selection circuit 27, so that the high speed clock selection circuit 27 selects the oscillation clock signal PLLCLK generated with the high speed PLL oscillation circuit 23. Accordingly, as shown FIG. 2, after the timing T4, the oscillation clock signal PLLCLK generated with the high speed PLL oscillation circuit 23 is supplied to the logic circuit unit 1 as the high speed clock signal HCLK.

[0063] In the embodiment, it is supposed that an external noise such as an electromagnetic wave, vibration, and the like, or an external disturbance effect such as moisture, dust, a foreign matter, and the like occurs at a timing T5. Associated with the external noise or the external disturbance effect, when the first crystal oscillator 3 externally connected to the LSI stops the oscillation operation, the low speed crystal oscillation circuit 21 stops the oscillation operation as well. Accordingly, the low speed crystal oscillation circuit 21 stops generating the oscillation clock signal LCLK.

[0064] As shown in FIG. 2, at the timing T5, when the low speed clock control circuit 24 detects that the low speed crystal oscillation circuit 21 stops supplying the oscillation clock signal LCLK, the low speed clock control circuit 24 supplies the oscillation enable signal EN4 with the logic level “1”, so that the high speed CR oscillation circuit 28 starts the oscillation operation. Accordingly, the high speed CR oscillation circuit 28 starts the oscillation operation.

[0065] At a timing T6 after the oscillation stabilization period TB (for example, a few tens ms), the high speed CR oscillation circuit 28 becomes the state of transmitting the oscillation clock signal CRCLK. At this moment, the frequency division circuit 29 divides the oscillation clock signal CRCLK by N to generate the frequency division clock signal DIVC having the frequency equal to or substantially similar to the frequency of the oscillation clock signal LCLK generated with the low speed crystal oscillation circuit 21. Then, the frequency division circuit 29 supplies the frequency division clock signal DIVC to the low speed clock selection circuit 26.

[0066] Further, at the timing T5, the low speed clock control circuit 24 supplies the low speed clock selection control signal LSS with the logic level “1” to the low speed clock selection circuit 26 and the high speed clock control circuit 25, so that the low speed clock selection circuit 26 selects the frequency division clock signal DIVC.

[0067] Accordingly, in the embodiment, even when the first crystal oscillator 3 stops the oscillation operation, after the timing T6 shown in FIG. 2, the frequency division clock signal DIVC generated with the frequency division circuit 29 is supplied to the logic circuit unit 1 as the low speed clock signal LSCLK. Further, the oscillation clock signal CRCLK generated with the high speed CR oscillation circuit 28 is supplied to the logic circuit unit 1 as the high speed clock signal HCLK.

[0068] As described above, in the clock signal generation unit 2 in the embodiment, during the oscillation stabilization period TA from the timing T0 when the power is turned on to the timing T2 when the oscillation operation of the low speed crystal oscillation circuit 21 is stabilized, the oscillation clock signal CRCLK generated with the high speed CR oscillation circuit 28 having the oscillation stabilization period TB that is relatively short is supplied to the logic circuit unit 1 as the high speed clock signal HCLK.

[0069] Further, the frequency division circuit 29 is configured to divide the oscillation clock signal CRCLK generated with the high speed CR oscillation circuit 28 by N to generate the frequency division clock signal DIVC having the frequency equal to or substantially similar to the frequency of the oscillation clock signal LCLK generated with the low speed crystal oscillation circuit 21. Then, the frequency division clock signal DIVC is supplied to the logic circuit unit 1 as the low speed clock signal LSCLK.

[0070] In other word, after the power is turned on, until the oscillation operation of the low speed crystal oscillation circuit 21 is stabilized, the oscillation clock signal CRCLK, which is generated with the high speed CR oscillation circuit 28 as the high speed clock signal HCLK is divided by N to generate the frequency division clock signal DIVC having the lower frequency. Then, the frequency division clock signal DIVC is supplied to the logic circuit unit 1 as the low speed clock signal LSCLK. Accordingly, in the logic circuit unit 1, it is possible to reduce the startup time of the circuit operated with only the low speed clock signal LSCLK, or both the low speed clock signal LSCLK and the high speed clock signal HCLK.

[0071] Further, in the clock signal generation unit 2 in the embodiment, after the timing T2 when the oscillation operation of the low speed crystal oscillation circuit 21 is stabilized, the oscillation clock signal LCLK generated with the low speed crystal oscillation circuit 21 is supplied to the logic circuit unit 1 as the low speed clock signal LSCLK.

[0072] Further, in the clock signal generation unit 2 in the embodiment, when the low speed crystal oscillation circuit 21 accidently stops generating the oscillation clock signal LCLK (at the timing T5), the high speed CR oscillation circuit 28 and the frequency division circuit 29 are started one again. Then, the operation is automatically switched (at the timing T6), so that the frequency division clock signal DIVC generated with the frequency division circuit 29 is supplied to the logic circuit unit 1 as the low speed clock signal LSCLK, and the oscillation clock signal CRCLK generated with the high speed CR oscillation circuit 28 is supplied to the logic circuit unit 1 as the high speed clock signal HCLK.

[0073] Accordingly, even when the first crystal oscillator 3 externally connected to the LSI for generating the low speed clock signal LSCLK and the second crystal oscillator 4 externally connected to the LSI for generating the high speed clock signal HCLK accidently stop due to the external disturbance, it is possible to continuously supply the low speed clock signal LSCLK and the high speed clock signal HCLK to the logic circuit unit 1.

[0074] A second embodiment of the present invention will be explained next. FIG. 3 is a block diagram showing an internal configuration of an LSI with a clock signal generation circuit disposed therein according to the second embodiment of the present invention.

[0075] As shown in FIG. 3, the clock signal generation unit 2 includes a reference clock selection circuit 30. Other components of the clock signal generation unit 2 are similar to those of the clock signal generation unit 2 shown in FIG. 1. In the following description, an operation of the clock signal generation unit 2, especially an operation of the reference clock selection circuit 30, will be mainly explained.

[0076] In the second embodiment, the reference clock selection circuit 30 is configured to select one indicated with the low speed clock selection control signal LSS from the oscillation clock signal LCLK supplied from the low speed crystal oscillation circuit 21 and the frequency division clock signal DIVC supplied from the frequency division circuit 29. Further, the reference clock selection circuit 30 is configured to supply the selected one to the high speed PLL oscillation circuit 23 as a reference oscillation clock signal RCLK.

[0077] In the second embodiment, with the reference oscillation clock signal RCLK as the reference clock, the high speed PLL oscillation circuit 23 is configured to generate the oscillation clock signal PLLCLK having a frequency higher than that of the reference oscillation clock signal RCLK and a phase synchronized with that of the reference oscillation clock signal RCLK. Then, the high speed PLL oscillation circuit 23 supplies the oscillation clock signal PLLCLK to the high speed clock selection circuit 27.

[0078] An operation of the clock signal generation unit 2 shown in FIG. 3 will be explained with reference to FIG. 4. FIG. 4 is a time chart showing the operation of the clock signal generation circuit according to the second embodiment of the present invention.

[0079] As shown in FIG. 4, when the power is turned on at the timing T0, the startup control circuit 20 supplies the oscillation enable signal EN1 with the logic level “1” to the low speed crystal oscillation circuit 21 and the high speed PLL oscillation circuit 23, so that the low speed crystal oscillation circuit 21 and the high speed PLL oscillation circuit 23 start the oscillation operation. Further, the startup control circuit 20 supplies the oscillation enable signal EN1 with the logic level “0” to the high speed crystal oscillation circuit 22, so that the high speed crystal oscillation circuit 22 stops the oscillation operation.

[0080] According to the oscillation enable signal EN1 with the logic level “1” supplied at the timing T0, the low speed crystal oscillation circuit 21 starts the oscillation operation. At the timing T2 after the oscillation stabilization period TA, the low speed crystal oscillation circuit 21 becomes the state of transmitting the oscillation clock signal LCLK. Accordingly, the period between the timing T0 and the timing T2, the low speed crystal oscillation circuit 21 does not generate the oscillation clock signal LCLK.

[0081] Accordingly, during the period, the low speed clock control circuit 24 supplies the oscillation enable signal EN4 with the logic level “1” to the high speed CR oscillation circuit 28, so that the high speed CR oscillation circuit 28 starts the oscillation operation. As a result, the high speed CR oscillation circuit 28 starts the oscillation operation. At the timing T1 after the oscillation stabilization period TB, the high speed CR oscillation circuit 28 becomes the state of transmitting the oscillation clock signal CRCLK. At this moment, the frequency division circuit 29 supplies the frequency division clock signal DIVC obtained through dividing the oscillation clock signal CRCLK by N to the low speed clock selection circuit 26 and the reference clock selection circuit 30.

[0082] Further, in the second embodiment, when the power is turned on at the timing T0, the startup control circuit 20 supplies the reset pulse signal RS to the low speed clock control circuit 24 and the high speed clock control circuit 25. According to the reset pulse signal RS, the high speed clock control circuit 25 supplies the high speed clock selection control signal HCS to the high speed clock selection circuit 27, so that the high speed clock selection circuit 27 selects the oscillation clock signal CRCLK, and the low speed clock control circuit 24 supplies the low speed clock selection control signal LSS with the logic level “1” to the low speed clock selection circuit 26, so that the low speed clock selection circuit 26 selects the frequency division clock signal DIVC.

[0083] Accordingly, as shown in FIG. 4, after the timing T1, the oscillation clock signal CRCLK generated with the high speed CR oscillation circuit 28 is supplied to the logic circuit unit 1 as the high speed clock signal HCLK, and the frequency division clock signal DIVC generated with the frequency division circuit 29 is supplied to the logic circuit unit 1 as the low speed clock signal LSCLK.

[0084] It is noted that, in the second embodiment, the high speed PLL oscillation circuit 23 is not started at this moment as shown in FIG. 4. Alternatively, the high speed PLL oscillation circuit 23 may be started through a software processing, so that the high speed clock selection circuit 27 selects the oscillation clock signal PLLCLK generated with the high speed PLL oscillation circuit 23.

[0085] In the second embodiment, it is supposed that an external noise such as an electromagnetic wave, vibration, and the like, or an external disturbance effect such as moisture, dust, a foreign matter, and the like occurs at the timing T5. Associated with the external noise or the external disturbance effect, when the first crystal oscillator 3 externally connected to the LSI stops the oscillation operation, the low speed crystal oscillation circuit 21 stops the oscillation operation as well. Accordingly, the low speed crystal oscillation circuit 21 stops generating the oscillation clock signal LCLK.

[0086] As shown in FIG. 4, at the timing T5, when the low speed clock control circuit 24 detects that the low speed crystal oscillation circuit 21 stops supplying the oscillation clock signal LCLK, the low speed clock control circuit 24 supplies the oscillation enable signal EN4 with the logic level “1”, so that the high speed CR oscillation circuit 28 starts the oscillation operation. Accordingly, the high speed CR oscillation circuit 28 starts the oscillation operation. At the timing T6 after the oscillation stabilization period TB, the high speed CR oscillation circuit 28 becomes the state of transmitting the oscillation clock signal CRCLK. At this moment, the frequency division circuit 29 divides the oscillation clock signal CRCLK by N to generate the frequency division clock signal DIVC having the frequency equal to or substantially similar to the frequency of the oscillation clock signal LCLK generated with the low speed crystal oscillation circuit 21. Then, the frequency division circuit 29 supplies the frequency division clock signal DIVC to the low speed clock selection circuit 26.

[0087] Further, at the timing T5, the low speed clock control circuit 24 supplies the low speed clock selection control signal LSS with the logic level “1” to the low speed clock selection circuit 26 and the reference clock selection circuit 30, so that the low speed clock selection circuit 26 selects the frequency division clock signal DIVC. Accordingly, the high speed PLL oscillation circuit 23 starts the oscillation operation with the frequency division clock signal DIVC as the reference clock. At the timing T6 after the oscillation stabilization period TC, the high speed PLL oscillation circuit 23 becomes the state of transmitting the oscillation clock signal PLLCLK.

[0088] Accordingly, in the second embodiment, even when the first crystal oscillator 3 or the second crystal oscillator 4 stops the oscillation operation due to the external disturbance effect and the like, after the timing T6 shown in FIG. 2, the frequency division clock signal DIVC generated with the frequency division circuit 29 is supplied to the logic circuit unit 1 as the low speed clock signal LSCLK. Further, the oscillation clock signal PLLCLK generated with the high speed PLL oscillation circuit 23 is supplied to the logic circuit unit 1 as the high speed clock signal HCLK.

[0089] In the second embodiment, the high speed clock selection circuit 27 is configured to select the oscillation clock signal PLLCLK, the oscillation clock signal CRCLK, the frequency division clock signal DIVC, and the oscillation clock signal LCLK depending on whether the low speed crystal oscillation circuit 21 supplies the oscillation clock signal LCLK or not. Alternatively, the low speed clock control circuit 24 and the high speed clock selection circuit 27 may be configured to select the oscillation clock signal PLLCLK, the oscillation clock signal CRCLK, the frequency division clock signal DIVC, and the oscillation clock signal LCLK depending on whether the high speed crystal oscillation circuit 22 supplies the oscillation clock signal HOCLK or not.

[0090] Further, in the second embodiment, the low speed clock control circuit 24 is configured to detect that the low speed crystal oscillation circuit 21 stops generating the oscillation clock signal LCLK, and select the low speed clock signal LSCLK. Alternatively, software may be executed detect that the low speed crystal oscillation circuit 21 stops generating the oscillation clock signal LCLK, and select the low speed clock signal LSCLK.

[0091] In the first embodiment and the second embodiment, the operation of the clock signal generation unit 2 is explained with reference to FIGS. 2 and 4 immediately after the power is turned on as an example. The operation of the clock signal generation unit 2 may be performed when an entire portion or a part of the logic circuit unit 1 is stopped and returned to the normal operation in the state that the power is turned on.

[0092] In the first embodiment and the second embodiment, the LSI shown in FIGS. 1 and 3 includes the first crystal oscillator 3 and the second crystal oscillator 4 disposed externally as the crystal oscillator. Alternatively, the LSI shown in FIGS. 1 and 3 may include a ceramic oscillator. In this case, instead of the low speed crystal oscillation circuit 21, a low speed ceramic oscillation circuit is provided, and instead of the high speed crystal oscillation circuit 22, a high speed ceramic oscillation circuit is provided

[0093] The disclosure of Japanese Patent Application No. 2011-074838, filed on Mar. 30, 2011, is incorporated in the application by reference.

[0094] While the invention has been explained with reference to the specific embodiments of the invention, the explanation is illustrative and the invention is limited only by the appended claims.