SINGLE-TO-DIFFERENTIAL CONVERSION CIRCUIT

[0001] This application claims priority to Taiwanese Patent Application No. 100111572, filed on Apr. 1, 2011, the disclosure of which is incorporated herein by reference.

[0002] 1. Field of the Invention

[0003] The invention relates to a single-to-differential conversion circuit, more particularly to a single-to-differential conversion circuit with gain compensation.

[0004] 2. Description of the Related Art

[0005] In a telecommunication system, the receiver usually needs to use a single-to-differential conversion circuit to convert a received radio frequency (RF) signal into a differential signal having a first differential voltage and a second differential voltage. Under ideal conditions, the first and second differential voltages should be the same in magnitude, and 180° out of phase.

[0006] Looking at the current technology of the related circuit and the small signal model for a single-to-differential conversion circuit as shown in FIGS. 1 and 2, a simple description is provided as follows:

[0007] After a first transistor M₁ receives a RF signal, under ideal conditions and when the equivalent impedances Z_gs1, Z_gs2, Z₃ (where Z_gs1 is the equivalent impedance between the gate and source of the first transistor M₁, Z_gs2 is the equivalent impedance between the gate and source of a second transistor M₂, and Z₃ is a third equivalent impedance) are sufficiently large in magnitude (or the equivalent impedances Z_gs1, Z_gs2, and Z₃ approach positive infinity), and when the load equivalent impedance Z_L is sufficiently small in magnitude, the single-to-differential conversion circuit can output a first differential voltage V_o1 and a second differential voltage V_o2 as follows:

$V_{o1}=-g_m\left(\frac{V_1}{2}\right)Z_1$ $V_{o1}=g_m\left(\frac{V_1}{2}\right)Z_2$

[0008] Where Z₁ is a first equivalent impedance, Z₂ is a second equivalent impedance, V₁ is an input voltage, and g_m is a transconductance coefficient of the first transistor M₁ (or the second transistor M₂). In the implementations of the current technology, the first and second equivalent impedances Z₁, Z₂ are implemented by resistors, and the third equivalent impedance Z₃ is implemented by resistors or transistors.

[0009] Therefore, under ideal conditions, when the first equivalent impedance Z₁ is equal to the second equivalent impedance Z₂, the single-to-differential conversion circuit will output a group of differential voltages including the first differential voltage V_o1 and the second differential voltage V_o2. When the first differential voltage V_o1 and the second differential voltage V_o2 are equal, the phase difference is 180°.

[0010] However, during the operation of the single-to-differential conversion circuit described above, the input voltage V₁ is usually attenuated when transmitted to a node X because the equivalent impedance Z_gs1 between the gate and the source of the first transistor M₁, the equivalent impedance Z_gs2 between the gate and the source of the second transistor M₂, and/or the third equivalent impedance Z₃ are not large enough. The magnitude of the voltage V_x at the node X is thus smaller than half the input voltage V₁, and the gate-source voltage V_gs1 of the first transistor M₁ is therefore not equal to the gate-source voltage V_gs2 of the second transistor M₂. The gain mismatch of the first and second differential voltages V_o1, V_o2 in the set of differential signals will result in unbalanced set of differential signals. Therefore, it is worth looking into efficiently solving the gain mismatch problem when designing the receiver circuit of a telecommunication system.

[0011] Therefore, an object of the present invention is to provide a single-to-differential conversion circuit with gain compensation.

[0012] According to one embodiment of the present invention, a single-to-differential conversion circuit of the present invention comprises a first transistor, a second transistor, and a transforming unit. Both of the first and second transistors has a first terminal, a second terminal, and a third terminal. The third terminal of the first transistor receives an input signal.

[0013] The transforming unit has a first induction element, a second induction element, and a third induction element. The first induction element has a first inductive terminal coupled to the second terminal of the first transistor, and a second inductive terminal to be coupled to a voltage source. The second induction element has a first inductive terminal to be coupled to the voltage source, and a second inductive terminal coupled to the second terminal of the second transistor. The third induction element has a first inductive terminal coupled to the first terminal of the first transistor and the first terminal of the second transistor, and a second inductive terminal to be coupled to ground.

[0014] The first induction element and the third induction element undergo a first electrical coupling according to a first coupling parameter. The second induction element and the third induction element undergo a second electrical coupling according to a second coupling parameter.

[0023] FIG. 3 shows the preferred embodiment of a single-to-differential conversion circuit of the present invention that comprises a first transistor 11, a second transistor 12, and a transforming unit 13.

[0024] The first transistor 11 has a first terminal, a second terminal, and a third terminal which receives an input signal. The second transistor 12 has a first terminal, a second terminal and a third terminal. In the present embodiment, the first and second transistors 11, 12 are both N-type metal oxide semiconductor-field effect transistors. The first terminals of both first and second transistors 11, 12 are source terminals. The second terminals of both first and second transistors 11, 12 are drain terminals. The third terminals of both first and second transistors 11, 12 are gate terminals.

[0025] The transforming unit 13 has a first induction element 131, a second induction element 132 and a third induction element 133. The first induction element 131 has a first inductive terminal electrically coupled to the second terminal of the first transistor 11, and a second inductive terminal electrically coupled to a voltage source V_DD. The second induction element 132 has a first inductive terminal electrically coupled to the voltage source V_DD, and a second inductive terminal electrically coupled the second terminal of the second transistor 12. The third induction element 133 has a first inductive terminal electrically coupled to the first terminal of the first transistor 11 and the first terminal of the second transistor 12 (this connection node is referred to as node X), and a second inductive terminal electrically coupled to a ground terminal. The first induction element 131 and the third induction element 133 undergo a first electrical coupling according to a coupling parameter. The second induction element 132 and the third induction element 133 undergo a second electrical coupling according to the coupling parameter.

[0026] For simplicity, FIG. 4 is the equivalent circuit diagram of FIG. 3. Two fourth induction elements 134 are the equivalence of the third induction element 133 and the two fourth induction elements 134 are electrically coupled in series. Every fourth induction element 134 has an inductance value L₄ twice that of the inductance value L₃ of the third induction element 133 (L₄=2×L₃).

[0027] The following description refers to FIG. 4 and describes the relevant theoretical foundation of the preferred embodiment of the present invention.

[0028] With the preferred embodiment operating at a first cycle (the positive half cycle of the input signal), because an alternating current flows via the fourth induction elements 134, according to the coupling relationship of the transforming unit 13, there is created a first induction current I_k at the first and second induction elements 131, 132, and the current direction is flowing out of the first induction element 131, calculated by:

$I_k=I_4·K·\sqrt{\frac{2L_3}{L_0}}$

[0029] wherein I₄ is the current flowing through the fourth induction elements 134, K is the coupling coefficient, and L₀=L₁=L₂, which means the first and second induction elements 131, 132 have the inductance values L₁, L₂ respectively, that are equal to each other.

[0030] When the preferred embodiment is operating at a second cycle (the negative half cycle of the input signal), there is created a second induction current I_k′ at the first and second induction elements 131, 132, where the second induction current I_k′ is equal to the first induction current I_k. The current direction of the second induction current I_k′ is flowing into the second induction element 132.

[0031] From the above, assuming the first transistor 11 has the third terminal voltage V₁=V_IN, and the second transistor 12 has the third terminal voltage V₂=0, a first differential voltage V_o1 (from the first terminal of the first induction element) and a second differential voltage V_o2 (from the second terminal of the second induction element) can be calculated as follows:

$\begin{array}{c}{V}_{o1}=-\left(g_{m1}V_{\mathrm{gs}1}-I_k\right)Z_{L1}\\ =-\left(g_{m1}V_{\mathrm{gs}1}-I_4·K·\sqrt{\frac{2L_3}{L_0}}\right)Z_{L0}\\ =-\left[g_{m1}\left(V_{\mathrm{IN}}-V_X\right)-I_4·K·\sqrt{\frac{2L_3}{L_0}}\right]Z_{L0}\end{array}$ $\begin{array}{c}{V}_{o2}=-\left(g_{m2}V_{\mathrm{gs}2}+I_k\right)Z_{L2}\\ =-\left(g_{m2}V_{\mathrm{gs}2}-I_4·K·\sqrt{\frac{2L_3}{L_0}}\right)Z_{L0}\\ =-\left[g_{m2}\left(-V_X\right)+I_4·K·\sqrt{\frac{2L_3}{L_0}}\right]Z_{L0}\end{array}$

[0032] where g_m1, g_m2 are the transconductance coefficients of the first and second transistors 11, 12, respectively. V_gs1 is the voltage between the third and first terminals of the first transistor 11. V_gs2 is the voltage between the third and first terminals of the second transistor 12. I_k is the first inductive current. Z_L1/Z_L2 are the equivalent impedances of the first and second induction elements 131, 132, and Z_L1=Z_L2=Z_L0. V_X is the voltage at the node X.

[0033] Assuming g_m1=g_m2=g_m, then the voltage V_X at the node X is as follows:

$V_X=\frac{\left(g_m+Y_{\mathrm{gs}1}\right)·Z_{L3}}{1+\left(2g_m+Y_{\mathrm{gs}1}+Y_{\mathrm{gs}2}\right)·Z_{L3}}·V_{\mathrm{IN}}=A·V_{\mathrm{IN}}$

[0034] and the current I₄ flowing through the fourth induction elements 134 is as follows:

$\begin{array}{c}{I}_4=g_m\left(V_{\mathrm{IN}}\right)+\left(V_{\mathrm{IN}}-{\mathrm{AV}}_{\mathrm{IN}}\right)Y_{\mathrm{gs}1}+\left(-{\mathrm{AV}}_{\mathrm{IN}}\right)Y_{\mathrm{gs}2}\\ =\left[g_m+\left(1-A\right)Y_{\mathrm{gs}1}+\left(-A\right)Y_{\mathrm{gs}2}\right]V_{\mathrm{IN}}\end{array}$

[0035] where Y_gs1 is the equivalent reactance between the third terminal and the first terminal of the first transistor 11. Y_gs2 is the equivalent reactance between the third terminal and the first terminal of the second transistor 12. Z_L3 is the equivalent impedance of the third induction element 133. A is a matching coefficient.

[0036] Therefore, according to the above equations, the relationship of the first and second differential voltages V_o1, V_o2 to the input voltage V_IN can be obtained as follows:

$\frac{V_{o1}}{V_{\mathrm{IN}}}=-\left\{g_m\left(1-A\right)-\left[g_m+\left(1-A\right)Y_{\mathrm{gs}1}+\left(-A\right)Y_{\mathrm{gs}2}\right]·K·\sqrt{\frac{2L_3}{L_0}}\right\}Z_{L0}$ $\frac{V_{o2}}{V_{\mathrm{IN}}}=-\left\{g_m\left(-A\right)+\left[g_m+\left(1-A\right)Y_{\mathrm{gs}1}+\left(-A\right)Y_{\mathrm{gs}2}\right]·K·\sqrt{\frac{2L_3}{L_0}}\right\}Z_{L0}$

[0037] According to the above description, when there is a gain mismatch in the single-to-differential conversion circuit of the preferred embodiment (i.e., the equivalent impedance Z_gs1 between the third and first terminals of the first transistor 11, the equivalent impedance Z_gs2 between the third and first terminals of the second transistors 12, and/or the equivalent impedance Z_L3 of the third induction element 133 are not big enough in magnitude), the matching coefficient A will have a value less than 0.5. If the first to third induction elements 131-133 do not electrically couple (i.e., the coupling coefficient K is 0), then

$\frac{V_{o1}}{V_{\mathrm{IN}}}>\frac{V_{o2}}{V_{\mathrm{IN}}}$

[0038] Therefore, the first differential voltage V_o1 and the second differential voltage V_o2 will not balance.

[0039] If during the design, the coupling coefficient K of the transforming unit 13 is

$K=\frac{g_m}{2\left[g_m+\left(1-A\right)Y_{\mathrm{gs}1}+\left(-A\right)Y_{\mathrm{gs}2}\right]·\sqrt{\frac{2L_3}{L_0}}},$

[0040] the first electrical coupling can decrease the absolute value of the first differential voltage V_o1, and the second electrical coupling can increase the absolute value of the second differential voltage V_o2. The first differential voltage V_o1 and the second differential voltage V_o2 are then equal in magnitude (i.e., the absolute value of both first and second differential voltages V_o1, V_o2 are equal), and 180° out of phase.

[0041] Therefore, the coupling coefficient K of the transforming unit 13 can be used to compensate the gain mismatch of the single-to-differential conversion circuit. There may be some variance during circuit operations and differences in the circuit components. The transconductance coefficient g_m1 of the first transistor 11 may not be equal to the transconductance coefficient g_m2 of the second transistor 12, the inductance L₁ of the first induction element 131 may not be equal to the inductance L₂ of the second induction element 132, and the first and second coupling parameters between the first and second induction elements 131, 132 and the third induction element 133 and the related electrical couplings may be different. However, the present embodiment discloses the method to compensate the gain mismatch problem in the single-to-differential conversion circuit.

[0042] According to the foundation of the above description, if the present embodiment is to be applied to a high frequency situation, for example, anti-collision radar for cars (approximately operating at 77 GHz), an embodiment of the transforming unit 13 of the single-to-differential conversion circuit is shown in FIG. 5, which uses a transmission line model.

[0043] Referring to both FIGS. 3 and 5, a first transmission line section 91 replaces the first induction element 131, a second transmission line section 92 replaces the second induction element 132, and a third transmission line section 93 replaces the third induction element 133. The lengths of the first and second transmission line sections 91, 92 are one eight of the wavelength of the input signal (λ/8). The length of the third transmission line section 93 is one quarter of the wavelength of the input frequency (λ/4). The coupling effect of the first, second and third transmission line sections 91, 92 and 93 can compensate the gain mismatching problem in the single-to-differential conversion circuit.

[0044] If the present embodiment is to be applied to a mid-to-low frequency situation, an embodiment of the transforming unit 13 of the single-to-differential conversion circuit is shown in FIG. 6, which uses a transformer model.

[0045] Referring to both FIGS. 3 and 6, a first loop unit 81 replaces the first induction unit 131 and the second induction unit 132. A second loop unit 82 replaces the third induction unit 133. The first loop unit 81 is disposed to surround the second loop unit 82 in a co-planar manner. The second loop unit 82 is spaced apart from the first loop unit 81 by a first distance d. The distance d influences the coupling parameter K, and the shorter the distance d, the bigger will be the coupling parameter K. Therefore, during the design, the adjustment of the first distance d changes the coupling parameter K to compensate the gain mismatching problem of the single-to-differential conversion circuit.

[0046] Referring to both FIG. 3 and FIG. 7, which is similar to the implementation of FIG. 6, but where the first loop unit 81 is disposed to surround the second loop unit 82 in a non-coplanar manner, the second loop unit 82 is spaced apart from the first loop unit 81 by a second distance b. The distance b influences the coupling parameter K. The shorter the distance b, the bigger will be the coupling parameter K. Therefore, during the design, the adjustment of the second distance b can change the coupling parameter K to compensate the gain mismatching problem of the single-to-differential conversion circuit.

[0047] On an extra note, FIG. 5 to FIG. 7 are three derivations of the transforming unit 13 in the single-to-differential conversion circuit when used in different products. The invention is not limited to these embodiments.

[0048] Worth noting is that the first induction unit 131 and the third induction unit 133 can also undergo a first electrical coupling according to a first coupling parameter, and the second induction unit 132 and the third induction unit 133 can also undergo a second electrical coupling according to a second coupling parameter. When designing, the first and second coupling parameters can be changed to compensate for the gain mismatching problem of the single-to-differential conversion circuit.

[0049] According to the above description, the embodiments can use electrical coupling to compensate a gain mismatching problem in a single-to-differential conversion circuit, thereby achieving the goal of the present invention.

[0050] While the present invention has been described in connection with what are considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.