SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

[0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2011-004954, filed Jan. 13, 2011, the entire contents of which are incorporated herein by reference.

[0002] Embodiments described herein relate generally to a semiconductor memory device and a method of manufacturing the same.

[0003] As a technique of increasing the density of a memory without depending on lithography, structures such as a structure in which a one-time-programmable (OTP) element is sandwiched between multiple interconnection layers and a structure in which a plurality of NAND flash memory layers are formed by repeating epitaxial growth of silicon films have been proposed. However, these structures have the problem that the number of times of lithography increases as the number of stacked layers increases. Therefore, a collectively processed, three-dimensionally stacked memory has been proposed as a technique replacing these structures.

[0004] In this three-dimensionally stacked memory, a hole (memory hole) is formed at once through a plurality of electrodes stacked on a semiconductor substrate, and a memory film is formed on the inner walls of the hole. After that, the hole is filled with a polysilicon film (silicon pillar). Consequently, a memory string including a plurality of memory elements connected in series in the stacking direction can be formed at one time. This makes it possible to implement a memory for which the number of lithography steps hardly increases even when the number of layers to be stacked is increased.

[0005] In the three-dimensionally stacked memory as described above, the insulating film (memory film) of the memory element is formed on the inner walls of the hole before the formation of a polysilicon film serving as a channel. After that, only the insulating film formed on the bottom of the hole must be removed in order to supply an electric current to the memory string by improving the connection between the polysilicon film and, for example, a source line (for example, polysilicon) positioned below the polysilicon film. This imposes the technical limitation that it is necessary to use a memory film configuration that can withstand processing with diluted hydrofluoric acid to remove the insulating film from the bottom. When using, for example, the multilevel-cell technology as a method of further increasing the density of the three-dimensionally stacked memory, this limitation increases the difficulty in development of the memory film configuration, so the situation is not necessarily favorable.

[0006] To improve this situation, a three-dimensionally stacked memory using a U-shaped silicon pillar as a memory string has been proposed. This U-shaped silicon pillar includes a pair of columnar portions and a connecting portion for connecting the lower ends of these columnar portions. The upper portion of one of the pair of columnar portions is connected to a bit line, and the upper portion of the other columnar portion is connected to a source line. That is, there is no polysilicon-polysilicon contact on the bottom of a memory hole, and this obviates the removal of an insulating film from the bottom. This can increase the degree of freedom of the memory film configuration.

[0007] On the other hand, to reduce the chip occupation ratio of the three-dimensionally stacked memory cell array as described above and a control circuit for controlling the array, a technique of forming the control circuit on a semiconductor substrate immediately below the memory cell array has been proposed. If the control circuit is formed below the memory cell array, however, the control circuit, for example, a sense amplifier and a bit line interconnection must be connected by a contact plug formed in a memory cell array end portion. That is, the bit line interconnection is connected to a bit line extension formed below the memory cell array via the contact plug formed in the memory cell array end portion, and the bit line extension is connected to, for example, a transistor (sense amplifier) formed on the semiconductor substrate.

[0008] This structure poses the problems that, for example, a fine interconnection layer (the bit line extension) equivalent to a bit line is necessary below the memory cell array, a region having a considerable size is necessary in the memory cell array periphery in order to form a deep contact, and the bit line practically gets longer to increase the bit line capacitance, thereby affecting the operating speed.

[0018] In general, according to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes a plurality of memory cells for storing data. The single-crystal semiconductor layer is formed on an insulating layer on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the insulating layer and memory cell array portion. The circuit portion is formed on the single-crystal semiconductor layer. The Ge concentration in the lower portion of the single-crystal semiconductor layer on the memory cell array portion is higher than that in the upper portion of the single-crystal semiconductor layer.

[0019] A semiconductor memory device according to the first embodiment will be explained below with reference to FIGS. 1, 2, 3, 4, 5, 6, and 7. The first embodiment is an example in which a single-crystal semiconductor layer in which a control circuit is to be formed is formed immediately above a memory cell array.

[0020] The structure of the semiconductor memory device according to the first embodiment will be explained below with reference to FIGS. 1, 2, and 3.

[0021] FIG. 1 is a sectional view taken along the row and column directions of the semiconductor memory device according to the first embodiment. FIG. 2 is a perspective view of a memory cell string shown in FIG. 1. FIG. 3 is an enlarged sectional view of the memory cell string.

[0022] As shown in FIG. 1, the semiconductor memory device according to this embodiment includes a memory cell array portion A and circuit portion B. Note that the memory cell array portion A indicates a layer in which a memory cell array is formed, and the circuit portion B indicates a layer in which circuits (for example, a control circuit) are formed.

[0023] In the memory cell array portion A as shown in FIG. 2, a plurality of memory cell strings 200 each including a U-shaped silicon pillar SP are formed above a semiconductor substrate (Si substrate) 100. The plurality of memory cell strings 200 are arranged in a matrix in the row and column directions.

[0024] Each memory cell string 200 includes a plurality of memory cell transistors MTr, and two selection transistors (a drain-side selection transistor SDTr and source-side selection transistor SSTr) formed on the two ends of the plurality of memory cell transistors MTr.

[0025] The plurality of memory cell transistors MTr are formed at the intersections of the U-shaped silicon pillar SP and a plurality of control gates CG (word lines), and have current paths connected in series in a stacking direction (a direction perpendicular to the semiconductor substrate 100). As shown in FIG. 3, each memory cell transistor MTr includes a memory film 300 between the U-shaped silicon pillar SP and control gate CG. The memory film 300 includes a tunnel insulating film 303, charge storage layer 302, and block insulating film 301 formed in this order around the U-shaped silicon pillar SP.

[0026] The drain-side selection transistor SDTr is formed at the intersection of the U-shaped silicon pillar SP and a drain-side selection gate SGD. The source-side selection transistor SSTr is formed at the intersection of the U-shaped silicon pillar SP and a source-side selection gate SGS. As shown in FIG. 3, the drain-side selection transistor SDTr and source-side selection transistor SSTr each have the same structure as that of the memory cell transistor MTr.

[0027] Also, to decrease the resistances of the control gates CG and selection gates SG (drain-side selection gate SGD and source-side selection gate SGS), a silicide layer 101 is formed on the end face of each gate in the column direction.

[0028] The U-shaped silicon pillar SP is formed into a U-shape in a section in the column direction. The U-shaped silicon pillar SP includes a pair of columnar portions extending in the stacking direction, and a connecting portion formed to connect the lower ends of the pair of columnar portions. The connecting portion is formed in a back gate BG, and forms a back gate transistor BGTr. Also, the U-shaped silicon pillar SP is formed such that a straight line connecting the central axes of the pair of columnar portions is parallel to the column direction. Furthermore, the U-shaped silicon pillars SP are arranged in a matrix in a plane taken along the row and column directions. In addition, as shown in FIG. 3, the U-shaped silicon pillar SP has a hollow H1, and the hollow H1 is filled with an insulator 304.

[0029] The plurality of control gates CG are stacked above the back gate BG, and arranged to perpendicularly intersect the columnar portions of the U-shaped silicon pillars SP. Each control gate CG extends along the row direction. Also, each control gate CG is shared by two adjacent columnar portions (two central columnar portions) of four columnar portions of two memory cell strings 200 adjacent to each other in the column direction. Furthermore, the plurality of control gates CG have a staircase shape in the end portion in the row direction. In other words, the end portion of each control gate CG projects when viewed from the upper surface. That is, an interconnection layer M1 is connected to the projecting upper surface of each control gate CG via a contact plug 104.

[0030] The back gate BG is formed below the lowermost control gates CG. The back gate BG two-dimensionally extends in the row and column directions so as to cover the connecting portions of the U-shaped silicon pillars SP.

[0031] The drain-side selection gate SGD and source-side selection gate SGS are formed above the uppermost control gates CG. The drain-side selection gate SGD and source-side selection gate SGS extend in the row direction. The drain-side selection gate SGD and source-side selection gate SGS are formed to intersect the columnar portions of the U-shaped silicon pillar SP, and formed by line-and-space as they are insulated and isolated from each other in the column direction. The upper surface of the end portion of the selection gate SG in the row direction is connected to interconnection layer M1 via a contact plug 103.

[0032] Source lines SL are formed above the source-side selection gates SGS. Each source line SL is shared by two adjacent columnar portions of four columnar portions of two memory cell strings 200 adjacent to each other in the column direction. The source lines SL extend in the row direction, and are formed by line-and-space as they are insulated and isolated from each other in the column direction.

[0033] A plurality of bit lines BL are formed above the source line SL. The bit lines BL extend in the column direction, and are formed by line-and-space as they are insulated and isolated from each other in the row direction.

[0034] In this embodiment, the circuit portion B is formed above the memory cell array portion A. The circuit portion B includes control circuit transistors Tr formed on a single-crystal semiconductor layer 109.

[0035] The single-crystal semiconductor layer 109 is formed on an isolation insulating layer 105 formed on the memory cell array portion A. The isolation insulating layer 105 is, for example, a TEOS film, and has a film thickness of about 500 nm. Also, shallow trench isolation (STI) 110 for element isolation consisting of, for example, a silicon oxide film is formed in the single-crystal semiconductor layer 109. Details of the single-crystal semiconductor layer 109 will be described later.

[0036] The control circuit transistors Tr are formed outside the STI 110 regions on the single-crystal semiconductor layer 109, and form, for example, driving circuits for applying voltages to individual electrodes in the memory cell array portion A, and a control circuit for controlling these circuits. One of the source and drain of the control circuit transistor Tr is connected to the bit line BL (interconnection layer M1) via an interconnection layer M2 and contact plug 112, and the other is connected to an interconnection layer M3 via a contact plug 113, interconnection layer M2, and a contact plug 114. Also, one of the source and drain of another control circuit transistor Tr is connected to interconnection layer M1 connected to the control gate CG, via interconnection layer M2 and contact plug 112, and the other is connected interconnection layer M3 via contact plug 113, interconnection layer M2, and contact plug 114.

[0037] Contact plugs 112 are formed in contact holes reaching interconnection layers M1 through the single-crystal semiconductor layer 109 and isolation insulating layer 105. That is, contact plugs 112 are formed immediately above interconnection layers M1, and connect the memory cell array portion A and the circuit portion B positioned immediately above the memory cell array portion A. Furthermore, to prevent a shortcircuit in the single-crystal semiconductor layer 109, a sidewall insulating film 111 consisting of a silicon nitride film or the like is formed on the side surfaces of the contact holes.

[0038] The single-crystal semiconductor layer 109 of this embodiment includes a first semiconductor layer 107 and second semiconductor layer 108, and has a film thickness of about 2 μm.

[0039] The first semiconductor layer 107 is, for example, a single-crystal silicon germanium (SiGe) layer formed on the isolating insulating layer 105. The composition ratio of the single-crystal SiGe layer 107 is Si_1-XGe_X (X≧0.5, preferably, X≧0.75). That is, the germanium concentration in the single-crystal SiGe layer 107 is 50 atm % or more. The single-crystal SiGe layer 107 is also formed in a crystal connecting hole 106 extending through the isolation insulating layer 105 and memory cell array portion A and reaching the Si substrate 100, and is connected to the Si substrate 100. Thus, the first semiconductor layer 107 is connected to the Si substrate 100 as a single crystal via the crystal connecting hole 106, and hence is formed into a single crystal by succeeding the crystal orientation of the Si substrate 100.

[0040] The second semiconductor layer 108 is, for example, a single-crystal silicon (Si) layer formed on the first semiconductor layer 107. The single-crystal Si layer 108 is grown by using the single-crystal first semiconductor layer 107 as a crystal nucleus, and hence is formed into a single crystal by succeeding the crystal orientation of the Si substrate 100 and that of the first semiconductor layer 107. The Ge concentration in the second semiconductor layer 108 is set lower than that of the first semiconductor layer 107. That is, in the single-crystal semiconductor layer 109, the Ge concentration in the upper portion is lower than that in the lower portion. Note that the second semiconductor layer 108 is not limited to an Si layer and may also be an SiC or SiGe layer, but it is desirably an Si or SiC layer in order to improve the breakdown voltage characteristic. That is, in the single-crystal semiconductor layer 109, the Si concentration in the upper portion is desirably higher than that in the lower portion, and the C concentration in the upper portion is desirably higher than that in the lower portion. This makes it possible to improve the crystallinity and breakdown voltage characteristic of the control circuit element formation surface.

[0041] Note that the two-layered structure including the first semiconductor layer 107 and second semiconductor layer 108 has been explained as an example of the single-crystal semiconductor layer 109, but the present embodiment is not limited to this. That is, the single-crystal semiconductor layer 109 can also be formed as a gradation layer in which the Ge concentration gradually (moderately) decreases from the lower portion toward the upper portion, without any interface between the first semiconductor layer 107 and the second semiconductor layer 108 in the single-crystal semiconductor layer 109. This can reduce stress resulting from the difference between the crystal lattice constants.

[0042] Note also that the crystal connecting hole 106 is desirably formed to extend through the memory cell array portion A having a film thickness of, for example, 1 μm or more, and desirably formed for every few mm in the row and column directions. Since this increases the contact area between the crystal connecting holes 106 and the Si substrate 100, the single-crystal characteristic of the single-crystal semiconductor layer 109 can be improved.

[0043] Furthermore, the crystal connecting hole 106 is not limited to a column or square pillar, and can also be formed as a slit extending along the row or column direction. In addition, although the crystal connecting hole 106 is formed in the end portion of the memory cell array portion A in the row direction in FIG. 1, it may also be formed in the central portion of the memory cell array A so as not to be connected to each electrode and the like.

[0044] A method of manufacturing the semiconductor memory device according to the first embodiment will be explained below with reference to FIGS. 4, 5, 6, and 7.

[0045] FIGS. 4, 5, 6, and 7 are sectional views of manufacturing steps taken along the row and column directions of the semiconductor memory device according to the first embodiment. Note that in this embodiment, various well known methods are applicable as a method of manufacturing the memory cell array portion A in the three-dimensionally stacked memory. In this embodiment, therefore, a method of manufacturing the circuit portion B positioned above the memory cell array portion A will mainly be explained.

[0046] First, as shown in FIG. 4, a memory cell array portion A is formed on an Si substrate 100 by a well known method. More specifically, a back gate BG, control gates CG, selection gates SG, memory films 300, and U-shaped silicon pillars SP are formed above the Si substrate 100, thereby forming a back gate transistor BGTr, memory cell transistors MTr, source-side selection transistors SSTr, and drain-side selection transistors SDTr.

[0047] Then, a source line SL (interconnection layer M0) to be connected on the U-shaped silicon pillars SP on the source side, contact plugs 102 to be connected to the U-shaped silicon pillars SP on the drain side, contact plugs 103 to be connected to the selection gates SG, and contact plugs 104 to be connected to the control gates CG are formed. After that, bit lines BL to be connected to contact plugs 102, and interconnection layers M1 to be connected to contact plugs 103 and 104 are formed. Thus, the memory cell array portion A is formed.

[0048] Subsequently, a 500-nm-thick isolation insulating layer 105 consisting of a TEOS film is formed on the entire surface of the memory cell array portion A by, for example, chemical vapor deposition (CVD).

[0049] As shown in FIG. 5, a crystal connecting hole 106 is formed through the isolation insulating layer 105 and an interlayer dielectric film in the memory cell array portion A so as to reach the Si substrate 100. This exposes the surface of the Si substrate 100 as the bottom surface of the crystal connecting hole 106.

[0050] The sectional shape of the crystal connecting hole 106 in the row and column directions is almost square, and the length of one side is, for example, 25 nm. The sectional shape of the crystal connecting hole 106 is not limited to a square, and can also be, for example, a circle. In effect, a single crystal (to be described later) can be formed even when forming the crystal connecting hole 106 having a circular sectional shape 5 nm in diameter.

[0051] When increasing the diameter (the length of the diagonal of a square), the diameter is desirably half or less the depth of the crystal connecting hole 106. For example, when the depth of the crystal connecting hole 106 is 1 μm, the diameter is desirably 500 nm or less. This is so because if the diameter of the crystal connecting hole 106 is much larger than its depth, the ratio of the area with which SiGe, to be formed in the crystal connecting hole 106 later, is in contact with the single-crystal, high-melting-point Si substrate 100 to the amount of SiGe increases. That is, in single-crystal formation (to be described later), a large number of crystallization start points are formed, and this makes it difficult to form single-crystal SiGe in the crystal connecting hole 106.

[0052] Then, a polycrystalline or amorphous SiGe layer 107′ is formed in the crystal connecting hole 106 and on the isolation insulating layer 105 by CVD or the like. That is, the SiGe layer 107′ is buried in the crystal connecting hole 106, and brought into contact with the Si substrate 100 exposed as the bottom surface of the crystal connecting hole 106. The composition ratio of the SiGe layer 107′ is Si_1-XGe_X (X≧0.5, desirably, X≧0.75). This makes it possible to readily melt the SiGe layer 107′ by annealing at about 1,050° C. in a later step, thereby reliably forming a single crystal when compared with solid-phase growth or the like. In this step, it is also possible to form a single-crystal nucleus by short-time annealing at 1,050° C. This protects the structure of the already formed memory cell array A from being destroyed. Note that a polycrystalline or amorphous Ge single-element layer may also be used instead of the SiGe layer 107′.

[0053] Subsequently, a TEOS film (not shown) is formed on the SiGe layer 107′ formed on the isolation insulating layer 105, by using, for example, plasma-enhanced chemical vapor deposition (PECVD). In the later annealing step, this TEOS film prevents the melted SiGe layer 107′ from flowing and separating, thereby preventing deterioration of the crystallinity.

[0054] As shown in FIG. 6, rapid thermal annealing (RTA) is performed on the SiGe layer 107′. This RTA is performed in a nitrogen ambient at 950 to 1,100° C., for example, 1,050° C. for 10 seconds. Consequently, the SiGe layer 107′ is temporarily melted. After being melted, the SiGe layer 107′ recrystallizes when the temperature decreases. In this process, the SiGe layer 107′ recrystallizes from a portion close to the surface of the Si substrate 100. Consequently, the SiGe layer 107′ recrystallizes to a portion on the isolation insulating layer 105 by succeeding the crystal orientation of the single-crystal Si substrate 100 in contact with the bottom of the SiGe layer 107′, thereby forming a single-crystal SiGe layer (first semiconductor layer) 107. In this process, the SiGe layer 107′ on the isolation insulating layer 105 evenly recrystallizes from the lower portion, thereby forming the single-crystal SiGe layer 107 having high flatness.

[0055] Since the melting point of Ge is 938° C. and that of Si is 1,414° C., the melting point of the SiGe layer 107′ is a temperature between them. Therefore, as the composition ratio of Si increases, the melting point of the SiGe layer 107′ increases. However, it is presumably possible to form the single-crystal SiGe layer 107 as described above, provided that the melting point of the SiGe layer 107′ is at least lower than that of the single-crystal Si substrate 100.

[0056] As shown in FIG. 7, after the TEOS film (not shown) on the SiGe layer 107 is removed by processing with diluted hydrofluoric acid, a single-crystal Si layer (second semiconductor layer) 108 is formed on the single-crystal SiGe layer 107 by epitaxial growth by using the single-crystal SiGe layer 107 as a crystal nucleus. Accordingly, a semiconductor layer consisting of a single crystal (a single-crystal semiconductor layer 109) can be formed to have an arbitrary film thickness on the isolation insulating layer 105. In this embodiment, the single-crystal semiconductor layer 109 having a film thickness of 2 μm is formed. Note that an SiGe or SiC layer may be formed by epitaxial growth instead of the single-crystal Si layer 108.

[0057] After that, STI 110 for element isolation consisting of, for example, a silicon oxide film is formed in the single-crystal semiconductor layer 109.

[0058] Then, as shown in FIG. 1, a circuit portion B (control circuit) is formed on the cell array A by a manufacturing process complying with a known transistor formation process.

[0059] More specifically, gate insulating films and gate electrodes forming control circuit transistors Tr are formed, and source/drain diffusion layers (not shown) are formed. After that, an interlayer dielectric film is formed on the entire surface. Subsequently, contact holes reaching interconnection layers M1 (bit lines BL) formed above the memory cell array portion A are formed through the interlayer dielectric film, single-crystal semiconductor layer 109, and isolation insulating layer 105. A sidewall insulating film 111 is formed on the side surfaces of the contact holes by low-pressure chemical vapor deposition (LPCVD) and reactive ion etching (RIE). After that, contact plugs 112 consisting of, for example, tungsten are buried in the contact holes. That is, contact plugs 112 are formed immediately above interconnection layers M1.

[0060] At the same time, contact plugs 113 to be connected to the source/drain diffusion layers (not shown) of the control circuit transistors Tr are formed. After that, interconnection layers M2 to be connected to contact plugs 113 are formed to connect interconnection layers M1 and control circuit transistors Tr. Interconnection layers M2 consist of, for example, aluminum (Al) or copper (Cu). In addition, contact plugs 114 to be connected to interconnection layers M2, interconnection layers M3, bonding pads (not shown), and the like are formed, thereby forming the circuit portion B above the memory cell array portion A.

[0061] In the above-mentioned first embodiment, the circuit portion B (control circuit) for controlling, for example, voltages to be applied to the memory cell array portion A is formed on it. This makes it possible to form a contact to the bit line BL through a gap between control circuits in an arbitrary position. That is, the bit line BL and circuit portion B can be connected by one plug by forming contact plug 112 immediately above the bit line BL. Accordingly, unlike in the conventional structure in which a circuit portion is formed below a memory cell array, an interconnection or the like need not be returned in the memory cell array end portion and connected to the circuit portion below the memory cell array. Consequently, the chip area can be reduced.

[0062] Likewise, the selection gates SG and control gates CG can be connected to the control circuits by forming contact plugs 103 and 104 immediately above these gates. This can also reduce the chip area.

[0063] Furthermore, the operating speed can be increased because the interconnections between the memory cell array portion A (for example, the bit lines BL, control gates CG, and selection gates SG) and the circuit portion B practically shorten.

[0064] A three-dimensionally stacked memory sometimes requires an annealing step at 900° C. or more in order to form memory elements. Therefore, a method of forming a control circuit below a memory cell array beforehand poses problems such as the diffusion of impurity diffusion layers of transistor elements and the thermal resistance of metal contacts in the control circuit during the annealing step for forming memory elements.

[0065] By contrast, in this embodiment, the circuit portion B is formed above the memory cell array portion A, so the circuit portion B is formed after the memory cell array portion A is formed during the manufacturing process. This makes it unnecessary to take account of characteristic deterioration of the circuit portion B in the annealing step for forming memory elements. That is, the degree of freedom of the circuit increases because it is unnecessary to take account of, for example, the diffusion of impurity diffusion layers of transistor elements and the thermal resistance of interconnections in the circuit portion B. For example, it is possible to use Al or Cu interconnections having low thermal resistance but a low electrical resistance, thereby increasing the operating speed. Accordingly, logic circuits and the like requiring a high speed can be formed on the entire surface of the memory cell array by using Al or Cu interconnections.

[0066] Also, in a method of epitaxially growing an Si layer directly from a crystal connecting hole, the Si layer on an isolation insulating layer tends to form a large uneven shape like a pyramid shape due to the difference between the growth rates of crystal faces. This makes the method unrealistic because the cost of a later planarizing step increases.

[0067] By contrast, in this embodiment, the circuit portion B above the memory cell array portion A is formed on the single-crystal semiconductor layer 109. The single-crystal semiconductor layer 109 is formed by forming the single-crystal SiGe layer 107 on the memory cell array portion A by succeeding the crystal orientation of the single-crystal Si substrate 100 by forming the crystal connecting hole 106, and then forming the single-crystal Si layer 108 by epitaxial growth by using the single-crystal SiGe layer 107 as a nucleus. By thus forming the single-crystal semiconductor layer 109, it is possible to form the low-cost circuit portion B having a high breakdown voltage above the memory cell array portion A.

[0068] Note that it is also effective to dope boron as a dopant impurity to the single-crystal SiGe layer 107, in order to improve the element isolation breakdown voltage. More specifically, during the manufacturing process, gaseous B₂H₆ can be added when the SiGe layer 107′ is deposited, or the impurity can be doped into the single-crystal SiGe layer 107 by ion implantation or vapor-phase doping before the single-crystal Si layer 108 is epitaxially grown.

[0069] Furthermore, p-type conductivity can be given to the SiGe layer 107′ to be buried in the crystal connecting hole, by adding, for example, gaseous B₂H₆ when depositing the layer. Consequently, the potential of the single-crystal semiconductor layer 109 on the memory cell array portion A can be fixed at the same potential as that of the Si substrate 100. This contributes to a stable operation of the control circuit.

[0070] Also, this embodiment has been explained by taking an example in which the memory cell array portion A is a collectively processed, three-dimensionally stacked memory, but the present embodiment is not limited to this. For example, this embodiment is also applicable to a three-dimensional memory other than a collectively processed memory, and to a two-dimensionally configured memory. Furthermore, this embodiment is not limited to a NAND flash memory, and also applicable to various memories.

[0071] In a three-dimensionally stacked memory (including a collectively processed memory), stacked control gates are processed into a staircase shape in the end portion of a memory cell array, and connected to a control circuit via contact plugs formed on the upper surfaces of this staircase shape. To connect the control gate to a driver circuit (control circuit) in this configuration, however, it is necessary to connect the control gate to an interconnection layer formed on the memory cell array via the contact plug, and connect the interconnection layer to the control circuit below the memory cell array via another deep contact plug in the memory cell array end portion.

[0072] Thus, the number of electrodes to be driven per unit area is large in the three-dimensional memory. When peripheral circuits are formed outside or below the memory cell array, therefore, the chip area required to lay out interconnections to these electrodes often increases.

[0073] By contrast, in this embodiment, interconnections need not be extracted outside the cell array and can be brought into direct contact with the electrodes, so the chip area can be reduced. This structure has a large effect especially in a memory device in which memory cells are three-dimensionally arranged in the stacking direction.

[0074] A semiconductor memory device according to the second embodiment will be explained below with reference to FIGS. 8 and 9. The second embodiment is an example in which STI is formed to extend through a single-crystal semiconductor layer in a circuit portion immediately above a memory cell array. Note that in the second embodiment, an explanation of the same features as those of the above-mentioned first embodiment will not be repeated, and different features will be explained.

[0075] The structure of the semiconductor memory device according to the second embodiment will be explained below with reference to FIG. 8.

[0076] FIG. 8 is a sectional view taken along the row and column directions of the semiconductor memory device according to the second embodiment.

[0077] As shown in FIG. 8, the second embodiment differs from the above-mentioned first embodiment in that STI 110 formed in a single-crystal semiconductor layer 109 extends through it.

[0078] More specifically, the film thickness of the single-crystal semiconductor layer 109 on a memory cell array portion A is decreased to 300 nm. The STI 110 is formed to extend from the first surface (upper surface) of the single-crystal semiconductor layer 109 to its second surface (lower surface) opposing the first surface. That is, the STI 110 is in contact with an isolation insulating layer 105. In other words, semiconductor layers are removed except for element regions.

[0079] In the STI 110 extending through the single-crystal semiconductor layer 109, contact plugs 112 for connecting the memory cell array portion A and a circuit portion B positioned immediately above it are formed. Therefore, contact plugs 112 are not in contact with the single-crystal semiconductor layer 109, so no shortcircuit occurs in it. That is, no sidewall insulating film need be formed on the side surfaces of contact holes.

[0080] A method of manufacturing the semiconductor memory device according to the second embodiment will be explained below with reference to FIG. 9.

[0081] FIG. 9 is a sectional view of a manufacturing step taken along the row and column directions of the semiconductor memory device according to the second embodiment.

[0082] First, the steps shown in FIGS. 4, 5, and 6 in the first embodiment are performed. That is, a memory cell array portion A is formed on an Si substrate 100, and a single-crystal SiGe layer 107 succeeding the crystal orientation of the Si substrate 100 is formed.

[0083] Then, as shown in FIG. 9, a TEOS film (not shown) on the SiGe layer 107 is removed by processing with diluted hydrofluoric acid, and a single-crystal Si layer 108 is formed on the single-crystal SiGe layer 107 by epitaxial growth by using the single-crystal SiGe layer 107 as a crystal nucleus. Accordingly, a semiconductor layer consisting of a single crystal (a single-crystal semiconductor layer 109) can be formed to have an arbitrary film thickness on an isolation insulating layer 105. In this embodiment, the film thickness of the single-crystal semiconductor layer 109 is, for example, 300 nm. That is, the single-crystal semiconductor layer 109 thinner than that of the first embodiment is formed.

[0084] After that, STI 110 for element isolation consisting of a silicon oxide film or the like is formed in the single-crystal semiconductor layer 109. More specifically, STI trenches are first formed to extend from the upper surface of the single-crystal semiconductor layer 109 to its lower surface opposing the upper surface. In other words, the semiconductor layers are removed except for prospective element regions, thereby exposing the surface of the isolation insulating layer 105 as the bottom surfaces of the STI trenches. In this step, the surface of the isolation insulating layer 105 may also be partially removed. After that, a silicon oxide film or the like is buried in the STI trenches, thereby forming the STI 110.

[0085] Subsequently, as shown in FIG. 8, a circuit portion B (control circuit) is formed on the cell array A by a manufacturing process complying with a known transistor formation process.

[0086] More specifically, gate insulating films and gate electrodes forming control circuit transistors Tr are formed, and source/drain diffusion layers (not shown) are formed. After that, an interlayer dielectric film is formed on the entire surface. Then, contact holes reaching interconnection layers M1 (bit lines BL) formed above the memory cell array portion A are formed through the interlayer dielectric film, single-crystal semiconductor layer 109, and isolation insulating layer 105. In this step, the contact holes are formed to extend through the STI 110 in the single-crystal semiconductor layer 109. After that, contact plugs 112 consisting of, for example, tungsten are buried in the contact holes, and the same steps as those of the first embodiment are performed.

[0087] The above-mentioned second embodiment can achieve the same effects as those of the first embodiment.

[0088] In addition, in the second embodiment, the STI 110 is formed to extend through the single-crystal semiconductor layer 109 in the circuit portion B, and contact plugs 112 connecting the circuit portion B and memory cell array portion A are formed in the STI 110. Therefore, contact plugs 112 are not in contact with the single-crystal semiconductor layer 109. Since this obviates the step of forming a sidewall insulating film on the inner walls of the contact holes, the manufacturing process can be simplified.

[0089] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.