Power-supply control

[0001] This application claims priority to U.S. Provisional Application Ser. No. 60/878, 921 which was filed on Jan. 05, 2007, and which is incorporated by reference.

[0002] This application is related to U.S. patent application Ser. No. ______ (Attorney docket number 1938-023-05), which is commonly owned with and was filed on the same day as the present application, and which is incorporated by reference.

[0003] Multiphase switching power supplies are used in many applications. For example, a multiphase buck converter may be used to generate a regulated output voltage (e.g., 1.8 V) from an input voltage (e.g., 3.3 V) having a magnitude that is greater than the magnitude of the output voltage.

[0004] An uncoupled-inductor (UI) power supply is a type of multiphase supply that typically has one filter inductor per phase, where the filter inductor of each phase is magnetically uncoupled from the filter inductors of the other phases.

[0005] For a specified output ripple voltage and transient response, a UI power supply has a relatively high efficiency, but also has a relatively large filter capacitance. The output ripple voltage is the voltage ripple that is superimposed on the regulated output voltage, and typically has a magnitude in the range of a few millivolts. The transient response is a measure of how fast the power supply stabilizes the regulated output voltage in response to a change in the load current. And the efficiency is a measure of the power consumed and dissipated as heat by the power supply itself; the higher the efficiency, the less power the supply consumes, and vice-versa. In a multiphase switching power supply, it is the power supply's switching circuitry that typically consumes most of the power consumed by the supply. Furthermore, the larger the filter capacitance, typically the larger and more expensive the power supply.

[0006] A coupled-inductor (CI) power supply is a type of multiphase supply that typically has one inductor per phase, where the inductor of one phase is magnetically coupled to the inductor(s) of at least one of the other phases.

[0007] Compared to a UI power supply for a specified given output ripple voltage and transient response, a CI power supply typically has a lower efficiency but a smaller filter capacitance.

[0008] Consequently, a designer may have no choice but to select a UI power supply for a system, such as a battery-powered system (e.g., a laptop computer), where, to extend the battery life and/or to minimize the system's heat generator, the efficiency of the supply is more important than the size and cost of the supply.

[0009] Conversely, a designer may have no choice but to select a CI power supply for a system, such as hand-held system (e.g., a cell phone or MP3 player), where, to fit the system within a relatively small housing and within a desired price range, the size and cost of the supply are more important than the efficiency of the supply.

[0010] An embodiment of a power-supply controller is operable to couple a first node of a first inductor to first and second reference nodes, the first inductor composing a first phase of a power supply and having a second node coupled to an output node of the power supply. The controller is also operable to couple a first node of a second inductor to third and fourth reference nodes, the second inductor composing a second phase of the power supply and having a second node. Furthermore, the controller is operable to uncouple the second node of the second inductor from the output node of the power supply.

[0011] For example, where the first and second inductors are magnetically coupled, such a controller allows the power supply to operate as a UI supply in one mode, and as a CI supply in another mode. For example, the controller may operate the power supply as a UI supply during a steady-state load condition so that the supply operates with better efficiency than a CI supply would for the specified output ripple voltage. And the controller may operate the power supply as a CI supply during a load insertion transient (i.e., a step increase in the load current) so that the supply operates with a better transient response than a UI supply would for the supply's filter capacitance.

[0012] Consequently, a designer may use such a controller to design a power supply that has at least one feature of a UI supply and at least one feature of a CI supply.

[0013] Furthermore, the controller may allow a power supply to have one or more features that are unavailable in conventional UI and CI power supplies.

[0031] FIG. 1 is a schematic diagram of an embodiment of a power supply 10 and a load 20. The supply 10 includes non-configurable, i.e., fixed, power-supply phases 12₁ and 12₂, a configurable power-supply phase 14, a power-supply controller 16, and an output filter capacitor 18. The supply 10 generates a regulated output voltage V_o from an input voltage V_in, and provides Vo to the dynamic load 20. As discussed below, by adjusting the configuration of the phase 14, the controller 16 may operate the supply 10 in multiple modes. For example, the controller 16 may operate the supply 10 as a UI supply during steady-state load conditions for increased efficiency as compared to a CI supply for a specified output ripple voltage on V_o. Furthermore, the controller 16 may operate the supply 10 as a CI supply in response to a load-insertion transient for a better output-voltage transient response as compared to a UI supply for a special filter capacitor 18. The controller 16 may also operate the supply 10 in other modes. For example, the controller 16 may operate the supply 10 in an energy-recovery mode for an improved response to a load-release transient. And although described as being a multi-phase buck converter where V_in>V_o, the supply 10 may be any other type of switching power supply.

[0032] The fixed power-supply phase 12₁ includes a switching circuit 22₁ and an inductor L₁. The switching circuit 22₁ includes high-side and low-side N-channel MOS power transistors 24₁₁ and 24₁₂, which the controller 16 may drive in phase opposition such that when the transistor 24₁₁ is conducting, i.e., “on”, the transistor 24₁₂ is non-conducting, i.e., “off”. Because the transistors 24₁₁ and 24₁₂ form a half-bridge driver, one may also call the fixed supply phase 12 a half-bridge phase. The inductor L₁ includes a winding (e.g., a copper wire) 26₁, which is wound about a magnetically permeable core 28₁. As is known, one may model the inductor L₁ as including a magnetizing inductance L_M, a leakage inductance L_l, and a winding resistance R_DC in electrical series. But for clarity, these model components are omitted from FIG. 1.

[0033] The fixed power-supply phase 12₂ includes a switching circuit 22₂ and an inductor L₂. The switching circuit 22₂ is similar to the switching circuit 22₁, and the inductor L₂ includes a winding 26₂ that is wound about a magnetically permeable core 28₂.

[0034] The configurable power-supply phase 14 includes a switching circuit 30 and two serially coupled inductors L_3a and L_3b, where L_3a may be, but need not be, equal to L_3b.

[0035] The switching circuit 30 includes high-side and low-side N-channel MOS power transistors 32₁ and 32₂, which are coupled to an input node of the inductor L_3a, and also includes N-channel MOS power transistors 34₁ and 34₂, which are coupled to an output node of the inductor L_3b. Because the transistors 32₁, 32₂, 34₁, and 34₂ form a pseudo full-bridge driver - the transistor 34₂ would be coupled to ground, not V_o, in a true full-bridge driver - one may also call the configurable supply phase 12₁ a full-bridge phase. As discussed below in conjunction with FIGS. 3-13C, by setting the conduction states of the transistors 32₁, 32₂, 34₁, and 34₂ in respective configurations, the controller 16 may set the mode in which the supply 10 operates.

[0036] The inductors L_3a and L_3b include a winding 36 that is partially wound about each of the cores 28₁ and 28₂ such that a current i₁ or i₂ flowing through fixed phase 12₁ or fixed phase 12₂ tends to induce magnetically in the configurable phase 14 a current i₃ when the transistors 32₂ and 34₂ are on and the transistors 32₁ and 34₁ are off. In an embodiment, L₁=L₂=L_3a+L_3b, and L_3a=L_3b.

[0037] FIG. 2 is a diagram of an embodiment of the windings 26₁ and 26₂, the cores 28₁ and 28₂, and the winding 36 of FIG. 1. Although shown as including an air gap in each rung, the cores 28₁ and 28₂ may each omit the air gap in one or both of the rungs. Furthermore, although shown as each having the same width, the gaps may have different widths. Moreover, the cores 28₁ and 28₂ may be made from any suitable core magnetically permeable material. Alternatively, one or both of the cores 28₁ and 28₂ may be made from a suitable non-magnetically permeable material. Or, the transformer formed by the windings 26₁ and 26₂ may be coreless. For example, the windings 26₁ and 26₂ may be effectively wrapped around an air core or the equivalent thereof.

[0038] Referring again to FIG. 1, the controller 16 of the power supply 10 receives V_in and V_o, and includes drive nodes 38a-38h, which are respectively coupled to the gates of the transistors 24₁₁, 24₁₂, 24₂₁, 24₂₂, 32₁, 32₂, 34₁, and 34₂ so that the controller may turn these transistors on and off. The controller 16 may also receive and generate additional signals that are omitted from FIG. 1. Furthermore, the controller 16 may switch the supply 10 according to any conventional technique such as a pulse-width-modulation (PWM) technique or a constant-on-time technique. Moreover, the controller 16 may be the same as or similar to a power-supply controller described in U.S. 2003/0173941, which is incorporated by reference.

[0039] The output filter capacitor 18 low-pass filters V_o, and may include an equivalent series resistance (ESR) that may give rise to at least a portion of the voltage ripple superimposed on V_o. Although only one filter capacitor 18 is shown, the supply 10 may include multiple filter capacitors coupled together in electrical parallel. Furthermore, one or more LC filters may be disposed between the capacitor 18 and the load 20 to further reduce the voltage ripple.

[0040] The load 20, which is powered by, but which is not part of, the power supply 10, may, within a relatively short time period, significantly change the amount of current that it draws from the supply 10. For example, the load 20 may be a processor having a sleep mode. When the processor “goes to sleep”, it may reduce the current it draws from the supply 10 by hundreds of milliamps within a few microseconds, and thus may give rise to a load-release transient. Conversely, when the processor “wakes up”, it may significantly increase the current it draws from the supply 10 by hundreds of milliamps within a few microseconds, and thus may give rise to a load-insertion transient.

[0041] Still referring to FIG. 1, alternative embodiments of the power supply 10 are contemplated. For example, the supply 10 may be replaced by its electrical dual, where V_in and V_o are negative relative to ground, and the N-channel transistors 24, 32, and 34 are replaced with respective P-channel transistors. Alternately, the N-channel transistors 24, 32, and 34 may be replaced with respective insulated-gate bipolar transistors (IGBTs), bipolar transistors (BJTs), or other suitable devices.

[0042] FIG. 3 is a schematic diagram that shows the configuration of the power supply 10 of FIG. 1 during an embodiment of a first operating mode in which the power supply operates as a three-phase CI supply. Like numbers reference components common to FIGS. 1 and 3, although for clarity, the controller 16 and some of the reference numbers are omitted from FIG. 3.

[0043] In the first operating mode, the controller 16 (FIG. 1) turns the transistor 34₁ off and turns the transistor 34₂ on, and maintains these transistors in these respective states for the duration of the first operating mode. To represent this schematically, the transistor 34₁ is shown as being disconnected from the output node of the inductor L_3b to indicate that this transistor is electrically open and is thus off, and the source and drain of the transistor 34₂ are shown connected together to indicate that this transistor is electrically closed and is thus on. Consequently, the inductors L₁ and L₂ are magnetically coupled to L_3a and L_3b, respectively, with the cores 28₁ and 28₂ and are also coupled to one another via the inductors L_3a and L_3b.

[0044] FIGS. 4A-4E are plots of signals generated by an embodiment of the power supply of FIG. 1 during the first operational mode under a steady-state load condition—a steady-state load condition exists when the current drawn by the load 20, i.e., the load current, is substantially constant. Some of these signals may be capacitively coupled to the simulated probe, hence the excursion above and below zero.

[0045] FIG. 4A is a plot of the voltage with which the controller 16 (FIG. 1) drives the gate of the transistor 24₁₁. The voltages with which the controller 16 drives the transistors 24₂₁ and 32₁ may each have a similar amplitude profile, but may be offset in phase from the voltage at the gate of the transistor 24₁₁ by, for example, approximately +120° and approximately −120°, respectively. The voltages with which the controller 16 drives the gates of the transistors 24₁₂, 24₂₂, and 32₂ are the complements of the respective voltages with which the controller drives the gates of the transistors 24₁₁, 24₁₂, and 32₁, with an optional guard delay to prevent the push-pull coupled pairs of these transistors (e.g., transistors 24₁₁ and 24₁₂) from conducting a “crowbar” current. That is, there may be a delay between the time that the drive voltage for the transistor 24₁₁ goes low and the time that the drive voltage for the transistor 24₁₂ goes high to prevent the transistors 24₁₁ and 24₁₂ from simultaneously being on and conducting a current directly between V_in and ground. Preventing simultaneous conduction of both transistors of a push-pull coupled pair of transistors is often called “shoot-through protection.”

[0046] FIG. 4B is a plot of the voltage across the inductor L₁, this voltage being caused by the leakage-inductance portion of L₁. The voltages across the inductor L₂ and the series combination of L_3a and L_3b may each have a similar amplitude profile, but may be offset in phase from the voltage across L₁ by, for example, approximately +120° and approximately −120°, respectively.

[0047] FIG. 4C is a plot of the current through the fixed phase 12₁, the current through the fixed phase 12₂ having a similar amplitude profile but being offset in phase (e.g., approximately +/−120°) from the current through the phase 12₁. In an embodiment, the peak-to-peak current through each phase 12₁ and 12₂ is approximately 18 Amperes (A).

[0048] FIG. 4D is a plot of the current through the configurable phase 14. In an embodiment, the peak-to-peak current through the phase 14 is approximately 14 A. In this embodiment, the reason that the peak-to-peak current through the configurable phase 14 is less than the peak-to-peak current through each fixed phase 12₁ and 12₂ is because the inductors L₁ and L₂ are not directly coupled to each other via a common core, but are instead magnetically coupled via the inductors L_3a and L_3b.

[0049] FIG. 4E is a plot of the sum of the currents, i.e., the total current through all three supply phases 12₁, 12₂, and 14. In an embodiment, the peak-to-peak amplitude of the total current is approximately 35 A.

[0050] Referring to FIGS. 3-4E, the operation of the power supply 10 is described during an embodiment of the first operating mode under a steady-state load condition.

[0051] Generally, in the first operating mode, the power supply 10 operates substantially the same as a conventional three-phase CI power supply, and, therefore, provides substantially the same features associated with a CI power supply. With the transistors 34₁ and 34₂ off and on, respectively, the controller 16 (FIG. 1) drives the transistor 24₁₁ with the voltage of FIG. 4A, and drives the transistor 24₁₂ with a voltage inverted relative to the voltage of FIG. 4A as described above. The controller 16 drives the transistors 24₂₁ and 32₁ with voltages similar to the voltage driving the transistor 24₁₁, with these voltages being phase shifted, for example by +120° and −120°, relative to the voltage driving the transistor 24₁₁. Similarly, the controller 16 drives the transistors 24₂₂ and 32₂ with voltages similar to the voltage driving the transistor 24₁₂, with these voltages being phase shifted, for example by +120° and −120°, relative to the voltage driving the transistor 24₁₂.

[0052] FIG. 5 is a schematic diagram that shows the configuration of the power supply 10 of FIG. 1 during an embodiment of a second operating mode in which the power supply operates as a two-phase UI supply. Like numbers reference components common to FIGS. 1 and 5, although for clarity, the controller 16 and some of the reference numbers are omitted from FIG. 5. As discussed below, one may configure the controller 16 to operate the supply 10 in the second mode under a steady-state load condition for improved efficiency as compared to the first (three-phase CI) operating mode discussed above in conjunction with FIGS. 3-4E.

[0053] In the second operating mode, the controller 16 (FIG. 1) turns all of the transistors 32₁, 32₂, 34₁, and 34₂ off, and keeps these transistors off for the duration of the second operating mode; therefore, during the second operating mode, the configurable phase 14 is effectively removed from the power supply 10. To schematically represent the off states of the transistors 32₁, 32₂, 34₁, and 34₂, the transistors 32₁ and 32₂ are shown disconnected from the input node of the inductor L_3a to indicate that these transistors are electrically open and are thus off, and the transistors 34₁ and 34₂ are shown disconnected from the output node of the inductor L_3b to indicate that these transistors are also electrically open and are thus off.

[0054] FIGS. 6A-6D are plots of signals generated by an embodiment of the power supply of FIG. 1 during the second operating mode under a steady-state load condition. Some of these signals may be capacitively coupled to the simulated probe, hence the excursion above and below zero.

[0055] FIG. 6A is a plot of the voltage with which the controller 16 (FIG. 1) drives the gate of the transistor 24₁₁ and the voltage with which the controller 16 drives the transistor 24₁₂ is the plotted voltage inverted, with an optional a guard delay as discussed above in conjunction with FIG. 4A.

[0056] FIG. 6B is a plot of the voltage with which the controller 16 (FIG. 1) drives the gate of the transistor 24₂₁. Therefore, in this embodiment, the controller 16 drives the transistor 24₂₁ approximately 180° out of phase relative to the transistor 24₁₁. The voltage with which the controller 16 drives the transistor 24₂₂ is the plotted voltage inverted, with an optional a guard delay as discussed above in conjunction with FIG. 4A. Therefore, in this embodiment, the controller 16 also drives the transistor 24₂₂ approximately 180° out of phase relative to the transistor 24₁₂.

[0057] FIG. 6C is a plot of the currents through the fixed phases 12₁ and 12₂. In an embodiment, the peak-to-peak current through each phase 12₁ and 12₂ is approximately 12 Amperes (A).

[0058] FIG. 6D is a plot of the total current through the phases 12₁ and 12₂. In an embodiment, the peak-to-peak amplitude of the total current is 11 A.

[0059] Referring to FIGS. 5-6D, the operation of the power supply 10 is described during an embodiment of the second mode.

[0060] Generally, as discussed above, in the second operating mode, the power supply 10 operates substantially the same as a conventional two-phase UI supply, and, therefore, may provide substantially the same features associated with a UI power supply. With the transistors 32₁, 32₂, 34₁, and 34₂ off, the controller 16 (FIG. 1) drives the transistor 24₁₁ with the voltage of FIG. 6A, and drives the transistor 24₁₂ with the inverse of this voltage as described above. Similarly, the controller 16 drives the transistor 24₁₂ with the voltage of FIG. 6B, and drives the transistor 2422 with the inverse of this voltage as described above.

[0061] Comparing FIGS. 4E and 6D, the peak-to-peak amplitude (approximately 35 A) of the total phase current while the supply 10 is operating in the first, three-phase CI operating mode is more than triple the peak-to-peak amplitude (approximately 11 A) of the total phase current while the supply 10 is operating in the second, UI operating mode. Consequently, one may configure the controller 16 to operate the supply 10 in the second, two-phase UI mode under a steady-state load condition so that the supply operates with better efficiency than in the first operating mode.

[0062] FIG. 7 is a schematic diagram that shows the configuration of the power supply 10 of FIG. 1 during an embodiment of a third operating mode in which the supply operates as a three-phase CI supply. But as discussed below, the difference between the first and third modes is that in the first mode, the supply 10 is operating under a steady-state load condition, and in the third mode, the supply is responding to a load-insertion transient. Like numbers reference components common to FIGS. 1 and 7, although for clarity, the controller 16 and some of the reference numbers are omitted from FIG. 7.

[0063] In the third operating mode, the controller 16 (FIG. 1) turns the transistors 24₁₁, 24₂₁, 32₁, and 34₂ on, and turns the transistors 24₁₂, 24₂₂, 32₂, and 34₁ off for the duration of the third operating mode. Therefore, in this mode, the controller 16 couples the inductors L₁, L₂, and L_3a+L_3b in electrical parallel between V_in and V_o.

[0064] FIG. 8A is a plot of the load current experiencing an insertion transient.

[0065] FIG. 8B is a plot of the output voltage V_o generated by the supply 10 while in response to the load insertion of FIG. 8A operating in the second UI operating mode.

[0066] FIG. 8C is a plot of the output voltage V_o generated by the supply 10 in response to the load insertion of FIG. 8A while operating in the third, three-phase CI mode.

[0067] Referring to FIGS. 7-8C, the operation of the power supply 10 is described during an embodiment of the third operating mode.

[0068] Generally, as discussed above, in the third operating mode, the power supply 10 operates substantially the same as a conventional three-phase CI power supply under a load-insertion condition.

[0069] In response to detecting a load-insertion transient at time t₁, the controller 16 (FIG. 1) turns the transistors 24₁₁24₂₁, 32₁, and 34₂ on and turns the transistors 24₁₂, 24₂₂, 32₂, and 34₁ off for the duration of the third operating mode; consequently, the controller effectively couples the inductors L₁, L₂, and L_3a+L_3b in electrical parallel between V_in and V_o. The controller 16 may conventionally detect the load-insertion transient by detecting that the rate of decrease in the average value of V_o (i.e., V_o with the ripple filtered out) equals or exceeds a threshold rate.

[0070] The parallel coupling of the inductors L₁, L₂, and L_3a+L_3b causes the supply 10 to deliver a transient current that meets the load's increased current consumption. Because the inductors L₁, L₂, and L_3a+L_3b are magnetically coupled to one another, the effective inductance between V_in and V_o in this mode is the parallel combination of the leakage inductances of L₁, L₂, and L_3a+L_3b. Because these leakage inductances are typically smaller than the values that L₁, L₂, and L_3a+L_3b would have if they were not magnetically coupled to one another, the supply 10 may, while operating in the third mode, better respond to a load-insertion transient than a UI supply would provide for a given output ripple voltage and filter capacitor.

[0071] Consequently, assuming that the supply 10 is operating in the second, UI mode before the load-insertion transient, in response to the load-insertion transient, the controller 16 may switch the supply from the second, UI mode to the third, CI mode.

[0072] Comparing FIGS. 8B and 8C, in an embodiment, the supply 10 operating in the third, CI mode (FIG. 8C) responds better (e.g., a smaller undershoot 42 and a faster settling time 44 for V_o) to a load-insertion transient than the supply operating in the second, UI mode (FIG. 8B).

[0073] After V_o has stabilized, the controller 16 may exit the third mode and return to the second mode. The controller 16 may determine that V_o has stabilized when the rate at which V_o is decreasing is equal to or less than a rate threshold.

[0074] FIG. 9 is a schematic diagram that shows the configuration of the power supply 10 of FIG. 1 during an embodiment of a fourth operating mode in which the supply responds to a load-release transient. Like numbers reference components common to FIGS. 1 and 9, although for clarity, the controller 16 and some of the reference numbers are omitted from FIG. 9.

[0075] In the fourth, energy-recapture operating mode, the controller 16 (FIG. 1) turns the transistors 24₁₁, 24₂₁, 32₁, and 34₂ off and turns the transistors 24₁₂, 24₂₂, 32₂, and 34₁ on for the duration of the fourth operating mode to recapture the energy stored in the inductors L₁ and L₂ via the inductors L_3a and L_3b.

[0076] FIG. 10A is a plot of the load current experiencing a release transient.

[0077] FIG. 10B is a plot of the output voltage V_o generated by the supply 10 in response to the load-release of FIG. 10A while operating in the second, UI operating mode.

[0078] FIG. 10C is a plot of the output voltage V_o generated by the supply 10 in response the load release of FIG. 10A while operating in the fourth, energy-recapture mode.

[0079] Referring to FIGS. 9-10C, the operation of the power supply 10 is described during an embodiment of the fourth operating mode.

[0080] In response to detecting a load-release transient at time t₁, the controller 16 (FIG. 1) turns the transistors 24₁₁, 24₂₁, 32₁, and 34₂ off and turns the transistors 24₁₂, 24₂₂, 32₂, and 34₁ on. The controller 16 may conventionally detect the load-release transient by detecting that the rate of increase in the average value of V_o (i.e., V_o with the ripple filtered out) equals or exceeds a threshold rate.

[0081] Therefore, a decaying current i₁ flows from ground, through the transistor 24₁₂ and the inductor L₁, and into the load 20.

[0082] Likewise, a decaying current i₂ flows from ground, through the transistor 24₂₂ and the inductor L₂, and into the load 20.

[0083] Referring to FIG. 10B, if the power supply 10 is operating in the second, UI mode described above in conjunction with FIGS. 5-6D, then the currents i₁ and i₂ cause the output voltage V_o to have an under-damped transient response having an oscillating portion 46 and a settling time 48. Even though the load 20 has reduced its current draw, the inductors L₁ and L₂ temporarily continue to provide the currents i₁ and i₂ at the levels needed to maintain the load's previous current draw. Because the current through an inductor cannot change instantaneously, the excess current (the portion of i₁+i₂ not drawn by the load) flows into the filter capacitor 18 and causes the under-damped transient response in V_o. V_o settles to a stable level once the currents i₁ and i₂ through L₁ and L₂ stabilize to new steady-state levels that correspond to the new load current.

[0084] But referring to FIG. 10C, if the power supply 10 is operating in the fourth, energy-recapture mode, then the excess currents through L₁ and L₂ are effectively absorbed by the power source that provides V_in, thus causing V_o to have a significantly improved transient response. Because the inductors L₁ and L₂ are magnetically coupled to the inductors L_3a and L_3b, respectively, the currents i₁ and i₂ magnetically induce in the phase 14 a current i₃, which flows from ground through the transistor 32₂, the inductors L_3a and L_3b, and the transistor 34₁, and into the V_in source. Ideally, the excess of the i₁ +i₂ currents not drawn by the load 20 is effectively converted into the current i₃ due to the magnetic coupling between the inductors L₁, L₂, L_3a, and L_3b such that this excess current effectively flows back into the V_in source instead of into the filter capacitor 18. Consequently, the energy stored in this excess current is recaptured by the V_in source, and the V_o transient response of the power supply 10 is significantly improved. Due to imperfect coupling between L₁, L₂, L_3a, and L_3b, however, the V_in source may recapture less than all of the energy stored in the excess current.

[0085] After V_o has stabilized, then the controller 16 may exit the fourth mode and return to the second, UI mode. The controller 16 may determine that V_o has stabilized when the rate at which the average level of V_o is increasing is equal to or less than a threshold rate.

[0086] Still referring to FIGS. 9-10C, if the load 20 is an electric motor, such as a brushless DC motor, then the controller 16 (FIG. 1) may regeneratively brake the motor by operating the power supply 10 in the above-described fourth mode or in a variation of this mode. As the motor spins while being braked, it acts as an electrical generator, and thus generates respective voltages across and respective currents through its coils. By controlling the effective load applied to these coils, the controller 16 may adjust the braking torque effectively applied to the motor. Furthermore, the controller 16 may capture the energy generated by the braking motor by effectively directing these coil currents into the power supply V_in.

[0087] FIG. 11 is a schematic diagram that shows the configuration of the power supply 10 of FIG. 1 during an embodiment of a fifth operating mode in which the power supply operates as a two-phase CI power supply. Like numbers reference components common to FIGS. 1 and 11, although for clarity, the controller 16 and some of the reference numbers are omitted from FIG. 11.

[0088] In the fifth operating mode, the controller 16 (FIG. 1) turns the transistors 32₁ and 34₁ on and turns the transistors 32₂ and 34₂ off.

[0089] Consequently, the input node of the inductor L_3a is coupled to the output node of the inductor L_3b to form a closed loop 52 that includes the inductors L_3a and L_3b in electrical series.

[0090] The closed loop 52 magnetically couples the inductor L₁ to the inductor L₂, and thus magnetically couples together the two phases 12₁ and 12₂. When a current i₁ flows through the phase 12₁, i₁ induces in the loop 52 a current i₃, which induces a current i₂ in the phase 12₂. Similarly, when a current i₂ flows through the phase 12₁, i₂ induces in the loop 52 the current i₃, which induces the current i₁ in the phase 12₁.

[0091] Therefore, in the fifth operating mode, the controller 16 uses the adjustable phase 14 to magnetically couple together the phases 12₁ and 12₂ such that the controller may operate the supply 10 as a two-phase CI supply.

[0092] FIG. 12 is a schematic diagram of an embodiment of a power supply 60, which is similar to the power supply 10 of FIG. 1, but which includes a sense circuit 62 (a resistor in this embodiment) that allows the controller 16 to determine the level and direction of a current i₃ flowing in the phase 14. Like numbers reference components common to FIGS. 1 and 12, although for clarity, some of the reference numbers are omitted from FIG. 12. Furthermore, although shown as a resistor, the circuit 62 may include another element, or may include multiple elements. Moreover, the circuit 62 may be in electrical parallel with one or both of the inductors L_3a and L_3b instead of in series with these inductors.

[0093] FIG. 13A is a plot of the load current experiencing a load-release transient followed by a load-insertion transient.

[0094] FIG. 13B is a plot of the output voltage V_o generated by the supply 60 in response to the load current of FIG. 13A while the supply is operating in the second, UI mode.

[0095] FIG. 13C is a plot of the output voltage V_o generated by the supply 60 in response to the load current of FIG. 13A while the supply sequences through the second, fourth, fifth, second, third, and second operating modes.

[0096] Referring to FIGS. 12-13B, while operating in the second, UI mode, the supply 60 has a relatively poor V_o transient response to the load current of FIG. 13A. At time t₁, the supply 60 causes an overshoot 62 in V_o in response to the load-release transient as discussed above in conjunction with FIGS. 9 and 10B. And at time t₂, the supply 60 causes an undershoot 64 in V_o in response to the load-insertion transient as discussed above in conjunction with FIGS. 7 and 8B.

[0097] Comparatively, referring to FIGS. 12-13A and 13C, while sequencing through the second, fourth, fifth, second, third, and second operating modes, the supply 60 has an improved V_o transient response to the load current of FIG. 13A.

[0098] Before time t₁, the controller 16 operates the supply 60 in the second, UI mode as discussed above in conjunction with FIGS. 5-6D.

[0099] At time t₁, in response to detecting the load release, the controller 16 operates the supply 60 in the fourth, energy-recapture mode as described above in conjunction with FIGS. 9-10A and 10C to reduce the V_o overshoot as compared to the overshoot 62 of FIG. 12B.

[0100] Next, after time t₁ and in response to detecting that the rate of increase in the average level of V_o is equal to or less than a threshold rate, the controller 16 transitions the supply 60 to the fifth, two-phase CI mode as discussed above in conjunction with FIG. 11. This allows any current i₃ that remains flowing through the phase 14 from the fourth, energy-recapture mode to decay naturally and release its energy into the phases 12₁ and 12₂ via magnetic coupling.

[0101] Then, when the controller 16 senses via the circuit 62 that the current i₃ in the phase 14 is equal to or below a threshold current, the controller transitions the supply 16 back to the second, UI mode.

[0102] Next, at time t₂, in response to detecting the load insertion, the controller 16 operates the supply 60 in the third, three-phase CI mode described above in conjunction with FIGS. 7-8A and 8C to reduce the V_o undershoot as compared to the undershoot 64 of FIG. 13B.

[0103] Then, after time t₂ and in response to detecting that the rate of decrease in the average level of V_o is equal to or less than a threshold rate, the controller 16 transitions the supply 60 to the fifth, two-phase CI mode. This allows any current i₃ that remains flowing through the phase 14 from the third, three-phase CI mode to decay naturally and release its energy into the phases 12₁ and 12₂ via magnetic coupling.

[0104] Next, when the controller 16 senses via the circuit 62 that the current i₃ in the phase 14 is equal to or below a threshold current, the controller transitions the supply 60 back to the second, UI mode.

[0105] The controller 16 maintains the supply 60 in the second, UI mode until another load release or load insertion occurs.

[0106] Still referring to FIGS. 12-13A and 13C, other embodiments of the above mode sequences are contemplated. For example, if the period between t₁ and t₂ is so small that the current i₃ through the phase 14 never equals or falls below the threshold current, then the controller 16 may transition the supply 60 from the fifth, two-phase-CI mode directly into the third, three-phase CI mode without first transitioning the supply into the second, UI operating mode. Furthermore, if the period between t₁ and t₂ is even smaller, then the controller 16 may transition the supply 60 directly from the fourth, energy-recapture mode to the third, three-phase CI mode without first transitioning the supply into the second, UI and fifth, two-phase-CI modes.

[0107] FIG. 14 is a schematic diagram of an embodiment of a power supply 70, where like numbers reference components common to FIGS. 1 and 14. The supply 70 is similar to the supply 10 of FIG. 1, except that the phase 12₂ is omitted from the supply 70. Furthermore, the supply 70 may include in the phase 14 a sense circuit similar to the sense circuit 62 discussed above in conjunction with FIG. 12.

[0108] When the transistors 32₁, 32₂, 34₁, and 34₂ are off, then the controller 16 may operate the supply 70 in a single-phase UI mode. When the transistor 34₁ is off and the transistor 34₂ is on, then the controller 16 may operate the supply 70 in a two-phase CI mode. When the transistors 24₁₁, 32₁, and 34₂ are on and the transistor 34₁ is off, then the controller 16 may operate the supply 70 in a two-phase CI mode in response to a load-insertion transient. When the transistors 32₁ and 34₁ are on and the transistors 32₂ and 34₂ are off, then the controller 16 may operate the supply 70 in a mode in which energy stored in the phase 14 is released into the phase 12, via magnetic coupling between L₁ and L₃. And when the transistors 32₁ and 34₂ are off and the transistors 32₂ and 34₁ are on, then the controller 16 may operate the supply 70 in an energy-recapture mode in response to a load-release transient.

[0109] FIG. 15 is a schematic diagram of an embodiment of a power supply 80, where like numbers reference components common to FIGS. 1 and 15. The supply 80 is similar to the supply 10 of FIG. 1, except that the supply 80 includes N phases 12₁-12_N instead of only two phases 12₁ and 12₂. Furthermore, the supply 80 may include in the phase 14 a sense circuit similar to the sense circuit 62 discussed above in conjunction with FIG. 12.

[0110] When the transistors 32₁, 32₂, 34₁, and 34₂ are off, then the controller 16 may operate the supply 80 in an N-phase UI mode. When the transistor 34₁ is off and the transistor 34₂ is on, then the controller 16 may operate the supply 80 in an (N+1)-phase CI mode. When the transistors 24₁₁-24_N1, 32₁, and 34₂ are on and the transistor 34₁ is off, then the controller 16 may operate the supply 80 in an (N+1)-phase CI mode in response to a load-insertion transient. When the transistors 32₁ and 34₁ are on and the transistors 32₂ and 34₂ are off, then the controller 16 may operate the supply 80 in an N-phase CI mode. And when the transistors 32₁ and 34₂ are off and the transistors 32₂ and 34₁ are on, then the controller 16 may operate the supply 80 in an energy-recapture mode in response to a load-release transient.

[0111] FIG. 16 is a diagram of an embodiment of the windings 26₁ -26_N, the core 28₁ and the winding 36 of FIG. 15. The core 28 may be made from any suitable magnetically permeable material, and although shown as including an air gap in each rung, the core may omit the air gap in one or more of the rungs. Furthermore, although the gap width in the rung around which the winding 36 is wrapped is smaller than the other gap widths, the air gaps may have any suitable widths shown as each having the same width, the gaps may have different widths. Moreover, variations of the core 28 may be used with the supplies 10 (N=2), 60 (N=2), and 70 (N=1) of FIGS. 1, 12, and 14, respectively. Alternatively, the core 28 may be made from a suitable non-magnetically permeable material. Or, the transformer formed by the windings 26₁-26_N may be coreless. For example, the windings 26₁-26_N may be effectively wrapped around an air core or the equivalent thereof.

[0112] FIG. 17 is a schematic diagram of an embodiment of a computer system 90, which may include one or more of the power supplies 10 (FIG. 1), 60 (FIG. 12), 70 (FIG. 14), and 80 (FIG. 15). For example purposes, the computer system 90 is described as including two power supplies 10_a and 10_b that are similar to the supply 10 of FIG. 1.

[0113] In addition to the supplies 10_a and 10_b, the system 90 includes a memory 92, a processor 94, and one or more peripherals 96. Examples of the peripherals 96 include, e.g., a disk drive, key board, mouse, display, video card, and printer.

[0114] The supply 10_a provides a supply voltage V_oa to the memory 92, and the supply 10_b provides a supply voltage V_ob to the processor 94. Example levels of V_oa and V_ob include 1.8V and 3.3V.

[0115] From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.