Strained Transistor with Optimized Drive Current and Method of Forming

[0001] This application claims the benefit of U.S. Provisional Application No. 60/880,563, filed on Jan. 16, 2007, entitled “Dual Contact Etching Stop Layer Scheme for Advanced Device Control,” which application is hereby incorporated herein by reference.

[0002] The present invention relates generally to semiconductor devices, particularly to strained MOS transistors, and more particularly to strained MOS transistors with a strained layer formed over source/drain and gate regions, where carrier mobility is enhanced in a channel region.

[0003] While the scaling down of the device dimensions in a semiconductor integrated circuit continues, maintaining high drive current at scaled voltages and smaller gate dimensions becomes more important. Device drive current is closely related to gate length, gate capacitance, and carrier mobility. Different technology innovations have been made to address this issue. For example, strained silicon technology is demonstrated to boost carrier mobility in a MOS transistor without narrowing channel length. High-K (dielectric constant) gate dielectric is adopted to increase gate capacitance. A metal-gate electrode is used to increase gate capacitance and, therefore, increase the device drive current. A nonplanar device structure such as a FinFET transistor is developed to enable steeper channel-length scaling. Among these efforts, strained silicon technology has been demonstrated to significantly increase carrier mobility without adding much complexity into the existing manufacturing process.

[0004] With strained silicon technology, a silicon atom in a MOS transistor is displaced in its lattice. The displacement significantly reconfigures the energy band structure in the silicon to accelerate the flow of electrons and holes, thus increasing device drive current. Strain can be applied to a MOS transistor in different ways. One way to develop strain in a MOS transistor is by selectively forming an epitaxial layer of SiGe (silicon germanium) at the source/drain regions of a conventional MOS transistor. Because the lattice constant of the SiGe is larger than that of Si, the channel region between the two SiGe source/drain is placed under compressive stress. This device configuration enhances hole mobility in the channel region, thus increasing the drive current of a PMOS device. Conversely, a layer of silicon can be formed atop a relaxed SiGe layer. MOS transistors are then formed on the silicon layer. Due to the lattice constant mismatch between Si and SiGe, the Si layer is under constant biaxial, in-plane tensile strain. This device configuration has a benefit of enhancing the electron mobility in an NMOS device.

[0005] Strain can also be applied by forming a strained layer on a MOS transistor. The strained layer is also generally referred to as a strain-induced layer, stress layer, contact etching stop (CES) layer, or CES trained layer. In forming a CES layer, a silicon nitride film is deposited over a completed MOS transistor covering the source/drain regions, gate electrode and spacers. Because of the lattice spacing mismatch between the CES layer and underlying layer, an in-plane stress develops to match the spacing. A CES layer thus formed may exhibit different film stress over a broad range, from tensile to compressive, by controlling the N—H, Si—H and Si—N bond ratios in the CES layer and optimizing deposition conditions such as power, temperature and pressure in the processing chamber. It has been revealed that in-plane tensile stress in the channel region enhances electron mobility, thus increasing drive current in an NMOS device, and compressive stress parallel to channel length direction can enhance hole mobility, thus improving PMOS device performance.

[0006] FIG. 1 illustrates a strained NMOS and PMOS device of prior art formed in proximity on a silicon substrate 1. Shallow trench isolations (STI) 10 are formed in the silicon substrate 1 to isolate the NMOS device from the PMOS device. A tensile CES layer 14 formed atop the NMOS device introduces an in-plane tensile strain in the channel region 11, and therefore improves the drive current of the NMOS device. A compressive CES layer 16 formed atop the PMOS device introduces a compressive strain in the channel region 13, and therefore improves the drive current of the PMOS device. Although it is observed that the improvement on drive current is influenced by CES layer parameters such as the level of stress, the layer thickness, and the layer dimension. Little is revealed from prior art on how and in what manner these parameters affect the drive current in each type of MOS transistors. This situation has kept the current CES strained silicon technique more of a rule of thumb approach, where little can be done on device and process parameters to obtain an optimized increase on the device drive current. Moreover, in the prior art CES strained MOS transistors, the uniformity between enhanced MOS transistor drive currents is poor and scaled increase in drive current is difficult to achieve. This may result in detrimental effects in an integrated circuit such as skewed switching threshold, deteriorated noise margin, increased device time delay, and even a collapse of logic.

[0007] In view of these and other problems in the prior CES strain efforts to enhance carrier mobility and improve device performance, there is a need for a method of obtaining an optimized drive current increase with desired uniformity by fine tuning CES layer parameters in advanced MOS transistors.

[0008] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which provide a CES strained NMOS and PMOS devices having CES layer dimensions in a specific range, which can lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device, and method of forming.

[0009] In accordance with one preferred embodiment of the present invention, a semiconductor device formed in a substrate comprises an OD region, a gate region overlying the OD region having an gate electrode on top, a source and drain region formed on the opposite side of the gate region, substantially aligned with an edge of the gate region and the edges of the OD region, a compressive-stress layer having a first and second edge substantially conformally over the gate electrode and the OD region, wherein the space between a gate electrode edge and the first edge is greater than 0.4 um, wherein the space between an OD edge and the second edge is in the range of between about 60 nm to about 400 nm.

[0010] In accordance with another preferred embodiment of the present invention, a semiconductor device formed in a semiconductor substrate comprises a first PMOS transistor formed in a P-type OD region with a first and second edge, having a first poly gate electrode overlying the P-type OD region, parallel to the first edge, an first NMOS transistor formed in an N-type OD region, having a second poly gate electrode overlying said N-type OD region, a first compressive-stress layer having a first and second edge substantially conformally over the first gate electrode and the P-type OD region, wherein the space between an edge of the first gate electrode and the first edge of the compressive-stress layer is greater than 0.4 um, wherein the space between the second P-type OD edge and the second edge of the compressive-stress layer is in the range of between about 60 nm to about 400 nm.

[0011] In accordance with yet another preferred embodiment of the present invention, a PMOS transistor formed in a P-type active region (OD) in a semiconductor substrate comprises a gate region overlying the OD region having a poly gate electrode on the top, a source and drain region formed on the opposite side of the gate region, substantially aligned with an edge of the gate region and the edges of the OD region, a compressive-stress layer substantially conformally over the gate electrode and the OD region having a first and second edge, wherein the space between an edge of the gate electrode and the first edge of the compressive-stress layer is in the range of one to two times either P or G, whichever is larger, where P is the minimum design rule gate poly to P-type OD dimension, and G is the minimum design rule poly-to-poly spacing on an P-type OD region, wherein the space between an P-type OD edge and the second edge of the compressive-stress layer is in the range of between about one-third to about two-thirds of the sum of L and H, where L is the minimum P-type OD to N-well boundary dimension and H is the minimum spacing between an N-type OD and an N-well boundary.

[0012] An advantage of the preferred embodiments of the present invention is that it provides an optimized drive current increase in a CES strained PMOS device without adding complex processing steps. CES strained MOS transistors also exhibit improved drive current uniformity.

[0013] A further advantage of a preferred embodiment of the present invention is that the added process steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive CES layers does not require rework on an existed design database, and no extra design rules are imposed on the design and layout engineers.

[0025] The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0026] The present invention will be described with respect to preferred embodiments in a specific context, namely CES strained NMOS and PMOS devices with an optimized drive current and method of forming. MOS devices thus formed also exhibit an improved uniformity among drive currents. The intermediate stages of manufacturing a preferred embodiment of the present invention are illustrated. The variations of the preferred embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

[0027] FIG. 2 illustrates the formation of a CES strained PMOS transistor P1 in a preferred embodiment. P1 is formed in an N-well 2, which is formed on a silicon substrate 1. In other embodiments, P1 is formed in a bulk N-type silicon substrate. In yet other embodiments, a substrate made of strained semiconductor, compound semiconductor, multi-layers semiconductor or silicon on insulator (SOI), strained silicon-on-insulator (SSOI), strained silicon germanium on insulator (S—SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), and the like, can be used to form P1 from therein. Shallow trench isolations (STI) 10 are formed in the silicon substrate 1 to isolate P1 from adjacent devices. Preferably, the STIs 10 are formed by etching shallow trenches in the silicon substrate 1, and filling the trenches with an insulator such as silicon dioxide (SiO₂).

[0028] A gate dielectric 4 is deposited on the surface of the silicon substrate 1. The gate dielectric 4 may preferably be SiO₂ formed by any of the known methods, such as thermal oxidation, local oxidation of silicon (LOCOS), chemical vapor deposition (CVD), etc. Silicon nitride can also be used since it is an effective barrier to impurity diffusion. The silicon nitride film is preferably formed by thermal nitridation of silicon. It can also be prepared by plasma anodic nitridation using nitrogen-hydrogen. The silicon nitride film may also be formed by thermal nitridation of SiO₂. The gate dielectric may also be oxy-nitride, oxygen-containing dielectric, nitrogen-containing dielectric, high-k materials or any combinations thereof.

[0029] A gate electrode 6 is formed on gate dielectric 4. The gate electrode 6 is preferably polysilicon (referred to hereafter as “poly”), although it may be formed of metal, or a compound structure comprising a metal, semiconductor, metal oxide and/or silicide. The preferred method of formation is CVD. Other embodiments may use amorphous silicon, elemental metals that are conductive, alloys of elemental metals that are conductive, silicides or nitrides of elemental metals that are conductive, or any combination thereof. Typically, the gate electrode 6 and gate dielectric 4 are deposited as layers and then patterned to form a gate. A pair of spacers 8 is formed along the sidewalls of the gate dielectric 4 and gate electrode 6. As known in the art, spacers 8 are preferably formed by blanket depositing a dielectric layer over an entire region, then, anisotropically etching to remove the dielectric layer from horizontal surfaces, thus leaving spacers 8. FIG. 2 illustrates rectangular spacers.

[0030] In the preferred embodiment, the source/drain regions 12 are formed by implanting P-type impurities, such as boron, into the N-well 2. The spacers 8 are used as a mask so that edges of the source/drain regions 12 are substantially aligned with the spacers 8. Gate electrode 6 is preferably also implanted to reduce sheet resistance. In other embodiments, the source/drain regions 12 are formed by recessing the source/drain regions 12 followed by epitaxially growing silicon, SiGe, or SiC in the recesses with a desired dopant. This structure provides a compressive stress to the channel of the PMOS device and enhances hole mobility. In yet other embodiments, source/drain regions 12 are formed by expitaxially growing silicon, SiGe, or SiC with desired dopant on the top surface of the silicon substrate 1. Preferably, a SiO₂ film is formed in regions where no source and drain is to be formed. The subsequently deposited epitaxial film on the SiO₂ film can be removed. In the source/drain regions (i.e., where substrate surface is exposed), epitaxial film is grown.

[0031] To reduce the resistance of the gate electrode 6 and source/drain regions 12, an optionally silicide layer (not shown) may be formed on the top of gate electrode 6 and source/drain regions 12 by a silicide process. The silicide is preferably NiSi₂, CoSi₂, TiSi₂, or the like. To form a silicide layer, a thin layer of metal such as cobalt, nickel, titanium, or the like, is sputtered over the device. The device is then annealed to form a silicide between the deposited metal and the underlying exposed silicon regions. Un-reacted metal is removed by an etch process.

[0032] Next, as shown in FIG. 3A in a cross sectional view, a strain-inducing layer 14 is formed. Although this layer is preferably a CES layer and is interchangeably referred to as CES layer 14 throughout the description, it can be any strained layer or layers, even if the layer does not perform an etch stop function. The strain-inducing layer 14 may also be a composite layer comprising a CES layer and other layers. As previously discussed, this layer is strained in order to enhance the device performance. The types and strengths of the strain, also sometimes referred to as stress, are determined by the deposition process and material used. Generally, if a strained material has a smaller lattice constant than the underlying material, the strained material will have an inherent compressive strain and the underlying material will have an inherent tensile strain after relaxation. Conversely, if a strained material has a greater lattice constant than the underlying material, the strained material will have an inherent tensile strain and the underlying material will have an inherent compressive strain after relaxation.

[0033] In FIG. 3A, CES layer 14 is preferably formed of materials such as silicon nitride, oxynitride, oxide, silicon germanium or any combinations, generating compressive strain in the PMOS channel region. In other embodiments, a strained layer may be formed of materials such as silicon nitride, oxynitride, oxide, SiC, SiCN, CoSi₂ (Co silicide), NiSi₂ (Ni silicide), or any combinations, to create tensile strain in the channel region of an NMOS device. As known in the art, the type and magnitude of the strain are affected by the relative properties of the CES layer 14 and the underlying material.

[0034] Strain can also be adjusted by the type and concentration of impurities in the underlying material, which includes forming an epitaxial layer (not shown) in the source/drain regions 12. In one preferred embodiment, an epitaxial layer of silicon germanium is formed in the silicon source/drain regions 12, which typically increases the material's lattice constant (because germanium has a larger lattice constant). This structure provides a compressive stress to the channel of the PMOS device and enhances hole mobility. In another embodiment, a silicon carbon epitaxial layer is formed in the silicon source/drain regions of an NMOS transistor, which typically decreases the material's lattice constant (because carbon has a smaller lattice constant). This structure provides a tensile stress to the channel of the NMOS device and enhances electron mobility.

[0035] In a preferred embodiment, a CES layer 14 comprises a dielectric material. In alternative embodiments, a CES layer 14 comprises semiconductors, metals, and combinations thereof. The CES layer 14 may also be in the form of a single layer or composite layers. An advantageous feature of such material, as explained herein, is that these materials have an inherent stress when deposited, which induces a strain in the underlying material. In preferred embodiments, the CES layer 14 has a thickness from about 5 nm to about 500 nm.

[0036] FIG. 3B illustrates a top view of the strained PMOS transistor P1 as shown in FIG. 3A. The CES layer 14 is formed over the active region, which includes the source/drain regions 12 and channel region 11. An active region defines the dimension of a MOS transistor and is hereafter referred to as an “OD” region. The CES layer 14 may also cover the N-well region (as shown in FIG. 3A). Although CES layer 14 is shown as one layer, it can be formed of different layers. In the preferred embodiments, a photo mask named PILD is used to pattern the CES layer 14. To clarify the description, the horizontal distance between the edge of poly gate 6 and the edge of CES layer 14 is referred to hereinafter as ENx. The vertical distance between the OD edge and the edge of strained layer 14 is referred to hereinafter as ENy. It is revealed from the preferred embodiments that, of each technology generation, a CES layer 14 having an ENx and ENy in a specific range can lead to an optimized PMOS drive current increase and an improved drive current uniformity, when compared with a CES strained MOS transistor, where no limitation is imposed on ENx and ENy. A CES strained PMOS device without limitations on the CES layer dimension is from hereinafter referred to as a baseline PMOS device.

[0037] In preferred embodiments, the values of an optimized range of ENx and ENy corresponding to a technology generation are obtained through a wafer acceptance test (WAT) on a plurality of CES strained core transistors, such as that shown in FIG. 3B. A core transistor has a generic MOS transistor configuration where a single poly gate is formed over an OD region. A core transistor is so called herein to distinguish itself from a MOS transistor with more complex structures, such as one with multiple poly gate fingers, and one with a single poly gate and multiple dummy poly fingers on an OD region.

[0038] In obtaining the optimized range of ENx and ENy of a certain technology generation, a plurality of CES strained PMOS core transistors are formed on a silicon wafer scribe line. These transistors have a minimum channel length allowable by the specific technology generation (sometimes referred to as transistors with “on-rule” channel length) and channel width of various values. In one embodiment, a plurality of CES strained PMOS core transistors are provided, having a channel length of 65 nm and channel width (W) of 1 μm, 0.6 μm, and 0.14 μm. These transistors also have a fixed ENy of about 70 nm and ENx of various dimensions. Drive current (Idsat) is measured on each transistor, aiming to obtain an ENx corresponding to a maximum Idsat improvement. FIG. 4A shows the results from the WAT test. The plotting has an ENx on the horizontal coordinate and scaled Idsat improvement on the vertical coordinate, both in linear scale. Lines 20, 22, 24 illustrate the scaled drive current improvement upon a baseline PMOS device as a function of ENx. Lines 20, 22, and 24 correspond to transistors having a channel width of 1 μm, 0.6 μm, and 0.14 μm, respectively. It is shown that, significant increase of Idsat in the channel region is obtained when ENx reaches 0.4 μm. When ENx increases, Idsat in the channel region continues to increase. When ENx reaches about 1.8 μm, maximum Idsat increase is obtained on PMOS transistors with various channel width. Idsat remains substantially unchanged when ENx continues to increase.

[0039] A similar test is carried out to obtain the optimized range of ENy. In one embodiment, PMOS transistors used for obtaining the optimized range of ENy have a fixed ENx of about 0.5 μm and ENy of various dimensions. FIG. 4B shows results obtained from measuring the drive current with different ENy values. The plotting has an ENy on the horizontal coordinate in logarithmic scale and drive current (Idsat) improvement on the vertical coordinate in linear scale. Lines 26, 28, and 30 correspond to transistors used to form lines 20, 22 and 24 in FIG. 4A. It is shown that, significant increase of Idsat in the channel region is obtained when ENy reaches 60 nm. When ENy increases, Idsat in the channel region continues to increase. The drive current Idsat maxes out when ENy reaches about 200 nm. Idsat drops significantly, however, when ENy exceeds 400 nm.

[0040] FIGS. 5A-5B illustrate that CES strained PMOS devices formed with optimized ENx and ENy also exhibit an improved uniformity (scaled increase) among the enhanced drive currents. In FIG. 5A, a PMOS transistor P1 having a single poly gate 6 is formed over an OD region. P1 has a gate length of 0.14 μm and gate width of 0.4 μm. The poly to OD dimension is 0.5 μm. A first plurality of PMOS device samples having the foregoing dimension is provided. A compressive CES 14 with desired ENx and ENy of about 0.7 μm and 70 nm is formed on each PMOS device sample, covering the OD region. Idsat is measured on each sample and plotted as square points in FIG. 5B. The vertical axis of FIG. 5B represents the cumulative percentage, which is used to illustrate the distribution of measured drive current Idsat. The solid diamonds in FIG. 5B are Idsat values measured on a second plurality of counterpart prior art CES strained PMOS devices, without constraints on the dimensions of ENx and ENy. It can be seen from FIG. 5B that Idsat from the embodied CES strained PMOS devices has an Idsat distribution of from about 480 μA/μm to about 550 μA/μm, while Idsat from the prior art CES strained devices has a distribution of from about 450 μA/μm to about 580 μA/μm. The Idsat uniformity (the quotient of standard deviation over mean value) is enhanced from about 7% to about 4%. The same trend has been observed through similar comparisons on PMOS devices of various configurations, such as PMOS with multiply poly fingers, PMOS with multiply dummy poly fingers formed over OD region, foregoing PMOS structures with various poly pitches.

[0041] FIGS. 6A-6B illustrates the quantitative relationship between optimized ENx, ENy and minimum design rule dimensions and spacings of a certain processing technology. These limitations were obtained through wafer acceptance tests (WAT) similar to those described above and have been adopted in the embodied manufacturing processes as described below. It is revealed from FIG. 6A that an optimized ENx corresponding to an optimized drive current increase and optimized drive current uniformity is in the range of one to two times either P or G, whichever is larger, where P is the minimum gate poly to P-type OD dimension, and G is the minimum poly-to-poly spacing on an P-type OD region. It is revealed from FIG. 6B that an ENy leading to an optimized drive current increase and optimized drive current uniformity lies in the range of between about one-third to about two-thirds of the sum of L and H, where L is the minimum P-type OD to N-well boundary dimension and H is the minimum spacing between an N-type OD and an N-well.

[0042] Similar wafer acceptance test (WAT) has been conducted on CES strained NMOS core transistors. A CES layer is formed over a plurality of NMOS transistors of various configurations to create in-plane tensile strain in the channel region. Although a similar trend is observed where ENx and ENy within a range as described above can lead to improved drive current enhancement and improved drive current uniformity, the effect is less significant than that of a CES strained PMOS device.

[0043] FIG. 7 is a flow chart illustrating the steps of forming the CES layers in a CMOS manufacturing process in a preferred embodiment. FIGS. 8A-8F illustrate cross-sectional views after each processing step described in FIG. 7. To simplify the description, one PMOS device P1 adjacent to an NMOS device N1 is shown in each cross-sectional view. It should be understood that a processing step applied on P1 applies to all PMOS devices on the substrate, and a processing step applied on N1 applies to all NMOS devices on the substrate.

[0044] FIG. 8A shows a portion of an initial substrate where PMOS device P1 and NMOS device N1 have been formed in semiconductor substrate 2 through a known CMOS manufacturing process. P1 and N1 have a source/drain region 12p, 12n, and gate region 6p and 6n, respectively. STIs 10 are used to isolation P1 and N1.

[0045] According to STEP 11 in FIG. 7, a tensile CES layer 16 is formed over the substrate, aiming to create tensile strain in the channel region 13 of N1. Layer 16 is made of materials such as silicon nitride, oxynitride, oxide, SiC, SiCN, CoSi₂ (Co silicide), NiSi₂ (Ni silicide), or any combinations. In one preferred embodiment, CES layer 16 has a thickness of from about 5 nm to about 500 nm. The substrate after STEP 11 is shown in FIG. 8B.

[0046] At a STEP 12 in FIG. 7, a photo mask NILD is developed and a photolithography process is conducted to pattern the CES layer 16 over NMOS device N1 with desired ENx and ENy. In developing an NILD photo mask, the desired ENx and ENy values for an NMOS device (obtained through WAT test on NMOS core transistors as described earlier) are provided to an automatic photo mask generating process (also known as “logical operation process” in the art). Also input to said logical operation process are layout information of N-TYPE OD regions, P-well regions, and poly regions on a substrate, which is usually included in the finished design database provided by layout designers of an IC product, as known in the art. The logical operation process will first identify the N-TYPE OD regions on the substrate, where NMOS devices are formed. The logical operation process will then identify the poly regions 6n on the foregoing N-TYPE OD regions. Subsequently, the logical operation process will create a photolithography pattern, such that the distance between its horizontal edge and the N-TYPE OD edge is ENy, and the distance from its vertical edge to a gate poly 6n edge is ENx. Other operations carried out by the logical operation process include merging two CES layer patterns of same stress type having overlapping edges, merging two adjacent CES layer patterns of same stress type when the space between their edges is less than a pre-determined distance. In creating the photo mask, optical proximity correction (OPC) may be employed to take into account the errors introduced by photolithography system, as known to those skilled in the art. Known photolithography and etch processes are used to pattern CES layer 16 on N1. A result is shown in FIG. 8C in both cross-sectional and top view.

[0047] Further, as described in STEP 13 of FIG. 7, a compressive CES layer 14 is formed over the substrate, aiming to create compressive strain in the channel region 11 of PMOS transistor P1. CES layer 14 is made of materials such as silicon nitride, oxynitride, oxide, silicon germanium or any combinations. In one preferred embodiment, CES layer 14 has a thickness of about the same as that of layer 16. In other embodiments, the thickness of CES layer 14 may be substantially different from that of CES layer 16, in order to balance the drive current between P1 and N1. The substrate after STEP 13 is shown in FIG. 8D.

[0048] In STEP 14 of FIG. 7, a photo mask PILD is developed and a photolithography process is conducted to pattern the CES layer 14 over PMOS devices with desired ENx′ and ENy′. In doing so, the desired ENx′ and ENy′ values corresponding to optimized PMOS performance are provided to a logical operation process, together with layout information of P-TYPE OD regions, N-well regions, and poly regions on a substrate. The logical operation process will first identify the P-TYPE OD regions on the substrate, where PMOS devices are formed. The logical operation process will then identify the poly regions 6p on the foregoing P-TYPE OD regions. Subsequently, the logical operation process will create a photolithography pattern, such that the distance between its horizontal edge and the P-TYPE OD edge is ENy′, and the distance from its vertical edge to a gate poly edge is ENx′. After mask layer PILD is developed, known photolithography and etch processes are used to pattern the CES layer 14 on the P1. A result is shown in FIG. 8E in both cross-sectional and top view.

[0049] After the formation of the patterned compressive CES layer 14 on PMOS devices and patterned tensile CES layer 16 on NMOS devices, a blanket deposition of SiO₂ through CVD is conducted to form a first inter-layer dielectric layer (ILD), although other known materials and methods of forming an ILD layer are not excluded. A planarization process, such as chemical mechanical polishing (CMP) process may then be applied to create a flat substrate surface, as shown in FIG. 8F. Known CMOS manufacturing processes can continue from this point by, for example, cutting contact openings through the ILD where contacts to source/drain regions 12p, 12n and gate electrodes 6p, 6n are needed.

[0050] It can be recognized that, after the current processing step, the CES layers formed on substrate 2 surface may have the following lateral configuration. Between MOS transistors of same conductivity type, the adjacent CES layers may be in a tensile-ILD-tensile or compressive-ILD-compressive configuration. Between MOS transistors of opposite conductivity type, the adjacent CES layers have a tensile-ILD-compressive configuration.

[0051] In other embodiments, after the formation of the patterned compressive CES layer 14 on PMOS devices and patterned tensile CES layer 16 on NMOS devices, a tensile film 14′ or a compressive film 16′ may be formed filling the lateral space between adjacent CES layers on substrate 2 surface in order to balance the stresses in the CES layers 14 and 16, thus reaching a desired drive current balance between adjacent NMOS and PMOS devices.

[0052] In an additional embodiment, a plurality of PMOS and a plurality of NMOS transistors are formed on a semiconductor substrate through the processes described above. Each of the PMOS and NMOS transistors is covered by a compressive CES layer and a tensile CES layer, respectively, with desired ENx and ENy. In the current embodiment, the CES layer configurations between adjacent MOS devices may include tensile-compressive-tensile, compressive-tensile-compressive, tensile-tensile-tensile, compressive-compressive-compressive, tensile-compressive-compressive, and compressive-tensile-tensile. Various CES layer configurations between adjacent MOS devices are shown in FIG. 8G.

[0053] In a further embodiment, a PILD photo mask is first developed by a logical operation process described above to pattern compressive CES layer 14 for optimized PMOS performance. The NILD photo mask is then developed as the reverse of the PILD mask, thus eliminating the cost of creating a dedicated NILP mask. After the processing steps shown in FIG. 7, CES layers cover the entire substrate, as shown in FIG. 8H. This CES layer configuration casts little negative impact on NMOS device performance, because, as described earlier, an NMOS device is less sensitive to ENx and ENy of a tensile CES layer 16 formed thereon. Instead, CES layers thus formed alleviate reliability concerns created by previous embodiments, such as voids formed between adjacent CES layer edges, film edge peeling during subsequent process steps.

[0054] In an even further embodiment, a single photo mask PILD is developed by a logical operation process to pattern compressive CES layer 14 for optimized PMOS performance. The same mask layer is applied a second time on negative photoresist to pattern tensile CES layer 16. An NILD photo mask is not necessary, thus further reducing the cost of mask development.

[0055] As can be recognized by those skilled in the art, the preferred embodiments improve device performance without adding complex processing steps. Moreover, the added process steps can be readily integrated into a known CMOS process flow. Furthermore, the creation of NILD and PILD photo masks does not require additional works or changes on an existed design database. Optimized ENx and ENy corresponding to a certain technology node apply to all design projects developed using the same technology. No extra design rules are imposed on design and layout engineers.

[0056] Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. As an additional example shown in FIG. 9, a CES strained PMOS transistor P1 is rotated from the orientation of the previous embodiments such that the opposing edges of poly gate 6, P-TYPE OD region and the CES strained layers 14 are not aligned with the horizontal and vertical direction. In this case, ENx is the shortest distance between the edge of poly gate 6 and the edge of strained layer 14, while ENy is the shortest distance between the P-TYPE OD edge and the edge of strained layer 14. Furthermore, it will be readily understood by those skilled in the art that materials, process steps, process parameters in forming the preferred embodiments may be varied while remaining within the scope of the present invention.

[0057] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.