Die and Wafer Failure Classification System and Method

[0001] In the semiconductor manufacturing industry, semiconductor fabrication processes are used to make a wafer on which a plurality of integrated circuit dies are formed. A fabrication process is run to produce thousands (or more) parts and it is not uncommon to produce some dies that have irreparable defects or failures. The percentage of the integrated circuit dies produced that are operational is referred to as the “yield” of the process.

[0002] In order optimize the wafer/chip yield, a semiconductor manufacturer allocates engineers to analyze the yield of a process by grouping die failures into categories or classifications. Thus, one of the primary functions of a yield analysis engineer is to troubleshoot die failures, communicate the failure information and quantify the loss (impact on the yield) associated with the identified failure categories or classes. It is necessary to classify the failures before troubleshooting the failure causes.

[0003] Current failure classification techniques are completely manual. Engineers manually review failure pattern data to group wafer and die failures into categories and estimate yield loss based on the amount of loss that an engineer assigns to a lot. The amount of loss assigned to each failure class/category (also called a “detractor”) is based on the engineer's judgment, and therefore is subjective.

[0004] There are several problems with the current manual failure classification techniques. Because the yield analysis engineer uses his/her subjective judgment to assign a loss amount to a detractor, there is inherently a bias on the detractors. Classification becomes more difficult and the yield detractor analysis less accurate as the yield increases and the semiconductor fabrication process matures.

[0005] Briefly, a system and method are provided for classifying failures of semiconductor integrated circuit dies using a unique input vector created from die level characterization data to classify wafer (process related) and die level (defect related) patterns. The failure classification may then be used to assign the appropriate yield loss by die. The classification results produced by the plurality of classifiers are examined with a preference towards assigning a wafer level failure classification to failure data for a die when any of the plurality of failure classification results indicates a presence of a wafer level failure. According to one embodiment, the failure data for each die is analyzed with a plurality of failure classifiers, including at least one die level classifier to produce a die level classification result and at least one wafer level classifier to produce a wafer level classification result. In one embodiment, a die level classifier uses a back-propagation neural network model. The model is tuned during an offline training phase during which failure data for known die failures are analyzed. Similarly, a wafer failure classification library is updated with failure data for known die failures. The neural network model and the wafer failure classification library are used during a failure classification and hierarchy phase to assign a failure classification to a plurality of integrated circuit dies.

[0011] Reference is made first to FIG. 1 which illustrates a training subsystem 100 or portion of a classification system and method according to an embodiment of the invention. The training subsystem 100 identifies and characterizes failure signatures using electrical analysis, die bitmap images and physical failure analysis to produce a training input vector. The training subsystem 100 is performed offline based on the various analyses also performed offline.

[0012] More specifically, when a new failure signature is identified at 110, the failure is characterized at 120 based on one or more of the electrical analysis 130, bit failure map 132 and physical failure analysis 134. The failure characterization 120 creates a training input vector 140 that represents the failure signature. The input vector comprises, for example, bin map classification data, failure chip compression data, die level IC current data associated with a known failure/defect. Next, at 150, the fail signature type for the training input vector 140 is determined. If at 150 it is determined that the training input vector is a wafer level signature type of failure, then it is coupled to block 170 where a wafer classifying pattern matching algorithm may be used to spatially compare the wafer failure signature data represented by the training input vector to known wafer patterns stored in a configuration file. A comparison match threshold may be based on a percentage of chips that match a particular pattern. The block 170 outputs a wafer classification for that training input vector for a known defect/failure to a wafer level classification library. If at 150 it is determined that the training input vector 140 is a die level failure, then the data for the training input vector is coupled to a die level neural network model at 160 for training a die level neural network classifier model. The output of the neural network model 160 is a predictive model markup language back-propagation model (NN PMML) 162. One example of a neural network technology that may be used is the well known Clementine neural network, information about which is publicly available. However, the present invention is not limited to this particular neural network and other such neural network technologies may be used.

[0013] Thus, a training input vector comprises test data, current data, etc., associated with a known failure/defect for a particular type of chip. The offline training subsystem 100 is executed on all of the known or identified failure signatures (at 110). Again, the outputs of the training subsystem 100 are updates to a wafer level classification library 172 and updates to the die level NN model in the form NN PMML 162. There may be several hundred training input vectors in a training set for a particular type of integrated circuit chip or die.

[0014] Turning to FIG. 2, the classification and hierarchy subsystem 200 is described. After (prefuse) wafer testing 10 for a wafer is complete, the classification and hierarchy subsystem 200 takes information from the neural network model (NN PMML 162), and wafer level classification library 172 to classify each die failure signature resulting from the wafer testing 10, hereinafter referred to as a resultant die failure signature. Each resultant die failure signature is filtered through a common classification hierarchy to assign each die failure signature to its true failure classification and also looks for wafer level signatures from the die failure signatures. If there is a wafer level failure signature present on a particular wafer, then the classification assigned to a resultant die failure signature will be a wafer classification.

[0015] An input vector is created at 20 for each resultant die failure signature. The input vector is unique to a particular die X,Y on a wafer. The input vector is creating by combining failure chip compression data with chip characterization information derived from bit failure map data, electrical analysis data and physical failure analysis/test results. In essence, the input vector for a die is a set of raw failure data for which failure classification(s) is/are not known. The input vector is then coupled to a die classification step at 210, a bin map classification step at 220, an application test classification step at 230 and a wafer classification step at 240.

[0016] In the die classification step 210, a die failure classifier, implemented with a neural network model, analyzes data represented by the input vector and the NN PMML 162 to produce a die level classification result 212. The die level classification step 210 may be performed by a back-propagation neural network in one embodiment as indicated above. The die level classification result 212 is a measure or an indication of the degree to which the input vector is a die level failure and it is based on die information only for chips that have fail-chip compression data. As is known in the art, fail-chip compression data is a type of failure data that provides a spatial orientation of a failure density across a die. However, fail-chip compression data is not always available for a die. A die will not have fail-chip compression data if for some reason the die cannot be tested completely through the test flow process due to major failures. For example, common causes for the inability to produce fail-chip compression data for a die is the inability to make contact between the die and a tester device, more current or voltage is needed to test the die than is available in the tester device, etc. It is possible that may dies will not have fail-chip compression data resulting in the input vector for that die being devoid of data or having an incomplete set of data.

[0017] One solution is to replace the missing data in the input vector (caused by the lack of fail-chip compression data) with zeros. Nevertheless, when the die level neural network failure classifier 210 detects missing data in the input vector, the classifier 210 will output a system abort indicating an inability to classify the input vector or indicating an incorrect classification.

[0018] The bin map classifier 220 provides a solution to this data availability issue. The bin map classifier 220 checks bin map information and determines if the test results on the die indicate a test abort because the die could not be adequately tested. The bin map information is the initial die sorting data from the wafer tester process that groups dies into the following categories: DC test failures (continuity, short-circuits and open-circuits), output check failures (input leakage, pad-to-pad leakage), and functionality failures. Thus, the bin map information does not have fail chip compression information due to the test abort indication for a die. If the test results for a die indicate a test abort for that die, the failure classification assigned to that die is the bin map classification. In other words, the bin map classification result 222 is set to a “true” state for that die. The bin map classification may be viewed as another type of die level classification.

[0019] In the application test classification step 230, the input vector is analyzed to determine if an application specific or functional test failure (also known as product “guardbanding”) is present. The application test result 232 is set to a “true” state for a die as an indication of an application specific or functional failure of that die.

[0020] Finally, the wafer classification step 240 involves performing pattern recognition analysis on the input vector using the wafer failure classification library 172 to determine and classify a wafer level failure signature in the input vector. The wafer classification step 240 recognizes the fail signature and its location on the wafer since it is specific to a particular X,Y die. The wafer classification result 242 is a measure or an indication of a known wafer level failure pattern in the input vector.

[0021] Next, the classification hierarchy step 250 analyzes the classification results 212, 222, 232 and 242 to determine the final classification for the die. The output of the classification hierarchy 250 is a classification for a die based on a hierarchy. In one embodiment, the classification hierarchy 250 gives preference or priority to wafer level signatures over all other failure signatures (die level and application). This approach is used since the die could be simultaneously involved in both a wafer fabrication process issue as well as a die defect issue.

[0022] For example, as shown at 260 if the wafer classification result 242 for a die indicates that there is a wafer level failure pattern in the input vector, the final classification assigned at 270 for that die is a wafer level classification. Next, if the classification results 212, 222, 232, and 242 for a die indicate that it is not a wafer level failure signature, the application classification result is examined at 280 and if the application test result 232 is sufficiently strong or true to indicate an application failure signature the final classification assigned at 282 for that die is an application failure signature. Proceeding further down the hierarchy, if the classification results 212, 22, 232, and 242 for a die indicate that it is not a wafer level failure signature and not an application failure signature, the bin map classification result is examined at 290 and if it is sufficiently strong or true the final classification assigned to that die is a bin map type die level failure signature. Finally, if the classification results 212, 22, 232, and 242 for a die indicate that it is not a wafer level failure signature, not an application failure signature, and not a bin map failure signature, then the die classification result is examined at 300 and a confidence value for the die classification result is greater than a threshold, the final classification assigned to that die at 302 is a die level classification of the fail chip compression type.

[0023] Finally, if at 300 it is determined that the classification result results classification result 212 does not exceed the confidence threshold, then at 310, the failure classification for die X,Y “unknown”.

[0024] After steps 270, 282, 292, 302 and 310, the process ends for the input vector for a particular die X,Y, the process is then repeated for the input vector for another die on a wafer. There may be several different wafer level failure classifications (categories or classes), several types of application level failure classifications, several types of bin map die level failure classifications and several types of neural network die level failure classifications. Thus, each main category of failure classifications (wafer level, application level, bin map die level and neural network die level) may have sub-categories or classes. When a die is given a final classification through the processing of 260-310, it is assigned to the appropriate sub-category or class within that main classification. Thus, after the classification process is run for the input vectors for all of the dies on a wafer, the failure classification for each die is determined.

[0025] Reference is now made to FIGS. 3 and 4. One use of the data accumulated from the classification and hierarchy subsystem on a batch of wafers is to compute the yield loss percentage or fraction for each failure classification (class). The yield percentage may be computed over any number of wafers desired. The assigned classifications output by the classification and hierarchy subsystem is used at 400 to track the number of die (input vectors) that are assigned to each failure class, and in particular each main class and sub-class or sub-category. The count of the number of die assigned to each failure classification for a batch of wafers is tracked as shown in FIG. 4. Accordingly, at 410, the yield loss percentage for each failure class may be computed based on the total failure counts. For example, the yield loss percentage may be computed for each sub-class within a main failure classification. This is shown in FIG. 4 where for each of the wafer level sub-categories or classes Wafer Class 1 to Wafer Class N, the yield loss percentage is computed relative to the total count of die assigned to all wafer level classes (Wafer Class 1 to Wafer Class N). The yield loss percentage may be similarly computed for each of the die level failure sub-categories Die Class 1 to Die Class M and for each of the application level failure sub-categories Application Class 1 to Application Class P. Alternatively, the yield loss percentage for each sub-category may be computed across all failure classifications. In any event, using the foregoing techniques, it is possible to classify wafer level (process related) and die level (defect related) failure patterns and assign the appropriate yield loss by die.

[0026] FIG. 5 illustrates how the classification techniques described above may be used as part of a semiconductor yield analysis system. The classification and hierarchy subsystem 200 is a computer program that is stored in a memory 510 associated with a computer 500. The computer 500 is also connected to the wafer level failure classification library 172 and the die level classification model 162. It is assumed that the training subsystem 100 has already been run for numerous known failures. Wafers or individual dies are tested and analyzed using test and analysis equipment 600, producing test results which are stored in a data store or database 700. The computer 500 executes the classification and hierarchy subsystem program to classify the input vectors for the data in database 700 associated with each die. The computer 500 may also perform the computations described above in connection with FIGS. 3 and 4 to compute yield loss by failure classification.

[0027] The failure classification system and method described herein may be used for any type of semiconductor integrated circuit device, such as memory devices, application specific integrated circuit devices, processors, etc.

[0028] The system and methods described herein may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative and not meant to be limiting.