Semiconductor device

[0001] This invention relates to a semiconductor device, in particular, of the type which has semiconducting elements on their reduced plane occupation area so that the semiconductor device has the excellent thermally radiative property even in its narrowed plane size.

[0002] A semiconductor device is known which has an integral package of a power semiconducting element and a regulatory IC for controlling the power semiconducting element. As shown in FIG. 8, the semiconductor device of this type comprises a support plate 3; a power semiconducting element 21 mounted on support plate 3; a layered structure of a regulatory IC 22 mounted on power semiconducting element 21 or, as shown in FIG. 9, an apposed structure of a regulatory IC 22 secured on support plate 3 away from power semiconducting element 21. For example, FIG. 4 of Japanese Patent No. 2,566,207 discloses a semiconductor device of such a layered structure.

[0003] Such a semiconductor device naturally requires the semiconducting structure of good thermally radiative property because power semiconducting element 21 eradiates a larger amount of heat than regulatory IC 22 does. However, semiconductor device shown in FIG. 8 cannot indicate good thermally radiative property due to the less heat discharging performance because heat emitted from power semiconducting element 21 is discharged to outside only through support plate 3. In some cases, it would be preferable to thermally isolate regulatory IC 22 from power semiconducting element 21, especially in view of the function of semiconductor device which involves heating power semiconducting element 21 and power-saving regulatory IC 22. In this case, there would be a risk of disadvantageously deteriorating the electric property of regulatory IC 22 which may be overheated by heat directly transferred to regulatory IC 22 from power semiconducting element 21.

[0004] On the other hand, in semiconductor device of the apposed structure shown in FIG. 9 wherein power semiconducting element 21 and regulatory IC 22 are juxtaposed on support plate 3, it is possible to prevent direct heat transmission from power semiconducting element 21 to regulatory IC 22, however, it is still defective due to the inferior heat radiation since heat is inadequately discharged from power semiconducting element 21 to outside only through support plate 3. The apposed structure of FIG. 9 also has an additional disadvantage because it requires larger plane size of semiconductor device in the apposed structure of power semiconducting element 21 and regulatory IC 22 on support plate 3.

[0005] An object of the present invention is to provide a semiconductor device which has semiconducting elements stacked in the layered structure with an excellent thermally radiative property.

[0006] The semiconductor device according to the present invention comprises a thermally radiative and electrically conductive support plate (3); a first semiconducting element (1) having one main surface (1a) which is mounted and electrically connected on support plate (3); a thermally radiative and electrically conductive connecting lead (4) having one main surface (4a) which is mounted and electrically connected on the other main surface (1b) of first semiconducting element (1); a second semiconducting element (2) mounted on the other main surface (4b) of connecting lead (4); and a plurality of lead terminals (5) disposed adjacent to support plate (3). Connecting lead (4) bridges and electrically joins between at least one (5a) of lead terminals (5) and the other main surface (1b) of first semiconducting element (1). Thus, the semiconductor device can be made by piling first semiconducting element (1), connecting lead (4) and second semiconducting element (2) in turn on the reduced plane occupation area of support plate (3) for densified mounting of semiconducting elements in the semiconductor device.

[0007] Also, as heat-releasing and conductive connecting lead (4) spans between at least one (5a) of lead terminals (5) and first semiconducting element (1), heat generated from first semiconducting element (1) during the operation is effectively and fully discharged to outside through two heat transmission channels of support plate (3) and connecting lead (4) to one (5a) of lead terminals (5). Connecting lead (4) serves also to function as a current path to or from first semiconducting element (1) so that relatively large electric current can flow through connecting lead (4) for heavy current capacity and simplified wiring. In addition, connecting lead (4) bridging between connecting lead (4) and lead terminal (5a) has a mechanical strength enough to prevent deformation or warpage of connecting lead (4) when a pressure of encapsulant resin is applied during the transfer molding process of a lead frame assembly for encapsulation, thus completely avoiding an undesirable electrical contact between connecting lead (4) and support plate (3).

[0008] In an embodiment of the present invention, interposed between the other main surface (4b) of connecting lead (4) and second semiconducting element (2) is a lagging (7) which comprises an electrically insulating layer (7a) and an adiabatic layer (7b) to restrict or prohibit heat transfer from first semiconducting element (1) to second semiconducting element (2) due to thermal insulation by lagging (7).

[0009] The present invention can provide a semiconductor device of smaller or narrowed plane size due to the reduced plane occupation area of semiconducting elements. Also, heat generated from first semiconducting element can be well radiated, and first and second semiconducting elements can be thermally isolated from each other so that operating heat from first semiconducting element never deteriorates electric property of second semiconducting element to provide durable and reliable semiconductor devices.

[0010] The above-mentioned and other objects and advantages of the present invention will be apparent from the following description in connection with preferred embodiments shown in the accompanying drawings wherein:

[0011] FIG. 1 is a side elevation view of the semiconductor device according to the present invention before packaging by plastic encapsulation;

[0012] FIG. 2 is a plan view of the semiconductor device shown in FIG. 1;

[0013] FIG. 3 is a sectional view of an embodiment showing a lagging on a connecting lead;

[0014] FIG. 4 is a sectional view showing an embodiment of manufacturing the lagging;

[0015] FIG. 5 is a sectional view showing another embodiment of manufacturing the lagging;

[0016] FIG. 6 is a side elevation view of a second embodiment showing the semiconductor device according to the present invention before packaging by plastic encapsulation;

[0017] FIG. 7 is a side elevation view of a third embodiment showing the semiconductor device according to the present invention before packaging by plastic encapsulation;

[0018] FIG. 8 is a plan view of a prior art semiconductor device; and

[0019] FIG. 9 is a plan view of another prior art semiconductor device.

[0020] (1) . . . a first semiconducting element (a MOS-FET), (1a) . . . one main surface, (1b) . . . the other main surface, (2) . . . a second semiconducting element (a regulatory IC), (3) . . . a support plate, (4) . . . a connecting lead, (4a) . . . one main surface, (4b) . . . the other main surface, (4c) . . . a ramp, (5) . . . lead terminals, (5a) . . . a lead terminal, (5b) . . . lead terminals, (6) . . . a substrate, (6a) . . . one end, (6b) . . . the other end, (7) . . . a lagging, (7a) . . . a dielectric layer, (7b) . . . an adiabatic layer, (8) . . . lead wires,

[0021] Embodiments will be described hereinafter in connection with FIGS. 1 to 7 of the drawings regarding the semiconductor device according to the present invention applied to a power semiconductor device for use in a switching regulator.

[0022] As shown in FIG. 1, the semiconductor device according to the present invention comprises a MOS-FET 1 as a first semiconducting element or switching element whose one main surface 1a is mounted or secured on a support plate 3 through an electrically conductive adhesive or solder 10. Formed of nickel-plated, thermally radiative and electrically conductive metal such as copper or aluminum is support plate 3 to which one main electrode of MOS-FET 1 is electrically connected. The other main electrode, namely source electrode is formed on the other main surface 1b of MOS-FET 1 on the opposite side of support plate 3, and a connecting lead 4 is attached on source electrode of MOS-FET 1 via electrically conductive adhesive or solder 11.

[0023] As shown in FIG. 3, connecting lead 4 comprises a substrate 6 formed of thermally radiative and electrically conductive metal such as copper or aluminum, and one end 6a of substrate 6 is connected to source electrode of MOS-FET 1, the other end 6b of substrate 6 is connected to a lead terminal 5a through a solder 13. Substrate 6 comprises one main surface 4a connected to source electrode of MOS-FET 1 and lead terminal 5a, and the other surface 4b to which a second semiconducting element, namely regulatory IC 2 is applied. One and the other ends 6a and 6b of substrate 6 are disposed parallel to each other but at different heights due to the different heights of the other main surface 1b of MOS-FET 1 and lead terminal 5a so that connecting lead 4 has a ridge or bump 4c to compensate the difference in level between the other main surface 1b of MOS-FET 1 and lead terminal 5a, while positioning one and the other ends 6a and 6b of substrate 6 respectively on the other main surface 1b of MOS-FET 1 and lead terminal 5a. Bump 4c of connecting lead 4 shown in FIG. 1 is formed into a trapezoidal shape of three sides without the base, however, bump 4c may be formed into one or combination of various shapes upwardly away from support plate 3.

[0024] One end 6a of connecting lead 4 is wider than bump 4c so that one end 6a can serve to provide an area for supporting regulatory IC 2 and a thermally radiative plate for discharging heat from MOS-FET 1, and a lagging 7 is formed on the other main surface 4b. Lagging 7 has a two-layered structure which comprises an electrically insulative and dielectric layer 7a attached to substrate 6, and a thermally insulative or adiabatic layer 7b of high heat transfer resistance, secured on dielectric layer 7a for supporting regulatory IC 2 on adiabatic layer 7b. Dielectric layer 7a is formed of for example polyimide resin such as KAPTON® film of non-porous or pinhole-free insulating resin, and has its inherent adhesive property which bonds dielectric layer 7a on a surface of one end 6a of connecting lead 4. Otherwise, an adhesive tape may be attached to a bottom surface of dielectric layer 7a to adhere dielectric layer 7a on one end 6a of connecting lead 4 through adhesive tape. Adiabatic layer 7b is formed of foamed or expandable plastics such as polyimide foam. Resistance against heat transfer through foamed adiabatic layer 7b is greater than that of substantially foamless dielectric layer 7a so that lagging 7 effectively prevents heat produced from MOS-FET 1 from traveling to regulatory IC 2. Although heat transfer resistance of lagging 7 increases if dielectric layer 7a is formed of foamed plastics similarly to adiabatic layer 7b, inconsistently and concurrently, whole electrical insulation of lagging 7 is deteriorated to fail to establish a reliable electrical insulation between connecting lead 4 and regulatory IC 2.

[0025] FIG. 4 shows a first preparation of lagging 7 by fusing a corrugated resinous film 16 on an adhesive plastic tape 15 under pressure to form voids 7d at given intervals between plastic tape 15 as a dielectric layer 7a and resinous film 16 as an adiabatic layer 7b. FIG. 5 illustrates a second preparation of lagging 7 by heating and joining a resinous covering film 18 on a resinous foamless base plate 17 under pressure wherein covering film 18 contains a foaming agent to provide an adiabatic layer 7b, and base plate 17 provides a dielectric layer 7a without foaming agent so that foaming agent in covering film 18 expands during heating to form gas bubbles 7c.

[0026] Control IC 2 is secured on adiabatic layer 7b via an adhesive agent 12 disposed therebetween. Adhesive agent 12 may be omitted if adiabatic layer 7b has the own adhesive property. A gate terminal of MOS-FET 1 is connected to an electrode not shown of regulatory IC 2 through a lead wire 8 striding across connecting lead 4. A plurality of electrodes not shown on regulatory IC 2 are electrically connected to corresponding ones 5c of lead terminals 5 disposed near support plate 3. A lead terminal 5b is formed integrally with support plate 3 to provide an electrified path so that electric current, namely main or drain current of MOS-FET 1 flows through support plate 3 and lead terminal 5b.

[0027] Thus, this embodiment can provide a semiconductor device in a smaller plane size incorporated with semiconducting elements, namely MOS-FET 1 and regulatory IC 2 of their smaller plane occupation area by piling and bonding in turn MOS-FET 1, connecting lead 4 and regulatory IC 2 on support plate 3 to form the stacked structure into a lead frame assembly. In this case, plane area of the other main surface 1b of MOS-FET 1 is preferably designed to be larger than plane area on one end 6a of connecting lead 4 which is designed to be larger than plane area of regulatory IC 2 to facilitate wiring and bonding of lead wires 8 and connecting lead 4.

[0028] In operation, drive pulses are applied from regulatory IC 2 through lead wire 8 to gate terminal of MOS-FET 1 to repetitively turn MOS-FET 1 on and off under control of regulatory IC 2. During the on-period of MOS-FET 1, drain current passes through support plate 3, MOS-FET 1 and connecting lead 4 between lead terminals 5b and 5a while MOS-FET 1 emits heat which can effectively and sufficiently be released from support plate 3 through solder 10 and simultaneously also discharged from lead wire 5a through solder 11 and substrate 6. This means that the obtained semiconductor device has the ample radiation performance and can send heavy electric current into MOS-FET 1. In this case, it should be noted that no heat is transferred to regulatory IC 2 although MOS-FET 1 produces increased amount of heat since lagging 7 of connecting lead 4 perfectly shuts off heat from MOS-FET 1. In addition, the device can prevent short circuit accident by undesirable electrical communication between MOS-FET 1 and regulatory IC 2 since dielectric layer 7a accomplishes a complete electric insulation between MOS-FET 1 and regulatory IC 2. As above-mentioned, lagging 7 has three functions for firstly firmly joining connecting lead 4 and regulatory IC 2, secondly thermally isolating MOS-FET 1 and regulatory IC 2 from each other, and thirdly electrically insulating MOS-FET 1 and regulatory IC 2 from each other. Also, the arrangement has the featured structure of connecting lead 4 which bridges and electrically joins between one lead terminal 5a and the other main surface 1b of MOS-FET 1 to electrically connect the other end 6b of connecting lead's substrate 6 to lead terminal 5a. Lead frame assembly of the above stacked structure is sealed with a plastic encapsulant in a well-known transfer molding technique, and at that time, melt resin pressure for encapsulation is applied to each part of lead frame assembly. Connecting lead 4 has the resistance to deformation by applied melt resin pressure during the transfer molding, thereby positively avoiding unfavorable electrical contact between connecting lead 4 and support plate 3 or other parts.

[0029] The above-mentioned embodiments of the present invention may be varied. For example, bump 4c of connecting lead 4 may be formed into an inverted J-shape as shown in FIG. 6. Also, an inverted U-shaped bend 4d may be formed in slant bump 4c. These inverted J-shaped bump 4c or U-shaped bend 4d serve to alleviate or absorb external force to lead terminals 5, support plate 3 or MOS-FET 1.

[0030] The present invention is particularly applicable to a semiconductor device of highly densified mounting which produces a large amount of heat.