Electronic device with a memory cell

[0001] 1. Field of the Invention

[0002] The present invention relates to an electronic device having a memory cell comprising a resistive storage element which can be switched between a first storage state having a first conductivity and a second storage state having a second conductivity.

[0003] 2. Description of the Related Art

[0004] In contrast to static random access memories (SRAM) and dynamic random access memories (DRAM), non-volatile memory devices preserve the stored information even if they are not supplied by electrical energy. They combine the advantages of random access memories (no mechanics and almost instant access to any bit of information) with advantages of hard disk drives and other permanent storage media (long-term storage without power consumption). Thus, non-volatile random access memory devices are advantageous for many applications, and high effort is made in their development and improvement.

[0005] A number of non-volatile random access memory technologies exist, each of which provides specific advantages and disadvantages. Several particularly advantageous and promising technologies use resistive storage elements. Each storage element can be switched between a first storage state having a first conductivity and a second storage state having a second conductivity. Each of the storage states represents a “0” or a “1”. Information is written to the storage element by means of a localized magnetic field (MRAM; based on the magneto-resistive effect), by a thermally induced or supported phase change (PCRAM; based on materials existing in two different crystallographic phases with differing resistances) or by a generation or degradation of conductive bridges in an otherwise insulating material (CBRAM; based on an induced migration of ions into a material or a remigration out of the material).

[0006] In an idle state of the memory cell, the cell transistor coupled between the resistive storage element and a bit line is in a highly resistive OFF-state. If the conductivity of the resistive storage element is very low in one of the storage states, in this storage state and the idle state of the memory cell, the memory cell comprises a floating node between the resistive storage element and the transistor. The potential of this floating node is easily influenced by electromagnetic fields and particularly by potentials of adjacent conductors. The influenced potential may induce an unintentional change of the storage state of the resistive storage element, thereby corrupting the information stored in the resistive storage element.

[0007] The present invention relates to an electronic device with a memory cell and a control circuit. The memory cell comprises a resistive storage element having a first terminal and a second terminal. The resistive storage element is switchable between a first storage state having a first conductivity and a second storage state having a second conductivity. The memory cell also comprises an access switch which is coupled to the first terminal of the resistive storage element and a node. The access switch connects the first terminal of the resistive storage element to the node in an access state of the memory cell and insulates the first terminal of the resistive storage element from the node in an idle state of the memory cell. The memory cell furthermore comprises a protecting switch which is connected to the resistive storage element. The protecting switch, in the idle state of the memory cell, reduces the voltage across the resistive storage element produced by electromagnetic interference and, in the access state of the memory cell, enables the reading and the writing of the storage states of the resistive storage element The control circuit is operatively coupled to the access switch and the protecting switch and is suitable to control the function of the access switch and the protecting switch in the access state and in the idle state of the memory cell.

[0008] Furthermore, the present invention relates to an electronic device with a memory cell. The memory cell comprises a resistive storage element having a first terminal and a second terminal. The resistive storage element is switchable between a first storage state having a first conductivity and a second storage state having a second conductivity. A first electronic switch is coupled to the first terminal of the resistive storage element and a data line for connecting the first terminal to the data line in an access state of the memory cell, and for insulating the first terminal from the data line in an idle state of the memory cell. A second electronic switch is coupled to the second terminal of the resistive storage element and a reference potential line, for connecting the second terminal to the reference potential line in the access state and for insulating the second terminal from the reference potential line in the idle state.

[0009] Furthermore, the present invention relates to an electronic device with a memory cell and a control circuit. The memory cell comprises a resistive storage element having a first terminal and a second terminal. The resistive storage element is switchable between a first storage state having a first conductivity and a second storage state having a second conductivity. A first electronic switch is coupled to the first terminal of the resistive storage element and a data line. A second electronic switch is coupled to the first terminal of the resistive storage element and a reference potential line. The control circuit is operatively coupled to the first and the second electronic switches and is suitable for controlling the first and the second electronic switches in such a way that the second electronic switch connects the first terminal to the reference potential line when the first electronic switch does not connect the first terminal to the data line, and such that the second electronic switch does not connect the first terminal to the reference potential line when the first electronic switch connects the first terminal to the data line.

[0010] Furthermore, the present invention relates to an electronic device with a memory cell and a control circuit. The memory cell comprises a resistive storage element having a first terminal and a second terminal. The resistive storage element may be switched between a first storage state having a first conductivity and a second storage state having a second conductivity. A first electronic switch is coupled to the first terminal of the resistive storage element and a data line. A second electronic switch is coupled to the first and second terminals of the resistive storage element. The control circuit is operatively coupled to the first and the second electronic switches and is suitable for controlling the first and the second electronic switches such that the second electronic switch connects the first terminal to the second terminal when the first electronic switch does not connect the first terminal to the data line, and such that the second electronic switch does not connect the first terminal to the second terminal when the first electronic switch connects the first terminal to the data line.

[0011] So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

[0012] FIG. 1 is a schematic circuit diagram of an electronic device according to an embodiment of the present invention;

[0013] FIG. 2 is a schematic circuit diagram of a first embodiment of a memory cell of the electronic device of FIG. 1;

[0014] FIG. 3 is a schematic circuit diagram of a second embodiment of a memory cell of the electronic device of FIG. 1;

[0015] FIG. 4 is a schematic circuit diagram of a third embodiment of a memory cell of the electronic device of FIG. 1;

[0016] FIG. 5A displays a circuit symbol and FIG. 5B displays a schematic microscopic view of an embodiment of a resistive storage element; and

[0017] FIG. 6 is a schematic diagram of voltage and current characteristics of one embodiment of the resistive storage element.

Overview

[0018] One aspect of the present invention provides an electronic device having a memory cell comprising a resistive storage element, the memory cell and the electronic device providing a reduced risk of corruption of the information stored therein by electromagnetic interference. The electronic device may be, for example, a non-volatile memory device with a large number of resistive storage elements each storing one bit of information whereby each of the storage states is identified with one of the bit states “0” and “1”.

[0019] Each memory cell may be provided with a transistor or another kind of switch, which serves as a protective switch. This protective switch, in an idle state of the memory cell when no data is written to or read from the memory cell, either short-circuits the resistive storage element or insulates the second terminal not coupled to the conventional cell transistor from ground or any other reference potential line. In both cases, any electromagnetic interference from outside the memory cell generally does not induce a voltage across the resistive storage element, or at least the induced voltage is considerably reduced by the protective switch.

[0020] In the first case, in the idle state of the memory cell, the protective switch is in its low resistive ON-state and short-circuits the two terminals of the resistive storage element. Thereby, the electrostatic potentials of the terminals of the resistive storage elements are pinned to each other and no voltage can be induced across the resistive storage element. Alternatively, the protective switch is coupled to the first terminal which is coupled to an access switch as well and to a reference potential line wherein the second terminal of the resistive storage element is coupled to the same reference potential line or to another reference potential line with a predetermined potential difference.

[0021] In the second case, in the idle state, the protective switch is in its highly resistive OFF-state insulating the second terminal from a reference potential line, whereby the first terminal of the resistive storage element is insulated from a data line by an access switch in its OFF-state. The access switch and the protective switch may provide about the same high resistance in their OFF-states. Both terminals of the resistive storage element float, and both terminals are influenced by electromagnetic interference to nearly the same extent. Thus, only relatively small voltages across the resistive storage element can be induced by electromagnetic interference. The smaller the difference between the resistances of the access switch and the protective switch in their OFF-states is, the smaller are the voltages induced across the resistive storage element.

[0022] The present invention provides protection against the corruption of stored information. Since electronic switches and, in particular, field effect transistors and bipolar transistors can be miniaturized to a high extent, the chip space required for each single memory cell is enlarged merely to a small extent.

[0023] Furthermore, the electronic device according to embodiments of the invention can be easily produced with conventional semiconductor technologies and low production costs.

[0024] Furthermore, the protective switch can be easily designed in such a way that it protects the resistive storage element from voltages induced electromagnetically even if the electronic device is not supplied with electrical power. For this purpose, the protective switch is a normally-ON-switch (in the first of the above-described two cases) or a normally-OFF-switch (in the second of the above-described two cases), respectively.

[0025] Aspects of the present invention may be applied to resistive storage elements with two or any higher number of resistance states or storage states.

[0026] FIG. 1 is a schematic circuit diagram of an electronic device 10 according to an embodiment of the present invention. In this embodiment, the electronic device 10 is a memory device with an input/output section 12 comprising receiving and transmitting circuits for communication with other devices, e.g., a processor of a computer, via control, address and data lines 14. Furthermore, the memory device 10 comprises a row address decoder 16 and a column address decoder 18 operatively connected to the input/output section 12. A number of read and write circuits 20 is operatively connected to the column address decoder 18. A number of bit lines 22 are arranged generally in parallel to each other. Each of the bit lines 22 is connected to one of the read and write circuits 20. A number of word lines 24 are arranged generally in parallel to each other and perpendicular to the bit lines 22. The word lines 24 are coupled to the row address decoder 16. At each intersection of a bit line 22 and a word line 24, a memory cell 30 is arranged. The memory cells 30 may be arranged generally as a rectangular array. Each memory cell 30 is connected to the adjacent bit line 22 and the adjacent word line 24.

[0027] The memory device 10 is connected to other devices or external circuits via the control, address and data lines 14. The input/output section 12 receives control, address and data signals. The control signals in particular comprise read and write commands for the memory device 10. The address signals indicate addresses identifying one or more memory cells from which data is to be read or into which data is to be written, respectively. The data signals represent the data which are to be written into the memory cells identified by the address signals.

[0028] Furthermore, the memory device 10 transmits data signals to other devices or external circuits via the input/output section 12 and the control, address and data lines 14. These data signals represent the data read from memory cells 30.

[0029] In accordance with an address received by the input/output section 12, the row address decoder 16 selects and activates one of the word lines 24 which is identified by the address and the column address decoder 18 selects one or more of the read and write circuits 20 which are identified by the address. Each selected read and write circuit 20 then reads data from or writes data to the memory cell 30, coupled to the activated word line 24 and connected to the selected read and write circuit 20 via one of the bit lines 22. In one embodiment, the components of input/output section 12, control, address and data lines 14, row address decoder 16, column address decoder 18, read and write circuit 20, bit line 22, and word line 24 make up the control circuit of the electronic device 10. The structure and the read and write operation of the memory cells 30 are described below with respect to FIGS. 2 to 6.

[0030] Although the electronic device 10 is described above and displayed in FIG. 1 as a memory device, it is to be noted that the present invention refers to all kinds of electronic devices with memory cells. The application of the present invention to memory devices is particularly advantageous as it will become clear from the description below, and the structure and architecture may considerably differ from FIG. 1. However, the present invention is also applicable and advantageous for other kinds of electronic devices with memory cells. For example, the electronic device may additionally comprise processing circuits, memory cells other than that described below and other electronic, microelectronic or micromechanical features.

[0031] According to one embodiment of the present invention, the memory cells 30 comprise a resistive storage element 40. The structure of each embodiment of the memory cell 30 is described below with respect to FIGS. 2 to 4. In the following description for the embodiments shown in FIGS. 2 to 4, the same component may be referenced individually or collectively with the same reference numeral while variations of the same component are designated with subscripts reflecting individual embodiments.

[0032] FIG. 2 is a schematic circuit diagram of a memory cell 30₁ according to one embodiment of the present invention. A first terminal 32, of the memory cell 30₁ is coupled to ground 34₁ or to a line providing any other constant reference potential. A second terminal 36₁ of the memory cell 30₁ is coupled to a data line. A third terminal 38₁ of the memory cell 30₁ is coupled to a control line. In the embodiment described above with respect to FIG. 1, the data line connected to the second terminal 36₁ is one of the bit lines 22, and the control line connected to the third terminal 38₁ is one of the word lines 24.

[0033] Furthermore, the memory cell 30₁ comprises a resistive storage element 40₁. The resistive storage element 40₁ may be switched between a first storage state having a first conductivity and a second storage state having a second conductivity. The difference between the first and the second conductivities may be a few multiples of ten percent up to several orders of magnitude. Both the first and second storage states are persistent over a long period of time (e.g., of at least several seconds, a few minutes, hours, days or even years). In one embodiment, each of the first and second storage states is indefinitely persistent at least under normal operating conditions (temperature, electromagnetic fields, etc.).

[0034] An important characteristic for the resistive storage element is an element showing hysteresis with respect to its resistance or conductivity, respectively, whereby each of the first and the second storage states is one of the saturation states of the hysteresis. One example for a resistive storage element 40 will be described below in more detail with respect to FIGS. 5 and 6.

[0035] The resistive storage element 40₁ has a first terminal 42₁ and a second terminal 44₁. A first switch or an access switch 46₁ is coupled to the first terminal 42₁ of the resistive storage element 40₁. A second switch or a protective switch 48₁ is coupled to the second terminal 44₁ of the resistive storage element 40₁. The first switch 46₁, the resistive storage element 40₁ and the second switch 48₁ are connected respectively in series between the second and the first terminals 36₁, 32₁ of the memory cell 30₁. The first and second switches 46₁, 48₁ are operatively coupled to the third terminal 38₁ of the memory cell 30₁ such that the first and the second switches 46₁, 48₁ can be controlled via the third terminal 38₁ of the memory cell 30₁.

[0036] In FIG. 2 as well as in the subsequently discussed FIGS. 3 and 4, the first and second switches 46, 48 are represented as field effect transistors (FET). FETs are frequently used in microelectronic devices and particularly in memory cells as they can be miniaturized to an extremely high extent. However, bipolar transistors and other electronic switches may be used as the first and the second switches 46, 48 in all the embodiments described with respect to FIGS. 2 to 4 as well.

[0037] Referring back to FIG. 2, in an idle state of the memory cell ³⁰¹, when no information is read from or written to the memory cell 30₁, the first and the second switches 46₁, 48₁ are in their OFF-states with a high resistance. Any voltage between the second terminal 36₁ and the first terminal 32₁ does not affect the resistive storage element 40₁ and is not able to change or switch its storage state of the resistive storage element 40₁.

[0038] In an access state of the memory cell 30₁, both the first and the second switches 46₁, 48₁ are in their ON-states with a high conductivity. Thereby, any voltage between the second terminal 36₁ and the first terminal 32₁ of the memory cell 30₁ is directly applied to the first and the second terminals 42₁, 44₁ of the resistive storage element 40₁. In this access state, the storage state of the resistive storage element 40₁ may be detected or read by measuring the resistance of the resistive storage element 40₁. Furthermore, in the access state, the storage state of the resistive storage element 40₁ may be changed or switched or written, as will be described in more detail for a specific embodiment of the memory cell 30 below with respect to FIGS. 5 and 6.

[0039] The first and the second switches 46₁, 48₁ are provided and coupled to the third terminal 38₁ such that both switch generally synchronously. The switches 46₁, 48₁ are either both in their OFF-states or both in their ON-states. In the case of the FET switches displayed in FIG. 2, either both switches 46₁, 48₁ are nFETs or both switches 46₁, 48₁ are pFETs.

[0040] In one embodiment, the first and the second switches 46₁, 48₁ are provided in such a way that both are in their OFF-states when the third terminal 38₁ of the memory cell 30₁ is connected to a low potential and both are in their ON-states when the third terminal 38₁ is connected to a high potential. In this case, the memory cell 30₁ is in its idle state when its third terminal 38₁ is at a low potential. When the electronic device 10 is not supplied with power and all potentials including the potentials of the first and third terminals 34₁, 38₁ of the memory cell 30₁ are equal (i.e., the potential of the third terminal 38₁ is low with respect to the potential of the first terminal 34₁), the memory cell 30₁ is in its idle state.

[0041] Alternatively, the first and the second switches 46₁, 48₁ may be provided in such a way that both are in their ON-states and the memory cell 30₁ is in its access state when a low potential is provided to its third terminal 38₁. When the electronic device 10 is not supplied with power, the memory cell 30₁ is in its access state.

[0042] Whenever the memory cell 30₁ is in its idle state, the resistive storage element 40₁ is to a large extent protected or shielded from any electromagnetic interference. Both terminals 42₁, 44₁ of the resistive storage element 40₁ are insulated since the first and the second switches 46₁, 48₁ are in their OFF-states. Any capacitive coupling or any other electromagnetic interference induced by the potential of any more or less adjacent other elements affects both terminals 42₁, 44₁ of the resistive storage element in generally the same manner. Since both terminals 42₁, 44₁ are insulated, the same potential is induced at both terminals 42₁, 44₁. Thus, no voltage or merely a very low voltage is induced across the resistive storage element 40₁. Therefore, no programming or switching or changing of the storage state of the resistive storage element 40₁ will occur.

[0043] In a conventional memory cell, one terminal of the resistive storage element is permanently connected to ground or any other reference potential. Any electromagnetic interference thus affects the other terminal. This results in a voltage across the resistive storage element. This voltage may be high enough to switch the storage state of the resistive storage element, thereby corrupting the information stored in the memory cell.

[0044] FIG. 3 is a schematic circuit diagram of the memory cell 30₂ according to another embodiment of the present invention. Again, a first terminal 32₂ of the memory cell 30₂ is connected to ground 34₂ or to a line providing a constant reference potential. A first switch or an access switch 46₂ is coupled to a second terminal 36₂ of the memory cell 30₂ and to a first terminal 42₂ of a resistive storage element 40₂. A second terminal 44₂ of the resistive storage element 40₂ is connected to ground 34₂ via the first terminal 32₂ of the memory cell 30₂. A second switch or a protective switch 48₂ is connected to (i.e., across) the first and second terminals 42₂, 44₂ of the resistive storage element 40₂. Both the access switch 46₂ and the protective switch 48₂ are operatively connected to the third terminal 38 of the memory cell 30₂ such that both switches may be controlled simultaneously by potentials at the third terminal 38. The first and the second switches 46₂, 48₂ are provided in such a way that one of the switches 46₂, 48₂ is in an OFF-state and the other of the switches 46₂, 48₂ is in an ON-state when there is a low potential at the third terminal 38₂ of the memory cell 30₂ and the other way around when there is a high potential at the third terminal 38₂.

[0045] In an idle state of the memory cell 30₂, the access switch 46₂ is in its OFF-state insulating the first terminal 42₂ of the resistive storage element 40₂ from the second terminal 36₂ of the memory cell 30₂. Simultaneously, the protective switch 48₂ is in an ON-state short-circuiting or bypassing the resistive storage element 40₂ or its terminals 42₂, 44₂, respectively. Due to this short circuit, no voltage across the resistive element 40₂ can be induced by capacitive coupling or by any other electromagnetic interference. Thereby, the resistive storage element 40₂ is efficiently protected or shielded against any unwanted change of its storage state.

[0046] In an access state of the memory cell 30₂, the access switch 46₂ is in its ON-state connecting the first terminal 42₂ of the resistive storage element 40₂ to the second terminal 36₂ of the memory cell 30₂. Simultaneously, the protective switch 48₂ is in its OFF-state, thereby not connecting (or not short-circuiting) the terminals 42₂, 44₂ of the resistive storage element 40₂. In this access state, the storage state of the resistive storage element 40₂ may be detected, read, changed, switched or written via the second terminal 36₂ of the memory cell 30₂.

[0047] In FIG. 3, the access switch 46₂ is a nFET, and the protective switch 48₂ is a pFET. The gates of both are coupled to the third terminal 38₂ of the memory cell 30₂. When a low potential (with reference to ground 34₂) is provided to the third terminal 38₂ of the memory cell 30₂, the access switch 46₂ is in its OFF-state while the protective switch 48₂ is in its ON-state, and the memory cell 30₂ is in its idle state. When a high potential (with reference to ground 34) is provided to the third terminal 38₂ of the memory cell 30₂, the access switch 46₂ is in its ON-state while the protective switch 48₂ is in its OFF-state, and the memory cell 30₂ is in its access state. Again, this means that the memory cell 30₂ is in its idle state, and the resistive storage element 40₂ is protected from an unwanted change of its storage state, if no power is supplied to the electronic device 10 and all potentials at the terminals 32₂, 36₂, 38₂ of the memory cell 30₂ are generally equal.

[0048] Alternatively, the access switch 46₂ is a pFET, and the protective switch 48₂ is a nFET. In this case, the memory cell 30₂ is in its idle state when a high potential (with respect to ground 34₂) is provided to the third terminal 38₂ of the memory cell 30₂.

[0049] FIG. 4 is a schematic circuit diagram of a memory cell 30₃ according to a third embodiment of the present invention. This embodiment differs from the embodiment described above with respect to FIG. 3 in that the protective switch 48₃ is coupled to the first terminal 42₃ of the resistive storage element 40₃ and to a fourth terminal 50 of the memory cell 30₃. In the idle state of the memory cell 30₃, the first terminal 42₃ of the resistive storage element 40₃ is connected to the fourth terminal 50 of the memory cell 30₃ instead of the second terminal 44₃ of the resistive storage element 40₃. A second constant reference potential may be provided to the fourth terminal 50 of the memory cell 30₃, and the potential difference or voltage between the first and fourth terminals 32₃, 50 of the memory cell 30₃ is a protective voltage, as will be described in detail below with respect to FIG. 6.

[0050] FIG. 5A displays the circuit symbol of the resistive storage element 40, and FIG. 5B is a schematic microscopic view of one embodiment of the resistive storage element 40. A first electrode 62 comprising a chemically reactive material is connected to the first terminal 42, and a second electrode 64 comprising a chemically inert material is connected to the second terminal 44 of the resistive storage element 40. An insulator 66 is provided between the first and the second electrodes 62, 64. Metal-rich clusters 68 are formed in the insulator 66. In a first state of the resistive storage element 40, most of the clusters 68 are isolated from each other in such a way that they do not form a conducting connection between the electrodes 62, 64. The insulator 66 insulates the electrodes 62, 64 from each other and the resistive storage element 40 provides a high resistance.

[0051] When a sufficiently high voltage is applied to the electrodes 62, 64, an electrochemical reaction occurs at the chemically reactive first electrode 62 and metal ions from the first electrode 62 are driven into the insulator 66. These additional ions enlarge the existing clusters 68 or form new clusters such that a conductive bridge 70 is formed by a number of clusters 68 which are in contact with each other. The conductive bridge 70 significantly reduces the resistance of the resistive storage element 40. Typically, the conductivity or the resistance, respectively, of the resistive storage element 40 differs by several orders of magnitude between the two states. An element like this is also typically called a conductive bridging junction (CBJ). A typical resistance of a CBJ is in the range of about 10¹⁰Ω to 10¹¹Ω in the OFF-state and about 10⁴Ω to 10⁵Ω in the ON-state.

[0052] According to an example, the first or the active electrode 62 comprises or is made of silver. The second or chemically inert electrode 64 comprises or is made of tungsten. The insulator 66 comprises an insulating chalcogenide-glass (e.g., GeSe). Silver ions or other metal ions with high mobility are diffused into the insulator 66 (e.g., by photo-diffusion) and form the localized highly conductive regions or clusters 68. The first electrode 62 forms the anode and is represented by a black bar in the circuit symbol shown in FIG. 5A. The second electrode 64 is the cathode of the CBJ.

[0053] From the description of the resistive storage element 40, it is clear that the read and write circuits 20 shown in FIG. 1 need to be different from conventional sense amplifiers of DRAMs. It will become clear from the subsequently discussed schematic diagram displayed in FIG. 6 which features are advantageously comprised in each read and write circuit 20.

[0054] The data schematically displayed in FIG. 6 has been acquired with a combination of a current source and a current limiter for writing, or switching the storage state of the resistive storage element 40 and with a voltage source and a current detector for detecting or reading the storage state of the resistive storage element 40. However, a simplified configuration is possible wherein the current source, the current limiter, the voltage source and the voltage detector are more or less integrated. A current-limiting facility or feature is necessary to avoid a (thermal) destruction of the resistive storage element 40 once a conductive bridge 70 is formed and the resistance of the resistive storage element 40 is low. FIG. 6 schematically displays the correlation of voltage V at and current I through a serial connection of the CBJ or the resistive storage element 40 and a current limiter.

[0055] The correlation of voltage V and current I includes a first branch 82, 84, 86 corresponding to a high conductivity of the resistive storage element 40 and a second branch 92, 94 corresponding to a low conductivity of the resistive storage element 40. The first branch 82, 84, 86 comprises a generally horizontal section 82. In this section, caused by the above-mentioned current limiter, the current I is generally constant and independent from the voltage V across the serial connection of the resistive storage element and the current limiter.

[0056] When the resistive storage element 40 is in the low conductivity state and no conductive bridge 70 exists, the current I is about zero (branches 92, 94). This low conductive state exists up to a first threshold voltage V_th1 which mainly depends on the materials and the geometrical properties of the resistive storage element 40. For the measurements presented here, the value of the first threshold voltage V_th1 is about 200 mV to 250 mV.

[0057] When the voltage V exceeds the first threshold voltage V_th1, the above-mentioned electrochemical reaction at the chemically reactive anode 62 starts and ions are driven from the anode 62 into the insulator 66. Existing clusters 68 grow and/or new clusters emerge and the conductive bridge 70 is formed. Thereby, the conductivity of the resistive storage element 40 increases quickly (first transition branch 96) and the resistive storage element 40 arrives at the high conductivity state represented by the first branch 82, 84, 86.

[0058] The high conductivity state represented by the first branch 82, 84, 86 exists for voltages above a second threshold voltage V_th2. When the voltage V falls below the second threshold voltage V_th2, the ions are driven out of the insulator 66, and the electrochemical reaction at the chemically reactive anode 62 is reversed. Thereby, clusters 68 are made smaller or even disappear. The conductive bridge 70 is degraded and disappears and the conductivity of resistive storage element 40 is reduced (second transition branch 88). The resistive storage element 40 arrives at the low conductivity state represented by the second branch 92, 94.

[0059] In one embodiment, in both the low conductivity state and the high conductivity state, a voltage sufficiently exceeding the first threshold voltage V_th1 or sufficiently below the second threshold voltage V_th2, respectively, is maintained for a predetermined period of time to arrive at a well-defined state. Each of the low conductivity and high conductivity states serves as one of a first and a second storage state representing one of a logical “0” and a logical “1”.

[0060] As already mentioned above, the electrochemical reaction at the chemically reactive anode 62 starts, and ions are driven into or out of the insulator 66 as soon as the voltage V exceeds the first threshold voltage V_th1 or falls below the second threshold voltage V_th2, respectively. The size of the clusters 68, the number of conductive contacts between clusters 68, and thereby the conductivity of the conductive bridge 70 or even the number of conductive bridges roughly depend on the number of ions in the insulator 66. The number of ions in the insulator 66 depends on the total charge which flowed through the resistive storage element 40 at a voltage V exceeding the first threshold voltage V_th1 or below the second threshold voltage V_th2. Therefore, the conductivity of the resistive storage element 40 can be set or adjusted to more than two different values by controlling the current I and/or the period of time the resistive storage-element is exposed to a voltage V>V_th1 or V<V_th2. In this way, more than two different conductivity states representing an analogous number of storage states may be used, and a single memory cell may store more than only the values “0” and “1”, but also the values “2”, “3” etc.

[0061] For reading the conductivity state or storage state, respectively, of the resistive storage element 40, a predefined reading voltage V_r between the first threshold voltage V_th1 and the second threshold voltage V_th2 is applied to the resistive storage element 40. The current flowing at this reading voltage V_r is detected to detect the conductivity state and the storage state. In the binary case with two storage states, a low current means that the resistive storage element 40 is in the low conductivity state and a high current means that the resistive storage element 40 is in the high conductivity state.

[0062] The direction of the electrochemical reaction (oxidation or reduction) at the chemically reactive anode 62 and the direction of motion of the ions in the insulator 66 depend on the polarity of the voltage applied to the resistive storage element 40. Therefore, it does make a difference whether the anode or the cathode of the resistive storage element are oriented towards the second terminal 36 of the memory cell 30 and the bit line 22. However, the resistive storage element 40 may be integrated into each of the embodiments of the memory cell 30 described above with reference to FIGS. 2 to 4 in a reversed orientation as long as the read and write circuits 20 and the voltages and currents produced and detected by these are adapted correspondingly.

[0063] Resistive storage elements other than the CBJ described above with reference to FIGS. 5 and 6 may be used as well. Depending on the type of resistive storage element, it may be advantageous to apply a voltage to the fourth terminal 50 of the embodiment of the memory cell 30 described above with reference to FIG. 4 which is different from the potential of the ground 34. In particular, it may be advantageous to apply a protective voltage to the resistive storage element 40 in the idle state of the memory cell 30 which is near the middle or average of the voltages at which a change of the conductivity state is induced. In the embodiment described above, it may be particularly advantageous to apply the reading voltage V_r or a voltage between 0 and the reading voltage V_r to the resistive storage element 40 when the memory cell 30 is in its idle state.

[0064] As already mentioned above, the present invention can also be applied to a resistive storage element with three or more different storage states. In this case the present invention particularly protects the resistive storage element 40 in all its lowly conductive storage states in which the potential of one node is more or less floating and electromagnetic interference may induce a voltage V>V_th1 or V<V_th2.

[0065] Both switches 46, 48 of the memory cell 30 provide generally the same high resistance in their OFF-states. A switch 46, 48 in its highly resistive OFF-state is understood as not connecting. Likewise, a switch 46, 48 in its highly conductive ON-state is connecting.

[0066] The switches 46, 48 may be controlled via two different word lines. This may be particularly advantageous in the embodiments described above with reference to FIGS. 3 and 4 where both switches 46, 48 are not of the same type (nFET or pFET). One of these word lines controls the access switches 46 of the memory cells 30 and the other word line controls the protective switches 48 while one of the word lines is active and the other is inactive and vice versa.

[0067] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.