DC-DC converter utilizing a modified Schmitt trigger circuit and method of modulating a pulse width

[0001] This application claims priority to Korean Patent Application No. 2005-26110, filed on Mar. 29, 2005, the contents of which are herein incorporated by reference in its entirety.

[0002] 1. Technical Field

[0003] The present invention relates to a DC-DC converter and a method of controlling the same. More particularly, the present invention relates to a DC-DC converter utilizing a modified Schmitt trigger circuit and a method of modulating a pulse width.

[0004] 2. Description of the Related Art

[0005] DC-DC converters are used in many types of mobile electronic devices to provide a fixed output voltage. Pulse width modulation (PWM) has become a widely-used technique for controlling DC-DC converters. The DC-DC converter employing a conventional PWM method compares a reference input signal with a ramp signal outputted from an oscillator and generates a pulse signal having a duty cycle (or a duty ratio) that is proportional to the reference input signal. The pulse signal is amplified by a power switch and rectified by a filter consisting of an inductor and a capacitor to generate an output voltage that is proportional to the reference input signal. The output of the DC-DC converter is stabilized by a negative feedback circuit.

[0006] The conventional DC-DC converter that includes the oscillator for generating the ramp signal takes up a large amount of chip space in a semiconductor integrated circuit and exhibits relatively high power consumption.

[0007] Examples of DC-DC converters that generate an oscillated signal using a feedback loop without using an oscillator are disclosed in U.S. Pat. Nos. 5,481,178 and 5,770,940. FIG. 1 is a circuit diagram illustrating the conventional DC-DC converter having dual feedback loops as disclosed in U.S. Pat. No. 5,770,940.

[0008] The DC-DC converter shown in FIG. 1 is an example of a step-down switching regulator. Referring to FIG. 1, the switching regulator includes an error amplifier 106, a comparator 102, a switch 84, and an LC filter 86 consisting of an inductor 88 and a capacitor 90.

[0009] The switch 84 includes an input 92, an output line 94, and a control line 96. A diode 98 provides a current path for the inductor 88 when the switch 84 is opened. As shown in FIG. 1, the switching regulator circuit includes two feedback loops, i.e., a first feedback loop 100 including a first feedback circuit 114, and a second feedback loop 104 including a second feedback circuit 113.

[0010] The first feedback loop 100 is a quick response feedback loop that includes the comparator 102 and a driver (not shown). The comparator 102 includes built-in hysteresis, thereby providing a hysteretic window defining an upper voltage limit and a lower voltage limit.

[0011] The second feedback loop 104 is a relatively slow response feedback loop that includes the error amplifier 106. The slow response feedback loop can be used to sense a voltage at a point external to the DC-DC converter.

[0012] In the conventional DC-DC converter shown in FIG. 1, frequency of an output voltage VOUT is determined by the comparator 102 with built-in hysteresis.

[0013] Exemplary embodiments of the present invention provide a DC-DC converter and a method of modulating a pulse width.

[0014] In an exemplary embodiment of the present invention, a DC-DC converter includes a pulse width modulation (PWM) modulator, a power switch and a filter. The PWM modulator is configured to positively feed back a pulse width modulated signal of which a pulse width and a frequency are varied to generate an oscillated signal, configured to amplify a difference between a negatively fed-back direct current output signal and a reference signal to output a first signal, and configured to compare the first signal with the oscillated signal to generate a first switching signal and a second switching signal. The power switch is configured to transfer an input signal to a first output node in response to the first switching signal and the second switching signal, and configured to generate the pulse width modulated signal, wherein the pulse width modulated signal is provided to the first output node. The filter generates a direct current output voltage signal in response to the pulse width modulated signal, wherein the direct current output voltage signal is provided to a second output node.

[0015] In an exemplary embodiment of the present invention, a DC-DC converter includes an amplifier, a comparator, a switch driver, a power switch, a filter, a negative feedback circuit, and a positive feedback circuit. The amplifier is configured to amplify a difference between a reference signal and a first feedback signal to generate a first signal. The comparator is configured to compare a second feedback signal with the first signal to generate a second signal. The switch driver is configured to generate a first switching signal and a second switching signal in response to the second signal. The power switch is configured to transfer an input signal to a first output node in response to the first switching signal and the second switching signal, and generates a pulse width modulated signal of which a pulse width and a frequency are varied, wherein the pulse width modulated signal is provided to the first output node. The filter is configured to generate a direct current output voltage signal in response to the pulse width modulated signal, wherein the direct current output voltage signal is provided to a second output node. The negative feedback circuit is configured to generate the first feedback signal in response to the direct current output voltage signal. The positive feedback circuit is configured to generate the second feedback signal oscillated in response to the pulse width modulated signal.

[0016] In an exemplary embodiment of the present invention, a DC-DC converter includes an amplifier, an anti-overlap circuit, a switch driver, a power switch, a filter, a negative feedback circuit, and a positive feedback circuit. The amplifier is configured to amplify a difference between a reference signal and a first feedback signal to generate a first signal. The comparator is configured to compare a second feedback signal with the first signal to generate a second signal. The anti-overlap circuit is configured to generate a first pulse signal and a second pulse signal in response to the second signal, the second pulse signal having a second pulse width wider than a first pulse width of the first pulse signal. The switch driver is configured to generate a first switching signal and a second switching signal in response to the first pulse signal and the second pulse signal. The power switch is configured to transfer an input signal to a first output node in response to the first switching signal and the second switching signal and is configured to generate a pulse width modulated signal of which a pulse width and a frequency are varied, wherein the pulse width modulated signal is provided to the first output node. The filter is configured to generate a direct current output voltage signal in response to the pulse width modulated signal, wherein the direct current output voltage signal is provided to a second output node. The negative feedback circuit is configured to generate the first feedback signal in response to the direct current output voltage signal. The positive feedback circuit is configured to generate the second feedback signal oscillated in response to the pulse width modulated signal.

[0017] In an exemplary embodiment of the present invention, a method of modulating a pulse width includes: positively feeding back a pulse width modulated signal to generate an oscillated signal; negatively feeding back a direct current output signal; amplifying a difference between the negatively fed-back direct current output signal and a reference signal to output a first signal; comparing the first signal with the oscillated signal to generate a first switching signal and a second switching signal; amplifying a difference between the negatively fed-back direct current output signal and the reference signal, comparing the oscillated signal with the reference signal and generating the first switching signal and the second switching signal, wherein the direct current output signal follows the reference signal; transferring an input signal to a first output node in response to the first switching signal and the second switching signal to generate a pulse width modulated signal of which a pulse width and a frequency are varied at the first output node; and generating a direct current output voltage signal at a second output node in response to the pulse width modulated signal.

[0018] The present invention will become more apparent to those of ordinary skill in the art when descriptions of exemplary embodiments thereof are read with reference to the accompanying drawings.

[0019] FIG. 1 is a circuit diagram illustrating a conventional DC-DC converter having dual feedback loops.

[0020] FIG. 2A is a schematic circuit diagram illustrating a Schmitt trigger circuit.

[0021] FIG. 2B is a waveform diagram illustrating waveforms of signals associated with the Schmitt trigger circuit shown in FIG. 2A.

[0022] FIG. 3 is a detailed circuit diagram illustrating the Schmitt trigger circuit shown in FIG. 2A.

[0023] FIG. 4A is a circuit diagram illustrating a modified Schmitt trigger circuit according to an exemplary embodiment of the present invention.

[0024] FIG. 4B is a waveform diagram illustrating waveforms of signals associated with the modified Schmitt trigger circuit shown in FIG. 4A.

[0025] FIG. 5 is a circuit diagram illustrating a DC-DC converter employing a modified Schmitt trigger circuit according to an exemplary embodiment of the present invention.

[0026] FIG. 6 is a circuit diagram illustrating a DC-DC converter employing a modified Schmitt trigger circuit according to another exemplary embodiment of the present invention.

[0027] FIG. 7 is a circuit diagram illustrating an anti-overlap circuit included in the DC-DC converter shown in FIG. 6 according to an exemplary embodiment of the present invention.

[0028] FIG. 8 is a timing diagram illustrating signals associated with the anti-overlap circuit shown in FIG. 7.

[0029] FIGS. 9A and 9B are waveform diagrams illustrating simulation results of the anti-overlap circuit shown in FIG. 7.

[0030] FIG. 10 is a circuit diagram illustrating an anti-overlap circuit included in the DC-DC converter shown in FIG. 6 according to another exemplary embodiment of the present invention.

[0031] FIGS. 11A through 11C are waveform diagrams illustrating simulation results of the DC-DC converter shown in FIG. 6 in a case where a reference voltage is equal to about 1 volt.

[0032] FIGS. 12A through 12C are waveform diagrams illustrating simulation results of the DC-DC converter shown in FIG. 6 in a case where a reference voltage is equal to about 2 volts.

[0033] FIG. 13 is a schematic circuit diagram illustrating a system employing a DC-DC converter according to an exemplary embodiment of the present invention, which generates an output voltage of about 0 volts through about 3.6 volts.

[0034] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to similar or identical elements throughout the description of the figures.

[0035] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections, should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. For example, a first element could be termed a second element. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0036] It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

[0037] FIG. 2A is a schematic circuit diagram illustrating a Schmitt trigger circuit. FIG. 2B is a waveform diagram illustrating waveforms of signals associated with the Schmitt trigger circuit shown in FIG. 2A. Referring to FIG. 2A, the Schmitt trigger circuit has a hysteresis characteristic and includes a feedback circuit RF and a capacitor CF.

[0038] As shown in FIG. 2B, an input signal VP of the Schmitt trigger circuit exhibits a sawtooth waveform or a triangle waveform, and an output signal VO exhibits a pulse waveform. Additionally, the Schmitt trigger circuit has a high threshold voltage VTH and a low threshold voltage VTL. The high threshold voltage VTH may be defined as an upper limit that the input signal VP can reach when the output signal VO transitions from a logic ‘low’ state to a logic ‘high’ state. The low threshold voltage VTL may be defined as a lower limit that the input is signal VP can reach when the output signal VO transitions from the logic ‘high’ state to the logic ‘low’ state.

[0039] FIG. 3 is a detailed circuit diagram illustrating the Schmitt trigger circuit shown in FIG. 2A. Referring to FIG. 3, the Schmitt trigger circuit includes a comparator 151, an inverter 152, resistors R1, R2 and R3, a feedback circuit RF and a capacitor CF.

[0040] A high threshold voltage VTH and a low threshold voltage VTL may be expressed by the following equations 1 and 2. $\begin{array}{cc}\mathrm{VTL}=\frac{R2}{(R1R3)+R2}\times \mathrm{VDD}& \left[\mathrm{Equation}1\right]\end{array}$

[0041] where “R|R3” denotes the sum of the resistances of parallel resistors R1 and R3. $\begin{array}{cc}\mathrm{VTH}=\frac{(R2R3)}{R1+(R2R3)}\times \mathrm{VDD}& \left[\mathrm{Equation}2\right]\end{array}$

[0042] where “R2|R3” denotes the sum of the resistances of parallel resistors R2 and R3.

[0043] An oscillated frequency “fo” of the Schmitt trigger circuit shown in FIG. 3 may be expressed by the following equation 3. $\begin{array}{cc}\mathrm{fo}=\frac{1}{\mathrm{RF}\times \mathrm{CF}\times \left(\frac{\mathrm{VTH}}{\mathrm{VTL}}\times \frac{\mathrm{VDD}-\mathrm{VTL}}{\mathrm{VDD}-\mathrm{VTH}}\right)}& \left[\mathrm{Equation}3\right]\end{array}$

[0044] FIG. 4A is a circuit diagram illustrating a modified Schmitt trigger circuit according to an exemplary embodiment of the present invention. FIG. 4B is a waveform diagram illustrating waveforms of signals associated with the modified Schmitt trigger circuit shown in FIG. 4A.

[0045] Referring to FIG. 4A, the modified Schmitt trigger circuit includes an operational amplifier 210, a comparator 220, an inverter 230, a filter 240, a resistor RF and a capacitor CF. The operational amplifier 210 amplifies a voltage difference between an output signal VO of the modified Schmitt trigger circuit and a reference signal VREF. The comparator 220 compares an output signal VNF of the operational amplifier 210 with a feedback signal VPF to generate a pulse signal. The inverter 230 inverts an output signal of the comparator 220 and improves current drive capability. The filter 240 rectifies an output signal VIO, of the inverter 230, which has a pulse waveform to convert the rectified output signal to a direct current voltage signal VO. For example, the filter 240 may be implemented using an inductor and a capacitor.

[0046] Referring to FIG. 4B, the output signal VIO of the inverter 230 exhibits a pulse waveform, and the feedback signal VPF exhibits a sawtooth waveform.

[0047] Referring again to FIG. 4A, when a voltage level of the direct current voltage signal VO is higher than that of the reference signal VREF, the output signal VNF of the operational amplifier 210 may be equal to a low power voltage provided to the operational amplifier 210; for example, the output signal VNF may be equal to about 0 volts. When the voltage level of the direct current voltage signal VO is lower than that of the reference signal VREF, the output signal VNF of the operational amplifier 210 may be equal to a high power voltage VDD provided to the operational amplifier 210; for example, the output signal VNF may be equal to VDD.

[0048] As described above, the modified Schmitt trigger circuit shown in FIG. 4A rectifies the output signal VIO of the inverter 230 to generate the direct current voltage signal VO, and feeds back the direct current voltage signal VO to an inverting input terminal of the operational amplifier 210 to compare the fed-back direct current voltage signal VO with the reference signal VREF. The output signal VNF of the operational amplifier 210 may have a ‘high’ level or a ‘low’ level.

[0049] The modified Schmitt trigger circuit shown in FIG. 4A operates like a Schmitt trigger circuit using two threshold voltages. The low threshold voltage VTL and the high threshold voltage VTH are varied based on a magnitude of the reference signal VREF. The output signal VIO of the inverter 230 has a duty cycle (or a duty ratio) and a frequency varied in response to the reference signal VREF. The modified Schmitt trigger circuit shown in FIG. 4A operates so that a voltage level of the direct current voltage signal VO becomes equal to that of the reference signal VREF.

[0050] FIG. 5 is a circuit diagram illustrating a DC-DC converter employing a modified Schmitt trigger circuit according to an exemplary embodiment of the present invention. Referring to FIG. 5, the DC-DC converter includes an operational amplifier 310, a comparator 320, a switch driver 330, a power switch 340, a filter 350, a negative feedback circuit 370 and a positive feedback circuit 360.

[0051] The operational amplifier 310 amplifies a voltage difference between a reference signal VREF and a first feedback signal SFEED to generate a first signal VNF. The comparator 320 compares a second feedback signal VPF with the first signal VNF to generate a second signal VCO. The switch driver 330 generates a first switching signal VP and a second switching signal VN in response to the second signal VCO.

[0052] The power switch 340 transfers an input signal VI to a first output node NO1 in response to the first switching signal VP and the second switching signal VN, to generate a pulse width modulated signal VLX of which a pulse width and a frequency are varied at the first output node NO1. The filter 350 generates a direct current output voltage signal VO at a second output node NO2 in response to the pulse width modulated signal VLX. The negative feedback circuit 370 generates the first feedback signal SFEED in response to the direct current output voltage signal VO. The positive feedback circuit 360 generates the second feedback signal VPF oscillated in response to the pulse width modulated signal VLX.

[0053] The negative feedback circuit 370 may include a first resistor R12 and a second resistor R13. A first terminal of the first resistor R12 is coupled to the second output node NO2, and a second terminal of the first resistor R12 is coupled to an inverting input terminal of the operational amplifier 310.

[0054] The positive feedback circuit 360 may include a resistor R11 and a capacitor C12. A first terminal of the first resistor R11 is coupled to the first output node NO1, and a second terminal of the first resistor R11 is coupled to a non-inverting input terminal of the comparator 320. The capacitor C12 is coupled between the second terminal of the resistor R11 and ground.

[0055] The DC-DC converter shown in FIG. 5 positively feeds back the pulse width modulated signal VLX to the positive feedback circuit 360 to generate the second feedback signal VPF. Additionally, the DC-DC converter shown in FIG. 5 negatively feeds back the direct current output voltage signal VO to the negative feedback circuit 370 to compare the first feedback signal SFEED with the reference signal VREF, and then generates the switching signals VP and VN so that the direct current output voltage signal VO follows the reference signal VREF.

[0056] FIG. 6 is a circuit diagram illustrating a DC-DC converter employing a modified Schmitt trigger circuit according to another exemplary embodiment of the present invention. The DC-DC converter shown in FIG. 6 includes an anti-overlap circuit 390, which is not included in the DC-DC converter shown in FIG. 5.

[0057] Referring to FIG. 6, the DC-DC converter includes an operational amplifier 310, a comparator 320, the anti-overlap circuit 390, a switch driver 330, a power switch 340, a filter 350, a negative feedback circuit 370 and a positive feedback circuit 360.

[0058] The operational amplifier 310 amplifies a voltage difference between a reference signal VREF and a first feedback signal SFEED to generate a first signal VNF. The comparator 320 compares a second feedback signal VPF with the first signal VNF to generate a second signal VCO. The anti-overlap circuit 390 generates a first pulse signal V1 in response to the second signal VCO. Additionally, the anti-overlap circuit 390 generates a second pulse signal V2 having a pulse width wider than that of the first pulse signal V1. In an exemplary embodiment of the present invention, the second pulse signal V2 has high levels and low levels identical with those of the first pulse signal V1 over the same time intervals.

[0059] The switch driver 330 generates a first switching signal VP and a second switching signal VN in response to the first pulse signal V1 and the second pulse signal V2. The power switch 340, which transfers an input signal VI to a first output node NO1 in response to the first switching signal VP and the second switching signal VN, generates a pulse width modulated signal VLX of which a pulse width and a frequency are varied at the first output node NO1. The filter 350 generates a direct current output voltage signal VO at a second output node NO2 in response to the pulse width modulated signal VLX.

[0060] The negative feedback circuit 370 generates the first feedback signal SFEED in response to the direct current output voltage signal VO. The positive feedback circuit 360 generates the second feedback signal VPF oscillated in response to the pulse width modulated signal VLX.

[0061] FIG. 7 is a circuit diagram illustrating an anti-overlap circuit included in the DC-DC converter shown in FIG. 6 according to an exemplary embodiment of the present invention. Referring to FIG. 7, the anti-overlap circuit 390 includes a first NOR gate 392 and a second NOR gate 393, a first inverter 391 through a seventh inverter 399, and a first capacitor C31 and a second capacitor C32.

[0062] The first inverter 391 inverts a clock signal CLK, such as the second signal VCO of FIG. 6. The first NOR gate 392 performs a logical NOR operation on the second signal VCO and a third signal CLKP. The first capacitor C31 is coupled to an output terminal of the first NOR gate 392. The second inverter 394 inverts an output signal VA of the first NOR gate 392. The third inverter 395 inverts an output signal of the second inverter 394 to generate a fourth signal DCLKP. The fourth inverter 398 inverts an output signal of the third inverter 395 to generate a second pulse signal V2. The second NOR gate 393 performs a logical NOR operation on the output signal DCLK of the first inverter 391 and the fourth signal DCLKP. The second capacitor C32 is coupled to an output terminal of the second NOR gate 393. The fifth inverter 396 inverts an output signal VB of the second NOR gate 393. The sixth inverter 397 inverts an output signal of the fifth inverter 396 to generate the third signal CLKP. The seventh inverter 399 inverts an output signal of the fifth inverter 396 to generate a first pulse signal V1.

[0063] FIG. 8 is a timing diagram illustrating signals associated with the anti-overlap circuit shown in FIG. 7. In the timing diagram shown in FIG. 8, a time period delayed by the inverters and the NOR gates shown in FIG. 7 is assumed as ‘d’, and a delayed time due to the capacitors C31 and C32 is not considered.

[0064] Referring to FIG. 8, the second pulse signal V2 has a pulse width wider than that of the first pulse signal V1, and a time region where the second pulse signal V2 is at a logic ‘high’ level and the first pulse signal V1 is at a logic ‘low’ level, exists at each pulse. During the time region, a P-type switch (not shown) and an N-type switch (not shown) comprising the power switch 340 shown in FIG. 6 are turned off.

[0065] Such a dead time of a switching operation is required for preventing flow of a large current in a case where the P-type switch (not shown) and the N-type switch (not shown), comprising the power switch 340 shown in FIG. 6, are both turned on. When the delayed time due to the capacitors C31 and C32 shown in FIG. 7 is considered, an entire delayed time period is determined by the capacitors C31 and C32 rather than the inverters 391, 394 through 399 and the gates 392 and 393.

[0066] FIGS. 9A and 9B are waveform diagrams illustrating simulation results of the anti-overlap circuit 390 shown in FIG. 7. For the simulation, a capacitor having a capacitance of about 0.1 pF is used for the capacitors C31 and C32.

[0067] FIG. 9A is a waveform diagram illustrating a waveform of the output signal VCO of the comparator 320 shown in FIG. 6, and FIG. 9B is a waveform diagram illustrating waveforms of the first pulse signal V1 and the second pulse signal V2 outputted from the anti-overlap circuit 390.

[0068] As shown in FIG. 9B, the second pulse signal V2 encloses the first pulse signal V1, and a time region where the second pulse signal V2 is at the logic ‘high’ level and the first pulse signal V1 is at the logic ‘low’ level exists at each pulse. Additionally, a pulse width of the second pulse signal V2 is larger than that of the first pulse signal V1 by as much as AW1 in a left direction, and is larger than that of the first pulse signal V1 by as much as AW2 in a right direction.

[0069] FIG. 10 is a circuit diagram illustrating an anti-overlap circuit 390 included in the DC-DC converter shown in FIG. 6 according to another exemplary embodiment of the present invention. The anti-overlap circuit 390 shown in FIG. 10 further includes a power down function compared with the anti-overlap circuit 390 shown in FIG. 7.

[0070] Referring to FIG. 10, the anti-overlap circuit 390 includes a first NOR gate 392 and a second NOR gate 393, a first inverter 391 through a fifth inverter 397, a first NAND gate 401, a second NAND gate 402, a first capacitor C31 and a second capacitor C32.

[0071] The first inverter 391 inverts a clock signal CLK, i.e., the second signal VCO shown in FIG. 6. The first NOR gate performs a logical NOR operation on the second signal VCO and a third signal CLKP. The first capacitor C31 is coupled to an output terminal of the first NOR gate 392. The second inverter 394 inverts an output signal VA of the first NOR gate 392. The third inverter 395 inverts an output signal of the second inverter 394 to generate a fourth signal DCLKP. The first NAND gate 401 performs a logical NAND operation on the output signal DCLKP of the third inverter 395 and a power down signal PD to generate a second pulse signal V2. The second NOR gate 393 performs a logical NOR operation on the output signal DCLK of the first inverter 391 and the fourth signal DCLKP. The second capacitor C32 is coupled to an output terminal of the second NOR gate 393. The fourth inverter 396 inverts an output signal VB of the second NOR gate 393. The fifth inverter 397 inverts an output signal of the fourth inverter 396 to generate a third signal CLKP. The second NAND gate 402 performs a logical NAND operation on an output signal of the fourth inverter 396 and the power down signal to generate a first pulse signal V1.

[0072] The anti-overlap circuit 390 shown in FIG. 10 includes two NAND gates 401 and 402 instead of the inverters 398 and 399 of the anti-overlap circuit 390 shown in FIG. 7, and the power down signal PD is applied to an input terminal of each of the NAND gates 401 and 402. Hereinafter, operations of the anti-overlap circuit 390 shown in FIG. 10 will be explained.

[0073] When the power down signal PD is at a logic ‘low’ level, the pulse signals V1 and V2 outputted from the NAND gates 401 and 402 become the logic ‘high’ level. As a result, the switching signals VP and VN outputted from the switch driver 330 shown in FIG. 6 become the logic ‘high’ level, and the P-type switch comprising the power switch 340 shown in FIG. 6 is turned off and the N-type switch comprising the power switch 340 shown in FIG. 6 is turned on; thus, the first output node NO1 becomes the logic ‘low’ level. The power switch 340 according to an exemplary embodiment of the present invention is illustrated in FIG. 13.

[0074] FIGS. 11A through 11C are waveform diagrams illustrating simulation results of the DC-DC converter shown in FIG. 6 in a case where a reference voltage is equal to about 1 volt. Referring to FIG. 11A, a direct current output voltage signal VO outputted from a DC-DC converter follows a reference signal VREF having a direct voltage of about 1 volt. Referring to FIGS. 11B and 11C, the second feedback signal VPF applied to a non-inverting input terminal of a comparator 320 has a sawtooth waveform, and the pulse width modulated signal VLX outputted at the first output node NO1 has a variable pulse width and frequency.

[0075] FIGS. 12A through 12C are waveform diagrams illustrating simulation results of the DC-DC converter shown in FIG. 6 in a case where a reference voltage is equal to about 2 volts. Referring to FIG. 12A, a direct current output voltage signal VO outputted from a DC-DC converter follows a reference signal VREF having a direct voltage of about 2 volts. Referring to FIGS. 12B and 12C, the second feedback signal VPF applied to a non-inverting input terminal of the comparator 320 exhibits a sawtooth waveform, and the pulse width modulated signal VLX outputted at the first output node NO1 has a variable pulse width and frequency. A duty cycle (or a duty ratio) of the pulse width modulated signal VLX shown in FIG. 12C is larger than that of the pulse width modulated signal VLX shown in FIG. 11C, since the reference voltage VREF applied to the DC-DC converter shown in FIG. 12C is larger than that applied to the DC-DC converter shown in FIG. 11C.

[0076] FIG. 13 is a schematic circuit diagram illustrating a system employing a DC-DC converter according to an exemplary embodiment of the present invention, which generates an output voltage of about 0 volts through about 3.6 volts.

[0077] A pulse width modulation (PWM) modulator 540 includes an operational amplifier 310, a comparator 320, an anti-overlap circuit 390, a negative feedback circuit 370 and a positive feedback circuit 360 shown in FIG. 6. A P-type switch 520 and an N-type switch 530 correspond to a power switch 340 shown in FIG. 6. A filter 550 corresponds to a filter 350 shown in FIG. 6. A voltage source VBAT corresponds to an input signal VI shown in FIG. 6.

[0078] Referring to FIG. 13, the DC-DC converter includes an input voltage VBAT, the P-type switch 520, the N-type switch 530, the PWM modulator 540 and the filter 550. A resistor RL shown in FIG. 13 represents a load resistor.

[0079] The PWM modulator 540 positively feeds back a pulse width modulated signal VLX to generate an oscillated signal, and negatively feeds back a direct current output voltage signal VO to compare the fed-back direct current output voltage signal VO with a reference signal VREF. The PWM modulator 540 generates switching signals VP and VN so that the direct current output voltage signal VO follows the reference signal VREF, performing the pulse width modulation (PWM).

[0080] When the switching signal VP is at a logic ‘high’ state and the switching signal VN is at a logic ‘low’ state, both of the P-type switch 520 and the N-type switch 530 are turned off. When both of the switching signals VP and VN are at the logic ‘low’ state, the P-type switch 520 is turned on and the N-type switch 530 is turned off, and the input voltage VBAT is outputted through the filter 550.

[0081] When both the switching signals VP and VN are at the logic ‘high’ state, the P-type switch 520 is turned off and the N-type switch 530 is turned on. Accordingly, the input voltage VBAT is not provided to an output node, and a current path through an inductor L is formed by the N-type switch 530. The DC-DC converter shown in FIG. 13 outputs a stable direct current voltage of about 0 volts through about 3.6 volts.

[0082] As described above, the DC-DC converter according to exemplary embodiments of the present invention is capable of controlling a pulse width and a pulse frequency using a modified Schmitt trigger circuit and without using a hysteretic comparator. The DC-DC converter according to exemplary embodiments of the present invention may provide a stable direct current output voltage.

[0083] Additionally, the DC-DC converter according to exemplary embodiments of the present invention may reduce an integrated circuit (IC) chip size, for example, because an oscillator is not required.

[0084] The DC-DC converter according to exemplary embodiments of the present invention may quickly obtain a low output voltage by lowering a frequency of a pulse width modulated signal.

[0085] Although the exemplary embodiments of the present invention have been described with reference to the accompanying drawings for the purpose of illustration, it is to be understood that the inventive processes and apparatus are not to be construed as limited thereby. It will be readily apparent to those of ordinary skill in the art that various modifications to the foregoing exemplary embodiments may be made without departing from the scope of the invention as defined by the appended claims, with equivalents of the claims to be included therein.