Method for expanding a trench in a semiconductor structure

[0001] This application claims the benefit of priority to German Application No. 10 2004 006 545.4, filed in the German language on Feb. 10, 2004, the contents of which are hereby incorporated by reference.

[0002] The present invention relates to a method for expanding a trench in a semiconductor structure.

[0003] Although applicable to arbitrary semiconductor structures, the present invention and also the problem area on which it is based are explained on the basis of trenches for storage capacitors in semiconductor memory devices.

[0004] Modern semiconductor memory devices have trench capacitors in order that the individual memory cells comprising the trench capacitor and an associated selection transistor have a least possible space requirement.

[0005] Since the capacitance of a trench capacitor is directly proportional to its surface area, the trenches of the trench capacitors are usually expanded by an etching process in the lower region, which results in a desired enlargement of the surface area.

[0006] FIGS. 2-4 show process steps of a method for expanding a trench in a semiconductor structure which is disclosed in U.S. Pat. Ser. No. 2001/0016398 A1.

[0007] In FIG. 2, reference symbol 100 designates a silicon semiconductor substrate with a trench 50 provided therein. Situated on the surface of the silicon semiconductor substrate 100 is a pad stack 110, comprising a lower pad oxide layer 111 and an upper pad nitride layer 112, which have been used as a mask for forming the trench 50. An insulation collar 120 made of silicon, e.g. TEOS oxide, is provided in the upper trench region 154.

[0008] The semiconductor structure with the trench 50 shown in FIG. 2 is firstly treated with HF in order to remove natural oxide from the silicon surfaces 150 that are uncovered in the trench 50 and to terminate these silicon surfaces 150 with hydrogen, which remains on the silicon surfaces 150.

[0009] The HF treatment is preferably carried out for 60 to 180 seconds in a water/HF solution having a volume ratio of 200:1.

[0010] In a subsequent process step, illustrated in FIG. 3, firstly a rinsing with H₂O is effected and then an anisotropic wet etching with alkaline NH₄OH solution is effected, for example in an aqueous solution with a dilution of 100:1.

[0011] In this case, the trench 50 is expanded in the lower region 155 lying below the insulation collar 120. The diagrammatic drawing of FIG. 3 does not illustrate the fact that the expansion is effected anisotropically with regard to specific crystal planes in a manner dependent on the crystal orientation of the silicon semiconductor substrate 100.

[0012] Furthermore referring to FIG. 4, after a desired expansion has been obtained, the NH₄OH is removed from the trench 50 by rinsing with H₂O.

[0013] The H₂O rinsing gives rise to problems, however, in so far as dissolved SiO₂ precipitates as silica gel as a result of the negative pH shift of the water rinsing and forms complexes which can outdiffuse significantly more slowly than protons of the water rinsing can indiffuse. In other words, these precipitated complexes impede rapid rinsing of the trench 50, which has the effect that the etching in the lower trench region, where new protons can be supplied only slowly, advances in an uncontrolled manner until the complexes have outdiffused.

[0014] The mechanisms of the NH₄OH etching and of the subsequent water rinsing are reproduced by the corresponding chemical formulae below.

• • [0015] a) NH₄OH etching of silicon
  • [0016] 4 OH⁻+Si→SiO₂(OH)₂⁻² aq.+2 H⁺+4e⁻(alkaline stablized SiO₂)
  • [0017] 4 e—+4 H2O→4 OH—+2H₂
  • [0018] b) Water rinsing: negative pH shift→protonation of silica gel→destabilization
  • [0019] SiO₂(OH)₂²⁻+2 H⁺→Si(OH)₄→Si(OH)₃—O—Si(OH)₃+H₂O (condensation)

[0020] A typical value of the diffusion coefficient for the protons is 12×10⁻⁹ m²s⁻¹ and a typical value of the diffusion coefficient for SiOX is 0.5×10⁻⁹ m²s⁻¹.

[0021] Possible approaches for solving this problem might provide downstream HF etches that bring dissolved SiO₂ into solution again. The disadvantage consists in the consumption of SiO₂, that is to say also in an attack on the insulation collar 120. The etching rate is not significantly lowered by a dilution of the etching solution, for example 400:1 instead of 100:1. At lower temperatures, although the etching rate decreases, the solubility of SiO₂ likewise decreases.

[0022] The present invention provides an improved method for expanding a trench in a semiconductor structure in which the etching process can be better controlled.

[0023] According to one embodiment of the invention, there is a method for expanding a trench in a semiconductor structure in which there is provision of the trench in a semiconductor substrate; provision of hydrogen-terminated silicon surfaces in the trench; anisotropic wet etching of the silicon surfaces in the trench with an alkaline etchant; and rinsing of the trench with a proton-containing neutralizing agent for the removal of the alkaline etchant; in which case between the wet etching step and the rinsing step, an anodic passivation of the etched silicon surfaces in the trench is carried out, in the course of which an etching stop layer is formed on the etched silicon surfaces in the trench.

[0024] In the invention, between the wet etching step and the rinsing step, an anodic passivation of the etched silicon surfaces in the trench is carried out. This has the advantage that the etching process cannot continue in an uncontrolled manner in the lower trench region when rinsing out the alkaline etchant.

[0025] The method according to the invention makes it possible to stop the etching process without changing the pH of the etching chemical. The SiO₂ stabilized by NH₃ can be removed by comparatively rapid diffusion from the trench. Only afterward is the rinsing with H₂O effected.

[0026] The present invention thus makes it possible to decouple the etching process from the concentration of the reactive species by stopping the etching by means of an anodic current pulse which brings about an oxide passivation of the silicon surfaces.

[0027] In accordance with one preferred embodiment, the alkaline etchant is NH₄OH.

[0028] In accordance with a further preferred embodiment, the neutralizing agent is H₂O.

[0029] In accordance with a further preferred embodiment, the etching stop layer is a silicon oxide layer.

[0030] In accordance with a further preferred embodiment, the provision of hydrogen-terminated silicon surfaces in the trench is effected by means of an HF treatment.

[0031] In accordance with a further preferred embodiment, the trench has an aspect ratio of at least 5:1.

[0032] In accordance with a further preferred embodiment, the trench is expanded in the lower region and is masked in the upper region by means of an insulation collar for protection against the expansion.

[0033] In accordance with a further preferred embodiment, the trench is part of a trench capacitor of a semiconductor memory device.

[0034] In accordance with a further preferred embodiment, the etching stop layer is removed after rinsing of the trench.

[0035] In accordance with a further preferred embodiment, the anodic passivation is formed by a current pulse that is significantly shorter than the etching time.

[0036] The invention is described in more detail below with reference to the exemplary embodiments and illustrated in the drawings.

[0037] In the Figures:

[0038] FIG. 1 illustrates a process step of a method for expanding a trench in a semiconductor structure in one embodiment of the present invention.

[0039] FIGS. 2-4 illustrate process steps of a known method for expanding a trench in a semiconductor structure.

[0040] In the figures, identical reference symbols designate identical or functionally identical component parts.

[0041] The embodiment of the present invention begins with the process steps in accordance with FIGS. 2 and 3 that have already been described above.

[0042] In contrast to the known process explained comprehensively above, in the case of the process according to the invention, after the trench 50 has been expanded by means of the alkaline NH₄OH etching, an anodic passivation of the uncovered silicon surfaces by means of an SiO₂ layer 160 is performed. The alkaline stabilized SiO₂ can subsequently pass out of the trench 50 by diffusion before a negative pH shift occurs as a result of rinsing with water.

[0043] The anodic passivation is achieved for example by treating the relevant wafer in a single wafer reactor and applying to it an electrical potential which can be applied by means of a rear side contact, on the one hand, and by means of an inert electrode dipped into the etching solution, on the other hand.

[0044] The described etching process according to the invention typically lasts for 3 to 4 minutes, the stop time as a result of the anodic current pulse amounting to only a few seconds.

[0045] Consequently, it is possible to obtain a uniform silicon etching front in the entire trench 50.

[0046] The silicon oxide layer 160 on the etched surfaces 150 which is provided as a result of the anodic passivation may, if desired, be removed later in a short HF rinsing step after the water rinsing.

[0047] Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted thereto, but rather can be modified in diverse ways.

[0048] Although the lower trench region 155, which is expanded by the method according to the invention, has the substrate doping in the case of the embodiment described above, it is possible, of course, prior to the expansion method, to provide a buried plate in the substrate by indiffusion of a corresponding doping layer.

[0049] Moreover, the invention is applicable not just to an NH₄OH etching, but to any alkaline etching in the course of which corresponding complexes are precipitated during rinsing.

[0050] Finally, the trenches to be expanded do not have to be trenches for trench capacitors, but rather may be, in principle, arbitrary trenches in a semiconductor structure which serve for microelectronic or micromechanical purposes.

List of Reference Symbols

• [0051] 100 silicon semiconductor substrate
• [0052] 50 trench
• [0053] 120 insulation collar
• [0054] 110 pad stack
• [0055] 111 pad oxide
• [0056] 112 pad nitride
• [0057] 154 upper trench region
• [0058] 155 lower trench region
• [0059] 160 etching stop layer