Fractional frequency divider circuit and data transmission apparatus using the same

[0001] The present invention relates to a fractional frequency divider circuit and a data transmission apparatus using the same, and especially to a fractional frequency divider circuit suitable for supplying multiple kinds of clock to a data transmission apparatus used for high-speed communication, and a data transmission apparatus using the same.

[0002] A conventional high-speed interface circuit is formed of a receiver circuit (RX) that receives external data and performs serial-parallel conversion thereof, a transmitter circuit (TX) that performs parallel-serial conversion of internal data, and a PLL that multiplies an external reference clock and supplies it to the RX and TX. In an apparatus comprising multiple channels constituted such that an RX is coupled with a TX, one PLL generally supplies a clock commonly to the multiple channels. However, in this case, the data speed cannot be changed for each channel. It is thought to be possible to change the data speed by frequency-dividing the clock with a frequency divider circuit, however, it is difficult to realize this when the data speed ratio is not an integer.

[0003] A circuit shown in FIG. 5 is known as a fractional frequency divider circuit where the N of its frequency division ratio (1/N) is not an integer. (Refer to Patent Document 1.) The fractional frequency divider circuit shown in FIG. 5 uses adders et al., therefore the circuit scale becomes large. Furthermore, it is constituted such that it obtains a desired fraction frequency-divided output by varying the frequency division ratio over time and obtaining the average, therefore, it cannot be used at all as a clock to be supplied to an RX and a TX that require a waveform with a duty ratio of 50%. For this reason, conventionally a PLL is provided for each channel as shown in FIG. 6a, or two PLLs are shared by multiple channels as shown in FIG. 6b.

[Patent Document 1]

• • [0004] Japanese Patent Kokai Publication No. JP-P2001-251181A (FIG. 1)

[0005] A conventional fractional frequency divider circuit has a large circuit scale and it does not operate with a fixed frequency division ratio over time. Also, a conventional data transmission apparatus that has multiple channels and is able to change data speed for each channel is constituted such that it has multiple PLLs, therefore the circuit scale becomes large, and this results in the disadvantage of increase in consumption power. Therefore, there is much to be desired in the art.

[0006] According to a first aspect of the present invention, there is provided a fractional frequency divider circuit comprising an integer frequency divider circuit and a logic circuit. The integer frequency divider circuit is constituted by multiple master-slave flip-flops and frequency-divides a clock signal with a frequency-division ratio of 1/N (N is an integer). The logic circuit receives multiple signals outputted from master stages and slave stages of the master-slave flip-flops, and outputs a signal with a duty ratio of 50% obtained by frequency-dividing the clock signal with a frequency-division ratio of 2/N.

[0007] Furthermore, signals outputted from master stages or slave stages of the master-slave flip-flops are inputted into the logic circuit, and it also comprises a data latch circuit that outputs synchronously with a clock signal whose phase is different from the above-mentioned clock signal.

[0008] According to a second aspect of the present invention, there is provided a data transmission apparatus. The data transmission apparatus comprises a receiver circuit that performs serial-parallel conversion on a received signal and outputs the result, and a transmitter circuit that performs parallel-serial conversion on a transmitted signal and outputs the result, and a PLL that multiplies a reference clock signal and outputs a multiplied clock signal. The apparatus further comprises a fractional frequency divider circuit that outputs a signal obtained by frequency-dividing the multiplied clock signal with a frequency-division ratio of 2/N(N is an integer). The fractional frequency divider circuit comprises: an integer frequency divider circuit, constituted by multiple master-slave flip flops, that frequency-divides the multiplied clock signal with a frequency-division ratio of 1/N, and a logic circuit, into which multiple signals outputted from master stages and slave stages of the master-slave flip-flops are inputted. The logic circuit outputs a signal obtained by frequency-dividing the multiplied clock signal with a frequency-division ratio of 2/N(N is an integer). The receiver circuit and transmitter circuit are constituted such that they operate selectively switching over between the multiplied clock signal and a clock signal outputted by the fractional frequency divider circuit.

[0009] Furthermore, it is constituted such that signals outputted from master stages or slave stages of the master-slave flip-flops are inputted into the logic circuit, and there is a data latch circuit that outputs synchronously with a clock signal whose phase is different from the multiplied clock signal. Further, the waveform of the output signal of the logic circuit has a duty ratio of 50%.

[0010] Furthermore, the integer frequency divider circuit constitutes a frequency divider circuit that frequency-divides the multiplied clock signal and outputs the result to a phase comparator of the PLL.

[0011] Furthermore, the data transmission apparatus comprises multiple channels, wherein a pair of the receiver circuit and transmitter circuit is one channel, and for each channel, it can select between the multiplied clock signal and the clock signal outputted by the fractional frequency divider circuit.

[0012] The meritorious effects of the present invention are summarized as follows.

[0013] Since a fractional frequency divider circuit is incorporated as a part of a usual frequency divider circuit and its output is used, the clock data recovery operation, multiplexer operation, and demultiplexer operation of a data transmission apparatus becomes possible with small size and low power consumption.

[0014] FIG. 1 is a drawing showing a constitution of a fractional frequency divider circuit of Embodiment 1 of the present invention.

[0015] FIG. 2 is a timing chart explaining the operation of the fractional frequency divider circuit of Embodiment 1 of the present invention.

[0016] FIG. 3 is a drawing showing a constitution of a data transmission apparatus of Embodiment 2 of the present invention.

[0017] FIG. 4 is a drawing showing a constitution of a PLL and 1/2.5 frequency divider circuit of the data transmission apparatus of Embodiment 2 of the present invention.

[0018] FIG. 5 is a drawing showing the constitution of a conventional fractional frequency divider circuit.

[0019] FIGS. 6a and 6b are drawings showing a constitution of a data transmission apparatus according to the related art.

[0020] Hereinafter, embodiments of the present invention will be described with reference to drawings. FIG. 1 is a drawing showing a constitution of Embodiment 1 and FIG. 2 is a timing chart for explaining its operation. A fractional frequency divider circuit shown in FIG. 1 is able to output a 1/2.5 frequency-divided clock signal by taking out signals from an internal node B, internal node C, internal node D, and internal node E of a ⅕ frequency divider circuit 10, and processing them at a logic circuit 15.

[0021] The ⅕ frequency divider circuit 10 comprises master-slave flip-flops 1, 2, 3 and a NAND gate 4. L1 and L2, L3 and L4, and L5 and L6 are data latches that constitute master stages and slave stages respectively. The logic circuit 15 comprises data latches L7 and L8, and NAND gates 5, 6, and 7. At the data latches L1 through L7, D is a data input terminal and /Q is an inverted signal output terminal.

[0022] The 1/2.5 frequency divider circuit shown in FIG. 1 operates as a 4-phase clock of phases at 0, 90, 180 and 270 degrees. A 0-degree clock signal is inputted into the data latches L1, L3, and L5, and a 90-degree signal and 270-degree signal are inputted into the data latches L7 and L8, respectively.

[0023] Next, its operation is explained using FIG. 2. FIG. 2 is a timing chart showing the signal waveforms of each node of the frequency divider circuit shown in FIG. 1. At the nodes A through E and a node F of the ⅕ frequency divider circuit, signals with a cycle 5 times as long as the clock signal, albeit offset in phase and polarity, are obtained. The node B and the node D have the same waveform, which is a ⅕ frequency-divided waveform whose phase is offset from the clock signal by one cycle. By NANDing a signal obtained by latching the waveform of the node D with the data latch L7, into which a 90-degree clock signal with a phase offset of 90 degrees is inputted, with a signal of the node B, a ⅕ frequency-divided waveform whose low level duration is 1.25 cycle of the clock signal is obtained at a node G.

[0024] Similarly, by NANDing a signal obtained by latching a signal of the node E with the data latch L8, into which a 270-degree clock signal whose phase is offset from a 180-degree clock by 90 degrees is inputted, with the waveform of the node C, a ⅕ frequency-divided waveform whose low level duration is 1.25 cycle of the clock signal is obtained. The phases of the signals of the node G and a node H are shifted from each other by 2.5 cycle of the clock signal, and by NANDing these signals, a signal whose cycle is 2.5 cycle of the clock signal is obtained at a node I, which is an output of the NAND gate 7. In other words, a 1/2.5 frequency divider circuit that is able to obtain an output with a duty ratio of 50% can be realized according to the present invention.

[0025] In Embodiment 2, the present invention is applied to a data transmission apparatus with multiple channels wherein it is possible to set data speed for each channel separately. FIG. 3 is a block diagram of the present embodiment. A transmitter circuit (TX) and receiver circuit (RX) for one channel are shown in FIG. 3. In the present embodiment, two data speeds can be supported by providing a 1/2.5 frequency divider circuit at a PLL part and arranging two kinds of clock, and by providing a selection circuit for each of the TX and RX, and switching over between frequency-multiplied clocks (3.125 GHz and 1.25 GHz in FIG. 3).

[0026] The receiver circuit (RX) is comprised of a clock data recovery circuit (CDR) and a serial-parallel conversion circuit (DEMUX). The clock data recovery circuit (CDR) comprises a phase interpolator part (PI), a receiver flip-flop (FF), and a control circuit (CNT). At the phase interpolator part (PI), an inputted differential clock signal is frequency-divided by 2, a 4-phase clock signal whose cycle (period) is ½ of the inputted signal is generated, and the received data is latched at the FF. In FIG. 3, the FF is represented by one block diagram. From the 4-phase clock and latched output of the FF, the control circuit (CNT) extracts the phase relationship between the clock and data, and phase controls the clock output at the phase interpolator part (PI). This kind of a clock data recovery circuit is proposed by the present inventor in Japanese Patent Kokai Publication No. JP-P2003-333021A et al, the entire disclosure thereof being incorporated by reference thereto. Furthermore, the data from the FF is forwarded to the serial-parallel conversion circuit (DEMUX). At the serial-parallel conversion circuit (DEMUX), serial-parallel conversion is performed using the clock regenerated at the clock data recovery circuit (CDR).

[0027] The transmitter circuit (TX) synchronizes the output of a parallel-serial conversion circuit (MUX) with a selected clock signal (3.125 GHz and 1.25 GHz in FIG. 3) at a flip-flop FF and outputs a resultant signal as a transmission signal.

[0028] FIG. 4 is a block diagram showing an important part of the constitution of the PLL and 1/2.5 frequency divider circuit shown in FIG. 3. The PLL comprises a phase comparator (PD), charge pump circuit (CP), low pass filter (LF), voltage-controlled oscillator (VCO), ⅕ frequency divider circuit (⅕), and ½ frequency divider circuit. The PLL operates so that the phases of a reference signal (312.5 MHz) inputted into the PD differentially and a differential signal obtained by frequency-dividing the output of the VCO by 1/10 using the ⅕ frequency divider circuit and ½ frequency divider circuit match, and a 4-phase clock signal (3.125 GHz), a 10-fold multiplication of the reference signal, is outputted from the VCO.

[0029] The 1/2.5 frequency divider circuit is constituted by a ⅕ frequency divider circuit (⅕) and 1/2.5 circuit ( 1/2.5). The ⅕ frequency divider circuit (⅕) corresponds to the ⅕ frequency divider circuit 10 shown in FIG. 1 and 1/2.5 circuit to the logic circuit 15 shown in FIG. 1. In other words, in the present embodiment, an output that is a frequency-divided output of the PLL by 1/2.5 is originated from the internal signal of the ⅕ frequency divider circuit that constitutes (part of) the PLL, and a data transmission apparatus wherein it is possible to change data speed for each channel can be realized by adding a minimum amount of circuits.

[0030] The present invention is explained above using examples of embodiment. However, the present invention is not limited to the above embodiments, and it goes without saying that it includes various modifications and revisions, which may be made possible by a manufacturer, within the scope of the invention specified by each claim of the patent claims.

[0031] It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith.

[0032] Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items may fall under the modifications aforementioned.