Drive method of el display apparatus

[0001] The present invention relates to a self-luminous display panel such as an EL display panel which employs organic or inorganic electroluminescent (EL) elements as well as to a drive circuit (IC) for the display panel. Also, it relates to an information display apparatus and the like which employ the EL display panel, a drive method for the EL display panel, and the drive circuit for the EL display panel.

[0002] Generally, active-matrix display apparatus display images by arranging a large number of pixels in a matrix and controlling the light intensity of each pixel according to a video signal. For example, if liquid crystals are used as an electrochemical substance, the transmittance of each pixel changes according to a voltage written into the pixel. With active-matrix display apparatus which employ an organic electroluminescent (EL) material as an electrochemical substance, emission brightness changes according to current written into pixels.

[0003] In a liquid crystal display panel, each pixel works as a shutter, and images are displayed as a backlight is blocked off and revealed by the pixels or shutters. An organic EL display panel is of a self-luminous type in which each pixel has a light-emitting element. Consequently, organic EL display panels have the advantages of being more viewable than liquid crystal display panels, requiring no backlighting, having high response speed, etc.

[0004] Brightness of each light-emitting element (pixel) in an organic EL display panel is controlled by an amount of current. That is, organic EL display panels differ greatly from liquid crystal display panels in that light-emitting elements are driven or controlled by current.

[0005] A construction of organic EL display panels can be either a simple-matrix type or active-matrix type. It is difficult to implement a large high-resolution display panel of the former type although the former type is simple in structure and inexpensive. The latter type allows a large high-resolution display panel to be implemented, but involves a problem that it is a technically difficult control method and is relatively expensive. Currently, active-matrix type display panels are developed intensively. In the active-matrix type display panel, current flowing through the light-emitting elements provided in each pixel is controlled by thin-film transistors (transistors) installed in the pixels.

[0006] Such an organic EL display panel of an active-matrix type is disclosed in Japanese Patent Laid-Open No. 8-234683. An equivalent circuit for one pixel of the display panel is shown in FIG. 46. A pixel 16 consists of an EL element 15 which is a light-emitting element, a first transistor 11a, a second transistor 11b, and a storage capacitance 19. The light-emitting element 15 is an organic electroluminescent (EL) element. According to the present invention, the transistor 11a which supplies (controls) current to the EL element 15 is referred to as a driver transistor 11. A transistor, such as the transistor 11b shown in FIG. 46, which operates as a switch is referred to as a switching transistor 11.

[0007] The organic EL element 15, in many cases, may be referred to as an OLED (organic light-emitting diode) because of its rectification. In FIG. 46 or the like, a diode symbol is used for the lgiht-emitting element 15.

[0008] Incidentally, the light-emitting element 15 according to the present invention is not limited to an OLED. It may be of any type as long as its brightness is controlled by the amount of current flowing through the element 15. Examples include an inorganic EL element, a white light-emitting diode consisting of a semiconductor, atypical light-emitting diode, and a light-emitting transistor. Rectification is not necessarily required of the light-emitting element 15. Bidirectional diodes are also available. The EL element 15 according to the present invention may be any of the above elements.

[0009] In the example of FIG. 46, a source terminal (S) of the P-channel transistor 11a is designated as Vdd (power supply potential) and a cathode of the EL element 15 is connected to ground potential (Vk). On the other hand, an anode is connected to a drain terminal (D) of the transistor 11b. Besides, a gate terminal of the P-channel transistor 11a is connected to a gate signal line 17a, a source terminal is connected to a source signal line 18, and a drain terminal is connected to the storage capacitance 19 and a gate terminal (G) of the P-channel transistor 11a.

[0010] To drive the pixel 16, a video signal which represents brightness information is first applied to the source signal line 18 with the gate signal line 17a selected. Then, the transistor 11a conducts, the storage capacitance 19 is charged or discharged, and gate potential of the transistor 11b matches the potential of the video signal. When the gate signal line 17a is deselected, the transistor 11a is turned off and the transistor 11b is cut off electrically from the source signal line 18. However, the gate potential of the transistor 11a is maintained stably by the storage capacitance (capacitor) 19. Current delivered to the EL element 15 via the transistor 11a depends on gate-source voltage Vgs of the transistor 11a and the EL element 15 continues to emit light at an intensity which corresponds to the amount of current supplied via the transistor 11a.

[0011] Incidentally, the entire disclosure of the above document is incorporated herein in its entirety.

[0012] Since liquid crystal display panels are not self-luminous devices, there is a problem that they cannot display images without backlighting. Also, there has been a problem that a certain thickness is required to provide a backlight, which makes the display panel thicker. Besides, to display colors on a liquid crystal display panel, color filters must be used. Therefore, there has been a problem of the lowered usability of light. Also, there has been the problem of narrow color reproduction range.

[0013] Organic EL display panels are made of low-temperature polysilicon transistor arrays. However, since organic EL elements use current to emit light, there has been a problem that variations in the characteristics of the transistors will cause display irregularities.

[0014] The display irregularities can be reduced using current programming of pixels. For current programming, a current-driven driver circuit is required. However, with a current-driven driver circuit, variations will also occur in transistor elements which compose a current output stage. This in turn causes variations in gradation output currents from output terminals, making it impossible to display images properly.

[0015] To achieve this object, a driver circuit for an EL display panel (EL display apparatus) according to the present invention comprises a plurality of transistors which output unit currents and produces an output current by varying the number of transistors. Also, the driver circuit is characterized by comprising a multi-stage current mirror circuit. A transistor group which delivers signals via voltages is formed densely. Also, signals are delivered between the transistor group and current mirror circuit group via currents. Besides, reference currents are produced by a plurality of transistors.

[0016] A first invention of the present invention is a drive method of an EL display apparatus that comprises a switching element which turns on and off a current path between a driver transistor and an EL element, in each pixel, characterized in that the drive method comprises the steps of:

• • [0017] aggregating image data or data equivalent to image data; and
  • [0018] turning off the switching element for a longer period if the aggregated data is large in amount than if the aggregated data is small in amount.

[0019] A second invention of the present invention is an EL display apparatus comprising:

• • [0020] a display panel in which EL elements are formed in a matrix; and
  • [0021] a source driver circuit which supplies programming current to the display panel,
  • [0022] characterized in that the source driver circuit comprises an output stage which has a plurality of unit current elements and a variable circuit which controls current flowing from the unit current elements.

[0023] A third invention of the present invention is a drive method of an EL display apparatus that comprises a moving-picture detection circuit which detects moving pictures and a feature extraction circuit which extracts features of video images, characterized in that the drive method of the EL display apparatus implements:

• • [0024] a first operation of changing the number of selected pixel rows depending on output data from the moving-picture detection circuit; and
  • [0025] a second operation of changing the number of selected pixel rows depending on output data from the feature extraction circuit.

[0026] A fourth invention of the present invention is an EL display apparatus which controls brightness of a screen using a ratio between non-display and display areas on the screen, characterized in that the EL display apparatus comprises:

• • [0027] the display area in which EL elements and driver transistors that drive the EL elements are formed in a matrix;
  • [0028] gate signal lines which transmit voltages that turn on and off the EL elements in each pixel row;
  • [0029] a gate driver circuit which drives the gate signal lines;
  • [0030] an aggregation circuit which aggregates image data or data equivalent to image data; and
  • [0031] a conversion circuit which converts aggregation results produced by the aggregation circuit into a start pulse signal for the gate driver circuit.

[0032] A fifth invention of the present invention is a control method of an EL display apparatus which controls brightness of a screen using a ratio between non-display and display areas on the screen, characterized by generating a delay time when changing the ratio between the non-display and display areas on the screen from a first ratio to a second ratio.

[0033] A sixth invention of the present invention is the drive method of an EL display apparatus according to the fifth invention of the present invention, characterized in that the display area/(the non-display area+the display area on the screen) is from 1/16 to 1/1 both inclusive.

[0034] A seventh invention of the present invention is an EL display apparatus comprising:

• • [0035] a display panel in which each pixel contains a capacitor, an EL element, and a P-channel driver transistor which supplies current to the EL element and pixels are arranged in a matrix; and
  • [0036] a source driver circuit which supplies programming current to the display panel,
  • [0037] characterized in that the source driver circuit comprises an output stage which has an N-channel unit transistor that outputs a plurality of unit currents.

[0038] An eighth invention of the present invention is the EL display apparatus according to the seventh invention of the present invention, characterized in that if capacitance of a capacitor is Cs (pF) and one pixel occupies an area of S (square μm), a condition 500/S≦Cs≦20000/S is satisfied.

[0039] A ninth invention of the present invention is the EL display apparatus according to the seventh invention of the present invention, characterized in that if pixel size is A (square mm) and predetermined white raster display brightness is B (nt), where the programming current I (μA) from the source driver circuit satisfies a condition (A×B)/20≦I≦(A×B).

[0040] A tenth invention of the present invention is the EL display apparatus according to the seventh invention of the present invention, characterized in that if the number of gradations is K and size of the unit transistor is S t(square μm), conditions 40≦K/{square root}{square root over ( )}(St) and St≦300 are satisfied.

[0041] An eleventh invention of the present invention is the EL display apparatus according to the seventh invention of the present invention, characterized in that if the number of gradations is K, if channel length of the unit transistor of the unit transistor is L (μm), and if channel width is W (μm), a condition ({square root}{square root over ( )}(K/16))≦L/W≦({square root}{square root over ( )}(K/16))×20 is satisfied.

[0042] A twelfth invention of the present invention is an EL display apparatus comprising:

• • [0043] a first EL display panel which has a first display screen;
  • [0044] a second EL display panel which has a second display screen; and
  • [0045] a flexible board which connects source signal lines of the first EL display panel with source signal lines of the second EL display panel,
  • [0046] characterized in that if channel width of driver transistors which drive pixels is W (μm) and channel length is L (μm), W/L differs between the driver transistor which drives pixels in the first display screen and the driver transistor which drives pixels in the second display screen.

[0047] FIG. 1 is a block diagram of a pixel in a display panel according to the present invention;

[0048] FIG. 2 is a block diagram of a pixel in a display panel according to the present invention;

[0049] FIG. 3 is an explanatory diagram illustrating operation of a display panel according to the present invention;

[0050] FIG. 4 is an explanatory diagram illustrating operation of a display panel according to the present invention;

[0051] FIG. 5 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0052] FIG. 6 is a block diagram of a display apparatus according to the present invention;

[0053] FIG. 7 is an explanatory diagram illustrating a manufacturing method of a display panel according to the present invention;

[0054] FIG. 8 is a block diagram of a display apparatus according to the present invention;

[0055] FIG. 9 is a block diagram of a display apparatus according to the present invention;

[0056] FIG. 10 is a sectional view of a display panel according to the present invention;

[0057] FIG. 11 is a sectional view of a display panel according to the present invention;

[0058] FIG. 12 is an explanatory diagram illustrating a display panel according to the present invention;

[0059] FIG. 13 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0060] FIG. 14 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0061] FIG. 15 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0062] FIG. 16 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0063] FIG. 17 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0064] FIG. 18 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0065] FIG. 19 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0066] FIG. 20 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0067] FIG. 21 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0068] FIG. 22 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0069] FIG. 23 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0070] FIG. 24 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0071] FIG. 25 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0072] FIG. 26 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0073] FIG. 27 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0074] FIG. 28 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0075] FIG. 29 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0076] FIG. 30 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0077] FIG. 31 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0078] FIG. 32 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0079] FIG. 33 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0080] FIG. 34 is a block diagram of a display apparatus according to the present invention;

[0081] FIG. 35 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0082] FIG. 36 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0083] FIG. 37 is a block diagram of a display apparatus according to the present invention;

[0084] FIG. 38 is a block diagram of a pixel in a display panel according to the present invention;

[0085] FIG. 39 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0086] FIG. 40 is a block diagram of a display apparatus according to the present invention;

[0087] FIG. 41 is a block diagram of a display apparatus according to the present invention;

[0088] FIG. 42 is a block diagram of a pixel in a display panel according to the present invention;

[0089] FIG. 43 is a block diagram of a pixel in a display panel according to the present invention;

[0090] FIG. 44 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0091] FIG. 45 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0092] FIG. 46 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0093] FIG. 47 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0094] FIG. 48 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0095] FIG. 47 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0096] FIG. 48 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0097] FIG. 47 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0098] FIG. 48 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0099] FIG. 47 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0100] FIG. 48 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0101] FIG. 49 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0102] FIG. 50 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0103] FIG. 51 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0104] FIG. 52 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0105] FIG. 53 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0106] FIG. 54 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0107] FIG. 55 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0108] FIG. 56 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0109] FIG. 57 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0110] FIG. 58 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0111] FIG. 59 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0112] FIG. 60 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0113] FIG. 61 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0114] FIG. 62 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0115] FIG. 63 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0116] FIG. 64 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0117] FIG. 65 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0118] FIG. 66 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0119] FIG. 67 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0120] FIG. 68 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0121] FIG. 69 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0122] FIG. 70 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0123] FIG. 71 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0124] FIG. 72 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0125] FIG. 73 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0126] FIG. 74 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0127] FIG. 75 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0128] FIG. 76 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0129] FIG. 77 is an explanatory diagram illustrating a drive circuit according to the present invention;

[0130] FIG. 78 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0131] FIG. 79 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0132] FIG. 80 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0133] FIG. 81 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0134] FIG. 82 is an explanatory diagram illustrating a drive method of a display apparatus according to the present invention;

[0135] FIG. 83 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0136] FIG. 84 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0137] FIG. 85 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0138] FIG. 86 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0139] FIG. 87 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0140] FIG. 88 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0141] FIG. 89 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0142] FIG. 90 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0143] FIG. 91 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0144] FIG. 92 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0145] FIG. 93 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0146] FIG. 94 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0147] FIG. 95 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0148] FIG. 96 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0149] FIG. 97 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0150] FIG. 98 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0151] FIG. 99 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0152] FIG. 100 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0153] FIG. 101 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0154] FIG. 102 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0155] FIG. 103 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0156] FIG. 104 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0157] FIG. 105 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0158] FIG. 106 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0159] FIG. 107 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0160] FIG. 108 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0161] FIG. 109 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0162] FIG. 110 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0163] FIG. 111 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0164] FIG. 112 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0165] FIG. 113 is a block diagram of a pixel in a display panel according to the present invention;

[0166] FIG. 114 is a block diagram of a pixel in a display panel according to the present invention;

[0167] FIG. 115 is a block diagram of a pixel in a display panel according to the present invention;

[0168] FIG. 116 is a block diagram of a pixel in a display panel according to the present invention;

[0169] FIG. 117 is a block diagram of a pixel in a display panel according to the present invention;

[0170] FIG. 118 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0171] FIG. 119 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0172] FIG. 120 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0173] FIG. 121 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0174] FIG. 122 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0175] FIG. 123 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0176] FIG. 124 is an explanatory diagram illustrating a drive circuit of a display apparatus according to the present invention;

[0177] FIG. 125 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0178] FIG. 126 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0179] FIG. 127 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0180] FIG. 128 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0181] FIG. 129 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0182] FIG. 130 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0183] FIG. 131 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0184] FIG. 132 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0185] FIG. 133 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0186] FIG. 134 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0187] FIG. 135 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0188] FIG. 136 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0189] FIG. 137 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0190] FIG. 138 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0191] FIG. 139 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0192] FIG. 140 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0193] FIG. 141 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0194] FIG. 142 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0195] FIG. 143 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0196] FIG. 144 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0197] FIG. 145 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0198] FIG. 146 is an explanatory diagram illustrating a drive method of a display panel according to the present invention;

[0199] FIG. 147 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0200] FIG. 148 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0201] FIG. 149 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0202] FIG. 150 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0203] FIG. 151 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0204] FIG. 152 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0205] FIG. 153 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0206] FIG. 154 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0207] FIG. 155 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0208] FIG. 156 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0209] FIG. 157 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0210] FIG. 158 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0211] FIG. 159 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0212] FIG. 160 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0213] FIG. 161 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0214] FIG. 162 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0215] FIG. 163 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0216] FIG. 164 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0217] FIG. 165 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0218] FIG. 166 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0219] FIG. 167 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0220] FIG. 168 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0221] FIG. 169 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0222] FIG. 170 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0223] FIG. 171 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0224] FIG. 172 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0225] FIG. 173 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0226] FIG. 174 is an explanatory diagram illustrating a display apparatus according to the present invention;

[0227] FIG. 175 is an explanatory diagram illustrating a source driver IC according to the present invention;

[0228] FIG. 176 is an explanatory diagram illustrating a source driver IC according to the present invention.

• [0229] 11 Transistor (thin-film transistor)
• [0230] 12 Gate driver IC (circuit)
• [0231] 14 Source driver IC (circuit)
• [0232] 15 EL (element) (light-emitting element)
• [0233] 16 Pixel
• [0234] 17 Gate signal line
• [0235] 18 Source signal line
• [0236] 19 Storage capacitance (additional capacitor, additional capacitance)
• [0237] 50 Display screen
• [0238] 51 Write pixel (row)
• [0239] 52 Non-display pixel (non-display area, non-illuminated area)
• [0240] 53 Display pixel (display area, illuminated area)
• [0241] 61 Shift register
• [0242] 62 Inverter
• [0243] 63 Output buffer
• [0244] 71 Array board (display panel)
• [0245] 72 Laser irradiation range (laser spot)
• [0246] 73 Positioning marker
• [0247] 74 Glass substrate (array board)
• [0248] 81 Control IC (circuit)
• [0249] 82 Power supply IC (circuit)
• [0250] 83 Printed board
• [0251] 84 Flexible board
• [0252] 85 Sealing lid
• [0253] 86 Cathode wiring
• [0254] 87 Anode wiring (Vdd)
• [0255] 88 Data signal line
• [0256] 89 Gate control signal line
• [0257] 101 Bank (rib)
• [0258] 102 Interlayer insulating film
• [0259] 104 Contact connector
• [0260] 105 Pixel electrode
• [0261] 106 Cathode electrode
• [0262] 107 Desiccant
• [0263] 108 λ/4 plate
• [0264] 109 Polarizing plate
• [0265] 111 Thin encapsulation film
• [0266] 271 Dummy pixel (row)
• [0267] 341 Output stage circuit
• [0268] 371 OR circuit
• [0269] 401 Illumination control line
• [0270] 471 Reverse bias line
• [0271] 472 Gate potential control line
• [0272] 451 Electronic regulator circuit
• [0273] 452 SD (source-drain) short circuit of a transistor
• [0274] 471, 472, 473 Current source (transistor)
• [0275] 481 Switch (on/off means)
• [0276] 484 Current source (unit transistor)
• [0277] 483 Internal wiring
• [0278] 491 Electronic regulator
• [0279] 521 Transistor group
• [0280] 531 Resister
• [0281] 532 Decoder circuit
• [0282] 533 Level shifter circuit
• [0283] 541 Padder circuit
• [0284] 551 D/A converter
• [0285] 552 Operational amplifier
• [0286] 562 Inverter
• [0287] 581 Gate wiring
• [0288] 631 Sleep switch (reference current on/off means)
• [0289] 651 Counter
• [0290] 652 NOR
• [0291] 653 AND
• [0292] 654 Current output circuit
• [0293] 655 Switch
• [0294] 671 Coincidence circuit
• [0295] 681 Input/output pad
• [0296] 691 Reference current circuit
• [0297] 692 Current control circuit
• [0298] 701 Temperature detection means
• [0299] 702 Temperature control circuit
• [0300] 711 Unit gate output circuit
• [0301] 1121 Coil (transformer)
• [0302] 1122 Control circuit
• [0303] 1123 Diode
• [0304] 1124 Capacitor
• [0305] 1125 Resister
• [0306] 1126 Transistor
• [0307] 1131 Switching circuit (analog switch)
• [0308] 1251 Output switching circuit
• [0309] 1252 Changeover switch
• [0310] 1501 Analog switch
• [0311] 1502 Switch control line
• [0312] 1503 Connection wiring
• [0313] 1504 Cushioning sheet (plate)
• [0314] 1521 Inverter
• [0315] 1522 Connection terminal
• [0316] 1571 Antenna
• [0317] 1572 Key
• [0318] 1573 Housing
• [0319] 1574 Display panel
• [0320] 1581 Eye ring
• [0321] 1582 Magnifying lens
• [0322] 1583 Convex lens
• [0323] 1591 Supporting point (pivot point)
• [0324] 1592 Taking lens
• [0325] 1593 Storage section
• [0326] 1594 Switch
• [0327] 1601 Body
• [0328] 1602 Photographic section
• [0329] 1603 Shutter switch
• [0330] 1611 Mounting frame
• [0331] 1612 Leg
• [0332] 1613 Mount
• [0333] 1614 Fixed part
• [0334] 1731 Control electrode
• [0335] 1732 Video signal circuit
• [0336] 1733 Electron emission protuberance
• [0337] 1734 Holding circuit
• [0338] 1735 On/off control circuit
• [0339] 1741 Selection signal line
• [0340] 1742 On/off signal line

[0341] Some parts of drawings herein are omitted and/or enlarged/reduced herein for ease of understanding and/or illustration. For example, in a sectional view of a display panel shown in FIG. 11, a thin encapsulation film 111 and the like are shown as being fairly thick. On the other hand, in FIG. 10, a sealing lid 85 is shown as being thin. Some parts are omitted. For example, although the display panel according to the present invention requires a phase film such as a circular polarizing plate to prevent reflection, the phase film is omitted in drawings herein. This also applies to the drawings below. Besides, the same or similar forms, materials, functions, or operations are denoted by the same reference numbers or characters.

[0342] Incidentally, what is described with reference to drawings or the like can be combined with other examples or the like even if not noted specifically. For example, a touch panel or the like can be attached to a display panel in FIG. 8 to provide an information display apparatus shown in FIGS. 157 and 159 to 161. Also, a magnifying lens 1582 can be mounted to configure a view finder (see FIG. 58) used for a video camera (see FIG. 159, etc.) or the like. Also, drive methods described with reference to FIGS. 4, 15, 18, 21, 23, 29, 30, 35, 36, 40, 41, 44, 100, etc. can be applied to any display apparatus or display panel according to the present invention.

[0343] Also, thin-film transistors are cited herein as driver transistors 11 and switching transistors 11, this is not restrictive. Thin-film diodes (TFDs) or ring diodes may be used instead. Also, the present invention is not limited to thin-film elements, and transistors formed on silicon wafers may also be used. In that case, an array board 71 can be made of a silicon wafer. Needless to say, FETs, MOS-FETs, MOS transistors, or bipolar transistors may also be used. They are basically, thin-film transistors. It goes without saying that the present invention may also use varistors, thyristors, ring diodes, photodiodes, phototransistors, or PLZT elements. That is, the transistor element 11, gate driver circuit 12, and source driver circuit 14 according to the present invention can use any of the above elements.

[0344] An EL panel according to the present invention will be described below with reference to drawings. As shown in FIG. 10, an organic EL display panel consists of a glass substrate (array board) 71, transparent electrodes 105 formed as pixel electrodes, at least one organic functional layer (EL layer) 15, and a metal electrode (reflective film) (cathode) 106, which are stacked one on top of another, where the organic functional layer consists of an electron transport layer, light-emitting layer, positive hole transport layer, etc. The organic functional layer (EL layer) 15 emits light when a positive voltage is applied to the anode or transparent electrodes (pixel electrodes) 105 and a negative voltage is applied to the cathode or metal electrode (reflective electrode) 106, i.e. when a direct current is applied between the transparent electrodes 105 and metal electrode 106.

[0345] Preferably, the metal electrode 106 is made of metal with a small work function, such as lithium, silver, aluminum, magnesium, indium, copper, or an alloy thereof. In particular, it is preferable to use, for example, an Al—Li alloy. The transparent electrodes 105 may be made of, conductive materials with a large work function such as ITO, or gold and the like. If gold is used as an electrodematerial, the electrodes become translucent. Incidentally, IZO or other material may be used instead of ITO. This also applies to other pixel electrodes 105.

[0346] Incidentally, a desiccant 107 is placed in a space between the sealing lid 85 and array board 71. This is because the organic EL film 15 is vulnerable to moisture. The desiccant 107 absorbs water penetrating a sealant and thereby prevents deterioration of the organic EL film 15.

[0347] Although the glass lid 85 is used for sealing in FIG. 10, the film 111 (this may be a thin film, i.e., a thin encapsulation film) may be used for sealing as shown in FIG. 11. The encapsulation film (thin encapsulation film) 111 may be, for example, an electrolytic capacitor film on which DLC (diamond-like carbon) is vapor-deposited. This film features extremely low moisture penetration (high moisture resistance) It is used as the thin encapsulation film 111. Also, it goes without saying that DLC (diamond-like carbon) film may be vapor-deposited directly on a surface of the metal electrode 106. Besides, the thin encapsulation film may be formed by laminating thin resin films and metal films.

[0348] Desirably, film thickness of the thin film is such that n·d is equal to or less than main emission wavelength λ of the EL element 15 (where n is the refraction factor of the thin film, or the sum of refraction factors if two or more thin films are laminated (n·d of each thin film is calculated) d is the film thickness of the thin film, or the sum of refraction factors if two or more thin films are laminated). By satisfying this condition, it is possible to more than double the efficiency of light extraction from the EL element 15 compared to when a glass substrate is used for sealing. Also, an alloy, mixture, or laminate of aluminum and silver may be used.

[0349] A technique which uses a thin encapsulation film 111 for sealing instead of a sealing lid 85 as described above is called thin film encapsulation. In the case of “underside extraction (see FIG. 10; light is extracted in the direction of the arrow in FIG. 10)” in which light is extracted from the side of the array board 71, thin film encapsulation involves forming an EL film and then forming an aluminum electrode which will serve as a cathode on the EL film. Then, a resin layer is formed as a cushioning layer on the aluminum layer. Anorganic material such as acrylic or epoxy may be used for a cushioning layer. Suitable film thickness is from 1 μm to 10 μm (both inclusive). More preferably, the film thickness is from 2 μm to 6 μm (both inclusive). The encapsulation film 74 is formed on the cushioning film. Without the cushioning film, structure of the EL film would be deformed by stress, resulting in streaky defects. As described above, the thin encapsulation film 111 may be made, for example, of DLC (diamond-like carbon) or an electrolytic capacitor of a laminar structure (structure consisting of thin dielectric films and aluminum films vapor-deposited alternately).

[0350] In the case of “topside extraction (see FIG. 11; light is extracted in the direction of the arrow in FIG. 11)” in which light is extracted from the side of the EL layer 15, thin film encapsulation involves forming the EL film 15 and then forming an Ag—Mg film 20 angstrom (inclusive) to 300 angstrom thick on the EL film 15 to serve as a cathode (anode) A transparent electrode such as ITO is formed on the film to reduce resistance. Then, a resin layer is formed as a cushioning layer on the electrode film. A thin encapsulation film 111 is formed on the cushioning film.

[0351] Half the light produced by the organic EL layer 15 is reflected by the metal electrode 106 and emitted through the array board 71. However, the metal electrode 106 reflects extraneous light, resulting in glare, which lowers display contrast. To deal with this situation, a λ/4 phase plate 108 and polarizing plate (polarizing film) 109 are placed on the array board 71. These are generally called circular polarizing plates (circular polarizing sheets).

[0352] Incidentally, if the pixels are reflective electrodes, the light produced by the organic EL layer 15 is emitted upward. Thus, needless to say, the phase plate 108 and polarizing plate 109 are placed on the side from which light is emitted. Reflective pixels can be obtained by making pixel electrodes 105 from aluminum, chromium, silver, or the like. Also, by providing projections (or projections and depressions) on a surface of the pixel electrodes 105, it is possible to increase an interface with the organic EL layer 15, and thereby increase the light-emitting area, resulting in improved light-emission efficiency. Incidentally, the reflective film which serves as the cathode 106 (anode 105) is made as a transparent electrode. If reflectance can be reduced to 30% or less, no circular polarizing plate is required. This is because glare is reduced greatly. Light interference is reduced as well.

[0353] Preferably, LDD (low doped drain) structure is used for the transistors 11. The EL elements will be described herein taking organic EL elements (known by various abbreviations including OEL, PEL, PLED, OLED) 15 as an example, but this is not restrictive and inorganic EL elements may be used as well.

[0354] An organic EL display panel of active-matrix type must satisfy two conditions: that it is capable of selecting a specific pixel and give necessary display information and that it is capable of passing current through the EL element throughout one frame period.

[0355] To satisfy the two conditions, in a conventional organic EL pixel configuration shown in FIG. 46, a switching transistor is used as a first transistor 11b to select the pixel and a driver transistor is used as a second transistor 11a to supply current to an EL element (EL film) 15.

[0356] To display a gradation using this configuration, a voltage corresponding to the gradation must be applied the gate of the driver transistor 11a. Consequently, variations in a turn-on current of the driver transistor 11a appear directly in display.

[0357] The turn-on current of a transistor is extremely uniform if the transistor is monocrystalline. However, in the case of a low-temperature polycrystalline transistor formed on an inexpensive glass substrate by low-temperature polysilicon technology at a temperature not higher than 450, its threshold varies in a range of ±0.2 V to 0.5 V. The turn-on current flowing through the driver transistor 11a varies accordingly, causing display irregularities. The irregularities are caused not only by variations in the threshold voltage, but also by mobility of the transistor and thickness of a gate insulating film. Characteristics also change due to degradation of the transistor 11.

[0358] This phenomenon is not limited to low-temperature polysilicon technologies, and can occur in transistors formed on semiconductor films grown in solid-phase (CGS) by high-temperature polysilicon technology at a process temperature of 450 degrees (centigrade) or higher. Besides, the phenomenon can occur in organic transistors and amorphous silicon transistors.

[0359] As described below, the present invention provides a configuration or scheme which can accommodate the above technologies. Description will be given herein mainly of transistors produced by the low-temperature polysilicon technology.

[0360] In a method which displays gradations by the application of voltage as shown in FIG. 46, device characteristics must be controlled strictly to obtain a uniform display. However, current low-temperature polycrystalline polysilicon transistors or the like cannot satisfy a specification which prescribes that variations be kept within a predetermined range.

[0361] Each pixel structure in an EL display panel according to the present invention comprises at least four transistors 11 and an EL element as shown concretely in FIG. 1. Pixel electrodes are configured to overlap with a source signal line. Specifically, the pixel electrodes 105 are formed on an insulating film or planarized acrylic film formed on the source signal line 18 for insulation. A structure in which pixel electrodes overlap with at least part of the source signal line 18 is known as a high aperture (HA) structure. This reduces unnecessary light interference and allows proper light emission.

[0362] When the gate signal line (first scanning line) 17a is activated (a turn-on voltage is applied), a current to be passed through the EL element 15 is delivered from the source driver circuit 14 via the driver transistor 11a and switching transistor 11c of the EL element 15. Also, upon activation of (application of a turn-on voltage to) the gate signal line 17a, the transistor 11b opens to cause a short circuit between gate and drain of the transistor 11a and gate voltage (or drain voltage) of the transistor 11a is stored in a capacitor (storage capacitance, additional capacitance) 19 connected between the gate and drain of the transistor 11a (see FIG. 3(a)).

[0363] Preferably, the capacitor (storage capacitance) 19 should be from 0.2 pF to 2 pF both inclusive. More preferably, the capacitor (storage capacitance) 19 should be from 0.4 pF to 1.2 pF both inclusive. The capacity of the capacitor 19 is determined taking pixel size into consideration. If the capacity needed for a single pixel is Cs (pF) and an area (rather than an aperture ratio) occupied by the pixel is Sp (square μm), a condition 500/S≦Cs≦20000/S, and more preferably a condition 1000/Sp≦Cs≦10000/Sp should be satisfied. Since gate capacity of the transistor is small, Q as referred to here is the capacity of the storage capacitance (capacitor) 19 alone.

[0364] The gate signal line 17a is deactivated (a turn-off voltage is applied), a gate signal line 17b is activated, and a current path is switched to a path which includes the first transistor 11a, a transistor 11d connected to the EL element 15, and the EL element 15 to deliver the stored current to the EL element 15 (see FIG. 3(b)).

[0365] In this circuit, a single pixel contains four transistors 11. The gate of the transistor 11a is connected to the source of the transistor 11b. The gates of the transistors 11b and 11c are connected to the gate signal line 17a. The drain of the transistor 11b is connected to the source of the transistor 11c and source of the transistor 11d. The drain of the transistor 11c is connected to the source signal line 18. The gate of the transistor 11d is connected to the gate signal line 17b and the drain of the transistor 11d is connected to the anode electrode of the EL element 15.

[0366] Incidentally, all the transistors in FIG. 1 are P-channel transistors. Compared to N-channel transistors, P-channel transistors have more or less lower mobility, but they are preferable because they are more resistant to voltage and degradation. However, the EL element according to the present invention is not limited to P-channel transistors and the present invention may employ N-channel transistors alone. Also, the present invention may employ both N-channel and P-channel transistors.

[0367] Optimally, P-channel transistors should be used for all the transistors 11 composing pixels as well as for the built-in gate driver circuits 12. By composing an array solely of P-channel transistors, it is possible to reduce the number of masks to 5, resulting in low costs and high yields.

[0368] To facilitate understanding of the present invention, the configuration of the EL element according to the present invention will be described below with reference to FIG. 3. The EL element according to the present invention is controlled using two timings. The first timing is the one when required current values are stored. Turning on the transistor 11b and transistor 11c with this timing provides an equivalent circuit shown in FIG. 3(a). A predetermined current Iw is applied from signal lines. This makes the gate and drain of the transistor 11a connected, allowing the current Iw to flow through the transistor 11a and transistor 11c. Thus, the gate-source voltage of the transistor 11a is such that allows 11 to flow.

[0369] The second timing is the one when the transistor 11a and transistor 11c are closed and the transistor 11d is opened. The equivalent circuit available at this time is shown in FIG. 3(b). The source-gate voltage of the transistor 11a is maintained. In this case, since the transistor 11a always operates in a saturation region, the current Iw remains constant.

[0370] Results of this operation are shown in FIG. 5. Specifically, reference numeral 51a in FIG. 5(a) denotes a pixel (row) (write pixel row) programmed with current at a certain time point in a display screen 50. The pixel row 51a is non-illuminated (non-display pixel (row)) as illustrated in FIG. 5(b). Other pixels (rows) are display pixels (rows) 53 (current flows through the EL elements 15 of the pixels 16 in the display area 53, causing the EL elements 15 to emit light).

[0371] In the pixel configuration in FIG. 1, the programming current Iw flows through the source signal line 18 during current programming as shown in FIG. 3(a). The current Iw flows through the transistor 11a and voltage is set (programmed) in the capacitor 19 in such a way as to maintain the current Iw. At this time, the transistor 11d is open (off).

[0372] During a period when the current flows through the EL element 15, the transistors 11c and 11b turn off and the transistor 11d turns on as shown in FIG. 3(b). Specifically, a turn-off voltage (Vgh) is applied to the gate signal line 17a, turning off the transistors 11b and 11c. On the other hand, a turn-on voltage (Vgl) is applied to the gate signal line 17b, turning on the transistor 11d.

[0373] A timing chart is shown in FIG. 4. The subscripts in brackets in FIG. 4 (e.g., (1)) indicate pixel row numbers. Specifically, a gate signal line 17a (1) denotes a gate signal line 17a in a pixel row (1). Also, *H (where “*” is an arbitrary symbol or numeral and indicates a horizontal scanning line number) in the top row in FIG. 4 indicates a horizontal scanning period. Specifically, 1 H is a first horizontal scanning period. Incidentally, the items (1 H number, 1-H cycle, order of pixel row numbers, etc.) described above are intended to facilitate explanation and are not intended to be restrictive.

[0374] As can be seen from FIG. 4, in each selected pixel row (it is assumed that the selection period is 1 H), when a turn-on voltage is applied to the gate signal line 17a, a turn-off voltage is applied to the gate signal line 17b. During this period, no current flows through the EL element 15 (non-illuminated). In non-selected pixel rows, a turn-off voltage is applied to the gate signal line 17a and a turn-on voltage is applied to the gate signal line 17b. During this period, a current flows through the EL element 15 (illuminated).

[0375] Incidentally, the gate of the transistor 11a and gate of the transistor 11c are connected to the same gate-signal line 11a. However, the gate of the transistor 11a and gate of the transistor 11c may be connected to different gate signal lines 11 (see FIG. 32). Then, one pixel will have three gate signal lines (two in the configuration in FIG. 1). By controlling ON/OFF timing of the gate of the transistor 11b and ON/OFF timing of the gate of the transistor 11c separately, it is possible to further reduce variations in the current value of the EL element 15 due to variations in the transistor 11a.

[0376] By sharing the gate signal line 17a and gate signal line 17b and using different conductivity types (N-channel and P-channel) for the transistors 11c and 11d, it is possible to simplify the drive circuit and improve the aperture ratio of pixels.

[0377] With this configuration, a write paths from signal lines are turned off according to operation timing of the present invention That is, when a predetermined current is stored, an accurate current value is not stored in a capacitance (capacitor) between the source (S) and gate (G) of the transistor 11a if a current path is branched. By using different conductivity types for the transistors 11c and 11d and controlling their thresholds, it is possible to ensure that when scanning lines are switched, the transistor 11d is turned on after the transistor 11c is turned off.

[0378] In that case, however, since the thresholds of the transistors must be controlled accurately, it is necessary to pay attention to processes. The circuit described above can be implemented using four transistors at the minimum, but even if more than four transistors including a transistor 11e are cascaded for more accurate timing control or for reduction of mirror effect (described later), the principle of operation is the same. By adding the transistor 11e, it is possible to deliver programming current to the EL element 15 more precisely via the transistor 11c.

[0379] Incidentally, the pixel configuration according to the present invention is not limited to those shown in FIGS. 1 and 2. For example, pixels may be configured as shown in FIG. 113. FIG. 113 lacks the transistor 11d unlike the configuration in FIG. 1. Instead, a changeover switch 1131 is formed or placed. The switch 11d in FIG. 1 functions to turn on and off (pass and shut off) the current delivered from the driver transistor 11a to the EL element 15. As also described in subsequent examples, the on/off control function of the transistor 11d constitutes an important part of the present invention. The configuration in FIG. 113 achieves the on/off function without using the transistor 11d.

[0380] In FIG. 113, a terminal a of the changeover switch 1131 is connected to anode voltage Vdd. Incidentally, the voltage applied to the terminal a is not limited to the anode voltage Vdd. It may be any voltage that can turn off the current flowing through the EL element 15.

[0381] A terminal b of the changeover switch 1131 is connected to cathode voltage (indicated as ground in FIG. 113). Incidentally, the voltage applied to the terminal b is not limited to the cathode voltage. It may be any voltage that can turn on the current flowing through the EL element 15.

[0382] A terminal c of the changeover switch 1131 is connected with a cathode terminal of the EL element 15. Incidentally, the changeover switch 1131 may be of any type as long as it has a capability to turn on and off the current flowing through the EL element 15. Thus, its installation location is not limited to the one shown in FIG. 113 and the switch may be located anywhere on the path through which current is delivered to the EL element 15. Also, the switch is not limited by its functionality as long as the switch can turn on and off the current flowing through the EL element 15. In short, the present invention can have any pixel configuration as long as switching means capable of turning on and off the current flowing through the EL element 15 is installed on the current path for the EL element 15.

[0383] Also, the term “off” here does not mean a state in which no current flows, but it means a state in which the current flowing through the EL element 15 is reduced to below normal. The items mentioned above also apply to other configurations of the present invention.

[0384] The changeover switch 1131 will require no explanation because it can be implemented easily by a combination of P-channel and N-channel transistors. For example, it can be implemented by two circuits of analog switches. Of course, the switch 1131 can be constructed of only P-channel or N-channel transistors because it only turns off the current flowing through the EL element 15.

[0385] When the switch 1131 is connected to the terminal a, the Vdd voltage is applied to the cathode terminal of the EL element 15. Thus, current does not flow through the EL element 15 regardless of the voltage state of voltage held by the gate terminal G of the driver transistor 11a. Consequently, the EL element 15 is non-illuminated.

[0386] When the switch 1131 is connected to the terminal b, the GND voltage is applied to the cathode terminal of the EL element 15. Thus, current flows through the EL element 15 according to the state of voltage held by the gate terminal G of the driver transistor 11a. Consequently, the EL element 15 is illuminated.

[0387] Thus, in the pixel configuration shown in FIG. 113, no switching transistor 11d is formed between the driver transistor 11a and the EL element 15. However, it is possible to control the illumination of the EL element 15 by controlling the switch 1131.

[0388] In the pixel configurations shown in FIGS. 1, 2, etc., one pixel contains one driver transistor 11a. However, the present invention is not limited to this and one pixel may contain two or more driver transistors 11a. An example is shown in FIG. 116, where one pixel contains two driver transistors 11a1 and 11a2, whose gate terminals are connected to a common capacitor 19. By using a plurality of driver transistors 11a, it is possible to reduce variations in programming current. The other part of the configuration is the same as those shown in FIG. 1 and the like, and thus description thereof will be omitted.

[0389] In FIGS. 1 and 2, the current outputted by the driver transistor 11a is passed through the EL element 15 and turned on and off by the switching transistor 11d formed between the driver transistor 11a and the EL element 15. However, the present invention is not limited to this. For example, another configuration is illustrated in FIG. 117.

[0390] In the example shown in FIG. 117, the current delivered to the EL element 15 is controlled by the driver transistor 11a. The current flowing through the EL element 15 is turned on and off by the switching element 11d placed between the Vdd terminal and EL element 15. Thus, according to the present invention, the switching element 11d may be placed anywhere as long as it can control the current flowing through the EL element 15.

[0391] Variations in the characteristics of the transistor 11a are correlated to the transistor size. To reduce the variations in the characteristics, preferably the channel length of the first transistor 11a is from 5 μm to 100 μm (both inclusive). More preferably, it is from 10 μm to 50 μm (both inclusive). This is probably because a long channel length L increases grain boundaries contained in the channel, reducing electric fields, and thereby suppressing kink effect.

[0392] Thus, according to the present invention, circuit means which controls the current flowing through the EL element 15 is constructed, formed, or placed on the path along which current flows into the EL element 15 and the path along which current flows out of the EL element 15 (i.e., the current path for the EL element 15).

[0393] Even in the case of current mirroring, a type of current programming, by forming or placing a transistor 11g as a switching element between the driver transistor 11b and EL element 15 as shown in FIG. 114, it is possible to turn on and off (control) the current flowing through the EL element 15. Of course, the transistor 11g may be substituted with the switch 1131 in FIG. 113.

[0394] Incidentally, although the switching transistors 11d and 11c in FIG. 114 are connected to a single gate signal line 17a, the switching transistor 11c may be controlled by a gate signal line 17a1 and the switching transistor 11d may be controlled by a gate signal line 17a2 as shown in FIG. 115. The configuration in FIG. 115 makes pixel 16 control more versatile.

[0395] As shown in FIG. 42(a), the transistors 11b and 11c may be N-channel transistors. Also, as shown in FIG. 42(b), the transistors 11c and 11d may be P-channel transistors.

[0396] An object of the present invention is to propose a circuit configuration in which variations in transistor characteristics do not affect display. Four or more transistors are required for that. When determining circuit constants using transistor characteristics, it is difficult to determine appropriate circuit constants unless the characteristics of the four transistors are not consistent. Both thresholds of transistor characteristics and mobility of the transistors vary depending on whether the channel direction is horizontal or vertical with respect to the longitudinal axis of laser irradiation. Incidentally, variations are more of the same in both cases. However, the mobility and average threshold vary between the horizontal direction and vertical direction. Thus, it is desirable that all the transistors in a pixel have the same channel direction.

[0397] Also, if the capacitance value of the storage capacitance 19 is Cs and the turn-off current value of the second transistor 11b is Ioff, preferably the following equation is satisfied.
3<Cs/Ioff<24

[0398] More preferably the following equation is satisfied.
6<Cs/Ioff<18

[0399] By setting the turn-off current of the transistor 11b to 5 pA or less, it is possible to reduce changes in the current flowing through the EL to 2% or less. This is because when leakage current increases, electric charges stored between the gate and source (across the capacitor) cannot be held for one field with no voltage applied. Thus, the larger the storage capacity of the capacitor 19, the larger the permissible amount of the turn-off current. By satisfying the above equation, it is possible to reduce fluctuations in current values between adjacent pixels to 2% or less.

[0400] Also, preferably transistors composing an active matrix are p-channel polysilicon thin-film transistors and the transistor 11b is a dual-gate or multi-gate transistor. As high an ON/OFF ratio as possible is required of the transistor 11b, which acts as a source-drain switch for the transistor 11a. By using a dual-gate or multi-gate structure for the transistor 11b, it is possible to achieve a high ON/OFF ratio.

[0401] The semiconductor films composing the transistors 11 in the pixel 16 are generally formed by laser annealing in low-temperature polysilicon technology. Variations in laser annealing conditions result in variations in transistor 11 characteristics. However, if the characteristics of the transistors 11 in the pixel 16 are consistent, it is possible to drive the pixel using current programming such as the one shown in FIG. 1 so that a predetermined current will flow through the EL element 15. This is an advantage lacked by voltage programming. Preferably the laser used is an excimer laser.

[0402] Incidentally, the semiconductor film formation according to the present invention is not limited to the laser annealing method. The present invention may also use a heat annealing method and a method which involves solid-phase (CGS) growth. Besides, the present invention is not limited to the low-temperature polysilicon technology and may use high-temperature polysilicon technology. Also, the semiconductor films may be formed by amorphous silicon technology.

[0403] To deal with this problem, the present invention moves a laser spot (laser irradiation range) 72 in parallel to the source signal line 18 as shown in FIG. 7. Also, the laser spot 72 is moved in such a way as to align with one pixel row. Of course, the number of pixel rows is not limited to one. For example, laser may be shot by treating RGB in FIG. 55 (three pixel columns in this case) as a single pixel 16. Also, laser may be directed at two or more pixels at a time. Needless to say, moving laser irradiation ranges may overlap (it is usual for moving laser irradiation ranges to overlap).

[0404] Pixels are constructed in such a way that three pixels of RGB will form a square shape. Thus, each of the R, G, B pixels has oblong shape. Consequently, by performing annealing using an oblong laser spot 72, it is possible to eliminate variations in the characteristics of the transistors 11 within each pixel. Also, the characteristics (mobility, Vt, S value, etc.) of the transistors 11 connected to the same source signal line 18 can be made uniform (i.e., although the transistors 11 connected to adjacent source signal lines 18 may differ in characteristics, the characteristics of the transistors 11 connected to the same source signal line can be made almost equal).

[0405] In the configuration shown in FIG. 7, three panels are placed lengthwise within the length of the laser spot 72. An annealing apparatus which emits the laser spot 72 recognizes positioning markers 73a and 73b on a glass substrate 74 (automatic positioning based on pattern recognition) and moves the laser spot 72. The positioning markers 73 are recognized by a pattern recognition apparatus. The annealing apparatus (not shown) recognizes the positioning markers 73 and determines the location of the pixel column (makes the laser irradiation range 72 parallel to the source signal line 18). It emits the laser spot 72 in such a way as to overlap with the location of each pixel column for sequential annealing.

[0406] Preferably, the laser annealing method (which involves emitting a linear laser spot in parallel to the source signal line 18) described with reference to FIG. 7 is used for current programming of an organic EL display panel, in particular. This is because the transistors 11 placed in the direction parallel to the source signal line have the same characteristics (the characteristics of the pixel transistors adjacent in the longitudinal direction are quite similar to each other). This reduces changes in the voltage level of the source signal lines when the pixels are driven by current, and thus reduces the chances of insufficient write current.

[0407] For example, in the case of white raster display, since almost the same current is passed through the transistors 11a in adjacent pixels, the current outputted from the source driver IC 14 does not have significant amplitude changes. If the transistors 11a in FIG. 1 have the same characteristics and the currents used for current programming of pixels have the same value within the pixel column, the potential of the source signal line 18 during the current programming is constant. Thus, no potential fluctuation occurs in the source signal line 18. If the transistors 11a connected to the same source signal line 18 have almost the same characteristics, there should be no significant potential fluctuation in the source signal line 18. This is also true to other current-programmable pixel configurations such as the one shown in FIG. 38 (thus, it is preferable to use the manufacturing method shown in FIG. 7).

[0408] A method which involves programming two or more pixel rows simultaneously and which are described with reference to FIG. 27, 30, etc. can achieve a uniform image display (because the method is not prone to display irregularities due mainly to variations in transistor characteristics). In the case of FIG. 27, etc., since a plurality of pixel rows are selected simultaneously, if the transistors in adjacent pixel rows are uniform, irregularities in the characteristics of the transistors placed in the lengthwise direction can be absorbed by the source driver circuit 14.

[0409] Incidentally, although an IC chip is illustrated in FIG. 7 as being stacked on the source driver circuit 14, this is not restrictive and it goes without saying that the source driver circuit 14 may be formed in the same process as the pixel 16.

[0410] The present invention, in particular, ensures that a voltage threshold Vth2 of the driver transistor 11b will not fall below a voltage threshold Vth1 of the corresponding driver transistor 11a in the pixel. For example, gate length L2 of the transistor 11b is made longer than gate length L1 of the transistor 11a so that Vth2 will not fall below Vth1 even if process parameters of these thin-film transistors change. This makes it possible to suppress subtle current leakage.

[0411] Incidentally, the items mentioned above also apply to pixel configuration of a current mirror shown in FIG. 38. The pixel in FIG. 38 consists of a driver transistor 11a through which a signal current flows, a driver transistor 11b which controls drive current flowing through a light-emitting element such as an EL element 15, a transistor 11c which connects or disconnects a pixel circuit and data line “data” by controlling a gate signal line 17a1, a switching transistor 11d which shorts the gate and drain of the transistor 11a during a write period by controlling a gate signal line 17a2, a capacitance C19 which holds gate-source voltage of the transistor 11a after application of voltage, the EL element 15 serving as a light-emitting element, etc.

[0412] In FIG. 38, the transistors 11c and 11d are N-channel transistors and other transistors are P-channel transistors, but this is only exemplary and are not restrictive. A capacitance Cs has its one end connected to the gate of the transistor 11a, and the other end to Vdd (power supply potential), but it may be connected to any fixed potential instead of Vdd. The cathode (negative pole) of the EL element 15 is connected to the ground potential.

[0413] Next, the EL display panel or EL display apparatus of the present invention will be described. FIG. 6 is an explanatory diagram which mainly illustrates a circuit of the EL display apparatus. Pixels 16 are arranged or formed in a matrix. Each pixel 16 is connected with a source driver circuit 14 which outputs current for use in current programming of the pixel. In an output stage of the source driver circuit 14 are current mirror circuits (described later) corresponding to the bit count of a video signal. For example, if 64 gradations are used, 63 current mirror circuits are formed on respective source signal lines so as to apply desired current to the source signal lines 18 when an appropriate number of current mirror circuits is selected (see FIG. 48).

[0414] Incidentally, the minimum output current of one current mirror circuit is from 10 nA to 50 nA (both inclusive). Preferably, the minimum output current of the current mirror circuit should be from 15 nA to 35 nA (both inclusive) to secure accuracy of the transistors composing the current mirror circuit in the source driver IC 14.

[0415] Besides, a precharge or discharge circuit is incorporated to charge or discharge the source signal line 18 forcibly. Preferably, voltage (current) output values of the precharge or discharge circuit which charges or discharges the source signal line 18 forcibly can be set separately for R, G, and B. This is because the thresholds of the EL element 15 differ among R, G, and B (regarding the precharge circuit refer to FIGS. 65 and 67 and its explanation).

[0416] Organic EL elements are known to have heavy temperature dependence (temperature characteristics). To adjust changes in emission brightness caused by the temperature characteristics, reference current is adjusted (varied) in an analog fashion by adding nonlinear elements such as thermistors or posistors to the current mirror circuits to vary output current and adjusting the changes due to the temperature characteristics with the thermistors or the like.

[0417] According to the present invention, the source driver circuit 14 is made of a semiconductor silicon chip and connected with a terminal on the source signal line 18 of the array board 71 by glass-on-chip (COG) technology. The source driver circuit 14 can be mounted not only by the COG technology. It is also possible to mount the source driver circuit 14 by chip-on-film (COF) technology and connect it to the signal lines of the display panel. Regarding the driver IC, it may be made of three chips by constructing a power supply IC 82 separately.

[0418] On the other hand, the gate driver circuit 12 is formed by low-temperature polysilicon technology. That is, it is formed in the same process as the transistors in pixels. This is because the gate driver circuit 12 has a simpler internal structure and lower operating frequency than the source driver circuit 14. Thus, it can be formed easily even by low-temperature polysilicon technology and allows bezel width to be reduced. Of course, it is possible to construct the gate driver circuit 12 from a silicon chip and mount it on the array board 71 using the COG technology. Also, switching elements such as pixel transistors as well as gate drivers may be formed by high-temperature polysilicon technology or may be formed of an organic material (organic transistors).

[0419] The gate driver circuit 12 incorporates a shift register circuit 61a for a gate signal line 17a and a shift register circuit 61b for a gate signal line 17b. The shift register circuits 61 are controlled by positive-phase and negative-phase clock signals (CLKxP and CLKxN) and a start pulse (STx) (see FIG. 6). Besides, it is preferable to add an enable (ENABL) signal which controls output and non-output from the gate signal line and an up-down (UPDWN) signal which turns a shift direction upside down. Also, it is preferable to install an output terminal to ensure that the start pulse is shifted by the shift register and is outputted. Incidentally, shift timings of the shift registers are controlled by a control signal from a control IC 81. Also, the gate driver circuit 12 incorporates a level shift circuit which level-shifts external data.

[0420] Since the shift register circuits 61 have small buffer capacity, they cannot drive the gate signal lines 17 directly. Therefore, at least two or more inverter circuits 62 are formed between each shift register circuit 61 and an output gate 63 which drives the gate signal line 17.

[0421] The same applies to cases in which the source driver circuit 14 is formed on the array board 71 by polysilicon technology such as low-temperature polysilicon technology. A plurality of inverter circuits are formed between an analog switching gate such as a transfer gate which drives the source signal line 18 and the shift register of the source driver circuit 14. The following matters (shift register output and output stages which drive signal lines (inverter circuits placed between output stages such as output gates or transfer gates) are common to the gate driver circuit and source driver circuit.

[0422] For example, although the output from the source driver circuit 14 is shown in FIG. 6 as being connected directly to the source signal line 18, actually the output from the shift register of the source driver is connected with multiple stages of inverter circuits, and the inverter outputs are connected to analog switching gates such as transfer gates.

[0423] The inverter circuit 62 consists of a P-channel MOS transistor and N-channel MOS transistor. As described earlier, the shift register circuit 61 of the gate driver circuit 12 has its output end connected with multiple stages of inverter circuits 62 and the final output is connected to the output gate 63. Incidentally, the inverter circuit 62 may be composed solely of P-channel MOS transistors. In that case, however, the circuit may be configured simply as a gate circuit rather than an inverter.

[0424] FIG. 8 is a block diagram of signal and voltage supplies on a display apparatus according to the present invention or a block diagram of the display apparatus. Signals (power supply wiring, data wiring, etc.) are supplied from the control IC 81 to a source driver circuit 14a via a flexible board 84.

[0425] In FIG. 8, a control signal for the gate driver circuit 12 is generated by the control IC, level-shifted by the source driver circuit 14, and applied to the gate driver circuit 12. Since drive voltage of the source driver circuit 14 is 4 to 8 (V), the control signal with an amplitude of 3.3 (V) outputted from the control IC 81 can be converted into a signal with an amplitude of 5 (V) which can be received by the gate driver circuit 12.

[0426] In FIG. 8 and the like, what is denoted by reference numeral 14 has been described as a source driver, but instead of being a mere driver, it may incorporate a power circuit, buffer circuit (including a circuit such as a shift register), data conversion circuit, latch circuit, command decoder, shifting circuit, address conversion circuit, image memory, etc. Needless to say, a three-side free configuration or other configuration, drive system, etc. described with reference to FIG. 9 and the like are also applicable to the configuration described with reference to FIG. 8 and the like.

[0427] When the display panel is used for information display apparatus such as a cell phone, it is preferable to mount (form) the source driver IC (circuit) 14 and gate driver IC (circuit) 12 on one side of the display panel as shown in FIG. 9 (incidentally, a configuration in which driver ICs (circuits) are mounted (formed) on one side of a display panel is referred to as a three-side free configuration (structure). Conventionally, the gate driver IC 12 is mounted on an X side of a display area and a source is mounted on a Y side). This makes it easy in the design to center the center line of a display screen 50 on the display apparatus and mount the driver ICs. Using the three-side free configuration, the gate driver circuit may be produced by high-temperature polysilicon technology, low-temperature polysilicon technology or the like (i.e., at least one of the source driver circuit 14 and gate driver circuit 12 may be formed directly on the array board 71 by polysilicon technology).

[0428] Incidentally, the three-side free configuration includes not only a configuration in which ICs are placed or formed directly on the array board 71, but also a configuration in which a film (TCP, TAB, or other technology) with a source driver IC (circuit) 14 and gate driver IC (circuit) 12 mounted are pasted on one side (or almost one side) of the array board 71. That is, the three-side free configuration includes configurations and arrangements in which two sides are left free of ICs and all similar configurations.

[0429] If the gate driver circuit 12 is placed beside the source driver circuit 14 as shown in FIG. 9, the gate signal line 17 must be formed along the side C.

[0430] Incidentally, the thick solid line in FIG. 9, etc. indicates gate signal lines 17 formed in parallel. Thus, as many gate signal lines 17 as there are scanning signal lines are formed in parallel in part b (bottom of the screen) while a single gate signal line 17 is formed in part a (top of the screen).

[0431] Spacing between the gate signal lines 17 formed on the side C is from 5 μm to 12 μm (both inclusive) If it is less than 5 μm, parasitic capacitance will cause noise on adjacent gate signal lines. It has been shown experimentally that parasitic capacitance has significant effects when the spacing is 7 μm or less. Furthermore, when the spacing is less than 5 μm, beating noise and other image noise appear intensely on the display screen. In particular, noise generation differs between the right and left sides of the screen and it is difficult to reduce the beating noise and other image noise. When the spacing exceeds 12 μm, bezel width D of the display panel becomes too large to be practical.

[0432] To reduce the image noise, a ground pattern (conductive pattern which has been fixed at a constant voltage or set generally at a stable potential) can be placed under or above the gate signal lines 17. Alternatively, a separate shield plate (shield foil: a conductive pattern which has been fixed at a constant voltage or set generally at a stable potential) may be placed on the gate signal lines 17.

[0433] The gate signal lines 17 on the side C in FIG. 9 may be formed of ITO electrodes. However, to reduce resistance, preferably they are formed by laminating ITO and thin metal films. Also preferably they are formed of metal films. When using an ITO laminate, a titanium film is formed on the ITO, and a thin aluminum film or aluminum-molybdenum alloy film is formed on it. Alternatively, a chromium is formed on the ITO. For metal films, thin aluminum films or chromium films are used. This also applies to other examples of the present invention.

[0434] Incidentally, although it has been stated with reference to FIG. 9 and the like that the gate signal lines 17 are placed on one side of the display area, this is not restrictive and they may be placed on both sides. For example, the gate signal line 17a may be placed (formed) on the right side of the display screen 50 while the gate signal line 17b may be placed (formed) on the left side of the display screen 50. This also applies to other examples.

[0435] Also, the source driver IC 14 and gate driver IC 12 may be integrated into a single chip. Then, it suffices to mount only one IC chip on the display panel. This also reduces implementation costs. Furthermore, this makes it possible to simultaneously generate various voltages for use in the single-chip driver IC.

[0436] Incidentally, although it has been stated that the source driver IC 14 and gate driver IC 12 are made of silicon or other semiconductor wafers and mounted on the display panel, this is not restrictive. Needless to say, they may be formed directly on the display panel 82 using low-temperature polysilicon technology or high-temperature polysilicon technology.

[0437] Although it has been stated that pixels are of the three primary colors of R, G, and B, this is not restrictive. They may be of three colors of cyan, yellow, and magenta. They may be of two colors of B and yellow. Of course, they may be monochromatic. Alternatively, they may be of six colors of R, G, B, cyan, yellow, and magenta or of five colors of R, G, B, cyan, and magenta. These are natural colors which provide an expanded color reproduction range, enabling good display. Thus, the EL display apparatus according to the present invention is not limited to those which provide color display using the three primary colors of R, G, and B.

[0438] Mainly three methods are available to colorize an organic EL display panel. One of them is a color conversion method. It suffices to form a single layer of blue as a light-emitting layer. The remaining green and red colors needed for full color display can be produced from the blue color through color conversion. Thus, this method has the advantage of eliminating the need to paint the R, G, and B colors separately and prepare organic EL materials for the R, G, and B colors. The color conversion method does not lower yields unlike the multi-color painting method. Any of the three methods can be applied to the EL display panel of the present invention.

[0439] Also, in addition to the three primary colors, white light-emitting pixels may be formed. The white light-emitting pixels can be created (formed or constructed) by laminating R, G, and B light-emitting structures. A set of pixels consists of pixels for the three primary colors RGB and a white light-emitting pixel 16W. Forming the white light-emitting pixels makes it easier to express peak brightness of white, and thus possible to implement bright image display.

[0440] Even when using a set of pixels for the three primary colors RGB, it is preferable to vary pixel electrode areas for the different colors. Of course, an equal area may be used if luminous efficiencies of the different colors as well as color purity are well balanced. However, if one or more colors are poorly balanced, preferably the pixel electrodes (light-emitting areas) are adjusted. The electrode area for each color can be determined based on current density. That is, when white balance is adjusted in a color temperature range of 7000 K (Kelvin) to 12000 K (both inclusive), difference between current densities of different colors should be within ±30%. More preferably, the difference should be within +15%. For example, if current densities are around 100 A/square meter, all the three primary colors should have a current density of 70 A/square meter to 130 A/square meter (both inclusive) More preferably, all the three primary colors should have a current density of 85 A/square meter to 115 A/square meter (both inclusive).

[0441] The EL element 15 is a self-luminous element. When light from this self-luminous element enters a transistor serving as a switching element, a photoconductive phenomenon occurs. The photoconductive phenomenon is a phenomenon in which leakage (off-leakage) increases due to photoexcitation when a switching element such as a transistor is off.

[0442] To deal with this problem, the present invention forms a shading film under the gate driver circuit 12 (source driver circuit 14 in some cases) and under the pixel transistor 11. The shading film is formed of thin film of metal such as chromium and is from 50 nm to 150 nm thick (both inclusive). A thin film will provide a poor shading effect while a thick film will cause irregularities, making it difficult to pattern the transistor 11A1 in an upper layer.

[0443] In the case of the driver circuit 12 and the like, it is necessary to reduce penetration of light not only from the topside, but also from the underside. This is because the photoconductive phenomenon will cause malfunctions. If cathode electrodes are made of metal films, the present invention also forms a cathode electrode on the surface of the driver 12 and the like and uses it as a shading film.

[0444] However, if a cathode electrode is formed on the driver 12, electric fields from the cathode electrode may cause driver malfunctions or place the cathode electrode and driver circuit in electrical contact. To deal with this problem, the present invention forms at least one layer of organic EL film, and preferably two or more layers, on the driver circuit 12 simultaneously with the formation of organic EL film on the pixel electrode.

[0445] If a short circuit occurs between terminals of one or more transistors 11 or between a transistor 11 and signal line in the pixel, the EL element 15 may become a bright spot which remains illuminated constantly. The bright spot is visually conspicuous and must be turned into a black spot (turned off) The pixel 16 which corresponds to the bright spot is detected and the capacitor 19 is irradiated with laser light to cause a short circuit across the capacitor. As a result, the capacitor 19 can no longer hold electric charges, and thus the transistor 11a can be stopped from passing current. It is desirable to remove that part of a cathode film which will be irradiated with laser light to prevent the laser irradiation from causing a short circuit between a terminal electrode of the capacitor 19 and the cathode film.

[0446] Flaws in a transistor 11 in the pixel 16 will affect the source driver IC 14 and the like. For example, if a source-drain (SD) short circuit 452 occurs in the driver transistor 11a in FIG. 45, a Vdd voltage of the panel is applied to the source driver IC 14. Thus, preferably the power supply voltage of the source driver IC 14 is kept equal to or higher than the power supply voltage Vdd of the panel. Preferably, the reference voltage used by the source driver IC 14 can be adjusted with an electronic regulator 451.

[0447] If an SD short circuit 452 occurs in the transistor 11a, an excessive current flows through the EL element 15. In other words, the EL element 15 remains illuminated constantly (becomes a bright spot). The bright spot is conspicuous as a defect. For example, if a source-drain (SD) short circuit occurs in the transistor 11a in FIG. 45, current flows constantly from the Vdd voltage to the EL element 15 (when the transistor 11d is on) regardless of the magnitude of gate (G) terminal voltage of the transistor 11a. Thus, a bright spot results.

[0448] On the other hand, if an SD short circuit occurs in the transistor 11a and if the transistor 11c is on, the Vdd voltage is applied to the source signal line 18 and to the source driver circuit 14. If the power supply voltage of the source driver circuit 14 is not higher than Vdd, voltage resistance may be exceeded, causing the source driver circuit 14 to rupture. Thus, it is preferable that the power supply voltage of the source driver circuit 14 is equal to or higher than the Vdd voltage (the higher voltage of the panel).

[0449] An SD short circuit of the transistor 11a may go beyond a point defect and lead to rupture of the source driver circuit of the panel. Also, the bright spot is conspicuous, which makes the panel defective. Thus, it is necessary to turn the bright spot into a black spot by cutting the wiring which connects between the transistor 11 and EL element 15. Preferably an optical means such as laser light is used to cut the wiring.

[0450] A drive method according to the present invention will be described below. As shown in FIG. 1, the gate signal line 17a conducts when the row remains selected (since the transistor 11 in FIG. 1 is a P-channel transistor, the gate signal line 17a conducts when it is in low state) and the gate signal line 17b conducts when the row remains non-selected.

[0451] Parasitic capacitance (not shown) is present in the source signal line 18. The parasitic capacitance is caused by the capacitance at the junction of the source signal line 18 and gate signal line 17, channel capacitance of the transistors 11b and 11c, etc.

[0452] The time t required to change the current value of the source signal line 18 is given by t=CV/I, where C is stray capacitance, V is a voltage of the source signal line, and I is a current flowing through the source signal line. Thus, if the current value can be increased ten fold, the time required to change the current value can be reduced nearly tenfold. This also means that the current value can be changed to a predetermined value even if the parasitic capacitance of the source signal line 18 is increased tenfold. Thus, to apply a predetermined current value during a short horizontal scanning period, it is useful to increase the current value.

[0453] When input current is increased tenfold, output current is also increased tenfold, resulting in a tenfold increase in the EL brightness. Thus, to obtain predetermined brightness, a light emission period is reduced tenfold by reducing the conduction period of the transistor 17d in FIG. 1 tenfold compared to a conventional conduction period. Incidentally, the tenfold increases/decreases are cited as an example to facilitate understanding and are not meant to be restrictive.

[0454] Thus, in order to charge and discharge the parasitic capacitance of the source signal line 18 sufficiently and program a predetermined current value into the transistor 11a of the pixel 16, it is necessary to output a relatively large current from the source driver circuit 14. However, when such a large current is passed through the source signal line 18, its current value is programmed into the pixel and a current larger than the predetermined current flows through the EL element 15. For example, if a 10 times larger current is programmed, naturally a 10 times larger current flows through the EL element 15 and the EL element 15 emits 10 times brighter light. To obtain predetermined emission brightness, the time during which the current flows through the EL element 15 can be reduced tenfold. This way, the parasitic capacitance can be charged/discharged sufficiently from the source signal line 18 and the predetermined emission brightness can be obtained.

[0455] Incidentally, although it has been stated that a 10 times larger current value is written into the pixel transistor 11a (more precisely, the terminal voltage of the capacitor 19 is set) and that the conduction period of the EL element 15 is reduced to 1/10, this is only exemplary. In some cases, a 10 times larger current value may be written into the pixel transistor 11a and the conduction period of the EL element 15 may be reduced to 1/5. On the other hand, a 10 times larger current value may be written into the pixel transistor 11a and the conduction period of the EL element 15 may be halved.

[0456] The present invention is characterized in that the write current into a pixel is set at a value other than a predetermined value and that a current is passed through the EL element 15 intermittently. For ease of explanation, it has been stated herein that an N times larger current is written into the pixel transistor 11 and the conduction period of the EL element 15 is reduced to 1/N. However, this is not restrictive. Needless to say, N1 times larger current may be written into the pixel transistor 11 and the conduction period of the EL element 15 may be reduced to 1/N2 (N1 and N2 are different from each other) In white raster display, it is assumed that average brightness over one field (frame) period of the display screen 50 is B0. This drive method performs current (voltage) programming in such a way that the brightness B1 of each pixel 16 is higher than the average brightness B0. Also, a non-display area 53 appears during at least one field (frame) period. Thus, in the drive method according to the present invention, the average brightness over one field (frame) period is lower than B1.

[0457] Incidentally, the non-display area 52 and display area 53 are not necessarily spaced equally. For example, they may appear at random (provided that the display period or non-display period makes up a predetermined value (constant ratio) as a whole). Also, display periods may vary among R, G, and B. That is, display periods of R, G, and B or non-display period can be adjusted to a predetermined value (constant ratio) in such a way as to obtain an optimum white balance.

[0458] To facilitate explanation of the drive method according to the present invention, it is assumed that “1/N” means reducing 1F (one field or one frame) to 1/N. Needless to say, however, it takes time to select one pixel row and to program current values (normally, one horizontal scanning period (1 H)) and error may result depending on scanning conditions.

[0459] For example, the EL element 15 may be illuminated for 1/5 of a period by programming the pixel 16 with an N=10 times larger current. The EL element 15 illuminates 10/5=2 times more brightly. It is also possible to program an N=2 times larger current into the pixel 16 and illuminate the EL element 15 for 1/4 of the period. The EL element 15 illuminates 2/4=0.5 time more brightly. In short, the present invention achieves display other than constant display (1/1, i.e., non-intermittent display) by using a current other than an N=1 time current for current programming. Also, the drive system turns off the current supplied to the EL element 15, at least once during one frame (or one field) period. Also, the drive system at least achieves intermittent display by programming the pixel 16 with a current larger than a predetermined value.

[0460] A problem with an organic (inorganic) EL display is that it uses a display method basically different from that of an CRT or other display which presents an image as a set of displayed lines using an electron gun. That is, the EL display holds the current (voltage) written into a pixel for 1F (one field or one frame) period. Thus, a problem is that displaying moving pictures will result in blurred edges.

[0461] According to the present invention, current is passed through the EL element 15 only for a period of 1F/N, but current is not passed during the remaining period (1F(N−1)/N). Let us consider a situation in which the drive system is implemented and one point on the screen is observed. In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed intermittently in the temporal sense. When moving picture data are displayed intermittently, a good display condition is achieved without edge blur. In short, movie display close to that of a CRT can be achieved.

[0462] The drive method according to the present invention implements intermittent display. However, the intermittent display can be achieved by simply turning on and off the transistor 11d on a 1-H cycle. Consequently, a main clock of the circuit does not differ from conventional ones, and thus there is no increase in the power consumption of the circuit. Liquid crystal display panels need an image memory in order to achieve intermittent display. According to the present invention, image data is held in each pixel 16. Thus, the present invention requires no image memory for intermittent display.

[0463] The present invention controls the current passed through the EL element 15 by simply turning on and off the switching transistor 11d, the transistor 11e, and the like. That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is held as it is in the capacitor 19. Thus, when the transistor 11d is turned on the next time, the current passed through the EL element 15 has the same value as the current flowing through the EL element 15 the previous time. Even to achieve black insertion (intermittent display such as black display), the present invention does not need to speed up the main clock of the circuit. Also, it does not need to elongate a time axis, and thus requires no image memory. Besides, the EL element 15 responds quickly, requiring a short time from application of current to light emission. Thus, the present invention is suitable for movie display, and by using intermittent display, it can solve a problem with conventional data-holding display panels (liquid crystal display panels, EL display panels, etc.) in displaying moving pictures.

[0464] Furthermore, in a large display apparatus, if increased wiring length of the source signal line 18 results in increased parasitic capacitance in the source signal line 18, this can be dealt with by increasing the value of N. When the value of programming current applied to the source signal line 18 is increased N times, the conduction period of the gate signal line 17b (the transistor 11d) can be set to 1F/N. This makes it possible to apply the present invention to television sets, monitors, and other large display apparatus.

[0465] The drive method according to the present invention will be described with reference to drawings in more detail below. The parasitic capacitance of the source signal line 18 is generated by the coupling capacitance with adjacent source signal lines 18, buffer output capacitance of the source driver IC (circuit) 14, cross capacitance between the source signal line 18 and gate signal line 17, etc. This parasitic capacitance is normally 10 pF or larger. In the case of voltage driving, since voltage is applied to the source signal line 18 from the source driver IC 14 at low impedance, more or less large parasitic capacitance does not disturb driving.

[0466] However, in the case of current driving, especially image display at the black level, the pixel capacitor 19 needs to be programmed with a minute current of 20 nA or less. Thus, if parasitic capacitance larger than a predetermined value is generated, the parasitic capacitance cannot be charged and discharged during the time when one pixel row is programmed (normally within 1 H, but not limited to 1 H because two pixel rows may be programmed simultaneously). If the parasitic capacitance cannot be charged and discharged within a period of 1 H, sufficient current cannot be written into the pixel, resulting in inadequate resolution.

[0467] In the pixel configuration in FIG. 1, the programming current Iw flows through the source signal line 18 during current programming as shown in FIG. 3(a). The current Iw flows through the transistor 11a and voltage is set (programmed) in the capacitor 19 in such a way as to maintain the current Iw. At this time, the transistor 1d is open (off).

[0468] During a period when the current flows through the EL element 15, the transistors 11c and 11b turn off and the transistor 11d turns on as shown in FIG. 3(b). Specifically, a turn-off voltage (Vgh) is applied to the gate signal line 17a, turning off the transistors 11b and 11c. On the other hand, a turn-on voltage (Vgl) is applied to the gate signal line 17b, turning on the transistor 11d.

[0469] Suppose a current I1 is N times the current which should normally flow (a predetermined value), the current flowing through the EL element 15 in FIG. 3(b) is also Iw. Thus, the EL element 15 emits light 10 times more brightly that a predetermined value. In other words, as shown in FIG. 12, the larger the magnification N, the higher the display brightness B of the pixel 16. Thus, the magnification N and the brightness of the pixel 16 are proportional to each other.

[0470] If the transistor 11d is kept on for a period 1/N the period during which it is normally kept on (approximately 1F) and is kept off during the remaining period (N−1)/N, the average brightness over the 1F equals predetermined brightness. This display condition closely resembles the display condition under which a CRT is scanning a screen with an electronic gun. The difference is that 1/N of the entire screen illuminates (where the entire screen is taken as 1) (in a CRT, what illuminates is one pixel row—more precisely, one pixel).

[0471] According to the present invention, 1F/N of the image display area 53 moves from top to bottom of the screen 50 as shown in FIG. 13(b). According to the present invention, current flows through the EL element 15 only for the period of 1F/N, but current does not flow during the remaining period (1F(N−1) IN). Thus, the pixel is displayed intermittently. However, due to an afterimage, the entire screen appears to be displayed uniformly to the human eye.

[0472] Incidentally, as shown in FIG. 13, the write pixel row 51a is non-illuminated 52a. However, this is true only to the pixel configurations in FIGS. 1, 2, etc. In the pixel configuration of a current mirror shown in FIG. 38, etc., the write pixel row 51a may be illuminated. However, description will be given herein citing mainly the pixel configuration in FIG. 1 for ease of explanation. A drive method which involves driving a pixel intermittently by programming it with a current larger than the predetermined drive current Iw shown in FIGS. 13, 16, etc. is referred to as N-fold pulse driving.

[0473] In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed at intervals (intermittently) in the temporal sense. Liquid crystal display panels (EL display panels other than that of the present invention), which hold data in pixels for a period of 1F, cannot keep up with changes in image data during movie display, resulting is blurred moving pictures (edge blur of images). Since the present invention displays images intermittently, it can achieve a good display condition without edge blur of images. In short, movie display close to that of a CRT can be achieved.

[0474] Incidentally, to drive the pixel 16 as shown in FIG. 13, it is necessary to be able to separately control the current programming period of the pixel 16 (in the configuration shown in FIG. 1, the period during which the turn-on voltage Vgl is applied to the gate signal line 17a) and the period when the EL element 15 is under on/off control (in the pixel configuration shown in FIG. 1, the period during which the turn-on voltage Vgl or turn-off voltage Vgh is applied to the gate signal line 17b). Thus, the gate signal line 17a and gate signal line 17b must be separated.

[0475] For example, when only a single gate signal line 17 is laid from the gate driver circuit 12 to the pixel 16, the drive method according to the present invention can not be implemented using a configuration in which logic (Vgh or Vgl) applied to the gate signal line 17 is applied to the transistor 11b and the logic applied to the gate signal line 17 is converted (Vgh or Vgl) by an inverter and applied to the transistor 11d. Thus, the present invention requires a gate driver circuit 12a which operates the gate signal line 17a and gate driver circuit 12b which operates the gate signal line 17b.

[0476] Besides, the drive method according to the present invention provides a non-illuminated display even with the pixel configuration shown in FIG. 1 during periods other than the current programming period (1 H).

[0477] A timing chart of the drive method shown in FIG. 13 is illustrated in FIG. 14. The pixel configuration referred to in the present invention and the like is the one shown in FIG. 1 unless otherwise stated. As can be seen from FIG. 14, in each selected pixel row (the selection period is designated as 1 H), when a turn-on voltage (Vgl) is applied to the gate signal line 17a (see FIG. 14(a)), a turn-off voltage (Vgh) is applied to the gate signal line 17b (see FIG. 14(b)). During this period, current does not flow through the EL element 15 (non-illumination mode). In a non-selected pixel row, a turn-on voltage (Vgl) is applied to the gate signal line 17b and a turn-off voltage (Vgh) is applied to the gate signal line 17a. During this period, current flows through the EL element 15 (illumination mode). In the illumination mode, the EL element 15 illuminates at a brightness (NB) N times the predetermined brightness and the illumination period is 1F/N. Thus, the average display brightness of the display panel over 1F is given by (N·B)×(1/N)=B (the predetermined brightness).

[0478] FIG. 15 shows an example in which operations shown in FIG. 14 are applied to each pixel row. The figure shows voltage waveforms applied to the gate signal lines 17. Waveforms of the turn-off voltage are denoted by Vgh (high level) while waveforms of the turn-on voltage are denoted by Vgl (low level). The subscripts such as (1) and (2) indicate selected pixel row numbers.

[0479] In FIG. 15, a gate signal line 17a(1) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row to the source driver circuit 14. The programming current is N times larger than a predetermined value (for ease of explanation, it is assumed that N=10. Of course, since the predetermined value is a data current for use to display images, it is not a fixed value unless in the case of white raster display). Therefore, the capacitor 19 is programmed so that a 10 times larger current will flow through the transistor 11a. When the pixel row (1) is selected, in the pixel configuration shown in FIG. 1, a turn-off voltage (Vgh) is applied to the gate signal line 17b(1) and current does not flow through the EL element 15.

[0480] After 1 H, a gate signal line 17a(2) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row to the source driver circuit 14. The programming current is N times larger than a predetermined value (for ease of explanation, it is assumed that N=10). Therefore, the capacitor 19 is programmed so that 10 times larger current will flow through the transistor 11a. When the pixel row (2) is selected, in the pixel configuration shown in FIG. 1, a turn-off voltage (Vgh) is applied to the gate signal line 17b(2) and current does not flow through the EL element 15. However, since a turn-off voltage (Vgh) is applied to the gate signal line 17a(1) and a turn-on voltage (Vgl) is applied to the gate signal line 17b(1) of the pixel row (1), the EL element 15 illuminates.

[0481] After the next 1 H, a gate signal line 17a(3) is selected, a turn-off voltage (Vgh) is applied to the gate signal line 17b(3), and current does not flow through the EL element 15 in the pixel row (3). However, since a turn-off voltage (Vgh) is applied to the gate signal lines 17a(1) and (2) and a turn-on voltage (Vgl) is applied to the gate signal lines 17b(1) and

• • [0482] (2) in the pixel rows (1) and (2), the EL element 15 illuminates.

[0483] Through the above operation, images are displayed in sync with a synchronization signal of 1 H. However, with the drive method in FIG. 15, a 10 times larger current flows through the EL element 15. Thus, the display screen 50 is 10 times brighter. Of course, it goes without saying that for display at a predetermined brightness in this state, the programming current can be reduced to 1/10. However, a 10 times smaller current will cause a shortage of write current due to parasitic capacitance. Thus, the basic idea of the present invention is to use a large current for programming, insert a non-display area 52, and thereby obtain a predetermined brightness.

[0484] Incidentally, the drive method according to the present invention causes a current larger than a predetermined current to flow through the EL element 15, and thereby charges and discharges the parasitic capacitance of the source signal line 18 sufficiently. That is, there is no need to pass an N times larger current through the EL element 15. For example, it is conceivable to form a current path in parallel with the EL element 15 (form a dummy EL element and use a shield film to prevent the dummy EL element from emitting light) and divide the flow of current between the EL element 15 and the dummy EL element. For example, when a signal current is 0.2 μA, a programming current is set to 2.2 μA and the current of 2.2 μA is passed through the transistor 11a. Then, the signal current of 0.2 μA may be passed through the EL element 15 and 21A may be passed through the dummy EL element, for example. That is, the dummy pixel row 271 in FIG. 27 remains selected constantly. Incidentally, the dummy pixel row is either kept from emitting light or hidden from view by a shield film or the like even if it emits light.

[0485] With the above configuration, by increasing the current passed through the source signal line 18N times, it is possible to pass an N times larger current through the driver transistor 11a and pass a current sufficiently smaller than the N times larger current through the EL element 15. As shown in FIG. 5, this method allows the entire display screen 50 to be used as the image display area 53 without a non-display area 52.

[0486] FIG. 13(a) shows writing into the display screen 50. In FIG. 13(a), reference numeral 51a denotes a write pixel row. A programming current is supplied to the source signal line 18 from the source driver IC 14. In FIG. 13 and the like, there is one pixel row into which current is written during a period of 1 H, but this is not restrictive. The period may be 0.5 H or 2 Hs. Also, although it has been stated that a programming current is written into the source signal line 18, the present invention is not limited to current programming. The present invention may also use voltage programming (FIG. 46, etc.) which writes voltage into the source signal line 18.

[0487] In FIG. 13(a), when the gate signal line 17a is selected, the current to be passed through the source signal line 18 is programmed into the transistor 11a. At this time, a turn-off voltage is applied to the gate signal line 17b, and current does not flow through the EL element 15. This is because when the transistor 11d is on on the EL element 15, a capacitance component of the EL element 15 is visible from the source signal line 18 and the capacitance prevents sufficient current from being programmed into the capacitor 19. Thus, to take the configuration shown in FIG. 1 as an example, the pixel row into which current is written is a non-illuminated area 52 as shown in FIG. 13(b).

[0488] Suppose an N times larger current is used for programming (it is assumed that N=10 as described above), the screen becomes 10 times brighter. Thus, 90% of the display screen 50 can be constituted of the non-illuminated area 52. Thus, for example, if the number of horizontal scanning lines in the screen display area is 220 (S=220) in compliance with QCIF, 22 horizontal scanning lines can compose a display area 53 while 220−22=198 horizontal scanning lines can compose a non-display area 52. Generally speaking, if the number of horizontal scanning lines (number of pixel rows) is denoted by S, S/N of the entire area constitutes a display area 53, which is illuminated N times more brightly. Then, the display area 53 is scanned in the vertical direction of the screen. Thus, S (N−1)/N of the entire area is a non-illuminated area 52. The non-illuminated area presents a black display (is non-luminous). Also, the non-luminous area 52 is produced by turning off the transistor 11d. Incidentally, although it has been stated that the display area 53 is illuminated N times more brightly, naturally the value of N is adjusted by brightness adjustment and gamma adjustment.

[0489] In the above example, if a 10 times larger current is used for programming, the screen becomes 10 times brighter and 90% of the display screen 50 can be constituted of the non-illuminated area 52. However, this does not necessarily mean that R, G, and B pixels constitute the non-illuminated area 52 in the same proportion. For example, 1/8 of the R pixels, 1/6 of the G pixels, and 1/10 of the B pixels may constitute the non-illuminated area 52 with different colors making up different proportions. It is also possible to allow the non-illuminated area 52 (or illuminated area 53) to be adjusted separately among R, G, and B. For that, it is necessary to provide separate gate signal lines 17b for R, G, and B. However, allowing R, G, and B to be adjusted separately makes it possible to adjust white balance, making it easy to adjust color balance for each gradation (see FIG. 41).

[0490] As shown in FIG. 13(b), pixel rows including the write pixel row 51a compose a non-illuminated area 52 while an area of S/N (1F/N in the temporal sense) above the write pixel row 51a compose a display area 53 (when write scans are performed from top to bottom of the screen. When the screen is scanned from bottom to top, the areas change places). Regarding the display condition of the screen, a strip of the display area 53 moves from top to bottom of the screen.

[0491] In FIG. 13, one display area 53 moves from top to bottom of the screen. At a low frame rate, the movement of the display area 53 is recognized visually. It tends to be recognized easily especially when a user closes his/her eyes or moves his/her head up and down.

[0492] To deal with this problem, the display area 53 can be divided into a plurality of parts as shown in FIG. 16. If the total area of the divided display area is S (N−1)/N, the brightness is equal to the brightness in FIG. 13. Incidentally, there is no need to divide the display area 53 equally. Also, there is no need to divide the non-display area 52 equally.

[0493] Dividing the display area 53 reduces flickering of the screen. Thus, a flicker-free good image display can be achieved. Incidentally, the display area 53 may be divided more finely. However, the more finely the display area 53 is divided, the poorer the movie display performance becomes.

[0494] FIG. 17 shows voltage waveforms of gate signal lines 17 and emission brightness of the EL element. As can be seen from FIG. 17, a period (1F/N) during which the gate signal line 17b is set to Vgl is divided into a plurality of parts (K parts). That is, a period of 1F/(K·N) during which the gate signal line 17b is set to Vgl repeats K times. This reduces flickering and implements image display at a low frame rate. Preferably, the number of divisions is variable. For example, when the user presses a brightness adjustment switch or turns a brightness adjustment knob, the value of K may be changed in response. Also, the user may be allowed to adjust brightness. Alternatively, the value of K may be changed manually or automatically depending on images or data to be displayed.

[0495] Incidentally, although it has been stated with reference to FIG. 17 and the like that a period (1F/N) during which the gate signal line 17b is set to Vgl is divided into a plurality of parts (K parts) and that a period of 1F/(KN) during which the gate signal line 17b is set to Vgl repeats K times, this is not restrictive. A period of 1F/(KN) may be repeated L (L≠K) times. In other words, the present invention displays the display screen 50 by controlling the period (time) during which current is passed through the EL element 15. Thus, the idea of repeating the 1F/(K·N) period L (L≠K) times is included in the technical idea of the present invention. Also, by varying the value of L, the brightness of the display screen 50 can be changed digitally. For example, there is a 50% change of brightness (contrast) between L=2 and L=3. Also, when dividing the image display area 53, the period when the gate signal line 17b is set to Vg1 does not necessarily need to be divided equally.

[0496] In the example described above, the display screen 50 is turned on and off (illuminated and non-illuminated) as the current delivered to the EL element 15 is switched on and off. That is, approximately equal current is passed through the transistor 11a multiple times using electric charges held in the capacitor 19. The present invention is not limited to this. For example, the display screen 50 may be turned on and off (illuminated and non-illuminated) by charging and discharging the capacitor 19.

[0497] FIG. 18 shows voltage waveforms applied to gate signal lines 17 to achieve the image display condition shown in FIG. 16. FIG. 18 differs from FIG. 15 in the operation of the gate signal line 17b. The gate signal line 17b is turned on and off (Vgl and Vgh) as many times as there are screen divisions. FIG. 18 is the same as FIG. 15 in other respects, and thus description thereof will be omitted.

[0498] Since black display on EL display apparatus corresponds to complete non-illumination, contrast does not lower unlike in the case of intermittent display on liquid crystal display panels. Also, with the configurations in FIGS. 1, 2, 32, 43, and 117, intermittent display can be achieved by simply turning on and off the transistor 11d. With the configurations in FIGS. 38, 51, and 115, intermittent display can be achieved by simply turning on and off the transistor element 11e. In FIG. 113, intermittent display can be achieved by controlling the switching circuit 1131. In FIG. 114, intermittent display can be achieved by turning on and off the transistor 11g. This is because image data is stored in the capacitor 19 (the number of gradations is infinite because analog values are used). That is, the image data is held in each pixel 16 for a period of 1F. Whether to deliver a current which corresponds to the stored image data to the EL element 15 is controlled by controlling the transistors 11d and 11e.

[0499] Thus, the drive method described above is not limited to a current-driven type and can be applied to a voltage-driven type as well. That is, in a configuration in which the current passed through the EL element 15 is stored in each pixel, intermittent driving is implemented by switching on and off the current path between the driver transistor 11 and EL element 15.

[0500] It is important to maintain terminal voltage of the capacitor 19 in order to reduce flickering and power consumption. This is because if the terminal voltage of the capacitor 19 changes (charge/discharge) during one field (frame) period, flickering occurs when the screen brightness changes and the frame rate lowers. The current passed through the EL element 15 by the transistor 11a must be higher than 65%. More specifically, if the initial current written into the pixel 16 and passed through the EL element 15 is taken as 100%, the current passed through the EL element 15 just before it is written into the pixel 16 in the next frame (field) must not fall below 65%.

[0501] With the pixel configuration shown in FIG. 1, there is no difference in the number of transistors 11 in a single pixel between when an intermittent display is created and when an intermittent display is not created. That is, leaving the pixel configuration as it is, proper current programming is achieved by removing the effect of parasitic capacitance of the source signal line 18. Besides, movie display close to that of a CRT is achieved.

[0502] Also, since the operation clock of the gate driver circuit 12 is significantly slower than the operation clock of the source driver circuit 14, there is no need to upgrade the main clock of the circuit. Besides, the value of N can be changed easily.

[0503] Incidentally, the image display direction (image writing direction) may be from top to bottom of the screen in the first field (frame), and from bottom to top of the screen in the second field (frame). That is, an upward direction and downward direction may be repeated alternately.

[0504] Alternatively, it is possible to use a downward direction in the first field (frame), turn the entire screen into black display (non-display) once, and use an upward direction in the second field (frame). It is also possible to turn the entire screen into black display (non-display) once.

[0505] Incidentally, although top-to-bottom and bottom-to-top writing directions on the screen are used in the drive method described above, this is not restrictive. It is also possible to fix the writing direction on the screen to a top-to-bottom direction or bottom-to-top direction and move the non-display area 52 from top to bottom in the first field, and from bottom to top in the second field. Alternatively, it is possible to divide a frame into three fields and assign the first field to R, the second field to G, and the third field to B so that three fields compose a single frame. It is also possible to display R, G, and B in turns by switching among them every horizontal scanning period (1 H) (see FIGS. 125 to 132 and their description). The items mentioned above also apply to other examples of the present invention.

[0506] The non-display area 52 need not be totally non-illuminated. Weak light emission or dim image display will not be a problem in practical use. It should be regarded to be an area which has a lower display brightness than the image display area 53. Also, the non-display area 52 may be an area which does not display one or two colors out of R, G, and B. Also, it may be an area which displays one or two colors among R, G, and B at low brightness.

[0507] Basically, if the brightness of the display area 53 is kept at a predetermined value, the larger the display area 53, the brighter the display screen 50. For example, when the brightness of the image display area 53 is 100 (nt), if the percentage of the display screen 50 accounted for by the display area 53 changes from 10% to 20%, the brightness of the screen is doubled. Thus, by varying the proportion of the display area 53 in the entire screen 50, it is possible to vary the display brightness of the screen. The display brightness of the screen 50 is proportional to the ratio of the display area 53 to the screen 50.

[0508] The size of the display area 53 can be specified freely by controlling data pulses (ST2) sent to the shift register circuit 61. Also, by varying the input timing and period of the data pulses, it is possible to switch between the display condition shown in FIG. 16 and display condition shown in FIG. 13. Increasing the number of data pulses in one IF period makes the screen 50 brighter and decreasing it makes the screen 50 dimmer. Also, continuous application of the data pulses brings on the display condition shown in FIG. 13 while intermittent application of the data pulses brings on the display condition shown in FIG. 16.

[0509] FIG. 19(a) shows a brightness adjustment scheme used when the display area 53 is continuous as in FIG. 13. The display brightness of the screen 50 in FIG. 19(a1) is the brightest, the display brightness of the screen 50 in FIG. 19(a2) is the second brightest, and display brightness of the screen 50 in FIG. 19(a3) is the dimmest. FIG. 19(a) is most suitable for movie display.

[0510] Changes from FIG. 19(a1) to FIG. 19(a3) (or vice versa) can be achieved easily by controlling the shift register circuit 61 and the like of the gate driver circuit 12 as described above. In this case, there is no need to vary the Vdd voltage in FIG. 1. That is, the brightness of the screen 50 can be varied without changing the power supply voltage. Also, in the process of change from FIG. 19(a1) to FIG. 19(a3), the gamma characteristics of the screen do not change at all. Thus, the contrast and gradation characteristics of the display screen are maintained regardless of the brightness of the screen 50. This is an effective feature of the present invention.

[0511] In brightness adjustment of a conventional screen, low brightness of the screen 50 results in poor gradation performance. That is, even if 64 gradations can be displayed in a high-brightness display, in most cases, less than half the gradations can be displayed in a low-brightness display. In contrast, the drive method according to the present invention does not depend on the display brightness of the screen and can display up to 64 gradations, which is the highest.

[0512] FIG. 19(b) shows a brightness adjustment scheme used when the display areas 53 are scattered as in FIG. 16. The display brightness of the screen 50 in FIG. 19(b1) is the brightest, the display brightness of the screen 50 in FIG. 19(b2) is the second brightest, and display brightness of the screen 50 in FIG. 19(b3) is the dimmest. Changes from FIG. 19(b1) to FIG. 19(b3) (or vice versa) can be achieved easily by controlling the shift register circuit 61 of the gate driver circuit 12 and the like as described above. By scattering the display areas 53 as shown in FIG. 19(b), it is possible to eliminate flickering even at a low frame rate.

[0513] To eliminate flickering at an even lower frame rate, the display areas 53 can be scattered more finely as shown in FIG. 19(c). However, this lowers movie display performance. Thus, the drive method in FIG. 19(a) is suitable for moving pictures. The drive method in FIG. 19(c) is suitable when it is desired to reduce power consumption by displaying still pictures. Switching from FIG. 19(a) to FIG. 19(c) can be done easily by controlling the shift register circuit 61.

[0514] Mainly, N=two times, N=4 times, etc. are used in the above example. Needless to say, however, the present invention is not limited to integral multiples. It is not limited to a value equal to or larger than N=two, either. For example, less than half the screen 50 may be a non-display area 52 at a certain time point. A predetermined brightness can be achieved if a current Iw 5/4 a predetermined value is used for current programming and the EL element is illuminated for 4/5 of 1F.

[0515] The present invention is not limited to the above. For example, a current Iw 10/4 a predetermined value may be used for current programming to illuminate the EL element for 4/5 of 1F. In this case, the EL element illuminates at twice a predetermined brightness. Alternatively, a current Iw 5/4 a predetermined value may used for current programming to illuminate the EL element for 2/5 of 1F. In this case, the EL element illuminates at 1/2 the predetermined brightness. Also, a current Iw 5/4 a predetermined value may be used for current programming to illuminate the EL element for 1/1 of 1F. In this case, the EL element illuminates at 5/4 the predetermined brightness.

[0516] Thus, the present invention controls the brightness of the display screen by controlling the magnitude of programming current and illumination period IF. Also, by illuminating the EL element for a period shorter than the period of 1F, the present invention can insert a non-display area 52, and thereby improve movie display performance. By illuminating the EL element constantly for the period of 1F, the present invention can display a bright screen.

[0517] If pixel size is A square mm and predetermined brightness of white raster display is B (nt), preferably programming current I (IA) (programming current outputted from the source driver circuit 14) or the current written into the pixel satisfies:
(A×B)/20≦I≦(A×B)

[0518] This provides good light emission efficiency and solves a shortage of write current.

[0519] More preferably, the programming current I (μA) falls within the range:
(A×B)/10≦I≦(A×B)

[0520] FIG. 20 is an explanatory diagram illustrating another example of increasing the current flowing through a source signal line 18. This method selects a plurality of pixel rows simultaneously, charges and discharges parasitic capacitance and the like of the source signal line 18 using the total current flowing through the plurality of pixel rows, and thereby eases a shortage of write current greatly. Since a plurality of pixel rows are selected simultaneously, drive current per pixel can be reduced. Thus, it is possible to reduce the current flowing through the EL element 15. For ease of explanation, it is assumed that N=10 (the current passed through the source signal line 18 is increased tenfold).

[0521] According to the invention described with reference to FIG. 20, M pixel rows are selected simultaneously. A current N times larger than a predetermined current is applied to the source signal line 18 from the source driver IC 14. A current N/M times larger than the current passed through the EL element 15 is programmed into each pixel. As an example, to illuminate the EL element 15 at a predetermined emission brightness, current is passed through the EL element 15 for a duration of M/N the duration of one frame (one field) (M/N is used for ease of explanation and is not meant to be restrictive. As described earlier, it can be specified freely depending on the brightness of the screen 50). This makes it possible to charge and discharge parasitic capacitance of the source signal line 18 sufficiently, resulting in a sufficient resolution at the predetermined emission brightness.

[0522] Current is passed through the EL element 15 only for a period M/N the frame (field) period, but current is not passed during the remaining period (1F(N−1) M/N). In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed at intervals (intermittently) in the temporal sense. This achieves a good display condition without edge blur of images. Also, since the source signal line 18 is driven by an N times larger current, it is not affected by parasitic capacitance. Thus, this method can accommodate high-resolution display panels.

[0523] FIG. 21 is an explanatory diagram illustrating drive waveforms used to implement the drive method shown in FIG. 20. Waveforms of the turn-off voltage are denoted by Vgh (H level) while waveforms of the turn-on voltage are denoted by (L level). The subscripts (such as (1), (2), and (3)) indicate pixel row numbers. Incidentally, the number of rows is 220 in the case of a QCIF display panel, and 480 in the case of a VGA display panel.

[0524] In FIG. 21, a gate signal line 17a(1) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row to the source driver circuit 14. For ease of explanation, it is assumed here that the write pixel row 51a is the (1)-th pixel row.

[0525] The programming current flowing through the source signal line 18 is N times larger than a predetermined value (for ease of explanation, it is assumed that N=10. Of course, since the predetermined value is a data current for use to display images, it is not a fixed value unless in the case of white raster display). It is also assumed that five pixel rows are selected simultaneously (M=5). Therefore, ideally the capacitor 19 of one pixel is programmed so that a twice (N/M=10/5=2) larger current will flow through the transistor 11a.

[0526] When the write pixel row is the (1)-th pixel row, the gate signal lines 17a(1), (2), (3), (4), and (5) are selected as shown in FIG. 21. That is, the switching transistors 11b and the transistors 11c in the pixel rows (1), (2), (3), (4), and (5) are on. Also, the gate signal lines 17b are 180 degrees out of phase with the gate signal lines 17a. Thus, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52.

[0527] Ideally, the transistors 11a in the five pixels deliver a current of Iw×2 each to the source signal line 18 (i.e., a current of Iw×2×N=Iw×2×5=Iw×10 flows through the source signal line 18. Thus, if a predetermined voltage Iw flows when the N-fold pulse driving according to the present invention is not used, a current 10 times larger than Iw flows through the source signal line 18).

[0528] Through the above operation (drive method), the capacitor 19 of each pixel 16 is programmed with a twice larger current. For ease of understanding, it is assumed here that the transistors 11a have equal characteristics (Vt and S value) Since five pixel rows are selected simultaneously (M=5), five driver transistors 11a operate. That is, 10/5=2 times larger current flows through the transistor 11a per pixel. The total programming current of the five transistors 11a flows through the source signal line 18. For example, if a current conventionally written into the write pixel row 51a is Iw, a current of Iw×10 is passed through the source signal line 18. The write pixel rows 51b into which image data is written later than the write pixel row (1) are auxiliary pixel rows used to increase the amount of current delivered to the source signal line 18. However, there is no problem because regular image data is written into the write pixel rows 51b later.

[0529] Thus, the four pixel rows 51b provide the same display as the pixel row 51a during a period of 1 H. Consequently, at least the write pixel row 51a and the pixel rows 51b selected to increase current are in non-display mode 52. However, in the pixel configuration of a current mirror, such as shown in FIG. 38, or pixel configuration for voltage programming, the pixel rows may be in display mode.

[0530] After 1 H, the gate signal line 17a (1) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(6) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (6) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (1).

[0531] After the next 1 H, the gate signal line 17a(2) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(7) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (7) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (2). The entire screen is redrawn as it is scanned by shifting pixel rows one by one through the above operations.

[0532] With the drive method in FIG. 20, since each pixel is programmed with a twice larger current, ideally the emission brightness of the EL element 15 of each pixel is two times higher. Thus, the brightness of the display screen is twice higher than a predetermined value. To equalize this brightness with the predetermined brightness, an area which includes the write pixel rows 51 and which is half as large as the display screen 50 can be turned into a non-display area 52 as illustrated in FIG. 16.

[0533] As is the case with FIG. 13, when one display area 53 moves from top to bottom of the screen as shown in FIG. 20, the movement of the display area 53 is recognized visually if a low frame rate is used. It tends to be recognized easily especially when the user closes his/her eyes or moves his/her head up and down.

[0534] To deal with this problem, the display area 53 can be divided into a plurality of parts as illustrated in FIG. 22. If the total area of the divided non-display area 52 is S(N−1)/N, the brightness is equal to the brightness of the undivided display area.

[0535] FIG. 23 shows voltage waveforms applied to gate signal lines 17. FIG. 21 differs from FIG. 23 basically in the operation of the gate signal line 17b. The gate signal line 17b is turned on and off (Vgl and Vgh) as many times as there are screen divisions. FIG. 23 is the same as FIG. 21 in other respects, and thus description thereof will be omitted.

[0536] As described above, dividing the display area 53 reduces flickering of the screen. Thus, a flicker-free good image display can be achieved. Incidentally, the display area 53 may be divided more finely. The more finely the display area 53 is divided, the less flickering occurs. Since the EL element 15 is highly responsive, even if it is turned on and off at intervals shorter than 5 μsec, there is no lowering of the display brightness.

[0537] With the drive method according to the present invention, the EL element 15 can be turned on and off by turning on and off a signal applied to the gate signal line 17b. Thus, the drive method according to the present invention can perform control using a low frequency on the order of KHz. Also, it does not need an image memory or the like in order to insert a black screen (insert a non-display area 52). Thus, the drive circuit or method according to the present invention can be implemented at low costs.

[0538] FIG. 24 shows a case in which two pixel rows are selected simultaneously. It was found that on a display panel formed by low-temperature polysilicon technology, a method in which two pixel rows were selected simultaneously provided uniform display on a practical level. Probably this is because driver transistors 11a in adjacent pixels had very similar characteristics. In laser annealing, good results were obtained when laser stripes were irradiated in parallel with the source signal line 18.

[0539] This is because that part of a semiconductor film which is annealed simultaneously has uniform characteristics. That is, the semiconductor film is created uniformly within an irradiation range of laser stripes and the Vt and mobility of the transistors which use the semiconductor film are almost uniform. Thus, if a striped laser shot is moved in parallel with the source signal line 18, pixels (a pixel column, i.e., pixels arranged vertically on the screen) along the source signal line 18 take on almost equal characteristics. Therefore, if a plurality of pixel rows are turned on simultaneously for current programming, the current obtained by dividing the programming current by the number of selected pixels are programmed almost uniformly into the pixels This makes it possible to program a current close to a target value and achieve uniform display. Thus, the direction of a laser shot and the drive method described with reference to FIG. 24 and the like have a synergistic effect.

[0540] As described above, if the direction of a laser shot is made to coincide approximately with the direction of the source signal line 18 (see FIG. 7), the characteristics of the pixel transistors 11a arranged vertically become almost uniform, making it possible to do proper current programming (even if the characteristics of the pixel transistors 11a arranged horizontally are not uniform). The above operation is performed in sync with 1 H (one horizontal scanning period) by shifting selected pixel rows one by one or by shifting two or more selected pixel rows at once.

[0541] Incidentally, as described with reference to FIG. 8, the direction of the laser shot does not always need to be parallel with the direction of the source signal line 18. This is because even if the laser shot is directed at angles to the source signal line 18, pixel transistors 11a placed along one source signal line 18 can be made to take on almost equal characteristics. Thus, directing a laser shot in parallel with the source signal line 18 means bringing a pixel vertically adjacent to an arbitrary pixel along the source signal line 18 into a laser irradiation range. Besides, a source signal line 18 generally constitutes wiring which transmits programming current or voltage used as a video signal.

[0542] Incidentally, in the examples of the present invention a write pixel row is shifted every 1 H, but this is not restrictive. Pixel rows may be shifted every 2 Hs (two pixel rows at a time). Also, more than two pixel rows may be shifted at a time. Also, pixel rows may be shifted at desired time intervals or every second pixel may be shifted.

[0543] The shifting interval may be varied according to locations on the screen. For example, the shifting interval may be decreased in the middle of the screen, and increased at the top and bottom of the screen. For example, a pixel row may be shifted at intervals of 200 μsec. in the middle of the screen 50, and at intervals of 100 μsec. at the top and bottom of the screen 50. This increases emission brightness in the middle of the screen 50 and decreases it around the perimeters (at the top and bottom of the screen 50)). Needless to say, the shifting interval is varied smoothly among the top, middle, and bottom of the screen 50 to avoid brightness contours.

[0544] Incidentally, the reference voltage of the source driver circuit 14 may be varied with the scanning location on the screen 50 (see FIG. 146, etc.). For example, a reference current of 10 μA is used in the middle of the screen 50 and a reference current of 5 μA is used at the top of the screen 50. Varying a reference current in this way corresponding to a location in the screen 50, increases emission brightness in the middle of the screen 50 and decreases it around the perimeters (at the top and bottom of the screen 50)). Needless to say, the reference current is varied smoothly among the top, middle, and bottom of the screen 50 to avoid brightness contours.

[0545] Also, it goes without saying that images may be displayed by combining a drive method which varies the pixel-row shifting interval with the location on the screen and a drive method which varies the reference voltage with the location on the screen 50.

[0546] The shifting interval may be varied on a frame-by-frame basis. Also, it is not strictly necessary to select consecutive pixel rows. For example, every second pixel row may be selected.

[0547] Specifically, a possible drive method involves selecting the first and third pixel rows in the first horizontal scanning period, the second and fourth pixel rows in the second horizontal scanning period, the third and fifth pixel rows in the third horizontal scanning period, and the fourth and sixth pixel rows in the fourth horizontal scanning period. Of course, a drive method which involves selecting the first, third, and fifth pixel rows in the first horizontal scanning period also belongs to the technical category of the present invention. Also, one in every few pixel rows may be selected.

[0548] Incidentally, the combination of the direction of a laser shot and selection of multiple pixel rows is not limited to the pixel configurations in FIGS. 1, 2, and 32, but it is also applicable to other current-driven pixel configurations such as the current-mirror pixel configurations in FIGS. 38, 42, 50, etc. Also, it can be applied to voltage-driven pixel configurations in FIGS. 43, 51, 54, 46, etc. This is because as long as transistors in upper and lower parts of the pixel have equal characteristics, current programming can be performed properly using the voltage value applied to the same source signal line 18.

[0549] In FIG. 24, when the write pixel row is the (1)-th pixel row, the gate signal lines 17a(1) and (2) are selected (see FIG. 25). That is, the switching transistors 11b and the transistors 11c in the pixel rows (1) and (2) are on. Thus, at least the switching transistors 11d in the pixel rows (1) and (2) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52. Incidentally, in FIG. 24, the display area 53 is divided into five parts to reduce flickering.

[0550] Ideally, the transistors 1a in the two pixel rows deliver a current of Iw×5 each to the source signal line 18 (when N=10. Since K=2, a current of Iw×K×5=Iw×10 flows through the source signal line 18). Then, the capacitor 19 of each pixel 16 is programmed with a 5 times larger current.

[0551] Since two pixel rows are selected simultaneously (K=2), two driver transistors 11a operate. That is, 10/2=5 times larger current flows through the transistor 11a per pixel. The total programming current of the two transistors 1a flows through the source signal line 18.

[0552] For example, if the current written into the write pixel row 51a is Id, a current of Iw×10 is passed through the source signal line 18. There is no problem because regular image data is written into the write pixel row 51b later. The pixel row 51b provides the same display as the pixel row 51a during a period of 1 H. Consequently, at least the write pixel row 51a and the pixel row 51b selected to increase current are in non-display mode 52.

[0553] After the next 1 H, the gate signal line 17a(1) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(3) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (3) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (1).

[0554] After the next 1 H, the gate signal line 17a(2) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(4) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (4) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (2). The entire screen is redrawn as it is scanned by shifting pixel rows one by one through the above operations (of course, two or more pixel rows may be shifted simultaneously. For example, in the case of pseudo-interlaced driving, two pixel rows will be shifted at a time. Also, from the viewpoint of image display, the same image may be written into two or more pixel rows).

[0555] As in the case of FIG. 16, with the drive method in FIG. 24, since each pixel is programmed with a five times larger current (voltage), ideally the emission brightness of the EL element 15 is five times higher. Thus, the brightness of the display area 53 is five times higher than a predetermined value. To equalize this brightness with the predetermined brightness, an area which includes the write pixel rows 51 and which is 1/5 the display screen 50 can be turned into a non-display area 52.

[0556] As shown in FIG. 27, two write pixel rows 51 (51a and 51b) are selected in sequence from the upper side to the lower side of the screen 50 (see also FIG. 26. Pixels 16a and 16b are selected in FIG. 26). However, at the bottom of the screen, there does not exist 51b although the write pixel row 51a exists. That is, there is only one pixel row to be selected. Thus, the current applied to the source signal line 18 is all written into the write pixel row 51a. Consequently, twice as large a current as usual is written into the write pixel row 51a.

[0557] To deal with this problem, the present invention forms (places) a dummy pixel row 271 at the bottom of the screen 50, as shown in FIG. 27(b). Thus, after the pixel row at the bottom of the screen 50 is selected, the final pixel row of the screen 50 and the dummy pixel row 271 are selected. Consequently, a prescribed current is written into the write pixel row in FIG. 27(b).

[0558] Incidentally, although the dummy pixel row 271 is illustrated as being adjacent to the top end or bottom end of the display screen 50, this is not restrictive. It may be formed at a location away from the display screen 50. Besides, the dummy pixel row 271 does not need to contain a switching transistor 11d or EL element 15 such as those shown in FIG. 1. This reduces the size of the dummy pixel row 271.

[0559] FIG. 28 shows a mechanism of how the state shown in FIG. 27(b) takes place. As can be seen from FIG. 28, after the pixel 16c at the bottom of the screen 50 is selected, the final pixel row (dummy pixel row) 271 of the screen 50 is selected. The dummy pixel row 271 is placed outside the screen 50. That is, the dummy pixel row (dummy pixel) 271 does not illuminate, is not illuminated, or is hidden even if illuminated. For example, contact holes between the pixel electrode 105 and transistor 11 are eliminated, no EL film is formed on the dummy pixel row 271, or the like. Also, an insulating film may be formed on the pixel electrode 105 of the dummy pixel row 271.

[0560] Although it has been stated with reference to FIG. 27 that the dummy pixel (row) 271 is provided (formed or placed) at the bottom of the screen 50, this is not restrictive. For example when the screen is scanned from bottom to top (inverse scanning) as shown in FIG. 29(a), a dummy pixel row 271 should also be formed at the top of the screen 50 as shown in FIG. 29(b). That is, dummy pixel rows 271 are formed (placed) both at the top and bottom of the screen 50. This configuration accommodates in verses canning of the screen as well. Two pixel rows are selected simultaneously in the example described above.

[0561] The present invention is not limited to this. For example, five pixel rows may be selected simultaneously (see FIG. 23). When five pixel rows are selected simultaneously, four dummy pixel rows 271 should be formed. That is, the number of dummy pixel rows 271 equals the number of pixel rows selected simultaneously minus one. However, this is true only when the selected pixel rows are shifted one by one. When two or more pixel rows are shifted at a time, (M−1)×L dummy pixel rows should be formed, where M is the number of pixels selected and L is the number of pixel rows shifted at a time.

[0562] The dummy pixel row configuration or dummy pixel row driving according to the present invention uses one or more dummy pixel rows. Of course, it is preferable to use the dummy pixel row driving and N-fold pulse driving in combination.

[0563] In the drive method which selects two or more pixel rows at a time, the larger the number of pixel rows selected simultaneously, the more difficult it becomes to absorb variations in the characteristics of the transistors 11a. However, the current programmed into one pixel increases with decreases in the number M of pixel rows selected simultaneously, resulting in a large current flowing through the EL element 15, which in turn makes the EL element 15 prone to degradation.

[0564] FIG. 30 shows how to solve this problem. The basic concept behind FIG. 30 is to use a method of selecting a plurality of pixel rows simultaneously during 1/2 H (1/2 of a horizontal scanning period) as described with reference to FIGS. 22 and 29 and to use a method of selecting one pixel row in the latter 1/2 H (1/2 of the horizontal scanning period) as described with reference to FIGS. 5 and 13. This combination makes it possible to absorb variations in the characteristics of the transistors 11a and achieve high speed and uniform surfaces. Incidentally, although the period of 1/2 H is used for ease of understanding, this is not restrictive. The first period may be 1/4 H and the second period may be 3/4 H.

[0565] Referring to FIG. 30, for ease of understanding, it is assumed that five pixel rows are selected simultaneously in the first period and that one pixel row is selected in the second period. First, as shown in FIG. 30(a1), in the first period (first 1/2 H), five pixel rows are selected simultaneously. This operation has been described with reference to FIG. 22, and thus description thereof will be omitted. As an example, it is assumed that the current passed through the source signal line 18 is 25 times as large as a predetermined value. Thus, the transistor 11a in the pixel 16 (in the pixel configuration in FIG. 1) is programmed with a five times larger current (25/5 pixel rows=5). Since the current is 25 times larger, the parasitic capacitance generated in the source signal line 18 and the like is charged and discharged in an extremely short period. Consequently, the potential of the source signal line 18 reaches a target potential in a short period of time and the terminal voltage of the capacitor 19 of each pixel 16 is programmed to pass a 25 times larger current. The 25 times larger current is applied in the first 1/2 H (1/2 of the horizontal scanning period).

[0566] Naturally, since the same image data is written into the five write pixel rows, the transistors 11d in the five write pixel rows are turned off in order not to display the image. Thus, the display condition is as shown in FIG. 30(a2).

[0567] In the next 1/2 H period, one pixel is selected for current (voltage) programming. The condition is as shown in FIG. 30(b1). Current (voltage) programming is performed so as to pass a five times larger current through the write pixel row 51a as in the first period. Equal current is passed in FIG. 30(a1) and FIG. 30(b1) to reach a target current more quickly by decreasing the changes in the terminal voltage of the programmed capacitor 19.

[0568] Specifically, in FIG. 30(a1), current is passed through a plurality of pixels, approaching an approximate target value quickly. In this first stage, since a plurality of transistors 11a are programmed, variations in the transistors cause error with respect to the target value. In the second stage, only a pixel row where data will be written and held is selected and complete programming is performed by changing the value of current from the approximate target value to a predetermined target value.

[0569] Incidentally, scanning of the non-illuminated area 52 from top to bottom of the screen and scanning of the write pixel rows 51a from top to bottom of the screen are performed in the same manner as in examples in FIG. 13 and the like, and thus description thereof will be omitted.

[0570] FIG. 31 shows drive waveforms used to implement the drive method shown in FIG. 30. As can be seen from FIG. 31, 1 H (one horizontal scanning period) consists of two phases. An ISEL signal is used to switch between the two phases. The ISEL signal is illustrated in FIG. 31.

[0571] First, the ISEL signal will be described. The driver circuit 14 which performs operations shown in FIG. 30 comprises a current output circuit A and current output circuit B. Each of the current output circuits consists of a D/A circuit which converts 8-bit gradation data from digital to analog, an operation amplifier, etc. In the example in FIG. 30, the current output circuit A is configured to output 25 times larger current. On the other hand, the current output circuit B is configured to output 5 times larger current. Outputs from the current output circuit A and current output circuit B are controlled by a switch circuit formed (placed) in a current output section through the ISEL signals and are applied to the source signal line 18. Such current output circuits are placed on each source signal line 18.

[0572] When the ISEL signal is low, the current output circuit A which outputs 25 times larger current is selected and current from the source signal line 18 is absorbed by the source driver IC 14 (more precisely, the current is absorbed by the current output circuit A formed in the source driver IC 14). The magnification (such as ×25 or ×5) of the current from the current output circuits can be adjusted easily using a plurality of resisters and an analog switch.

[0573] As shown in FIG. 30, when the write pixel row is the (1)-th pixel row (see the 1 H column in FIG. 30), the gate signal lines 17a(1), (2), (3), (4), and (5) are selected (in the case of configuration shown in FIG. 1). That is, the switching transistors 11b and the transistors 11c in the pixel rows (1), (2), (3), (4), and (5) are on. Besides, since ISEL is low, the current output circuit A which outputs 25 times larger current is selected and connected to the source signal line 18. Also, a turn-off voltage (Vgh) is applied to the gate signal line 17b. Thus, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52.

[0574] Ideally, the transistors 11a in the five pixels deliver a current of Iw×2 each to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with a five times larger current. For ease of understanding, it is assumed here that the transistors have equal characteristics (Vt and S value).

[0575] Since five pixel rows are selected simultaneously (K=5), five driver transistors 11a operate. That is, 25/5=5 times larger current flows through the transistor 11a per pixel. The total programming current of the five transistors 11a flows through the source signal line 18. For example, if the current written into the write pixel row 51a by a conventional drive method is Iw, a current of Iw×25 is passed through the source signal line 18. The write pixel rows 51b into which image data is written later than the write pixel row (1) are auxiliary pixel rows used to increase the amount of current delivered to the source signal line 18. However, there is no problem because regular image data is written into the write pixel rows 51b later.

[0576] Thus, the pixel rows 51b provide the same display as the pixel row 51a during a period of 1 H. Consequently, at least the write pixel row 51a and the pixel rows 51b selected to increase current are in non-display mode 52.

[0577] In the next 1/2 H period (1/2 of the horizontal scanning period), only the write pixel row 51a is selected. That is, only the (1)-th pixel row is selected. As can be seen from FIG. 31, a turn-on voltage (Vgl) is applied only to the gate signal line 17a(1) and a turn-off voltage (Vgh) is applied to the gate signal lines 17a(2), (3), (4), and (5). Thus, the transistor 11a in the pixel row (1) is in operation (supplying current to the source signal line 18), but the switching transistors 11b and the transistors 11c in the pixel rows (2), (3), (4), and (5) are off. That is, they are non-selected.

[0578] Besides, since ISEL is high, the current output circuit B which outputs 5 times larger current is selected and connected to the source signal line 18. Also, a turn-off voltage (Vgh) is applied to the gate signal line 17b, which is in the same state as during the first 1/2 H. Thus, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52.

[0579] Thus, each transistor 11a in the pixel row (1) deliver a current of Iw×5 to the source signal line 18. Then, the capacitor 19 in each pixel row (1) is programmed with a 5 times larger current.

[0580] In the next horizontal scanning period, the write pixel row shifts by one. That is, the pixel row (2) becomes the current write pixel row. During the first 1/2 H period, when the write pixel row is the (2)-th pixel row, the gate signal lines 17a(2), (3), (4), and (5) and (6) are selected. That is, the switching transistors 11b and the transistors 11c in the pixel rows (2), (3), (4), (5), and (6) are on. Besides, since ISEL is low, the current output circuit A which outputs 25 times larger current is selected and connected to the source signal line 18. Also, a turn-off voltage (Vgh) is applied to the gate signal line 17b.

[0581] Thus, the switching transistors 11d in the pixel rows (2), (3), (4), (5), and (6) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52. On the other hand, since Vgl voltage is applied to the gate signal line 17b(1) of the pixel row (1), the transistor 11d is on and the EL element 15 in the pixel row (1) illuminates.

[0582] Since five pixel rows are selected simultaneously (K=5), five driver transistors 11a operate. That is, 25/5=5 times larger current flows through the transistor 11a per pixel. The total programming current of the five transistors 11a flows through the source signal line 18.

[0583] In the next 1/2 H period (1/2 of the horizontal scanning period), only the write pixel row 51a is selected. That is, only the (2)-th pixel row is selected. As can be seen from FIG. 31, a turn-on voltage (Vgl) is applied only to the gate signal line 17a(2) and a turn-off voltage (Vgh) is applied to the gate signal lines 17a (3), (4), (5), and (6).

[0584] Thus, the transistors 11a in the pixel rows (1) and (2) are in operation (the pixel row (1) supplies current to the EL element 15 and the pixel row (2) supplies current to the source signal line 18), but the switching transistors 11b and the transistors 11c in the pixel rows (3), (4), (5), and (6) are off. That is, they are non-selected.

[0585] Besides, since ISEL is high, the current output circuit B which outputs 5 times larger current is selected and the current output circuit 1222b is connected to the source signal line 18. Also, a turn-off voltage (Vgh) is applied to the gate signal line 17b, which is in the same state as during the first 1/2 H. Thus, the switching transistors 11d in the pixel rows (2), (3), (4), (5), and (6) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52.

[0586] Thus, each transistor 11a in the pixel row (1) deliver a current of Iw×5 to the source signal line 18. Then, the capacitor 19 in each pixel row (1) is programmed with a 5 times larger current. The entire screen is drawn as the above operations are performed in sequence.

[0587] The drive method described with reference to FIG. 30 selects G pixel rows (G is 2 or larger) in the first period and does programming in such a way as to pass N times larger current through each pixel row. In the second period, the drive method selects B pixel rows (B is smaller than G, but not smaller than 1) and does programming in such a way as to pass an N times larger current through the pixels.

[0588] Another scheme is also available. It selects G pixel rows (G is 2 or larger) in the first period and does programming in such a way that the total current in all the pixel rows will be an N times larger current. In the second period, this scheme selects B pixel rows (Bis smaller than G, but not smaller than 1) and does programming in such a way that the total current in the selected pixel rows (the current in the one pixel row if one pixel row is selected) will be an N times larger current. For example, in FIG. 30(a1), five pixel rows are selected simultaneously and a twice larger current is passed through the transistor 11a in each pixel. Thus, 5×2=10 times larger current flows through the source signal line 18. In the second period, one pixel row is selected in FIG. 30(b1). A 10 times larger current is passed through the transistor 11a in this pixel.

[0589] Incidentally, although a plurality of pixel rows are selected simultaneously in a period of 1/2 H and a single pixel row is selected in a period of 1/2 H in FIG. 31, this is not restrictive. A plurality of pixel rows may be selected simultaneously in a period of 1/4 H and a single pixel row may be selected in a period of 3/4 H. Also, the sum of the period in which a plurality of pixel rows are selected simultaneously and the period in which a single pixel row is selected is not limited to 1 H. For example, the total period may be 2 Hs or 1.5 Hs.

[0590] In FIG. 30, it is also possible to select two pixel rows simultaneously in the second period after selecting five pixel rows simultaneously in the first 1/2 H. This can also achieve a practically acceptable image display.

[0591] In FIG. 30, pixel rows are selected in two stages—five pixel rows are selected simultaneously in the first 1/2 H period and a single pixel row is selected in the second 1/2 H period, but this is not restrictive. For example, it is also possible to select five pixel rows simultaneously in the first stage, select two of the five pixel rows in the second stage, and finally select one pixel row in the third stage. In short, image data may be written into pixel rows in two or more stages.

[0592] In the example described above, pixel rows are selected one by one and programmed with current, or two or more pixel rows are selected at a time and programmed with current. However, the present invention is not limited to this. It is also possible to use a combination of the two methods according to image data: the method of selecting pixel rows one by one and programming them with current and the method of selecting two or more pixel rows at a time and programming them with current.

[0593] Now, interlaced driving according to the present invention will be described below. FIG. 133 shows a configuration of the display panel according to the present invention which performs the interlaced driving. In FIG. 133, the gate signal lines 17a of odd-numbered pixel rows are connected to a gate driver circuit 12a1. The gate signal lines 17a of even-numbered pixel rows are connected to a gate driver circuit 12a2. On the other hand, the gate signal lines 17b of the odd-numbered pixel rows are connected to a gate driver circuit 12b1. The gate signal lines 17b of the even-numbered pixel rows are connected to a gate driver circuit 12b2.

[0594] Thus, through operation (control) of the gate driver circuit 12a1, image data in the odd-numbered pixel rows are rewritten in sequence. In the odd-numbered pixel rows, illumination and non-illumination of the EL elements are controlled through operation (control) of the gate driver circuit 12b1. Also, through operation (control) of the gate driver circuit 12a2, image data in the even-numbered pixel rows are rewritten in sequence. In the even-numbered pixel rows, illumination and non-illumination of the EL elements are controlled through operation (control) of the gate driver circuit 12b2.

[0595] FIG. 134(a) shows operating state in the first field of the display panel. FIG. 134(b) shows operating state in the second field of the display panel. Incidentally, for ease of understanding, it is assumed that one frame consists of two fields. In FIG. 134, the oblique hatching which marks the gate driver circuits 12 indicates that the gate driver circuits 12 are not taking part in data scanning operation. Specifically, in the first field in FIG. 134(a), the gate driver circuit 12a1 is operating for write control of programming current and the gate driver circuit 12b2 is operating for illumination control of the EL element 15. In the second field in FIG. 134(b), the gate driver circuit 12a2 is operating for write control of programming current and the gate driver circuit 12b1 is operating for illumination control of the EL element 15. The above operations are repeated within the frame.

[0596] FIG. 135 shows image display status in the first field. FIG. 135(a) illustrates write pixel rows (locations of odd-numbered pixel rows programmed with current (voltage) The location of the write pixel row is shifted in sequence: FIG. 135(a1)→(a2)→(a3). In the first field, odd-numbered pixel rows are rewritten in sequence (image data in the even-numbered pixel rows are maintained). FIG. 135(b) illustrates display status of odd-numbered pixel rows. Incidentally, FIG. 135(b) illustrates only odd-numbered pixel rows. Even-numbered pixel rows are illustrated in FIG. 135(c). As can be seen from FIG. 135(b), the EL elements 15 of the pixels in the odd-numbered pixel rows are non-illuminated. On the other hand, the even-numbered pixel rows are scanned in both display area 53 and non-display area 52 as shown in FIG. 135(c) (N-fold pulse driving).

[0597] FIG. 136 shows image display status in the second field. FIG. 136(a) illustrates write pixel rows (locations of odd-numbered pixel rows programmed with current (voltage) The location of the write pixel row is shifted in sequence: FIG. 136(a1)→(a2)→(a3). In the second field, even-numbered pixel rows are rewritten in sequence (image data in the odd-numbered pixel rows are maintained). FIG. 136(b) illustrates display status of odd-numbered pixel rows. Incidentally, FIG. 136(b) illustrates only odd-numbered pixel rows. Even-numbered pixel rows are illustrated in FIG. 136(c). As can be seen from FIG. 136(b), the EL elements 15 of the pixels in the even-numbered pixel rows are non-illuminated. On the other hand, the odd-numbered pixel rows are scanned in both display area 53 and non-display area 52 as shown in FIG. 136(c) (N-fold pulse driving).

[0598] In this way, interlaced driving can be implemented easily on an EL display panel. Also, N-fold pulse driving eliminates shortages of write current and blurred moving pictures. Besides, current (voltage) programming and illumination of EL elements 15 can be controlled easily and circuits can be implemented easily.

[0599] Incidentally, the drive method according to the present invention is not limited to those shown in FIGS. 135 and 136. For example, a drive method shown in FIG. 137 is also available. Whereas in FIGS. 135 and 136, the odd-numbered pixel rows or even-numbered pixel rows being programmed belong to a non-display area 52 (non-illumination or black display), the example in FIG. 137 involves synchronizing the gate driver circuits 12b1 and 12b2 which control illumination of the EL elements 15. Needless to say, however, the write pixel row 51 being programmed with current (voltage) belongs to a non-display area (there is no need for this in the case of the current-mirror pixel configuration in FIG. 38). In FIG. 137, since illumination control is common to the odd-numbered pixel rows and even-numbered pixel rows, there is no need to provide two gate driver circuits: 12b1 and 12b2. The gate driver circuit 12b alone can perform illumination control.

[0600] The drive method in FIG. 137 uses illumination control for both odd-numbered pixel rows and even-numbered pixel rows. However, the present invention is not limited to this. FIG. 138 shows an example in which illumination control varies between odd-numbered pixel rows and even-numbered pixel rows. In FIG. 138, the illumination mode (display area 53 and non-display area 52) of odd-numbered pixel rows and illumination mode of even-numbered pixel rows have opposite patterns. Thus, display area 53 and non-display area 52 have the same size. However, this is not restrictive.

[0601] Also, in FIGS. 136 and 135, it is not strictly necessary that all the pixel rows in the odd-numbered pixel rows or even-numbered pixel rows should be non-illuminated.

[0602] In the above example, the drive method programs pixel rows with current (voltage) one at a time. However, the drive method according to the present invention is not limited to this. Needless to say, two pixel rows (a plurality of pixel rows) may be programmed with current (voltage) simultaneously as shown in FIG. 139 (see also FIG. 27 and its description) FIG. 139(a) shows an example concerning odd-numbered fields while FIG. 139(b) shows an example concerning an even-numbered fields. In odd-numbered fields, combinations of two pixel rows (1, 2), (3, 4), (5, 6), (7, 8), (9, 10), (11, 12), . . . , (n, n+1) are selected in sequence and programmed with current (where n is an integer not smaller than 1). In even-numbered fields, combinations of two pixel rows (2, 3), (4, 5), (6, 7), (8, 9), (10, 11), (12, 13), . . . , (n+1, n+2) are selected in sequence and programmed with current (where n is an integer not smaller than 1).

[0603] By selecting a plurality of pixel rows in each field and programming them with current, it is possible to increase the current to be passed through the source signal line 18, and thus write black properly. Also, by shifting combinations of pixel rows selected in odd-numbered fields and even-numbered fields at least by one pixel row, it is possible to increase the resolution of images.

[0604] Although in the example in FIG. 139, two pixel rows are selected in each field, this is not restrictive and three pixel rows may be selected. In this case, the three pixel rows selected in both odd-numbered fields and even-numbered fields may be shifted by either one pixel row or two pixel rows. Also, four or more pixel rows may be selected in each field. Besides, as shown in FIGS. 125 to 132, one frame may be composed of three or more field.

[0605] Also, although in the example in FIG. 139, two pixel rows are selected simultaneously, this is not restrictive. It is possible to divide 1 H into a first 1/2 H and second 1/2 H and perform current programming in odd-numbered fields by selecting the first pixel row in the first 1/2 H of the first 1 H and selecting the second pixel row in the second 1/2 H of the first 1 H, selecting the third pixel row in the first 1/2 H of the second 1 H and selecting the fourth pixel row in the second 1/2 H of the second 1 H, selecting the fifth pixel row in the first 1/2 H of the third 1 H and selecting the sixth pixel row in the second 1/2 H of the third 1 H, and so on.

[0606] In even-numbered fields, current programming can be performed by selecting the second pixel row in the first 1/2 H of the first 1 H and selecting the third pixel row in the second 1/2 H of the first 1 H, selecting the fourth pixel row in the first 1/2 H of the second 1 H and selecting the fifth pixel row in the second 1/2 H of the second 1 H, selecting the sixth pixel row in the first 1/2 H of the third 1 H and selecting the seventh pixel row in the second 1/2 H of the third 1 H, and so on.

[0607] Again, although in the above example, two pixel rows are selected in each field, this is not restrictive and three pixel rows may be selected. In this case, the three pixel rows selected in both odd-numbered fields and even-numbered fields may be shifted by either one pixel row or two pixel rows. Also, four pixel rows may be selected in each field.

[0608] The N-fold pulse driving method according to the present invention uses the same waveform for the gate signal lines 17b of different pixel rows and applies current by shifting the pixel rows at 1 H intervals. The use of such scanning makes it possible to shift illuminating pixel rows in sequence with the illumination duration of the EL elements 15 fixed to 1F/N. It is easy to shift pixel rows in this way while using the same waveform for the gate signal lines 17b of the pixel rows. It can be done by simply controlling data ST1 and ST2 applied to the shift register circuits 61a and 61b in FIG. 6. For example, if Vgl is output to the gate signal line 17b when input ST1 is low and Vgh is output to the gate signal line 17b when input ST1 is high, ST2 applied to the shift register circuit 17b can be set low for a period of 1F/N and set high for the remaining period. Then, inputted ST2 can be shifted using a clock CLK2 synchronized with 1 H.

[0609] Incidentally, the EL elements 15 must be turned on and off at intervals of 0.5 msec or longer. Short intervals will lead to insufficient black display due to persistence of vision, resulting in blurred images and making it look as if the resolution has lowered. This also represents a display state of a data holding display. However, increasing the on/off intervals to 100 msec will cause flickering. Thus, the on/off intervals of the EL elements must be not shorter than 0.5 μsec and not longer than 100 msec. More preferably, the on/off intervals should be from 2 msec to 30 msec (both inclusive). Even more preferably, the on/off intervals should be from 3 msec to 20 msec (both inclusive).

[0610] As also described above, an undivided black screen 52 achieves good movie display, but makes flickering of the screen more noticeable. Thus, it is desirable to divide the black insert into multiple parts. However, too many divisions will cause moving pictures to blur. The number of divisions should be from 1 to 8 (both inclusive). More preferably, it should be from 1 to 5 (both inclusive).

[0611] Incidentally, it is preferable that the number of divisions of a black screen can be varied between still pictures and moving pictures. When N=4, 75% is occupied by a black screen and 25% is occupied by image display. When the number of divisions is 1, a strip of black display which makes up 75% is scanned vertically. When the number of divisions is 3, three blocks are scanned, where each block consists of a black screen which makes up 25% and a display screen which makes up 25/3 percent. The number of divisions is increased for still pictures and decreased for moving pictures. The switching can be done either automatically according to input images (detection of moving pictures) or manually by the user. Alternatively, the switching can be done according to input outlet such as video on the display apparatus.

[0612] For example, for wallpaper display or an input screen on a cell phone, the number of divisions should be 10 or more (in extreme cases, the display may be turned on and off every 1 H). When displaying moving pictures in NTSC format, the number of divisions should be from 1 to 5 (both inclusive). Preferably, the number of divisions can be switched in three or more steps; for example, 0, 2, 4, 8 divisions, and so on Preferably, the ratio of the black screen to the entire display screen should be from 0.2 to 0.9 (from 1.2 to 9 in terms of N) both inclusive when the area of the entire screen is taken as 1. More preferably, the ratio should be from 0.25 to 0.6 (from 1.25 to 6 in terms of N) both inclusive. If the ratio is 0.20 or less, movie display is not improved much. When the ratio is 0.9 or more, the display part becomes bright and its vertical movements become liable to be recognized visually.

[0613] Also, preferably, the number of frames per second is from 10 to 100 (10 Hz to 100 Hz) both inclusive. More preferably, it is from 12 to 65 (12 Hz to 65 Hz) both inclusive. When the number of frames is small, flickering of the screen becomes conspicuous while too large a number of frames makes writing from the source driver circuit 14 and the like difficult, resulting in deterioration of resolution.

[0614] Needless to say, the above items also apply to the pixel configurations for current programming in FIG. 38 and the like as well as to the pixel configurations for voltage programming in FIGS. 43, 51, 54, and the like. This can be accomplished through on/off control of the transistor 11d in FIG. 38, transistor 11d in FIG. 43, and transistor 11e in FIG. 51. In this way, by turning on and off the wiring which delivers current to the EL elements 15, the N-fold pulse driving according to the present invention can be implemented easily.

[0615] Also, the gate signal line 17b may be set to Vgl for a period of 1F/N anytime during the period of 1F (not limited to 1F. Any unit time will do). This is because a predetermined brightness is obtained by turning off the EL element 15 for a predetermined period out of a unit time. However, it is preferable to set the gate signal line 17b to Vgl and illuminate the EL element 15 immediately after the current programming period (1 H). This will reduce the effect of retention characteristics of the capacitor 19 in FIG. 1.

[0616] Also, preferably the number of screen divisions is configured to be variable. For example, when the user presses a brightness adjustment switch or turns a brightness adjustment knob, the value of K may be changed in response. Alternatively, the value of K may be changed manually or automatically depending on images or data to be displayed.

[0617] In this way, the mechanism for changing the value of K (the number of divisions of the image display part 53) can be implemented easily. This can be achieved by simply making the time to change ST (when to set ST low during 1F) adjustable or variable.

[0618] Incidentally, although it has been stated with reference to FIG. 16 and the like that a period (1F/N) during which the gate signal line 17b is set to Vgl is divided into a plurality of parts (K parts) and that a period of 1F/(K·N) during which the gate signal line 17b is set to Vgl repeats K times, this is not restrictive. A period of 1F/(KN) may be repeated L (L≠K) times. In other words, the present invention displays the display screen 50 by controlling the period (time) during which current is passed through the EL element 15. Thus, the idea of repeating the 1F/(K·N) period L (L≠K) times is included in the technical idea of the present invention. Also, by varying the value of L, the brightness of the display screen 50 can be changed digitally. For example, there is a 50% change of brightness (contrast) between L=2 and L=3. The control described here is also applicable to other examples of the present invention (of course, it is applicable to what is described later herein). These are also included in the N-fold pulse driving according to the present invention.

[0619] The above examples involve placing (forming) the transistor 11d serving as a switching element between the EL element 15 and driver transistor 11a and turning on and off the screen 50 by controlling the transistor 11d. This drive method eliminates shortages of write current in black display condition during current programming and thereby achieves proper resolution or black display. That is, in current programming, it is important to achieve proper black display. The drive method described next achieves proper black display by resetting the driver transistor 11a. This example will be described below with reference to FIG. 32.

[0620] The pixel configuration in FIG. 32 is basically the same as the one shown in FIG. 1. With the pixel configuration in FIG. 32, a programmed Iw current flows through the EL element 15, illuminating the EL element 15. By being programmed, the driver transistor 11a retains a capability to pass current. The drive system shown in FIG. 32 resets (turns off) the transistor 11a using this capability to pass current. Hereinafter, this drive system will be referred to as reset driving.

[0621] To implement reset driving using the pixel configuration shown in FIG. 1, the transistors 11b and 11c must be able to be switched on and off independently of each other. Specifically, as illustrated in FIG. 32, it is necessary to be able to independently control the gate signal line 17a (gate signal line WR) used for on/off control of the transistor 11b and the gate signal line 17c (gate signal line EL) used for on/off control of the transistor 11c. The gate signal lines 17a and 17c can be controlled using two independent shift registers 61 as illustrated in FIG. 6.

[0622] Preferably, the drive voltage should be varied between the gate signal line 17a which drives the transistor 11b and the gate signal line 17b which drives the transistor 11d (when the pixel configuration in FIG. 1 is used). The amplitude value (difference between turn-on voltage and turn-off voltage) of the gate signal line 17a should be smaller than the amplitude value of the gate signal line 17b.

[0623] Too large an amplitude value of the gate signal line 17 will increase penetration voltage between the gate signal line 17 and pixel 16, resulting in an insufficient black level. The amplitude of the gate signal line 17a can be controlled by controlling the time when the potential of the source signal line 18 is not applied (or is applied (during selection)) to the pixel 16. Since changes in the potential of the source signal line 18 are small, the amplitude value of the gate signal line 17a can be made small.

[0624] On the other hand, the gate signal line 17b is used for on/off control of EL. Thus, its amplitude value becomes large. For this, output voltage is varied between the shift register circuits 61a and 61b. If the pixel is constructed of P-channel transistors, approximately equal Vgh (turn-off voltage) is used for the shift register circuits 61a and 61b while Vgl (turn-on voltage) of the shift register circuit 61a is made lower than Vgl (turn-on voltage) of the shift register circuit 61b.

[0625] Reset driving will be described below with reference to FIG. 33. FIG. 33 is a diagram illustrating a principle of reset driving. First, as illustrated in FIG. 33(a), the transistors 11c and 11d are turned off and the transistor 11b is turned on. As a result, the drain (D) terminal and gate (G) terminal of the driver transistor 11a are short-circuited, allowing a current Ib to flow. Generally, the transistor 11a has been programmed with current in the previous field (frame). In this state, as the transistor 11d is turned off and the transistor 11b is turned on, the drive current Ib flows through the gate (G) terminal of the transistor 11a. Consequently, the gate (G) terminal and drain (D) terminal of the transistor 11a have the same potential, resetting the transistor 11a (to a state in which no current flows).

[0626] Incidentally, before the operation in FIG. 33(a), it is preferable to turn off the transistors 11b and 11c, turn on the transistor 11d, and pass current through the driver transistor 11a. Preferably, this operation should be completed in a minimum time. Otherwise, there is a fear that a current will flow through the EL element 15, illuminating the EL element 15, and thereby lowering display contrast. Preferably, the operating time here is from 0.1% to 10% of 1 H (one horizontal scanning period) both inclusive. More preferably, it is from 0.2% to 2% or from 0.2 μsec to 5 μsec (both inclusive). Also, this operation (the operation to be performed before the operation in FIG. 33(a)) may be performed on all the pixels 16 of the screen at once. This operation will lower the drain (D) terminal voltage of the driver transistor 11a, making it possible to pass the current Ib smoothly in the state shown in FIG. 33(a). Incidentally, the above items also apply to other reset driving according to the present invention.

[0627] As the operation time of FIG. 33(a) becomes longer, a larger Ib current tends to flow, reducing the terminal voltage of the capacitor 19. Thus, the operation time of FIG. 33(a) should be fixed. It has been shown experimentally and analytically that preferably the operation time in FIG. 33(a) is from 1 H to 5 Hs (both inclusive).

[0628] Preferably, this period should be varied among R, G, and B pixels. This is because EL material varies among different colors and rising voltage varies among different EL materials. Optimum periods suitable for EL materials should be specified separately for the R, G, and B pixels. Although it has been stated that the period should be from 1 H to 5 Hs (both inclusive) in this example, it goes without saying that the period may be 5 Hs or longer in the case of a drive system which mainly concerns black insertion (writing of a black screen). Incidentally, the longer the period, the better the black display condition of pixels.

[0629] A state shown in FIG. 33(b) occurs during a period of 1 H to 5 Hs (both inclusive) after the state in FIG. 33(a). FIG. 33(b) shows a state in which the transistors 11c and 11b are on and the transistor 11d is off. This is a state in which current programming is being performed, as described earlier. Specifically, a programming current Iw is output (or absorbed) from the source driver circuit 14 and passed through the driver transistor 11a. The potential of the gate (G) terminal of the driver transistor 11a is set so that the programming current Iw flows (the set potential is held in the capacitor 19).

[0630] If the programming current Iw is 0 A, the transistor 11a is held in the state in FIG. 33(a) in which it does not pass current, and thus a proper black display is achieved. Also, when performing current programming for white display in FIG. 33(b), the current programming is started from offset voltage of completely black display even if there are variations in the characteristics of driver transistors in pixels. Thus, the time required to reach a target current value becomes uniform according to gradations. This eliminates gradation errors due to variations in the characteristics of the transistors 11a, making it possible to achieve proper image display.

[0631] After the programming in FIG. 33(b), the transistors 11b and 11c are turned off in sequence and the transistor 11d is turned on to deliver the programming current Iw (=Ie) to the EL element 15 from the driver transistor 11a, and thereby illuminate the EL element 15. What is shown in FIG. 33(c) has already been described with reference to FIG. 1 and the like, and thus detailed description thereof will be omitted.

[0632] The drive system (reset driving) described with reference to FIG. 33 consists of a first operation of disconnecting the driver transistor 11a from the EL element 15 (so that no current flows) and shorting between the drain (D) terminal and gate (G) terminal of the driver transistor (or between the source (S) terminal and gate (G) terminal, or generally speaking, between two terminals including the gate (G) terminal of the driver transistor) and a second operation of programming the driver transistor with current (voltage) after the first operation. At least the second operation is performed after the first operation. Incidentally, for reset driving, the transistors 11b and 11c must be able to be controlled independently as shown in FIG. 32.

[0633] In image display mode (if instantaneous changes can be observed), the pixel row to be programmed with current is reset (black display mode) and is programmed with current after 1H (also in black display mode because the transistor 11d is off) Next, current is supplied to the EL element 15 and the pixel row illuminates at a predetermined brightness (at the programmed current) That is, the pixel row of black display moves from top to bottom of the screen and it should look as if the image were rewritten at the location where the pixel row passed by.

[0634] Incidentally, although it has been stated that current programming is performed 1 H after a reset, this period may be approximately 5 Hs or shorter. This is because it takes a relatively long time for the reset in FIG. 33(a) to be completed. If this period is 5 Hs, five pixel rows will be displayed in black (six pixel rows including the pixel row going through current programming).

[0635] Also, the number of pixel rows which are reset at a time is not limited to one, and two or more pixel rows may be reset at a time. It is also possible to reset and scan two or more pixel rows at a time by overlapping some of them. For example, if four pixel rows are reset at a time, pixel rows (1), (2), (3), and (4) are reset in the first horizontal scanning period (1 unit), pixel rows (3), (4), (5), and (6) are reset in the second horizontal scanning period, pixel rows (5), (6), (7), and (8) are reset in the third horizontal scanning period, and pixel rows (7), (8), (9), and (10) are reset in the fourth horizontal scanning period. Incidentally the drive operations in FIGS. 33(b) and 33(c) are naturally carried out in sync with the drive operation in FIG. 33(a).

[0636] Needless to say, the drive operation in (c) of FIG. 33(b) may be performed after resetting all the pixels in the screen simultaneously or during scanning. Also, it goes without saying that pixel rows may be reset (at intervals of one or more pixel rows) in interlaced driving mode (scanning at intervals of one or more pixel rows). Also, pixel rows may be reset at random. The reset driving according to the present invention involves operating pixel rows (i.e., controlling the vertical direction of the screen). However, the concept of reset driving does not limit control directions to the pixel row direction. For example, it goes without saying that reset driving may be performed in the direction of pixel columns.

[0637] Incidentally, the reset driving in FIG. 33 can achieve better image display if combined with the N-fold pulse driving according to the present invention or with interlaced driving. Particularly, the configuration in FIG. 22 can easily implement intermittent N/K-fold pulse driving (this driving method provides two or more illuminated areas in a screen and can be implemented easily by turning on and off the transistor 11d by controlling the gate signal line 17b: this has been described earlier), and thus can achieve proper image display without flickering.

[0638] Needless to say, more excellent image display can be achieved by combining with precharge driving or the like described later. Thus, it goes without saying that reset driving can be performed in combination with other examples according to the present invention.

[0639] FIG. 34 is a block diagram of a display apparatus which implement reset driving. The gate driver circuit 12a controls the gate signal line 17a and gate signal line 17b in FIG. 32. By the application of on/off voltages to the gate signal line 17a, the transistor 11b is turned on and off. Also, by the application of on/off voltages to the gate signal line 17b, the transistor 11d is turned on and off. The gate driver circuit 12b controls the gate signal line 17c in FIG. 32. By the application of on/off voltages to the gate signal line 17c, the transistor 11c is turned on and off.

[0640] Thus, the gate signal line 17a is controlled by the gate driver circuit 12a while the gate signal line 17c is controlled by the gate driver circuit 12b. This makes it possible to freely specify the time to turn on the transistor 11b and reset the driver transistor 11a as well as the time to turn on the transistor 111c and program the driver transistor 11a with current. Other parts of the configuration are the same as or similar to those described earlier, and thus description thereof will be omitted.

[0641] FIG. 35 is a timing chart of reset driving. While a turn-on voltage is applied to the gate signal line 17a to turn on the transistor 11b and reset the driver transistor 11a, a turn-off voltage is applied to the gate signal line 17b to keep the transistor 11d off. This creates the state shown in FIG. 32(a). A current Ib flows during this period.

[0642] Although in the timing chart shown in FIG. 35, the reset time is 2 Hs (when a turn-on voltage is applied to the gate signal line 17a and the transistor 11b is turned on), this is not restrictive. The reset time may be longer than 2 Hs. If a reset can be performed very quickly, the reset time may be less than 1 H.

[0643] The duration of the reset period can be changed easily using a DATA (ST) pulse period inputted in the gate driver circuit 12. For example, if DATA inputted in an ST terminal is set high for a period of 2 Hs, the reset period outputted for each gate signal line 17a is 2 Hs. Similarly, if DATA inputted in the ST terminal is set high for a period of 5 Hs, the reset period outputted for each gate signal line 17a is 5 Hs.

[0644] After a reset period of 1 H, a turn-on voltage is applied to the gate signal line 17c(1) of the pixel row (1). As the transistor 11c turns on, the programming current Iw applied to the source signal line 18 is written into the driver transistor 11a via the transistor 11c.

[0645] After current programming, a turn-off voltage is applied to the gate signal line 17c of the pixel row (1), the transistor 11c is turned off, and the pixel disconnected from the source signal line. At the same time, a turn-off voltage is also applied to the gate signal line 17a and the driver transistor 11a exits the reset mode (incidentally, the use of the term “current-programming mode” is more appropriate than the term “reset mode” to refer to this period). On the other hand, a turn-on voltage is applied to the gate signal line 17b, the transistor 11d is turned on, and the current programmed into the driver transistor 11a flows through the EL element 15. What has been said about the pixel row (1) similarly applies to the pixel row (2) and subsequent pixel rows. Also, their operation is obvious from FIG. 35. Thus, description of (2) and subsequent pixel rows will be omitted.

[0646] In FIG. 35, the reset period has been 1 H. FIG. 36 shows an example in which the reset period is 5 Hs. The duration of the reset period can be changed easily using the DATA (ST) pulse period inputted in the gate driver circuit 12. FIG. 36 shows an example in which DATA inputted in the ST1 terminal of the gate driver circuit 12a is set high for a period of 5 Hs and the reset period outputted for each gate signal line 17a is 5 Hs. The longer the reset period, the more completely the reset is performed, resulting in a proper black display. However, display brightness is decreased accordingly.

[0647] In FIG. 36, the reset period has been 5 Hs. Besides, the reset mode is continuous. However, the reset mode need not necessarily be continuous. For example, the signal outputted from each gate signal line 17a may be turned on and off every 1 H. Such on/off operation can be achieved easily by operating an enable circuit (not shown) formed in the output stage of the shift register or controlling the DATA (ST) pulses inputted in the gate driver circuit 12.

[0648] In the circuit configuration shown in FIG. 34, the gate driver circuit 12a requires at least two shift register circuits (one for the gate signal line 17a, the other for the gate signal line 17b). This presents a problem of an increased circuit scale of the gate driver circuit 12a. FIG. 37 shows an example in which the gate driver circuit 12a has only one shift register. A timing chart of output signals resulting from operation of the circuit in FIG. 37 is shown in FIG. 35. Note that the gate signal lines 17 coming out of the gate driver circuits 12a and 12b are denoted by different symbols between FIGS. 35 and 37.

[0649] As can be seen from the fact that an OR circuit 371 is included in FIG. 37, the output of each gate signal line 17a is ORed with the output from the preceding stage to the shift register circuit 61a. That is, the gate signal line 17a outputs a turn-on voltage for a period of 2 Hs. On the other hand, the gate signal line 17c outputs the output of the shift register circuit 61a as it is. Thus, a turn-on voltage is applied for a period of 1 H.

[0650] For example, if the shift register circuit 61a outputs a high-level signal second, a turn-on voltage is output to the gate signal lines 17c of the pixel 16(1), which now is in a state of being programmed with current (voltage). At the same time, a turn-on voltage is also output to the gate signal lines 17a of the pixel 16 (2), turning on the transistor 11b of the pixel 16(2) and resetting the driver transistor 11a of the pixel 16(2).

[0651] Similarly, if the shift register circuit 61a outputs a high-level signal third, a turn-on voltage is output to the gate signal lines 17c of the pixel 16(2), which now is in a state of being programmed with current (voltage). At the same time, a turn-on voltage is also output to the gate signal lines 17a of the pixel 16(3, turning on the transistor 11b of the pixel 16(3) and resetting the driver transistor 11a of the pixel 16(3). Thus, the gate signal lines 17a outputs turn-on voltages for a period of 2 Hs, and the gate signal lines 17c receive a turn-on voltage for a period of 1 H.

[0652] In programming mode, since the transistors 11b and 11c turn on simultaneously (FIG. 33(b)), if the transistor 11c turns off before the transistor 11b during transition to non-programming mode (FIG. 33(c), the reset mode in FIG. 33(b) occurs. To prevent this situation, the transistor 11c must be turned off after the transistor 11b. For that, a turn-on voltage needs to be applied to the gate signal line 17a earlier than the gate signal line 17c.

[0653] The above example concerns the pixel configuration in FIG. 32 (basically, in FIG. 1). However, the present invention is not limited to this. For example, it is also applicable to current-mirror pixel configurations such as the one shown in FIG. 38. Incidentally, in FIG. 38, by turning on and off the transistor 11e, N-fold pulse driving illustrated in FIGS. 13, 15, etc. can be implemented. FIG. 39 is an explanatory diagram illustrating an example employing the current-mirror pixel configuration shown in FIG. 38. Reset driving in the current-mirror pixel configuration will be described below with reference to FIG. 39.

[0654] As shown in FIG. 39(a), the transistors 11c and 11e are turned off and the transistor 11d is turned on. Then, the drain (D) terminal and gate (G) terminal of the current-programming transistor 11b are short-circuited and a current Ib flows between them as shown in the figure. Generally, the transistor 11b has been programmed with current in the previous field (frame) and is capable of passing current (this is natural because the gate potential is held in the capacitor 19 for a period of 1F and image is displayed. However, current does not flow during a completely black display). In this state, as the transistor 11e is turned off and the transistor 11d is turned on, the drive current Ib flows through the gate (G) terminal of the transistor 11a (gate (G) terminal and the drain (D) terminal are short-circuited). Consequently, the gate (G) terminal and drain (D) terminal of the transistor 11a have the same potential, resetting the transistor 11a (to a state in which no current flows). Since the driver transistor 11b shares a common gate (G) terminal with the current-programming transistor 11a, the driver transistor 11b is also reset.

[0655] The reset mode (in which no current flows) of the transistors 11a and 11b is equivalent to a state in which a offset voltage is held in voltage offset canceling mode described with reference to FIG. 51 and the like. That is, in the state in FIG. 39(a), the offset voltage is held between the terminals of the capacitor 19 (the offset voltage is a starting voltage at which a current starts to flow: when a voltage equal to or larger than the starting voltage is applied, a current flows through the transistor 11). The offset voltage varies with the characteristics of the transistors 11a and 11b. Thus, in FIG. 39(a), a state in which the transistors 11a and 11b do not pass current is maintained in the capacitor 19 in each pixel (the transistors 11a and 11b pass a black display current close to zero, i.e., they have been reset to the starting voltage at which a current starts to flow).

[0656] In FIG. 39(a), as the reset period becomes longer, a larger Ib current tends to flow, reducing the terminal voltage of the capacitor 19, as in the case of FIG. 33(a). Thus, the operation time in FIG. 39(a) should be fixed. It has been shown experimentally and analytically that preferably the operation time in FIG. 39(a) is from 1 H to 10 Hs (ten horizontal scanning periods) both inclusive. More preferably, it should be from 1 H to 5 Hs or from 20 μsec to 2 msec (both inclusive). This also applies to the drive system in FIG. 33.

[0657] As in the case of FIG. 33(a), if the reset mode in FIG. 39(a) is synchronized with the current-programming mode in FIG. 39(b), there is no problem because the period from the reset mode in FIG. 39(a) to the current-programming mode in FIG. 39(b) is fixed (constant). That is, preferably the period from the reset mode in FIG. 33(a) or FIG. 39(a) to the current-programming mode in FIG. 33(b) or FIG. 39(b) should be from 1 H to 10 Hs (ten horizontal scanning periods) both inclusive. More preferably, it should be from 1 H to 5 Hs or from 20 μsec to 2 msec (both inclusive). If this period is short, the driver transistors 11 are not reset completely. If it is too long, the driver transistor 11 is turned off completely, which means that much time is required for current programming. Also, the brightness of the screen 50 is decreased.

[0658] After the state in FIG. 39(a), a state shown in FIG. 39(b) occurs. FIG. 39(b) shows a state in which the transistors 11c and 11d are turned on and the transistor 11e is turned off. This is a state in which current programming is being performed. Specifically, a programming current Iw is output (absorbed) from the source driver circuit 14 and passed through the current programming transistor 11a. The potential of the gate (G) terminal of the driver transistor 11a is set in the capacitor 19 so that the programming current Iw will flow.

[0659] If the programming current Iw is 0 A (black display) the transistor 11b is held in the state in FIG. 33(a) in which it does not pass current, and thus proper black display is achieved. Also, when performing current programming for white display in FIG. 39(b), the current programming is started from offset voltage of completely black display even if there are variations in the characteristics of driver transistors in pixels (the offset voltage is a starting voltage at which a current specified according to the characteristics of each driver transistor starts to flow). Thus, the time required to reach a target current value becomes uniform according to gradations. This eliminates gradation errors due to variations in the characteristics of the transistor 11a or 11b, making it possible to achieve proper image display.

[0660] After the current programming in FIG. 39(b), the transistors 11c and 11d are turned off in sequence and the transistor 11e is turned on to deliver the programming current Iw (=Ie) to the EL element 15 from the driver transistor 11b, and thereby illuminate the EL element 15. What is shown in FIG. 39(c) has already been described, and thus detailed description thereof will be omitted.

[0661] The drive system (reset driving) described with reference to FIGS. 33 and 39 consists of a first operation of disconnecting the driver transistor 11a or 11b from the EL element 15 (using the transistor 11e or 11d so that no current flows) and shorting between the drain (D) terminal and gate (G) terminal of the driver transistor (or between the source (S) terminal and gate (G) terminal, or generally speaking, between two terminals including the gate (G) terminal of the driver transistor) and a second operation of programming the driver transistor with current (voltage) after the first operation.

[0662] At least the second operation is performed after the first operation. Incidentally, the operation of disconnecting the driver transistor 11a or 11b from the EL element 15 in the first operation is not absolutely necessary. The drain (D) terminal and gate (G) terminal of the driver transistor are short-circuited in the first operation without disconnecting the driver transistor 11a or 11b from the EL element 15, nothing more than some variations in reset mode may result. Whether to omit disconnection should be determined by considering the characteristics of the transistors in the constructed array.

[0663] The current-mirror pixel configuration in FIG. 39 provides a drive method which resets the current-programming transistor 11a, and consequently resets the driver transistor 11b.

[0664] With the current-mirror pixel configuration in FIG. 39, it is not always necessary to disconnect the driver transistor 11b from the EL element 15 in reset mode. Thus, the following operations are performed: a first operation of shorting between the drain (D) terminal and gate (G) terminal of the current-programming transistor a (or between the source (S) terminal and gate (G) terminal, or generally speaking, between two terminals including the gate (G) terminal of the current-programming transistor or between two terminals including the gate (G) terminal of the driver transistor) and a second operation of programming the current-programming transistor with current (voltage) after the first operation. At least the second operation is performed after the first operation.

[0665] In image display mode (if instantaneous changes can be observed), the pixel row to be programmed with current is reset (black display mode) and is programmed with current after a predetermined H. The pixel row of black display moves from top to bottom of the screen and it should look as if the image were rewritten at the location where the pixel row passed by.

[0666] Although the above example has been described mainly in relation to pixel configuration for current programming, the reset driving according to the present invention can also be applied to pixel configuration for voltage programming. FIG. 43 is an explanatory diagram illustrating a pixel configuration (panel configuration) according to the present invention used to perform reset driving in a pixel configuration for voltage programming.

[0667] In the configuration shown in FIG. 43, a transistor 11e which resets a driver transistor 11a has been formed. When a turn-on voltage is applied to a gate signal line 17e, the transistor 11e turns on, causing a short circuit between the gate (G) terminal and drain (D) terminal of the driver transistor 11a. Also a transistor 11d which cuts off a current path between the EL element 15 and driver transistor 11a has been formed. The reset driving according to the present invention in a pixel configuration for voltage programming will be described below with reference to FIG. 44.

[0668] As illustrated in FIG. 44(a), the transistors 11b and 11d are turned off and the transistor 11e is turned on. The drain (D) terminal and gate (G) terminal of the driver transistor 11a are short-circuited and a current Ib flows as shown in the figure. Consequently, the gate (G) terminal and drain (D) terminal of the transistor 11a have the same potential, resetting the transistor 11a (to a state in which no current flows). Before resetting the transistor 11a, the transistor 11d is turned on, the transistor 11e is turned off, and current is passed through the transistor 11a in sync with an HD synchronization signal as described with reference to FIG. 33 or 39. Then the operation shown in FIG. 44(a) is performed.

[0669] Incidentally, in the pixel configuration for voltage programming, as the reset period becomes longer, a larger Ib current tends to flow, reducing the terminal voltage of the capacitor 19, as in the case of pixel configuration for current programming. Thus, the operation time in FIG. 44(a) should be fixed. Preferably, the operation time should be from 0.2 H to 5 Hs (five horizontal scanning periods) both inclusive. More preferably, it should be from 0.5 H to 4 Hs or from 2 μsec to 400 μsec (both inclusive).

[0670] Besides, it is preferable that the gate signal line 17e should be shared with the gate signal line 17a in a preceding stage. That is the gate signal line 17e should be shorted to the gate signal line 17a in the pixel row in the preceding stage. This configuration is referred to as a preceding-stage gate control system. Incidentally, the stage-stage gate control system uses waveforms of gate signal lines of a pixel row selected one or more Hs before the pixel row of interest. Thus, this system is not limited to the previous pixel row. For example, the driver transistor 11a of the pixel row of interest may be reset using the waveforms of gate signal lines two pixel rows ahead.

[0671] The stage-stage gate control system will be described more concretely. Suppose, the pixel row of interest is the (N)-th pixel row whose gate signal lines are 17e(N) and 17a(N) The preceding pixel row selected 1 H before is assumed to be the (N−1)-th pixel row whose gate signal lines are 17e(N−1) and 17a (N−1). The pixel row selected 1 H after the pixel row of interest is assumed to be the (N+1)-th pixel row whose gate signal lines are 17e(N+1) and 17a(N+1).

[0672] In the (N−1)-th H-period, as a turn-on voltage is applied to the gate signal line 17a(N−1) of the (N−1)-th pixel row, a turn-on voltage is also applied to the gate signal line 17e(N) of the (N)-th pixel row. This is because the gate signal line 17e (N) and the gate signal line 17a (N−1) of the pixel row in the preceding stage are shorted. Consequently, the pixel transistor 11b(N−1) in the (N−1)-th pixel row is turned on and the voltage applied to the source signal line 18 is written into the gate (G) terminal of the driver transistor 11a (N−1). At the same time, the pixel transistor 11e (N) in the (N)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11a(N) are shorted, and the driver transistor 11a(N) is reset.

[0673] In the (N)-th H-period which follows the (N−1)-th H-period, as a turn-on voltage is applied to the gate signal line 17a(N) of the (N)-th pixel row, a turn-on voltage is also applied to the gate signal line 17e(N+1) of the (N+1)-th pixel row. Consequently, the pixel transistor 11b (N) in the (N)-th pixel row is turned on and the voltage applied to the source signal line 18 is written into the gate (G) terminal of the driver transistor 11a (N). At the same time, the pixel transistor 11e(N+1) in the (N+1)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11a (N+1) are shorted, and the driver transistor 11a(N+1) is reset.

[0674] Similarly, in the (N+1)-th period which follows the (N)-th H-period, as a turn-on voltage is applied to the gate signal line 17a (N+1) of the (N+1)-th pixel row, a turn-on voltage is also applied to the gate signal line 17e(N+2) of the (N+2)-th pixel row. Consequently, the pixel transistor 11b(N+1) in the (N+1)-th pixel row is turned on and the voltage applied to the source signal line 18 is written into the gate (G) terminal of the driver transistor 11a(N+1). At the same time, the pixel transistor 11e(N+2) in the (N+2)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11a (N+2) are shorted, and the driver transistor 11a(N+2) is reset.

[0675] According to the above-described stage-stage gate control system of the present invention, the driver transistor 11a is reset for a period of 1 H, and then voltage (current) programming is performed.

[0676] As in the case of FIG. 33(a), if the reset mode in FIG. 44(a) is synchronized with the voltage-programming mode in FIG. 44(b), there is no problem because the period from the reset mode in FIG. 44(a) to the current-programming mode in FIG. 44(b) is fixed (constant). If this period is short, the driver transistors 11 are not reset completely. If it is too long, the driver transistor 11a is turned off completely, which means that much time is required for current programming. Also, the brightness of the screen 12 is decreased.

[0677] After the state in FIG. 44(a), a state shown in FIG. 44(b) occurs. FIG. 44(b) shows a state in which the transistor 11b is turned on and the transistors 11e and 11d are turned off. This state in FIG. 44(b), is a state in which voltage programming is being performed. Specifically, a programming voltage is output from the source driver circuit 14 and written into the gate (G) terminal of the driver transistor 11a (the potential of the gate (G) terminal of the driver transistor 11a is set in the capacitor 19). Incidentally, in the case of voltage programming, it is not always necessary to turn off the transistor 11d during voltage programming. Besides, the transistor 11e is not necessary if there is no need to combine with the N-fold driving shown in FIG. 13, 15, or the like or perform intermittent N/K-fold pulse driving (this driving method provides two or more illuminated areas in a screen and can be implemented easily by turning on and off the transistor 11e). Since this has been described earlier, description thereof will be omitted.

[0678] When performing voltage programming for white display using the configuration shown in FIG. 43 or drive method shown in FIG. 44, the voltage programming is started from offset voltage of completely black display even if there are variations in the characteristics of driver transistors in pixels (the offset voltage is a starting voltage at which a current specified according to the characteristics of each driver transistor starts to flow). Thus, the time required to reach a target current value becomes uniform according to gradations. This eliminates gradation errors due to variations in the characteristics of the transistor 11a, making it possible to achieve proper image display.

[0679] After the current programming in FIG. 44(b), the transistor 11d is turned off and the transistor 11d is turned on to deliver the programming current to the EL element 15 from the driver transistor 11a, and thereby illuminate the EL element 15, as shown in FIG. 44(c).

[0680] As described above, the reset driving according to the present invention using the voltage programming shown in FIG. 43 consists of a first operation of turning on the transistor 11d, turning off the transistor 11e, and passing current through the transistor 11a in sync with the HD synchronization signal; a second operation of disconnecting the transistor 11a from the EL element 15 and shorting between the drain (D) terminal and gate (G) terminal of the driver transistor 11a (or between the source (S) terminal and gate (G) terminal, or generally speaking, between two terminals including the gate (G) terminal of the driver transistor); and a third operation of programming the driver transistor 11a with voltage after the above operations.

[0681] In the above example, the transistor 11d is turned on and off to control the current delivered from the driver transistor 11a (in the case of configuration shown in FIG. 1) to the EL element 15. To turn on and off the transistor 11d, the gate signal line 17b needs to be scanned, for which the shift register circuit 61 (the gate driver circuit 12) is required. However, shift register circuits 61 are large in scale and the use of a shift register circuit 61 for the gate signal line 17b makes it impossible to reduce bezel width. A system described with reference to FIG. 40 solves this problem.

[0682] Incidentally, although the pixel configuration for current programming illustrated in FIG. 1 and the like is mainly described herein by way of examples, the present invention is not limited to this and it goes without saying that the present invention can also be applied to other configuration for current programming (current-mirror pixel configuration) described with reference to FIG. 38 and the like. Also, the technical concept of turning on and off elements as a block can also be applied to the pixel configuration for voltage programming in FIG. 41 and the like.

[0683] FIG. 40 shows an example of a block driving system. For ease of understanding, it is assumed that a gate driver circuit 12 is formed directly on an array board 71 or that a silicon chip, gate driver IC 12, is mounted on an array board 71. Source driver circuits 14 and source signal lines 18 are omitted to avoid complicating the drawing.

[0684] In FIG. 40, gate signal lines 17a are connected to the gate driver circuit 12. On the other hand, gate signal lines 17b are connected to illumination control lines 4b1. In FIG. 40, four gate signal lines 17b are connected to one illumination control line 401.

[0685] Incidentally, although four gate signal lines 17b are grouped into a block here, this is not restrictive and it goes without saying that more than four gate signal lines 17b may be grouped into a block. Generally, it is preferable to divide the screen 50 into five or more parts. More preferably, the screen 50 should be divided into ten or more parts. Even more preferably, the screen 50 should be divided into twenty or more parts. A small number of divisions will make flickering conspicuous. Too large a number of divisions will increase the number of illumination control lines 401, making it difficult to lay out the illumination control lines 401.

[0686] Thus, in the case of a QCIF display panel, which has 220 vertical scanning lines, at least 220/5=44 or more lines should be grouped into a block. More preferably, 220/10=11 or more lines should be grouped into a block. However, if odd-numbered rows and even-numbered rows are grouped into two different blocks, there is not much flickering even at a low frame rate, and thus the two blocks are sufficient.

[0687] In the example shown in FIG. 40, the current flowing through the EL elements 15 are turned on and off on a block-by-block basis by the application of either a turn-on voltage (Vgl) or turn-off voltage (Vgh) to illumination control lines 401a, 401b, 401c, 401d, . . . , 401n in sequence.

[0688] Incidentally, in the example in FIG. 40, the gate signal lines 17b do not intersect the illumination control lines 401. Thus, there can be no defect in which a gate signal line 17b would become short-circuited with an illumination control line 401. Also, since there is no capacitive coupling between gate signal lines 17b and illumination control lines 401, addition of capacitance is very small when the gate signal lines 17b are viewed from the illumination control lines 401. This makes it easy to drive the illumination control lines 401.

[0689] The gate driver circuit 12 is connected with the gate signal lines 17a. When a turn-on voltage is applied to gate signal lines 17a, the appropriate pixel rows are selected and the transistors 11b and 11c in the selected pixel rows are turned on. Then, currents (voltage) applied to the source signal lines 18 are programmed into the capacitors 19 in the pixels. On the other hand, the gate signal lines 17b are connected with the gate (G) terminals of the transistors 11d in the pixels. Thus, when a turn-on voltage (Vgl) is applied to the illumination control lines 401, current paths are formed between the driver transistors 11a and EL elements 15. When a turn-off voltage (Vgh) is applied, the anode terminals of the EL elements 15 are opened.

[0690] Preferably, control timing of turn-on/turn-off voltages applied to the illumination control lines 401 and a pixel row selection voltage (Vgl) outputted to the gate signal lines 17a by the gate driver circuit 12 are synchronized with one horizontal scanning clock (1 H). However, this is not restrictive.

[0691] The signals applied to the illumination control lines 401 simply turn on and off the current delivered to the EL elements 15. They do not need to be synchronized with image data outputted from the source driver circuits 14. This is because the signals applied to the illumination control lines 401 are intended to control the current programmed into the capacitors 19 in the pixels 16. Thus, they do not always need to be synchronized with the pixel row selection signal. Even when they are synchronized, the clock is not limited to a 1-H signal and may be a 1/2-H or 1/4-H signal.

[0692] Even in the case of the current-mirror pixel configuration shown in FIG. 38, the transistors 11e can be turned on and off if the gate signal lines 17b are connected to the illumination control lines 401. Thus, block driving can be implemented.

[0693] Incidentally, in FIG. 32, by connecting the gate signal lines 17a to the illumination control lines 401 and performing resets, it is possible to implement block driving. In other words, the block driving according to the present invention is a drive method which puts a plurality of pixel rows in non-illumination (black display) mode simultaneously using one control line.

[0694] In the above example, one selection pixel row is placed (formed) per pixel row. The present invention is not limited to this and a selection gate signal line may be placed (formed) for two or more pixel rows.

[0695] FIG. 41 shows such an example. Incidentally, for ease of explanation, the pixel configuration in FIG. 1 is employed mainly. In FIG. 41, the gate signal line 17a for pixel row selection selects three pixels (16R, 16G, and 16B) simultaneously. Reference character R is intended to indicate something related to a red pixel, reference character G indicates something related to a green pixel, and reference character B indicates something related to a blue pixel.

[0696] Thus, when the gate signal line 17a is selected, the pixels 16R, 16G, and 16B are selected and get ready to write data. The pixel 16R writes data into a capacitor 19R via a source signal line 18R, the pixel 16G writes data into a capacitor 19G via a source signal line 18G, and the pixel 16B writes data into a capacitor 19B via a source signal line 18B.

[0697] The transistor 11d of the pixel 16R is connected to a gate signal line 17bR, the transistor 11d of the pixel 16G is connected to a gate signal line 17bG, and the transistor 11d of the pixel 16B is connected to a gate signal line 17bB. Thus, an EL element 15R of the pixel 16R, EL element 15G of the pixel 16G, and EL element 15B of the pixel 16B can be turned on and off separately. Illumination times and illumination periods of the EL element 15R, EL element 15G, and EL element 15B can be controlled separately by controlling the gate signal line 17bR, gate signal line 17bG, and gate signal line 17bB.

[0698] To implement this operation, in the configuration in FIG. 6, it is appropriate to form (place) four shift register circuits: a shift register circuit 61 which scans the gate signal line 17a, shift register circuit 61 which scans the gate signal line 17bR, shift register circuit 61 which scans the gate signal line 17bG, and shift register circuit 61 which scans the gate signal line 17bB.

[0699] Incidentally, although it has been stated that a current N times larger than a predetermined current is passed through the source signal line 18 and that a current N times larger than a predetermined current is passed through the EL element 15 for a period of 1/N, this cannot be implemented in practice. Actually, signal pulses applied to the gate signal line 17 penetrate into the capacitor 19, making it impossible to set a desired voltage value (current value) on the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set on the capacitor 19. For example, even if 10 times larger current value is meant to be set, only approximately 5 times larger current value is set on the capacitor 19. For example, even if N=10 is specified, N=5 times larger current actually flows through the EL element 15. Thus, this method sets an N times larger current value to pass a current proportional or corresponding to the N-fold value through the EL element 15. Alternatively, this drive method applies a current larger than a desired value to the EL element 15 in a pulsed manner.

[0700] This method performs current (voltage) programming so as to obtain desired emission brightness of the EL element by passing a current larger than a desired value intermittently through the driver transistor 11a (in the case of FIG. 1) (i.e., a current which will give brightness higher than the desired brightness if passed through the EL element 15 continuously).

[0701] Preferably, N-channel transistors are used as the switching transistors 11b and 11c, etc. in FIG. 1 and the like. This will reduce penetration voltage reaching the capacitor 19. Also, since off-leakage of the capacitor 19 is reduced, this method can be applied to a 10-Hz or lower frame rate.

[0702] Depending on pixel configuration, if the penetration voltage tends to increase the current flowing through the EL element 15, white peak voltage will increase, increasing perceived contrast in image display. This provides for a good image display.

[0703] Conversely, it is also useful to use P-channel transistors as the switching transistors 11b and 11c in FIG. 1 to cause penetration, and thereby obtain a proper black display. When the P-channel transistor 11b turns off, the voltage goes high (Vgh), shifting the terminal voltage of the capacitor 19 slightly to the Vdd side. Consequently, the voltage at the gate (G) terminal of the transistor 11a rises, resulting in more intense black display. Also, the current used for first gradation display can be increased (a certain base current can be delivered up until gradation 1), and thus shortages of write current can be eased during current programming.

[0704] Another drive method according to the present invention will be described below with reference to drawings. FIG. 125 is an explanatory diagram illustrating a display panel which performs sequential driving according to the present invention. A source driver circuit 14 outputs R, G, and B data to connection terminals 618 by switching among them. Thus, the source driver circuit 14 only needs 1/3 as many output terminals as in FIG. 48.

[0705] Signals outputted from the source driver circuit 14 to the connection terminals 681 are allocated to 18R, 18G, and 18B by an output switching circuit 1251. The output switching circuit 1251 is formed directly on an array board 71 by polysilicon technology or amorphous silicon technology. Alternatively, it may be formed with silicon chips and mounted on the array board 71 by COG, TAB, or COF technology. Also, the output switching circuit 1251 may be incorporated into the source driver circuit 14 as a sub-circuit of the source driver circuit 14.

[0706] If a changeover switch 1252 is connected to an R terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18R. If the changeover switch 1252 is connected to a G terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18G. If the changeover switch 1252 is connected to a B terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18B.

[0707] Incidentally, in the configuration in FIG. 126, when the changeover switch 1252 is connected to the R terminal, the G terminal and B terminal of the changeover switch are open. Thus, the current entering the source signal lines 18G and 18B is 0 A. Consequently, the pixels 16 connected to the source signal lines 18G and 18B provide a black display.

[0708] When the changeover switch 1252 is connected to the G terminal, the R terminal and B terminal of the change over switch are open. Thus, the current entering the source signal lines 18R and 18B is 0 A. Consequently, the pixels 16 connected to the source signal lines 18R and 18B provide a black display.

[0709] In the configuration in FIG. 126, when the changeover switch 1252 is connected to the B terminal, the R terminal and G terminal of the changeover switch are open. Thus, the current entering the source signal lines 18R and 18G is 0 A. Consequently, the pixels 16 connected to the source signal lines 18R and 18G provide a black display.

[0710] Basically, if one frame consists of three fields, R image data is written in sequence into the pixels 16 in the screen 50 in the first field. In the second field, G image data is written in sequence into the pixels 16 in the screen 50. In the third field, B image data is written in sequence into the pixels 16 in the screen 50.

[0711] Thus, R data→G data→B data→R data→G data→B data→R data→ . . . are rewritten in sequence in the appropriate fields to implement sequential driving. Description of how N-fold pulse driving is performed by turning on and off the switching transistor 11d as shown in FIG. 1 has been given with reference to FIGS. 5, 13, 16, etc. Needless to say, such a drive method can be combined with sequential driving. Of course, it goes without saying that other drive methods according to the present invention can be combined with sequential driving.

[0712] In the above example, it has been stated that when image data is written into the R pixel 16, black data is written into the G pixel and B pixel, that when image data is written into the G pixel 16, black data is written into the R pixel and B pixel, and that when image data is written into the B pixel 16, black data is written into the R pixel and G pixel. The present invention is not limited to this.

[0713] For example, when image data is written into the R pixel 16, the G pixel and B pixel may retain the image data rewritten in the previous field. This can make the screen 50 brighter. When image data is written into the G pixel 16, the R pixel and B pixel may retain the image data rewritten in the previous field. When image data is written into the B pixel 16, the G pixel and R pixel may retain the image data rewritten in the previous field.

[0714] In order to retain image data in pixels other than the color pixel being rewritten, the gate signal line 17a can be controlled separately for the R, G, and B pixels. For example, as illustrated in FIG. 125, a gate signal line 17aR can be designated as a signal line which turns on and off the transistors 11b and 11c of the R pixel, a gate signal line 17aG can be designated as a signal line which turns on and off the transistors 11b and 11c of the G pixel, and a gate signal line 17aB can be designated as a signal line which turns on and off the transistors 11b and 11c of the B pixel. On the other hand, the gate signal line 17b can be designated as a signal line which commonly turns on and off the transistors 11d of the R, G, and B pixels.

[0715] With the above configuration, when the source driver circuit 14 outputs R image data and the changeover switch 1252 is set to an R contact, a turn-on voltage can be applied to the gate signal line 17aR and a turn-off voltage can be applied to the gate signal lines aG and aB. Thus, the R image data can be written into the R pixel 16 and the G pixel 16 and R pixel 16 can retain the image data of the previous field.

[0716] When the source driver circuit 14 outputs G image data in the second field and the changeover switch 1252 is set to a G contact, a turn-on voltage can be applied to the gate signal line 17aG and a turn-off voltage can be applied to the gate signal lines aR and aB. Thus, the G image data can be written into the G pixel 16 and the R pixel 16 and B pixel 16 can retain the image data of the previous field.

[0717] When the source driver circuit 14 outputs B image data in the third field and the changeover switch 1252 is set to a B contact, a turn-on voltage can be applied to the gate signal line 17aB and a turn-off voltage can be applied to the gate signal line aR and aG. Thus, the B image data can be written into the B pixel 16 and the R pixel 16 and G pixel 16 can retain the image data of the previous field.

[0718] In the example shown in FIG. 125, the gate signal lines 17a are placed (formed) in such a way as to turns on and off the transistors 11b of the R, G, and B pixels 16 separately. However, the present invention is not limited to this. For example, a gate signal line 17a common to the R, G, and B pixels 16 may be formed of placed as illustrated in FIG. 126.

[0719] In relation to the configuration in FIG. 125 and the like, it has been stated that when the R source signal line is selected by the changeover switch 1252, the G and B source signal lines are open. However, the open state is an electrically floating state and is not desirable.

[0720] FIG. 126 shows a configuration in which measures are taken to eliminate such floating state. A terminal a of a changeover switch 1252 of an output switching circuit 1251 is connected to a Vaa voltage (voltage for black display) A terminal b is connected to an output terminal of the source driver circuit 14. The changeover switch 1252 is installed for each of the R, G, and B pixels.

[0721] In the state shown in FIG. 126, a changeover switch 1252R is connected to a Vaa terminal. Thus, the Vaa voltage (voltage for black display) is applied to the source signal line 18R. A changeover switch 1252G is connected to a Vaa terminal. Thus, the Vaa voltage (voltage for black display) is applied to the source signal line 18G. A changeover switch 1252B is connected to the output terminal of the source driver circuit 14. Thus, a B image signal is applied to the source signal line 18B.

[0722] In the above state, the B pixel is being rewritten and a black display voltage is applied to the R pixel and G pixel. As the changeover switches 1252 are controlled in the above manner, an image composed of the pixels 16 are rewritten. Incidentally, control of the gate signal lines 17b is the same as in the examples described above, and thus detailed description thereof will be omitted.

[0723] In the above example, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel rewritten changes every field. The present invention is not limited to this. The color of the pixel rewritten may be changed every horizontal scanning period (1 H). For example, a possible drive method involves rewriting the R pixel in the first H, the G pixel in the second H, the B pixel in the third H, the R pixel in the fourth H, and so on. Of course, the color of the pixel rewritten may be changed every two horizontal scanning periods or every 1/3 field.

[0724] FIG. 127 shows an example, in which the color of the pixel rewritten changes every 1 H. Incidentally, in FIGS. 127 to 129, the oblique hatching indicates that the pixels 16 either retain image data from the previous field instead of being rewritten or are displayed in black. Of course, the black display of the pixels and retention of image data from the previous field may be repeated alternately.

[0725] Needless to say, in the drive system in FIGS. 125 to 129, it is also possible to use the N-fold pulse driving in FIG. 13 or simultaneous M-row driving. FIGS. 125 to 129 show writing of pixels 16. Although illumination control of the EL elements 15 is not described, it goes without saying that this example can be used in combination with examples described earlier or later. Of course, this drive method can be combined with the configuration which involves formation of the dummy pixel rows 271 described with reference to FIG. 27 and a drive method which uses the dummy pixel rows.

[0726] One frame need not necessarily consist of three fields and may consist of two fields or four or more fields. In one example illustrated herein, one frame consists of two fields and the R and G pixels out of the three primary RGB colors are rewritten in the first field and the B pixel is rewritten in the second field. In another example illustrated herein, one frame consists of four fields and the R pixel out of the three primary RGB colors is rewritten in the first field, the G pixel is rewritten in the second field, and the B pixel is rewritten in the third and fourth field. In these sequences, white balance can be achieved more efficiently if the luminous efficiencies of the R, G, and B EL elements 15 are taken into consideration.

[0727] In the above example, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel rewritten changes every field.

[0728] According to the example shown in FIG. 127, in the first field, an R pixel is rewritten in the first H, a G pixel is rewritten in the second H, a B pixel is rewritten in the third H, an R pixel is rewritten in the fourth H, and so on. Of course, the color of the pixel rewritten may be changed every two or more horizontal scanning periods or every 1/3 field.

[0729] According to the example shown in FIG. 127, in the first field, an R pixel is rewritten in the first H, a G pixel is rewritten in the second H, a B pixel is rewritten in the third H, and an R pixel is rewritten in the fourth H. In the second field, a G pixel is rewritten in the first H, a B pixel is rewritten in the second H, an R pixel is rewritten in the third H, and a G pixel is rewritten in the fourth H. In the third field, a B pixel is rewritten in the first H, an R pixel is rewritten in the second H, a G pixel is rewritten in the third H, and a B pixel is rewritten in the fourth H.

[0730] Thus, by rewriting the R, G, and B pixels in each field arbitrarily or with some regularity, it is possible to prevent separation among the R, G, and B colors. Also, flickering is reduced.

[0731] In FIG. 128, a plurality of pixel 16 colors are rewritten every 1 H. In FIG. 127, in the first field, the pixel 16 rewritten in the first H is an R pixel, the pixel 16 rewritten in the second H is a G pixel, the pixel 16 rewritten in the third H is a B pixel, the pixel 16 rewritten in the fourth H is an R pixel.

[0732] In FIG. 128, positions of the different-colored pixels rewritten are changed every 1 H. By assigning R, G, and B pixels to different fields (needless to say, this may be done with some regularity) and rewriting them in sequence, it is possible to prevent separation among the R, G, and B colors as well as to reduce flickering.

[0733] Incidentally, even in the example in FIG. 128, the R, G, and B pixels should have the same illumination time or luminous intensity in each picture element, which is a set of R, G, and B pixels. Needless to say, this is also done in the examples in FIGS. 126, 127, and the like to avoid color irregularities.

[0734] As shown in FIG. 128, in order to rewrite pixels of different colors in each H (three colors—R, G, and B—are rewritten in the first H in the first field in FIG. 128), in FIG. 125, the source driver circuit 14 can be configured to output image signals of arbitrary colors (or colors determined with some regularity) to the terminals and the changeover switches 1252 can be configured to connect to the R, G, and B contacts arbitrarily (or with some regularity) The panel in an example in FIG. 129 has W (white) pixels 16W in addition to the three primary colors RGB. By forming or placing pixels 16W, it is possible to achieve peak brightness of colors properly as well as to achieve a high brightness-display. FIG. 129(a) shows an example in which R, G, B, and W pixels 16 are formed in each pixel row. FIG. 129(b) shows an example in which R, G, B, and W pixels are placed in turns in different pixel rows.

[0735] Needless to say, the drive method in FIG. 129 can incorporate the drive methods in FIGS. 127, 128, etc. Also, it goes without saying that N-fold pulse driving, simultaneous M-row driving, etc. can be incorporated. These matters can easily be implemented by those skilled in the art based on this specification, and thus description thereof will be omitted.

[0736] Incidentally, for ease of explanation, it is assumed that the display panel according to the present invention has the three primary colors RGB, but this is not restrictive. The display panel may have cyan, yellow, and magenta in addition to R, G, and B, or it may have any one of R, G, and B or any two of R, G, and B.

[0737] Also, although it has been stated that the sequential driving system handles R, G, and Bin each field, it goes without saying that the present invention is not limited to this. Besides, the examples in FIGS. 125 to 129 illustrate how image data is written into pixels 16. They do not illustrate (although, of course, they are related to) a method of displaying images by operating the transistors 11d and passing current through the EL elements 15 unlike in FIG. 1. In the configuration shown in FIG. 1, current is passed through the EL elements 15 by controlling the transistors 11d.

[0738] Also, the drive methods in FIGS. 127, 128, etc. can display RGB images in sequence by controlling the transistors 11d (in the case of FIG. 1). For example, in FIG. 130(a) an R display area 53R, G display area 53G, and B display area 53B are scanned from top to bottom (or from bottom to top) of the screen during one frame (one field) period. The remaining area becomes a non-display area 52. That is, intermittent driving is performed.

[0739] FIG. 130(b) shows an example in which a plurality of RGB display areas 53 are generated during one field (one frame) period. This drive method is analogous to the one shown in FIG. 16. Thus, it will require no explanation. In FIG. 130(b), by dividing the display area 53, it is possible to eliminate flickering even at a lower frame rate.

[0740] FIG. 131(a) shows a case in which R, G, and B display areas 53 have different sizes (needless to say, the size of a display area 53 is proportional to its illumination period). In FIG. 131(a), the R display area 53R and G display area 53G have the same size. The B display area 53B has a larger size than the G display area 53G. In an organic EL display panel, B often has a low light emission efficiency. By making the B display area 53B larger than the display areas 53 of other colors as shown in FIG. 131(a), it is possible to achieve a white balance efficiently.

[0741] FIG. 131(b) shows an example in which there are a plurality of B display periods 53B (53B1 and 53B2) during one field (one frame) period. Whereas FIG. 131(a) shows a method of varying the size of one B display area 53B to allow the white balance to be adjusted properly, FIG. 131(b) shows a method of displaying multiple B display areas 53B having the same surface area to achieve a proper white balance.

[0742] The drive system according to the present invention is not limited to either FIG. 131(a) or FIG. 131(b). It is intended to generate R, G, and B display areas 53 and create an intermittent display, and thereby correct blurred moving pictures and insufficient writing into the pixels 16. With the drive method in FIG. 16, independent display areas 53 for R, G, and B are not generated. R, G, and B are displayed simultaneously (it should be stated that a W display area 53 is presented). Incidentally, it goes without saying that FIG. 131(a) and FIG. 131(b) may be combined. For example, it is possible to combine the drive method of using display areas 53 of different sizes for R, G, and B in FIG. 131(a) with the drive method of generating multiple display areas 53 for R, G, or B in FIG. 131(b).

[0743] Incidentally, the drive method in FIGS. 130 and 131 is not limited to the drive methods in FIGS. 125 to 129 according to the present invention. Needless to say, with a configuration in which the currents flowing through the EL elements 15 (EL elements 15R, EL elements 15G, and EL elements 15B) are controlled separately for R, G, and B as shown in FIG. 41, the drive method in FIGS. 130 and 131 can be implemented easily. By applying turn-on/turn-off voltages to the gate signal line 17bR, it is possible to turn on and off the R pixel 16R. By applying turn-on/turn-off voltages to the gate signal line 17bG, it is possible to turn on and off the G pixel 16G. By applying turn-on/turn-off voltages to the gate signal line 17bB, it is possible to turn on and off the B pixel 16B.

[0744] The above driving can be implemented by forming or placing a gate driver circuit 12bR which controls the gate signal line 17bR, a gate driver circuit 12bG which controls the gate signal line 17bG, and a gate driver circuit 12bB which controls the gate signal line 17bB, as illustrated in FIG. 132. By driving the gate driver circuits 12bR, 12bG, and 12bB in FIG. 132 by the method described in FIG. 6 or the like, the drive method in FIGS. 130 and 131 can be implemented. Of course, it goes without saying that the drive methods in FIG. 16 and the like can be implemented using the configuration of the display panel in FIG. 132.

[0745] Also, with the configuration shown in FIGS. 125 to 128, the drive method in FIGS. 130 and 131 can be implemented using a gate signal line 17b common to the R, G, and B pixels without using a gate signal line 17bR which controls the EL elements 15R, a gate signal line 17bG which controls the EL elements 15G, and a gate signal line 17bB which controls the EL elements 15B as long as black image data can be written into pixels 16 other than the pixels 16 whose image data is rewritten.

[0746] It has been stated with reference to FIGS. 15, 18, 21, etc. that the gate signal line 17b (EL-side selection signal line) applies a turn-on voltage (Vgl) and turn-off voltage (Vgh) every horizontal scanning period (1 H). However, in the case of a constant current, light emission quantity of the EL elements 15 is proportional to the duration of the current. Thus the duration is not limited to 1 H.

[0747] To introduce a concept of output enable (OEV), the following provisions are made. By performing OEV control, turn-on and turn-off voltages (Vgl voltage and Vgh voltage) can be applied to the pixels 16 from the gate signal line 17a and 17b within one horizontal scanning period (1 H).

[0748] For ease of explanation, it is assumed that in the display panel according to the present invention, the pixel rows to be programmed with current are selected by the gate signal line 17a (in the case of FIG. 1). The output from the gate driver circuit 12a which controls the gate signal line 17a is referred to as a WR-side selection signal line. Also, it is assumed that EL elements 15 are selected by the gate signal line 17b (in the case of FIG. 1). The output from the gate driver circuit 12b which controls the gate signal line 17b is referred to as an EL-side selection signal line.

[0749] The gate driver circuits 12 are fed a start pulse, which is shifted as holding data in sequence within a shift register. Based on the holding data in the shift register of the gate driver circuit 12a, it is determined whether to output a turn-on voltage (Vgl) or turn-off voltage (Vgh) to the WR-side selection signal line. An OEV1 circuit (not shown) which turns off output forcibly is formed or placed in an output stage of the gate driver circuit 12a. When the OEV1 circuit is low, a WR-side selection signal which is an output of the gate driver circuit 12a is output as it is to the gate signal line 17a. The above relationship is illustrated logically in FIG. 224(a) (OR circuit). Incidentally, the turn-on voltage is set at logic level L (0) and the turn-off voltage is set at logic voltage H (1).

[0750] That is, when the gate driver circuit 12a outputs a turn-off voltage, the turn-off voltage is applied to the gate signal line 17a. When the gate driver circuit 12a outputs a turn-on voltage (logic low), it is ORed with the output of the OEV1 circuit by the OR circuit and the result is output to the gate signal line 17a. That is, when the OEV1 circuit is high, the turn-off voltage (Vgh) is output to the gate driver signal line 17a (see an exemplary timing chart in FIG. 176).

[0751] Based on holding data in a shift register of the gate driver circuit 12b, it is determined whether to output a turn-on voltage (Vgl) or turn-off voltage (Vgh) to the gate signal line 17b (EL-side selection signal line). An OEV2 circuit (not shown) which turns off output forcibly is formed or placed in an output stage of the gate driver circuit 12b. When the OEV2 circuit is low, an output of the gate driver circuit 12b is output as it is to the gate signal line 17b. The above relationship is illustrated logically in FIG. 176(a). Incidentally, the turn-on voltage is set at logic level L (0) and the turn-off voltage is set at logic voltage H (1).

[0752] That is, when the gate driver circuit 12b outputs a turn-off voltage (an EL-side selection signal is a turn-off voltage), the turn-off voltage is applied to the gate signal line 17b. When the gate driver circuit 12b outputs a turn-on voltage (logic low), it is ORed with the output of the OEV2 circuit by the OR circuit and the result is output to the gate signal line 17b. That is, when an input signal is high, the OEV2 circuit outputs the turn-off voltage (Vgh) to the gate driver signal line 17b. Thus, even if the EL-side selection signal from the OEV2 circuit is a turn-on voltage, the turn-off voltage (Vgh) is output forcibly to the gate signal line 17b. Incidentally, if an input to the OEV2 circuit is low, the EL-side selection signal is output directly to the gate signal line 17b (see the exemplary timing chart in FIG. 176).

[0753] Incidentally, screen brightness is adjusted under the control of OEV2. There are permissible limits to changes in screen brightness. FIG. 175 illustrates relationship between permissible changes (%) and screen brightness (nt) As can be seen from FIG. 175, relatively dark images have small permissible changes. Thus, in performing brightness adjustments of the screen 50 under the control of OEV2 or through duty cycle control, the brightness of the screen 50 should be taken into consideration. Permissible changes should be shorter when the screen is dark than when it is bright.

[0754] FIG. 140 shows 1/4-duty ratio driving. A turn-on voltage is applied to the gate signal line 17b (EL-side selection signal line) every 4 Hs and the locations to which the turn-on voltage is applied are scanned in sync with a horizontal synchronization signal (HD). Thus, the unit length of a conduction period is 1 H.

[0755] However, the present invention is not limited to this. The duration of the conduction period may be less than 1 H (1/2 H in FIG. 143) as shown in FIG. 143 or it may be equal to or less than 1 H. In short, the unit length of the conduction period is not limited to 1 H and a unit length other than 1 H can be generated easily using the OEV2 circuit formed or placed in the output stage of the gate driver circuit 12b (circuit which controls the gate signal line 17b). The OEV2 circuit is similar to the OEV1 circuit described earlier, and thus description thereof will be omitted.

[0756] In FIG. 141, the conduction period of the gate signal line 17b (EL-side selection signal line) does not have a unit length of 1 H. A turn-on voltage little shorter than 1 H is applied to the gate signal lines 17b (EL-side selection signal lines) in odd-numbered pixel rows. A turn-on voltage is applied to the gate signal lines 17b (EL-side selection signal lines) in even-numbered pixel rows for a very short period. The duration T1 of the turn-on voltage applied to the gate signal lines 17b (EL-side selection signal lines) in odd-numbered pixel rows plus the duration T2 of the turn-on voltage applied to the gate signal lines 17b (EL-side selection signal lines) in even-numbered pixel rows is designed to be 1 H. FIG. 141 shows a state of the first field.

[0757] In the second field which follows the first field, a turn-on voltage little shorter than 1 H is applied to the gate signal lines 17b (EL-side selection signal lines) in even-numbered pixel rows. A turn-on voltage is applied to the gate signal lines 17b (EL-side selection signal lines) in odd-numbered pixel rows for a very short period. The duration T1 of the turn-on voltage applied to the gate signal lines 17b (EL-side selection signal lines) in even-numbered pixel rows plus the duration T2 of the turn-on voltage applied to the gate signal lines 17b (EL-side selection signal lines) in odd-numbered pixel rows is designed to be 1 H.

[0758] The sum duration of turn-on voltage applications to gate signal lines 17b in a plurality of pixel rows may be designed to be constant. Alternatively, the illumination time of each EL element 15 in each pixel row in each field may be designed to be constant.

[0759] FIG. 142 shows a case in which the conduction period of the gate signal line 17b (EL-side selection signal line) is 1.5 Hs. The rise and fall of the gate signal line 17b at point A are designed to overlap. The gate signal line 17b (EL-side selection signal line) and source signal line 18 are coupled. Thus, any change in a waveform of the gate signal line 17b (EL-side selection signal line) penetrates to the source signal line 18. Consequently, any potential fluctuation in the source signal line 18 lowers accuracy of current (voltage) programming, causing irregularities in the characteristics of the driver transistors 11a to appear in the display.

[0760] Referring to FIG. 142, at point A, the voltage applied to the gate signal line 17B (EL-side selection signal line) (1) changes from turn-on voltage (Vgl) to turn-off voltage (Vgh). The voltage applied to the gate signal line 17B (EL-side selection signal line) (2) changes from turn-off voltage (Vgh) to turn-on voltage (Vgl). Thus, at point A, the signal waveform of the gate signal line 17B (EL-side selection signal line) (1) and the signal waveform of the gate signal line 17B (EL-side selection signal line) (2) cancel out each other. Consequently, even if the gate signal line 17B (EL-side selection signal line) and source signal line 18 are coupled, changes in the waveform of the gate signal line 17b (EL-side selection signal line) do not penetrate to the source signal line 18. This improves the accuracy of current (voltage) programming, resulting in a uniform image display.

[0761] Incidentally, in the example in FIG. 142, the conduction period is 1.5 Hs. However, the present invention is not limited to this. Needless to say, the duration of application of the turn-on voltage may be 1 H or less as illustrated in FIG. 144.

[0762] By adjusting the duration of application of the turn-on voltage to the gate signal line 17B (EL-side selection signal line), it is possible to adjust the brightness of the display screen 50 linearly. This can be done easily through control of the OEV2 circuit. Referring to FIG. 145, for example, display brightness in FIG. 145(b) is lower than in FIG. 145(a). Also, display brightness in FIG. 145(c) is lower than in FIG. 145(b).

[0763] FIG. 109 illustrates relationship between OEV2 and the signal waveform of the gate signal line 17b. In FIG. 109, the period during which OEV2 is low is the shortest in FIG. 109(a). Consequently, the turn-on voltage is applied to the gate signal line 17b for a short period of time, meaning that current flows through the EL element 15 for a short period of time. This results in a small duty ratio. In FIG. 109(b), the period during which OEV2 is low is longer. In FIG. 109(c) the period during which OEV2 is low is longer than in FIG. 109(b). Thus, the duty ratio in FIG. 109(c) is larger than in FIG. 109(b).

[0764] Incidentally, in the examples in FIGS. 109(a), 109(b) and 109(c), duty cycle control is performed in a period shorter than 1 H. However, the present invention is not limited to this. The unit duration of duty cycle control may be 1 H as shown in FIG. 109(d). FIG. 109(d) shows an example in which the duty ratio is 1/2.

[0765] The period during which OEV2 is low is the shortest in FIG. 109(a). Consequently, the turn-on voltage is applied to the gate signal line 17b for a short period of time, meaning that current flows through the EL element 15 for a short period of time. This results in a small duty ratio.

[0766] The period during which OEV2 is low is the shortest in FIG. 109(a). Consequently, the turn-on voltage is applied to the gate signal line 17b for a short period of time, meaning that current flows through the EL element 15 for a short period of time. This results in a small duty ratio.

[0767] As shown in FIG. 146, multiple sets of turn-on voltage and turn-off voltage may be applied in a period of 1 H. FIG. 146(a) shows an example in which six sets are applied. FIG. 146(b) shows an example in which three sets are applied. FIG. 146(c) shows an example in which one set is applied. In FIG. 146, display brightness is lower in FIG. 146(b) than in FIG. 146(a). It is lower in FIG. 146(c) than in FIG. 146(b). Thus, by controlling the number of conduction periods, display brightness can be adjusted (controlled) easily.

[0768] The current-driven source driver IC (circuit) 14 according to the present invention will be described below. The source driver IC according to the present invention is used to implement the drive methods and drive circuits according to the present invention described earlier. It is used in combination with drive methods, drive circuits, and display apparatus according to the present invention. Incidentally, although the source driver circuit will be described as an IC chip, this is not restrictive and the source driver circuit may be built on the array board 71 of the display panel using low-temperature polysilicon technology, amorphous silicon technology, or the like.

[0769] First, an example of a conventional current-driven source driver circuit is shown in FIG. 55, which provides a principle needed to describe current-driven source driver IC (source driver circuit) 14 according to the present invention.

[0770] In FIG. 55, reference numeral 551 denotes a D/A converter. The D/A converter 551 is fed an n-bit data signal and outputs an analog signal based on the inputted data. The analog signal enters an operational amplifier 552, which feeds into an N-channel transistor 471a. Current flowing through the N-channel transistor 471a flows to a resister 531. A terminal voltage of the register R provides a negative input to the operational amplifier 552. The voltage at the negative terminal equals the voltage at the positive terminal of the operational amplifier 552. Thus, the output voltage of the D/A converter 551 equals the terminal voltage of the resister 531.

[0771] If the resistance of the resister 531 is 1 MΩ and the output of the D/A converter 551 is 1 (V), a current of 1 (V)/1 MΩ=1 (μA) flows through the resister 531, forming a constant current circuit. Thus, analog output of the D/A converter 551 varies with the value of data signal, and a predetermined current flows through the resister 531 according to the analog output to provide a programming current Iw.

[0772] However, the D/A converter circuit 551 has a large circuit scale. So does the operational amplifier 552. Formation of the D/A converter circuit 551 and operational amplifier 552 in a single output circuit results in a huge source driver IC 14, which is practically impossible to build.

[0773] The present invention has been made in view of the above point. The source driver circuit 14 according to the present invention has a circuit configuration and layout configuration which reduces the scale of a current output circuit and minimizes variations in output current among current output terminals.

[0774] FIG. 47 is a block diagram showing a current-driven source driver IC (circuit) 14 according to one example of the present invention. FIG. 47 shows a multi-stage current mirror circuit comprising three-stage current sources (471, 472, 473).

[0775] In FIG. 47, the current value of the current source 471 in the first stage is copied by the current mirror circuit to N current sources 472 in the second stage (where N is an arbitrary integer). The current values of the second-stage current sources 472 are copied by the current mirror circuit to M current sources 473 in the third stage (where M is an arbitrary integer). Consequently, this configuration causes the current value of the first-stage current source 471 to be copied to N×M third-stage current sources 473.

[0776] For example, when driving the source signal lines 18 with one source driver IC 14, there are 176 outputs (because the source signal lines require a total of 176 outputs for R, G, and B). Here it is assumed that N=16 and M=11. Thus, 16×11=176 and the 176 outputs can be covered. In this way, by using a multiple of 8 or 16 for N or M, it becomes easier to lay out and design the current sources of the driver IC.

[0777] The current-driven source driver IC (circuit) 14 employing the multi-stage current mirror circuit according to the present invention can absorb variations in transistor characteristics because it has the second-stage current sources 472 in between instead of copying the current value of the first-stage current source 471 directly to N×M third-stage current sources 473 using the current mirror circuit.

[0778] In particular, the present invention is characterized in that a first-stage current mirror circuit (current source 471) and second-stage current mirror circuits (current sources 472) are placed close to each other. If a first-stage current source 471 are connected with third-stage current sources 473 (i.e., in the case of two-stage current mirror circuit), the second-stage current sources 473 connected to the first-stage current source are large in number, making it impossible to place the first-stage current source 471 and third-stage current sources 473 close to each other.

[0779] The source driver circuit 14 according to the present invention copies the current value of the first-stage current mirror circuit (current source 471) to the second-stage current mirror circuits (current sources 472), and the current values of the second-stage current mirror circuits (current sources 472) to the third-stage current mirror circuits (current sources 473). With this configuration, the second-stage current mirror circuits (current sources 472) connected to the first-stage current mirror circuit (current source 471) are small in number. Thus, the first-stage current mirror circuit (current source 471) and second-stage current mirror circuits (current sources 472) can be placed close to each other.

[0780] If transistors composing the current mirror circuits can be placed close to each other, naturally variations in the transistors are reduced, and so are variations in current values. The number of the third-stage current mirror circuits (current sources 473) connected to the second-stage current mirror circuits (current sources 472) are reduced as well. Consequently, the second-stage current mirror circuits (current sources 472) and third-stage current mirror circuits (current sources 473) can be placed close to each other.

[0781] That is, transistors in current receiving parts of the first-stage current mirror circuit (current source 471), second-stage current mirror circuits (current sources 472) and third-stage current mirror circuits (current sources 473) can be placed close to each other on the whole. In this way, transistors composing the current mirror circuits can be placed close to each other, reducing variations in the transistors and greatly reducing variations in current signals from output terminals.

[0782] In the present invention, the terms “current sources 471, 472, and 473” and “current mirror circuits” are used interchangeably. That is, current sources are a basic construct of the present invention and the current sources are embodied into current mirror circuits. Thus, a current source is not limited to a current mirror circuit and may be a constant current circuit consisting of a combination of a operational amplifier 552, transistor 471, and register R.

[0783] FIG. 48 is a structural drawing of a more concrete source driver IC (circuit) 14. It illustrates part of third current sources 473. This is an output part connected to one source signal line 18. It is composed of multiple current mirror circuits (unit transistors 484 (1 unit)) of the same size as a current mirror configuration in the final stage. Their number is bit-weighted according to the data size of image data.

[0784] Incidentally, the transistors composing the source driver IC (circuit) 14 according to the present invention are not limited to a MOS type and may be a bipolar type. Also, they are not limited to silicon semiconductors and may be gallium arsenide semiconductors. Also, they may be germanium semiconductors. Alternatively, they may be formed directly on a substrate-using low-temperature polysilicon technology, other polysilicon technology, or amorphous silicon technology.

[0785] FIG. 48 illustrates an example of the present invention which handles 6-bit digital input. Six bits are the sixth power of two, and thus provide a 64-gradation display. This source driver IC 14, when mounted on an array board, provides 64 gradations each of red (R), green (G), and blue (B), meaning 64×64×64=approximately 260,000 colors.

[0786] Sixty-four (64) gradations require 1 D0-bit unit transistor 484, two D1-bit unit transistors 484, four D2-bit unit transistors 484, eight D3-bit unit transistors 484, sixteen D4-bit unit transistors 484, and thirty-two D5-bit unit transistors 484 for a total of 63 unit transistors 484. Thus, the present invention produces one output using as many unit transistors 484 as the number of gradations (64 gradations in this example) minus 1. Incidentally, even if one unit transistor is divided into a plurality of sub-unit transistors, this simply means that a unit transistor is divided into sub-unit transistors, and makes no difference in the fact that the present invention uses as many unit transistors as the number of gradations minus 1.

[0787] In FIG. 48, D0 represents LSB input and D5 represents MSB input. When a D0 input terminal is high (positive logic) a switch 481a is closed (the switch 481a is an on/off means and may be constructed of a single transistor or may be an analog switch consisting of a P-channel transistor and N-channel transistor. Then, current flows to a current source (single-unit) 484 composing a current mirror. The current flows through internal wiring 483 in the IC 14. Since the internal wiring 483 is connected to the source signal line 18 via a terminal electrode of the IC 14, the current flowing through internal wiring 483 provides a programming current for the pixels 16.

[0788] For example, when a D1 input terminal is high (positive logic), a switch 481b is closed. Then, current flows to two current sources (single-unit) 484 composing a current mirror. The current flows through the internal wiring 483 in the IC 14. Since the internal wiring 483 is connected to the source signal line 18 via a terminal electrode of the IC 14, the current flowing through internal wiring 483 provides a programming current for the pixels 16.

[0789] The same applies to the other switches 481. When a D2 input terminal is high (positive logic), a switch 481c is closed. Then, current flows to four current sources (single-unit) 484 composing a current mirror. When a D5 input terminal is high (positive logic), a switch 481f is closed. Then, current flows to 32 (thirty-two) current sources (single-unit) 484 composing a current mirror.

[0790] In this way, based on external data (D0 to D5), current flows to the corresponding current sources (single-unit). That is, current flows to 0 to 63 current sources (single-unit) depending on the data.

[0791] Incidentally, for ease of explanation, it is assumed that there are 63 current sources for a 6-bit configuration, but this is not restrictive. In the case of 8-bit configuration, 255 unit transistors 484 can be formed (placed). For a 4-bit configuration, 15 unit transistors 484 can be formed (placed). The transistors 484 constituting the unit current sources have a channel width W and channel width L. The use of equal transistors makes it possible to construct output stages with small variations.

[0792] Besides, not all the unit transistors 484 need to pass equal current. For example, individual unit transistors 484 may be weighted. For example a current output circuit may be constructed using a mixture of single-unit unit transistors 484, double-sized unit transistors 484, quadruple-sized unit transistors 484, etc. However, if unit transistors 484 are weighted, the weighted current sources may not provide the right proportions, resulting in variations. Thus, even when using weighting, it is preferable to construct each current source from transistors each of which corresponds to a single-unit current source.

[0793] The unit transistor 484 should be equal to or larger than a certain size. The smaller the transistor size, the larger the variations in output current. The size of a transistor 484 is given by the channel length L multiplied by the channel width W. For example, if W=3 μm and L=4 μm, the size of the unit transistor 484 constituting a unit current source is W×L=12 square μm. It is believed that crystal boundary conditions of silicon wafers have something to do with the fact that a smaller transistor size results in larger variations. Thus, variations in output current of transistors are small when each transistor is formed across a plurality of crystal boundaries.

[0794] Relationship between size of transistors and variations in output current is shown in FIG. 119. The horizontal axis of the graph in FIG. 119 represents transistor size (square μm). The vertical axis represents variations in output current in percentage terms. The variations (%) in output current here were determined using groups of 63 unit current sources (unit transistors) 484 formed on a wafer. Thus, although the horizontal axis of the graph represents the size of a transistor (size of a unit transistor 484) constituting one current source, since there are actually 63 transistors connected in parallel, the total area of the transistors is 63 times larger. However, FIG. 119 is based on the size of a unit transistor 484. Thus, FIG. 119 shows that variations in the output current of 63 unit transistors 484 with an area of 30 square μm each is 0.5%.

[0795] In the case of 64 gradations, 100/64=1.5%. Thus, the variations in the output current must be within 1.5%. From FIG. 119, it can been seen that in order for the variations to be within 1.5%, the size of the unit transistor must be equal to or larger than 2 square μm (in the case of 64 gradations, sixty-three 2-square μm unit transistors operate) On the other hand, there are limits to transistor size because larger transistors increase the size of an IC chip and there are limits to the width per one output. In this respect, the upper limit to the size of the unit transistor 484 is 300 square μm. Thus, in the case of 64 gradations, the size of the unit transistor 484 must be from 2 square μm to 300 square μm (both inclusive) In the case of 128 gradations, 100/128=1%. Thus, the variations in the output current must be within 1%. From FIG. 119, it can been seen that in order for the variations to be within 1%, the size of the unit transistor must be equal to or larger than 8 square μm. Thus, in the case of 128 gradations, the size of the unit transistor 484 must be from 8 square μm to 300 square μm (both inclusive).

[0796] Generally, if the number of gradations is K and the size of a unit transistor 484 is St (square μm), the following relationship should be satisfied:
40≦K/{square root}{square root over ( )}(St) and St≦300

[0797] More preferably, the following relationship should be satisfied:
120≦K/{square root}{square root over ( )}(St) and St≦300

[0798] In the above example 64 gradations are represented by 63 transistors. When representing 64 gradations by 127 unit transistors 484, the unit-transistor 484 size is the total size of two unit transistors 484. For example, in the case where 64 gradations are represented by 127 unit transistors 484, if the size of a unit transistor 484 is 10 square μm, the unit-transistor 484 size is given in FIG. 119 as 1×2=20. Similarly, in the case where 64 gradations are represented by 255 unit transistors 484, if the size of a unit transistor 484 is 10 square μm, the unit-transistor 484 size is given in FIG. 119 as 10×4=40.

[0799] It is necessary to take into consideration not only the size, but also the shape of the unit transistor 484. This is to reduce kink effect. A kink is a phenomenon in which current flowing through a unit transistor 484 changes when the voltage between the source (S) and drain (D) of the unit transistor 484 is varied with the gate voltage of the unit transistor 484 kept constant. In the absence of kink effect (in ideal state), the current flowing through the unit transistor 484 does not change even if the voltage applied between the source (S) and drain (D) of the unit transistor 484 is varied.

[0800] Kink effect occurs when the source signal lines 18 vary due to variations in Vt of driver transistors 11a shown in FIG. 1 and the like. The driver circuit 14 passes programming current through the source signal line 18 so that the programming current will flow through the driver transistor 11a of the pixel. The programming current causes changes in the gate terminal voltage of the driver transistor 11a, and consequently the programming current flows through the driver transistor 11a. As can be seen From FIG. 3, when a selected pixel 16 is in programming mode, the gate terminal voltage of the driver transistor 11a equals the potential of the source signal line 18.

[0801] Thus, the potentials of the source signal lines 18 vary due to variations in Vt of the driver transistors 11a in pixels 16. The potential of a source signal line 18 equals the source-drain voltage of the unit transistor 484 of the driver circuit 14. That is, variations in Vt of the driver transistors 11a in the pixels 16 cause the source-drain voltage applied to the unit transistors 484 to vary. Then, the source-drain voltage causes variations in the output voltage of the unit transistor 484 due to kinks.

[0802] FIG. 123 is a graph showing deviation (variation) in L/W of unit transistors from a target value. When the L/W ratio of unit transistors is equal to smaller than 2, the deviation from the target value is large (the slope of the straight line is large). However, as L/W increases, the deviation from the target value tends to decrease. When L/W of unit transistors is equal to larger than 2, the deviation from the target value is small. Also, the deviation from the target value is 0.5% or less when L/W=2 or more. Thus, this value can be used for source driver circuits 14 to indicate accuracy of transistors. Incidentally, L is the channel length of the unit transistor 484 and W is the channel width of the unit transistor 484.

[0803] However, it is not that the channel length L of the unit transistor 484 can be increased indefinitely. The larger the channel length L, the larger the IC chip 14. Also, a large channel length L leads to increased gate terminal voltage in the unit transistor 484, increasing the power supply voltage required for the source driver IC 14. Increased power supply voltage involves the use of a highly voltage resistant IC process. A source driver IC 14 produced by a voltage resistant IC process leads to large variations in the output of the unit transistor 484 (see FIG. 121 and its description). Results of analysis indicate that preferably L/W should be 100 or less. More preferably, it should be 50 or less.

[0804] In view of the above circumstances, it is preferable that L/W of a unit transistor is two or more. Also, preferably L/W is 100 or less. More preferably, L/W is 40 or less.

[0805] Besides, L/W also depends on the number of gradations. If the number of gradations is small, there is no problem even if there are variations in the output current of the unit transistor 484 due to kink effect because there are large differences between gradations. However, in the case of a display panel with a large number of gradations, since there are small differences between gradations, even small variations in the output current of the unit transistor 484 due to kink effect will decrease the number of gradations.

[0806] In view of the above circumstances, the driver circuit 14 according to the present invention is configured to satisfy the following relationship:
({square root}{square root over ( )}(K/16))≦L/W≦ and ({square root}{square root over ( )}(K/16))×20
where K is the number of gradations, L is the channel length of the unit transistor 484, and W is the channel width of the unit transistor. This relationship is illustrated in FIG. 120. The area above the straight line in FIG. 120 is relevant to the present invention.

[0807] The variations in the output current of the unit transistor 484 also depend on the voltage resistance of the source driver IC 14. The voltage resistance of the source driver IC generally means the power supply voltage of the IC. For example, voltage resistance of 5 V means the use of the power supply voltage at a standard voltage of 5 V. Incidentally, IC voltage resistance can translate into maximum working voltage. Semiconductor IC makers have standardized voltage-resistance processes such as a 5-V voltage-resistance process and 10-V voltage-resistance process.

[0808] It is believed that film properties and film thickness of a gate insulating film of the unit transistor 484 have something to do with the fact that IC voltage resistance affects variations in the output current of the unit transistor 484. The transistors produced in a process with high IC voltage resistance have a thick gate insulating film. This is intended to avoid dielectric breakdown even under application of a high voltage. A thick gate insulating film makes its control difficult and increases variations in its film properties. This increases variations in the transistors. Also, the transistors produced in a high voltage-resistance process have low mobility. With low mobility, even slight changes in electrons injected into transistor gates cause changes in characteristics. This increases variations in the transistors. To reduce variations in the unit transistors 484, it is preferable to adopt an IC process with low IC voltage resistance.

[0809] FIG. 121 illustrates relationship between IC voltage resistance and output variations of unit transistors 484. The variation rate on the vertical axis is based on the variation of unit transistors 484 produced in a 1.8-V voltage resistance process, which variation is taken to be 1. FIG. 121 shows output variations of unit transistors 484 which were produced in various IC voltage resistance processes and have a shape of L/W=12/6 (μm). A plurality of unit transistors 484 were produced in each IC voltage resistance process and variations in their output current were determined. The voltage resistance processes were composed discretely of 1.8-V voltage resistance, 2.5-V voltage resistance, 3.3-V voltage resistance, 5-V voltage resistance, 8-V voltage resistance, and 10-V voltage resistance, 15-V voltage resistance processes. However, for ease of explanation, variations in the transistors formed in the different voltage resistance processes are plotted on the graph and connected with straight lines.

[0810] As can be seen from FIG. 121, the variation rate (variations in the output current of the unit transistors 484) increases gradually up until an IC voltage resistance of 9 V. However, when the IC voltage resistance exceeds 10 V, the slope of the variation rate with respect to the IC voltage resistance becomes large.

[0811] In FIG. 121, the permissible limit to the variation rate is 3 for 64- to 256-gradation display. The variation rate varies with the area, L/W, etc. of the unit transistor 484. However, the variation rate with respect to the IC voltage resistance is hardly affected by the shape of the unit transistor 484. The variation rate tends to increase above an IC voltage resistance of 9 to 10 V.

[0812] On the other hand, the potential at an output terminal 681 in FIG. 48 varies with the programming current in the driver transistor 11a of the pixel 16. The gate terminal voltage of the driver transistor 11a is approximately equal to the potential of the source signal line 18. Also, the source signal line 18 and the output terminal 681 of the source driver IC (circuit) 14 are equal in potential. When the driver transistor 11a of the pixel 16 passes white raster (maximum white display) current, its gate terminal voltage is designated as Vw. When the driver transistor 11a of the pixel 16 passes black raster (completely black display) current, its gate terminal voltage is designated as Vb. The absolute value of Vw−Vb must be 2 V or larger. When the voltage Vw is applied to the output terminal 681, inter-channel voltage of the unit transistor 484 must be 0.5 V or higher.

[0813] Thus, a voltage of 0.5 V to ((Vw−Vb)+0.5) V is applied to the output terminal 681 (during current programming, the gate terminal voltage of the driver transistor 11a of the pixel 16 is applied to the output terminal 681, which is connected with the source signal line 18). Since Vw−Vb equals 2 V, a voltage of up to 2 V+0.5 V=2.5 V is applied to the output terminal 681. Thus, even if the output voltage (current) of the source driver IC 14 is based on a rail-to-rail circuit configuration (circuit configuration capable of outputting a voltage up to the IC power supply voltage), the IC voltage resistance must be 2.5V. The amplitude required by a terminal 741 is 2.5 V or more.

[0814] Thus, it is preferable to use a voltage resistance process in the range of 2.5-V to 10-V (both inclusive) for the source driver IC 14. More preferably, a voltage resistance process in the range of 3-V to 9-V (both inclusive) is used for the source driver IC 14.

[0815] Incidentally, it has been described that a voltage resistance process in the range of 2.5-V to 10-V (both inclusive) is used for the source driver IC 12. This voltage resistance is also applied to examples (e.g., a low-temperature polysilicon process) in which the source driver circuit 14 is formed directly on an array board 71. Working voltage resistance of a source driver circuit 14 formed directly on an array board 71 can be high and exceeds 15 V in some cases. In such cases, the power supply voltage used for the source driver circuit 14 may be substituted with the IC voltage resistance illustrated in FIG. 121. Also, the source driver IC 14 may have the IC voltage resistance substituted with the power supply voltage used.

[0816] The area of a unit transistor 484 is correlated with the variations in its output current. FIG. 122 is a graph obtained by varying the transistor width W of a unit transistor 484 with the area of the unit transistor 484 kept constant. In FIG. 121, the variation of the unit transistor 484 with a channel width W of 2 μm is taken as 1. The vertical axis of the graph represents a relative proportion, where the variation which occurs when the channel width W is 2 μm is taken as 1.

[0817] As can be seen from FIG. 122, the variation rate increases gradually when W of the unit transistor 484 is from 2 μm to 9 or 10 μm. The increase in the variation rate tends to become large when W is 10 μm or more. Also, the variation rate tends to increase when the channel width W=2 μm or less.

[0818] In FIG. 122, the permissible limit to the variation rate is 3 for 64- to 256-gradation display. The variation rate varies with the area of the unit transistor 484. However, the variation rate with respect to the IC voltage resistance is hardly affected by the area of the unit transistor 484.

[0819] Thus, preferably, the channel width W of the unit transistor 484 is from 2 μm to 10 μm (both inclusive). More preferably, the channel width W of the unit transistor 484 is from 2 μm to 9 μm (both inclusive). However, when the number of gradations is 64, a channel width W of 2 μm to 15 μm (both inclusive) is practically acceptable.

[0820] As illustrated in FIG. 52, current flowing through second-stage current mirror circuits 472b is copied to transistors 473a which compose third-stage current mirror circuits. If a current mirror ratio is 1, the current flows through transistors 473b. The current is copied to the unit transistor 484 in the final stage.

[0821] D0, which is provided by one unit transistor 484, provides the value of the current flowing through the unit transistor 473 of the final-stage current source. D1, which is provided by two unit transistors 484, provides a two times larger current value than the final-stage current source. D2, which is provided by four unit transistors 484, provides a four times larger current value than the final-stage current source; and D5, which is provided by 32 unit transistors 484, provides a 32 times larger current value than the final-stage current source. The above is based on the assumption that the mirror ratio of the final-stage current mirror circuits is 1.

[0822] Programming current Iw is output (drawn) to the source signal line via switches controlled by 6-bit image data consisting of D0, D1, D2, . . . , and D5. Thus, according to activation and deactivation of the 6-bit image data consisting of D0, D1, D2, . . . , and D5, currents 1 time, 2 times, 4 times, and/or 32 times as large as the final-stage current source 473 are added and outputted to the output line. That is, according to activation and deactivation of the 6-bit image data consisting of D0, D1, D2, . . . , and D5, 0 to 63 times as large a current as the final-stage current source 473 is output from the output line (the current is drawn from the source signal line 18.

[0823] Actually, as illustrated in FIGS. 76, 77, 78, and 118, in the source driver IC 14, reference currents (IaR, IaG, and IaB) for R, G, and B, respectively, can be adjusted by registers 491 (491R, 491G, and 491B). By adjusting the reference currents Ia, the white balance can be adjusted easily.

[0824] In order to achieve full-color display on an EL display panel, it is necessary to provide a reference current for each of R, G, and B. The white balance can be adjusted by controlling the ratios of the RGB reference currents. In the case of current driving as well as the present invention, the value of current passed by the unit transistor 484 is determined based on one reference current. Thus, the current passed by the unit transistor 484 can be determined by determining the magnitude of the reference current. Consequently, the white balance in every gradation can be achieved by setting a reference current for each of R, G, and B. The above matters work because the source driver circuit 14 produces current outputs varied in steps (is current-driven). Thus, the point is how the magnitude of the reference current can be set for each of R, G, and B.

[0825] The light emission efficiency of an EL element is determined by, or depends heavily on, the thickness of a film vapor-deposited or applied to the EL element. The film thickness is almost constant within each lot. Through lot control of the film thickness of the EL element 15, it is possible to determine relationship between the current passed through the EL element 15 and light emission efficiency. That is, the current value used for white balancing is fixed for each lot.

[0826] FIG. 49 is an exemplary circuit diagram showing 176 outputs (N×M=176) of a three-stage current mirror circuit. In FIG. 49, the current source 471 constituted of the first-stage current mirror circuit is referred to as a parent current source, the current sources 472 constituted of the second-stage current mirror circuits are referred to as child current sources, and the current sources 473 constituted of the third-stage current mirror circuits are referred to as grandchild current sources.

[0827] The use of an integral multiple for the third-stage current mirror circuits which are the final-stage current mirror circuits makes it possible to minimize variations in the 176 outputs and produce high-accuracy current outputs.

[0828] Incidentally, dense placement means placing the first current source 471 and the second current sources 472 (the current or voltage output and current or voltage input) at least within a distance of 8 mm. More preferably, they are placed within 5 mm. It has been shown analytically that when placed at this density, the current sources can fit into a silicon chip with little difference in transistor characteristics (Vt and mobility (μ)). Similarly, the second current sources 472 and third current sources 473 (the current output and current input) are placed at least within a distance of 8 mm. More preferably, they are placed within 5 mm. Needless to say, the above items also apply to other examples of the present invention.

[0829] The current or voltage output and current or voltage input mean the following relationships. In the case of voltage-based delivery shown in FIG. 50, the transistor 471 (the output) of the (I)-th current source and the transistor 472a (the input) of the (I+1)-th current source are placed close to each other. In the case of current-based delivery shown in FIG. 51, the transistor 471a (the output) of the (I)-th current source and the transistor 472b (the input) of the (I+1)-th current source are placed close to each other.

[0830] Incidentally, although it is assumed in FIGS. 49, 50, etc. that there is one transistor 471, this is not restrictive. For example, it is also possible to form a plurality of small sub-transistors 471 and connect the source or drain terminals of the sub-transistors with the register 491 to form a unit transistor 484. By connecting the plurality of small sub-transistors in parallel, it is possible to reduce variations of the unit transistor 484.

[0831] Similarly, although it is assumed that there is one transistor 472a, this is not restrictive. For example, it is also possible to form a plurality of small sub-transistors 472a and connect the gate terminals of the transistors 472a with the gate terminal of the transistor 471. By connecting the plurality of small transistors 472a in parallel, it is possible to reduce variations of the transistor 472a.

[0832] Thus, according to the present invention, the following configurations can be illustrated: a configuration in which one transistor 471 is connected with a plurality of transistors 472a, a configuration in which a plurality of transistors 471 are connected with one transistor 472a, and a configuration in which a plurality of transistors 471 are connected with a plurality of transistors 472a. These examples will be described in more detail below.

[0833] The above items also apply to a configuration of transistors 473a and 473b in FIG. 52 in FIG. 52. Possible configurations include a configuration in which one transistor 473a is connected with a plurality of transistors 473b, a configuration in which a plurality of transistors 473a are connected with one transistor 473b, and a configuration in which a plurality of transistors 473a are connected with a plurality of transistors 473b. By connecting the plurality of small transistors 473 in parallel, it is possible to reduce variations of the transistor 473.

[0834] The above items also apply to relationship between transistors 472a and 472b in FIG. 52. Also, preferably a plurality of transistors 473b are used in FIG. 48. Similarly, it is preferable to use plurality of transistors 473 in FIGS. 56 and 57.

[0835] Although it has been stated that the source driver IC 14 consists of a silicon chip, this is not restrictive. The source driver IC 14 may be constructed of another semiconductor chip formed on a gallium substrate or germanium substrate. Also, the unit transistor 484 may be a bipolar transistor, CMOS transistor, FET, Bi-CMOS transistor, or DMOS transistor. However, in terms of reducing variations in the output of the unit transistor 484, preferably a CMOS transistor is used for the unit transistor 484.

[0836] Preferably, the unit transistor 484 is an N-channel transistor. The unit transistor consisting of a P-channel transistor has 1.5 times larger output variations than the unit transistor consisting of an N-channel transistor.

[0837] Since it is preferable that the unit transistor 484 of the source driver IC 14 is an N-channel transistor, the programming current of the source driver IC 14 is a current drawn from the pixel 16. Thus, the driver transistor 11a of the pixel 16 is a P-channel transistor. The switching transistor 11d in FIG. 1 is also a P-channel transistor.

[0838] Thus, the configuration in which the unit transistor 484 in the output stage of the source driver IC (circuit) 14 is an N-channel transistor and the driver transistor 11a of the pixel 16 is a P-channel transistor is characteristic of the present invention. Incidentally, it is preferable that all the transistors (transistors 11a, 11b, 11c, and 11d) composing the pixel 16 are P-channel transistors. This eliminates the process of forming N-channel transistors, resulting in low costs and high yields.

[0839] Incidentally, although it has been stated that the unit transistor 484 is formed in the IC 14, this is not restrictive. The source driver circuit 14 may be formed by low-temperature polysilicon technology. In that case again, it is preferable that the unit transistors 484 in the source driver circuit 14 are N-channel transistors.

[0840] FIG. 51 shows an example of configuration for current-based delivery. FIG. 50 also shows an example of configuration for current-based delivery. FIGS. 50 and 51 are similar in terms of circuit diagrams and differ in layout configuration, i.e., wiring layout. In FIG. 50, reference numeral 471 denotes a first-stage N-channel current source transistor, 472a denotes a second-stage N-channel current source transistor, and 472b denotes a second-stage P-channel current source transistor.

[0841] In FIG. 51, reference numeral 471a denotes a first-stage N-channel current source transistor, 472a denotes a second-stage N-channel current source transistor, and 472b denotes a second-stage P-channel current source transistor.

[0842] In FIG. 50, the gate voltage of the first-stage current source consisting of a variable register 491 (used to vary current) and the N-channel transistor 471 is delivered to the gate of the N-channel transistor 472a of the second-stage current source. Thus, this is a layout configuration of a voltage-based delivery type.

[0843] In FIG. 51, the gate voltage of the first-stage current source consisting of a variable register 491 and the N-channel transistor 471a is applied to the gate of the N-channel transistor 472a of the adjacent second-stage current source, and consequently the value of the current flowing through the transistor is delivered to the P-channel transistor 472b of the second-stage current source. Thus, this is a layout configuration of a current-based delivery type.

[0844] Incidentally, although this example of the present invention focuses on relationship between the first current source and second current source for ease of explanation or understanding, this is not restrictive and it goes without saying that this example also applies (can be applied) to relationship between the second current source and third current source as well as relationship between other current sources.

[0845] In the layout configuration of the current mirror circuit of the voltage-based delivery type shown in FIG. 50, the N-channel transistor 471 of the first-stage current source and the N-channel transistor 472a of the second-stage current source composing the current mirror circuit are separated (or liable to get separated, to be precise), and thus the two transistors tend to differ in characteristics. Consequently, the current value of the first-stage current source is not transmitted correctly to the second-stage current source and there can be variations.

[0846] In contrast, in the layout configuration of the current mirror circuit of the current-based delivery type shown in FIG. 51, the N-channel transistor 471a of the first-stage current source and the N-channel transistor 472a of the second-stage current source composing the current mirror circuit are located adjacent to each other (easy to place adjacent to each other), and thus the two transistors hardly differ in characteristics. Consequently, the current value of the first-stage current source is transmitted correctly to the second-stage current source and there can be little variations.

[0847] In view of the above circumstances, it is preferable to use a layout configuration of the current-based delivery type instead of the voltage-based delivery type for the circuit configuration of the multi-stage current mirror circuit according to the present invention (the source driver IC (circuit) 14 of the current-based delivery type according to the present invention) in terms of reduced variations. Needless to say the above example can be applied to other examples of the present invention.

[0848] Incidentally, although delivery from the first-stage current source to the second-stage current source has been cited for the sake of explanation, the same applies to delivery from the second-stage current source to the third-stage current source, delivery from the third-stage current source to the fourth-stage current source, and soon. Also, it goes without saying that the present invention may adopt a single-stage current source configuration (see FIGS. 164, 165, 166, etc.)

[0849] FIG. 52 shows a current-based delivery version of three-stage current mirror circuit (three-stage current source) shown in FIG. 49 (which, therefore shows a circuit configuration of a voltage-based delivery type).

[0850] In FIG. 52, a reference current is created first by the variable register 491 and N-channel transistor 471. Incidentally, although it is stated that the reference current is adjusted by the variable register 491, actually the source voltage of the N-channel transistor 471 is set and regulated by an electronic regulator formed (or placed) in the source driver IC (circuit) 14. Alternatively, the reference current is adjusted by directly supplying the source terminal of the transistor 471 with current outputted from a current-type electronic regulator consisting of a large number of unit transistors (single-unit) 484 as shown in FIG. 48 (see FIG. 53).

[0851] The gate voltage of the first-stage current source constituted of the transistor 471 is applied to the gate of the N-channel transistor 472a of the adjacent second-stage current source, and the current consequently flowing through the transistor is delivered to the P-channel transistor 472b of the second-stage current source. Also, the gate voltage of the P-channel transistor 472b of the second-stage current source is applied to the gate of the N-channel transistor 473a of the adjacent third-stage current source, and the current consequently flowing through the transistor is delivered to the N-channel transistor 473b of the third-stage current source. A large number of unit transistors 484 are formed (placed) at the gate of the N-channel transistor 473b of the third-stage current source according to the required bit count as illustrated in FIG. 48.

[0852] The configuration in FIG. 53 is characterized in that the first-stage current source 471 of the multi-stage current mirror circuit is equipped with a current-value adjustment element. This configuration allows output current to be controlled by varying the current value of the first-stage current source 471.

[0853] Variations in the Vt of transistors (variations in characteristics) are on the order of 100 mV within a wafer. However, variations in Vt of transistors formed within 100μ of each other should be 10 mV or less (actual measurement) That is, by configuring a current mirror circuit with transistors formed close to each other, it is possible to reduce variations in the output current of the current mirror circuit. This reduces variations in the output current among terminals of the source driver IC.

[0854] Incidentally, although variations in Vt are described as variations among transistors, variations among transistors are not limited to variations in Vt. However, since variations in Vt are a main cause of variations among transistors, it is assumed that the variations in Vt=the variations among transistors, for ease of understanding.

[0855] FIG. 118 shows formation areas of transistors versus variations in the output current of unit transistors 484 based on measurement results. The variations in the output current are variations in current at a threshold voltage (Vt). Black dots indicate variations in the output current of evaluation sample transistors (10 to 200 in number) created in a formation area. There is almost no variation (output current variations only within a margin of error, meaning that a constant output current is produced) in the output current of transistors formed in area A (a formation area of 0.5 square millimeters or less) in FIG. 118. Conversely, in area C (a formation area of 2.4 square millimeters or more), variations in the output current with respect to the formation area tend to increase sharply. In area B (a formation area of 0.5 to 2.4 square millimeters), variations in the output current are almost proportional to the formation area.

[0856] However, the absolute value of output current varies from wafer to wafer. However, this problem can be dealt with by adjusting the reference voltage or setting it to a fixed value in the source driver circuit (IC) 14 of the present invention. Also, it can be dealt with (solved) by modifying the current mirror circuit ingeniously.

[0857] The present invention varies (controls) the amount of current flowing through the source signal line 18 by switching the number of currents flowing through the unit transistors 484 using input digital data (D). When the number of gradations is 64 or more, since 1/64=0.015, theoretically variations in output current should be within 1 to 2%. Incidentally, output variations within 1% are difficult to distinguish visually and output variations of 0.5% or below are impossible to distinguish (look uniform).

[0858] To keep output current variations (%) within 1%, the formation area of a transistor group (the transistors among which variations should be suppressed) should be kept within 2 square millimeters as indicated by the results shown in FIG. 118. More preferably, the output current variations (i.e., variations in the Vt of transistors) should be kept within 0.5%. That is, the formation area of a transistor group 521 can be kept within 1.2 square millimeters as indicated by the results shown in FIG. 118. Incidentally, the formation area is given by the vertical length multiplied by the horizontal length. For example, a formation area of 1.2 square millimeters results from 1 mm×1.2 mm.

[0859] The same applies to a set of unit transistors 484 (a block of 63 transistors 484 in the case of 64 gradations, see FIG. 48, etc.). The formation area of the set of unit transistors 484 should be kept within 2 square millimeters. More preferably, the formation area of the set of unit transistors 484 should be kept within 1.2 square millimeters.

[0860] Incidentally, the above applies to 8-bit (256 gradations) or larger data. For a smaller number of gradations, for example, in the case of 6-bit data (64 gradations), variations in output current may be somewhere around 2% (virtually no problem in terms of image display). In this case, the formation area of a transistor group 521 can be kept within 5 square millimeters. There is no need for the two transistor groups 521 (transistor groups 521a and 521b are shown in FIG. 52) to satisfy this condition. Effect of the present invention can be achieved if at least one of the transistor groups (one or more transistor groups 521 if there are more than three) satisfy the condition. Preferably, this condition should be satisfied for a lower level transistor group 521 (521a is higher than 521b). This will reduce image display problems.

[0861] In the source driver circuit (IC) 14 of the present invention, a plurality of current sources consisting of parent, child, and grandchild current sources are connected in multiple stages (of course there may be two stages consisting of parent and child current sources) and placed densely, as shown in FIG. 52. Current-based delivery is made between current sources (between the transistor groups 521). Specifically, transistors enclosed by dotted lines in FIG. 52 (transistor groups 521) are placed densely. The transistor groups 521 make voltage-based delivery between each other. The parent current source 471 and child current sources 472a are formed (placed) approximately in the center of the source chip. This makes it possible to relatively shorten the distance between the transistors 472a composing the child current sources placed on the left and right of the chip and the transistors 472b composing current child sources. That is, the top-level transistor group 521a is placed at the approximate center of the IC chip. Then, lower-level transistor groups 521b are placed on the left and right of the IC chip 14. Preferably, the transistors are placed, formed, or produced in such a way that approximately equal numbers of lower-level transistor groups 521b will be on the left and right of the IC chip 14. Incidentally, the above items are not limited to IC chips 14, but apply to source driver circuits 14 formed directly on array boards 71 using low-temperature polysilicon technology or high-temperature polysilicon technology. The same is true of the other items.

[0862] According to the present invention, one transistor group 521a is constructed, placed, formed, or built at the approximate center of the IC chip 14 and eight transistor groups 521b each are formed on the left and right of the chip (N=8+8, see FIG. 47). Preferably the child transistor groups 521b are arranged in such a way that their numbers will be equal on the left and right of the chip or that the difference between the number of the child transistor groups 521b formed or placed on the left with respect to the center of the chip where the parent is formed and the number of the child transistor groups 521b formed or placed on the right of the chip will be four or less. More preferably, the difference between the number of the child transistor groups 521b formed or placed on the left of the chip and the number of the child transistor groups 521b formed or placed on the right of the chip is one or less. The above items similarly apply to grandchild transistor groups (omitted in FIG. 52).

[0863] Voltage-based delivery (voltage connection) is made between the parent current source 471 and child current sources 472a. Consequently, tends to be affected by variations in the Vt of the transistors. Thus, the transistors in the transistor group 521a are placed densely. The formation area of the transistor group 521a is kept within 2 square millimeters. More preferably, it is kept within 1.2 square millimeters as shown in FIG. 118. If the number of gradations is 64 or less, of course, the formation area may be within 5 square millimeters.

[0864] Data is delivered between the transistor group 521a and child transistors 472b via current, and thus the current may flow some distance. Regarding the distance (e.g., between the output terminals of the higher-level transistor group 521a and input terminals of the lower-level transistor group 521b) the transistors 472a composing the second current sources (child) and the transistors 472b composing the second current sources (child) should be placed at least within 10 mm of each other as described above. Preferably, the transistors should be placed or formed within 8 mm. More preferably, they should be placed within 5 mm.

[0865] It has been shown analytically that differences in characteristics (Vt and mobility (μ)) of transistors placed in a silicon chip do not have much impact in the case of current-based delivery if the distance is within this range. Preferably, the above conditions are satisfied especially by lower-level transistor groups. For example, if the transistor group 521a is at the top level with the transistor groups 521b lying below it and transistor groups 521c lying further below them, the current-based delivery between the transistor groups 521b and transistor groups 521c should satisfy the above conditions. Thus, according to the present invention it is not always necessary that all the transistor groups 521 satisfy the above conditions. It is sufficient that at least a pair of transistor groups 521 satisfy the above conditions. This is because the lower the level, the more transistor groups 521 there are.

[0866] This similarly applies to the transistors 473a constituting the third (grandchild) current sources and transistors 473b constituting the third current sources. Needless to say, almost the same applies to voltage-based delivery.

[0867] The transistor groups 521b are formed, built, or placed in the left-to-right direction of the chip (in the longitudinal direction, i.e., at locations facing the output terminal 681). The transistor groups 521b are formed, built, or placed in the left-to-right direction of the chip (in the longitudinal direction, i.e., at locations facing the output terminal 681). According to the present invention, the number M of the transistor groups 521b is 11 (see FIG. 47).

[0868] Voltage-based delivery (voltage connection) is made between the child current sources 472b and grandchild current sources 473a. Thus, the transistors in the transistor groups 521b are placed densely as is the case with the transistor group 521a. The formation area of the transistor group 521b should be within 2 square millimeters as shown in FIG. 118. More preferably, it should be within 1.2 square millimeters. However, even slight variations in the Vt of the transistors in the transistor groups 521b tend to appear on the screen. Thus, preferably the formation area should be area A (0.5 square millimeters or less) in FIG. 118.

[0869] Data is delivered between the grandchild transistors 473a and transistors 473b (current-based delivery), and thus the current may flow some distance in the transistor group 521b. The description of distances provided earlier applies here as well. The transistors 473a constituting the third (grandchild) current sources and transistors 473b constituting the second (grandchild) current sources should be placed within at least 8 mm of each other. More preferably, they should be placed within 5 mm.

[0870] FIG. 53 shows the current-value adjustment element constituted of an electronic regulator. The electronic regulator consists of a resister 531 (which is formed of polysilicon, controls current, and creates reference voltages), decoder circuit 532, level-shifter circuit 533, etc. Incidentally, the electronic regulator outputs current. A transistor 481 functions as an analog switch circuit.

[0871] Incidentally, in the source driver IC (circuit) 14, transistors may be referred to as current sources. This is because transistors function as current sources in current mirror circuits and the like composed of transistors.

[0872] Electronic regulators circuits are formed (or placed) according to the number of colors used by the EL display panel. For example, if the three primary colors RGB are used, preferably three electronic regulators are formed (or placed) corresponding to the colors so that the colors can be adjusted independently. However, if one color is used as a reference (is fixed), as many electronic regulators circuits as the number of colors minus 1 should be formed (or placed).

[0873] FIG. 68 shows a configuration in which resistive elements 491 are formed (or placed) to control reference voltages of the three primary colors RGB independently. Of course, it goes without saying that the resistive elements 491 may be substituted with electronic regulators. Also, resistive elements 491 may be built into the source driver IC (circuit) 14. Basic current sources including patent and child current sources such as the current source 471 and current sources 472 are placed densely in a output current circuit 654 in an area illustrated in FIG. 68. The dense placement reduces variations in outputs from the source signal lines 18. As illustrated in FIG. 68, by placing them in the output current circuit 654 at the center of the source driver IC (circuit) 14, it becomes easy to distribute current to the left and right of the source driver IC (circuit) 14 from the current source 471 and current sources 472, resulting in reduced output variations between the left and right sides (it is all right to place them in a reference current generator circuit or controller instead of the current output circuit. That is, 654 is an area where an output circuit is not formed).

[0874] However, it is not always necessary to place them in the output current circuit 654 at the center They may be placed at an end or both ends of the IC chip. Also, they may be formed or placed in parallel with the output current circuit 654.