Semiconductor device and driving method of semiconductor device

[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2003-429147, filed on Dec. 25, 2003, the entire contents of which are incorporated herein by reference.

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device and a driving method of a semiconductor device.

[0004] 2. Background Art

[0005] Such a semiconductor memory device as a NAND type flash memory or the like requires a voltage which is higher than a power source voltage and is constant in order to write, erase or read data. For this reason, a semiconductor device is provided with a booster circuit which boosts a power source and a regulator circuit which holds an output voltage of the booster circuit in a constant voltage.

[0006] FIG. 18 shows one example of a boosted potential generating portion in a conventional semiconductor memory device 10. A clock generating circuit 11 outputs a clock signal Φ, and a booster circuit 12 boosts a power source voltage by the clock signal Φ and a reversed signal (hereinafter, called “Φb”) of the clock signal Φ having phases reversed to each other.

[0007] A regulator circuit 13 is provided with resistors R1, R2, a differential amplifier AMP1, an inverter In1, and AND gates G1, G2. In a potential detecting circuit 14, the resistors R1 and R2 potential-divides an output potential Vout of the booster circuit 12 to produce a monitor potential MON, and the differential amplifier AMP1 compares the monitor potential MON with a reference potential Vref. The differential amplifier AMP1 outputs “H (High)” level, when the monitor potential MON is larger than the reference potential Vref, while it outputs “L (Low)” level, when the monitor potential MON is smaller than the reference potential Vref. An output signal from the differential amplifier AMP1 is inverted by the inverter In1, and it is inputted into one of input terminals of the AND gates G1 and G2 as a flag signal FLG. Further, the other input terminals of the AND gates G1 and G2 are respectively inputted with clock signals Φ and Φb.

[0008] When the output potential Vout is relatively low and the monitor potential MON is smaller than the reference potential Vref, the flag signal FLG is H level. Therefore, the AND gates G1 and G2 allow the clock signals Φ and Φb to pass through the booster circuit 12, so that the booster circuit 12 boosts the power source voltage. On the other hand, when the output potential Vout is relatively high and the monitor potential MON exceeds the reference potential Vref, the flag signal FLG becomes L level. Accordingly, the AND gates G1 and G2 interrupt the clock signals Φ and Φb, so that the booster circuit 12 stop its boosting operation.

[0009] Thus, the regulator circuit 13 holds the monitor potential MON in almost the reference potential Vref by allowing passing-through of the clock signals Φ and Φb or by interrupting them. Since the monitor potential MON depends on the output potential Vout, the regular circuit 13 holds the output potential Vout in about a certain constant potential. Thereby, by setting the values of the reference potential Vref and the resistors R1 and R2 properly, the regulator circuit 13 can hold the output potential in almost a predetermined expected potential value.

[0010] The above technique is described in JP-A2003-242790 (hereinafter, called Patent Literature 1), U.S. Pat. No. 6,294,950 (hereinafter, called Patent Literature 2) and JP-A08-190789 (hereinafter, called Patent Literature 3).

[0011] Now, in order to boost the output potential Vout up to a predetermined expected potential value in a short time, it is necessary to elevate a boosting ability of the booster circuit 12. When the boosting ability of the booster circuit 12 is elevated, as shown in FIG. 19, there occurs such a problem that overshoot and ripple become large. The overshoot means such a phenomenon that a potential transiently exceeds a expected potential value at a time of boosting. The ripple means such a phenomenon that, when an output potential Vout after being boosted is held in an expected potential value, the output potential Vout oscillates at an expected potential value. These phenomena occur due to RC delay from detection of the output Vout to feedback of a flag signal FLG to AND gates G1 and G2.

[0012] These problems become significant when the values of the resistors R1 and R2 are made large in order to reduce a value of a current flowing in the resistors R1 and R2, which acts a load current on the booster circuit 12. This is because, when the values of the resistors R1 and R2 are made large, the RC time constant in the potential detecting circuit 14 becomes large so that response of the potential detecting circuit 14 is delayed.

[0013] In the Patent Literature 1 and the Patent Literature 2, a semiconductor device which compares a voltage obtained by voltage-dividing an output voltage of a booster circuit with a reference voltage to change a frequency of a clock generating circuit. However, in such a flash memory as an NAND type flash memory, clock signals are ordinarily supplied to a plurality of booster circuits by one clock generating circuit. Thereby, there arises a problem that, when the frequency of the clock generating circuit itself is changed, the frequencies of all the clock signals supplied to the plurality of booster circuits change. On the other hand, when clock generating circuits are provided so as to correspond to each of the plurality of booster circuits, there occur such a problem that the size of the semiconductor memory device is made large and such a problem that the amplitude or the frequency of the clock signal is fluctuated.

[0014] A semiconductor device according to an embodiment of the present invention comprises a clock generating circuit which generates a clock signal; a booster circuit which boosts a supply voltage by using the clock signal to output the boosted voltage; a potential detecting circuit which detects an output potential of the booster circuit to output a frequency changing signal depending on the output potential; and a frequency changing circuit which is interposed between the clock generating circuit and the booster circuit to change the frequency of the clock signal from the clock generating circuit to the booster circuit on the basis of the frequency changing signal.

[0015] A driving method of a semiconductor device according to an embodiment of the present invention, said semiconductor device including a clock generating circuit generating a clock signal, a booster circuit boosting a supply voltage using the clock signal to output the boosted voltage, a potential detecting circuit connected to an output of the boosting circuit, and a frequency changing circuit interposed between the clock generating circuit and the booster circuit, comprises:

• • [0016] detecting an output potential of the booster circuit at the potential detecting circuit; generating a frequency changing signal depending on the output potential at the potential detecting circuit; changing a frequency of the clock signal from clock generating circuit to the booster circuit on the basis of the frequency changing signal.

[0017] FIG. 1 is a bock diagram of a boosted potential generating section of a semiconductor device 100 according to a first embodiment of the present invention;

[0018] FIG. 2 is a circuit diagram showing a clock generating circuit 111, one of booster circuits 112 and one of regulator circuits 113;

[0019] FIG. 3 is a circuit diagram showing a specific example of a frequency changing circuit 120;

[0020] FIG. 4 is a timing chart showing a relationship between a frequency changing signal CLKCHG and a clock output signal CLKOUT;

[0021] FIG. 5 is a circuit diagram showing a specific example of the booster circuit 112;

[0022] FIG. 6 is a timing chart showing signal levels of clock signals Φ and Φbar;

[0023] FIG. 7 is a graph showing an output potential Vout of the first embodiment;

[0024] FIG. 8 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB, a clock output signal CLKOUT and a clock signal Φ;

[0025] FIG. 9 is a circuit diagram showing a clock generating circuit 111, one of booster circuits 112 and one of regulator circuits 213 according to a second embodiment;

[0026] FIG. 10 is a circuit diagram showing a specific example of a frequency changing circuit 220;

[0027] FIG. 11 is a timing chart showing a relationship among a frequency switching signal CLKCHG, an enabling signal CLKENB and a clock output signal CLKOUT;

[0028] FIG. 12 is a graph showing an output potential Vout of the second embodiment;

[0029] FIG. 13 is a timing chart showing a relationship among a frequency switching signal CLKCHG, an enabling signal CLKENB, a clock output signal CLKOUT and a clock signal Φ;

[0030] FIG. 14 is a circuit diagram showing a clock generating circuit 111, one of booster circuits 112 and one of regulator circuits 313 according to a third embodiment;

[0031] FIG. 15 is a graph showing an output potential Vout of the third embodiment;

[0032] FIG. 16 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB, a clock output signal CLKOUT and a clock signal Φ;

[0033] FIG. 17 is a block diagram of a semiconductor memory device 400 according to an embodiment of the present invention;

[0034] FIG. 18 is a block diagram of a boosted potential generating section of a conventional semiconductor memory device 10; and

[0035] FIG. 19 is a graph of an output potential Vout in the boosted potential generating section of a conventional semiconductor device.

[0036] Embodiments of the present invention will be explained below with reference to the drawings. However, these embodiments do not limit the present invention. The semiconductor devices according to these embodiments is each provided between a clock generating circuit and a booster circuit with a frequency changing circuit for changing the frequency of a clock signal. Thereby, even if a boosting ability of the booster circuit is improved, overshoot and ripple of an output voltage can be reduced.

[0037] FIG. 1 is a block diagram of a boosted potential generating section of a semiconductor device 100 according to a first embodiment of the present invention. The semiconductor device 100 is provided with a clock generating circuit 111, booster circuits 112 and regulator circuits 113. Thus, a plurality of the booster circuits 112 are provided to correspond to one clock generating circuit 111. The regulator circuit 113 is provided between each booster circuit 112 and the clock generating circuit 111 so as to correspond to each booster circuit 112. The clock generating circuit 111 may be constituted of an oscillator such as, for example, a ring oscillator. The booster circuit 112 may be a charge pump of Dickson type such as, for example, shown in FIG. 5.

[0038] The clock generating circuit 111 generates a clock signal. The booster circuit 112 boosts a supply voltage using the clock signal and further outputs the boosted supply voltage. The regulator circuit 113 detects an output potential Vout of the booster circuit 112 to perform switching between passing-through and interruption of the clock signal from the clock generating circuit 111 through the booster circuit 112 on the basis of the detected output signal Vout and adjust the frequency of the clock signal. Thereby, the regulator circuit 113 holds the output potential Vout in a desired expected voltage value.

[0039] The plurality of booster circuits 112 are provided for each clock generating circuit 111. As a representative one of such semiconductor devices, there is a NAND type flash memory. In the NAND type flash memory, an output voltage Vout is used for writing data in a memory cell, erasing the same or reading data from the memory cell.

[0040] FIG. 2 is a circuit diagram showing the clock generating circuit 111, and respective ones of the booster circuits 112 and the regular circuits 113. A portion defined with a broken line in FIG. 1 corresponds to a portion shown in FIG. 2. The regulator circuit 113 includes resistors R10, R20 and R30, differential amplifiers AMP10 and AMP20, a frequency changing circuit 120, AND gates G10 and G20, and inverters In10 and In20.

[0041] The resistors R10, R20 and R30 are connected in series between an output of the booster circuit 112 and a ground GND. The resistors R10, R20 and R30 may be fixed resistors or variable resistors. The resistors R10, R20 and R30 potential-divide the output voltage Vout to produce a monitor potential MON1 from a node N1 between the resistor R10 and the resistor R20 and a monitor potential MON2 from a node N2 between the resistor R20 and R30, respectively. Since the monitor potentials MON1 and MON2 changes in proportion to the output potential Vout, the output potential Vout can be monitored.

[0042] In order to reduce a current I_R flowing in the resistors R1, R2 and R3, it is preferable that the sum of resistance values of the resistors R1, R2 and R3 is made larger. This is because that the current I_R acts as a load current for blocking a boosting operation of the booster circuit 112. However, the resistance values of the resistors R1, R2 and R3 are large, a RC time constant of the potential detecting circuit 114 becomes large, so that response of the potential detecting circuit 114 is delayed.

[0043] One inputs of the differential amplifiers AMP10 and AMP20 are respectively connected to nodes N1 and N2, while the other inputs thereof are both connected to a reference potential Vref. The differential amplifier AMP10 compares the monitor potential MON1 with the reference potential Vref to outputs a flag signal FLG1 on the basis of the comparison result. In details, when the monitor potential MON1 is lower than the reference potential Vref, the differential amplifier AMP10 makes the flag signal FLG1 L (Low), and when the monitor potential MON1 exceeds the reference potential Vref, the differential amplifier AMP10 makes the flag signal FLG1H (High).

[0044] The differential amplifier AMP20 compares the monitor potential MON2 with the reference potential Vref to output a signal on the basis of the comparison result. Since an output of the differential amplifier AMP20 is connected with the inverter In10, a flag signal FLG2 is a signal obtained by reversing an output signal of the differential amplifier AMP20. In details, when the monitor potential MON2 is lower than the reference potential Vref, the differential amplifier AMP20 outputs Low and the flag signal FLG 2 becomes High. When the monitor potential MON2 exceeds the reference potential Vref, the differential amplifier AMP20 outputs High and the flag signal FLG2 becomes Low.

[0045] The frequency changing circuit 120 is connected between the clock generating circuit 111 and the booster circuit 112. The frequency changing circuit 120 is inputted with a clock input signal CLKIN from the clock generating circuit 111 and is inputted with the flag signal FLG1 from the differential amplifier AMP10 as a frequency changing signal CLKCHG. The frequency changing circuit 120 changes the frequency of the clock input signal CLKIN on the basis of the frequency changing signal CLKCHG. For example, when the frequency changing signal CLKCHG is inactive (Low), namely, the flag signal FLG1 is low, the frequency changing circuit 120 outputs the clock input signal CLKIN as a clock output signal CLKOUT without changing the frequency “w” of the clock input signal CLKIN. When the frequency changing signal CLKCHG is active (High), namely, the flag signal FLG1 is high, the frequency changing circuit 120 lowers the frequency w of the clock input signal CLKIN to w/2 and outputs this signal as the clock output signal CLKOUT.

[0046] The AND gates G10 and G20 is connected between the frequency changing circuit 120 and the booster circuit 112. One input terminal of the AND gate G10 is inputted with the flag signal FLG2 as an enabling signal CLKENB, and the other input terminal of thereof is inputted with the clock output signal CLKOUT. Thereby, when the enabling signal CLKENB is active (High), namely, the flag signal FLG2 is high, the AND gate G10 allows passing-through of the clock output signal CLKOUT as a clock signal Φ. When the enabling signal CLKENB is inactive (Low), namely, the flag signal FLG2 is low, the AND gate G10 interrupts the clock output signal CLKOUT. One input of the AND gate G20 is inputted with the flag signal FLG2 as an enabling signal CLKENB and the other input thereof is inputted with a reversed signal of the clock output signal CLKOUT. Thereby, when the enabling signal CLKENB is active (High), the AND gate G20 allows passing-through of the reversed signal of the clock output signal CLKOUT as a clock signal Φbar. When the enabling signal CLKENB is inactive (Low), the AND gate G10 interrupts the reversed signal of the clock output signal CLKOUT.

[0047] The monitor potential MON2 is lower than the monitor potential MON1 by the magnitude corresponding to interposition of the resistor R20. Thereby, for example, when the output potential Vout increases from zero, the monitor potential MON1 first exceeds the reference potential Vref and then the monitor potential MON2 exceeds the reference potential Vref. Therefore, from a state (state 1) that the flag signal FLG1 is Low and the flag signal FRG2 is High, the flag signal FLG1 is changed to High (state 2) and the flag signal FRG2 is further changed to Low (state 3).

[0048] At a time of the state 1, the frequency changing signal CLKCHG is inactive and the enabling signal CLKENB is active. Therefore, the frequency changing circuit 120 outputs the clock input signal CLKIN with the frequency “w” as the clock output signal CLKOUT, and the AND gates G10 and G20 output the clock output signals CLKOUT as clock signals Φ and Φbar.

[0049] At a time of the state 2, both the frequency changing signal CLKCHG and the enabling signal CLKENB are active. Therefore, the frequency changing circuit 120 outputs a clock signal 2*CLK obtained by reducing the frequency w of the clock input signal CLKIN to w/2 as the clock output signal CLKOUT, and the AND gates G10 and G20 output the clock signal 2*CLK as the clock signals Φ and Φbar.

[0050] At a time of the state 3, the frequency changing signal CLKCHG is active and the enabling signal CLKENB becomes inactive. Therefore, the frequency changing circuit 120 outputs the clock signal 2*CLK, but the AND gates G10 and G20 interrupt the clock signal 2*CLK.

[0051] On the other hand, when the output potential Vout falls below High (H) potential, the monitor potential MON2 first lowers below the reference potential Vref, and the monitor potential MON1 lowers below the reference potential Vref. Therefore, from a state (the state 3) that the flag signal FLG1 is High and the flag signal FRG2 is Low, the flag signal FLG2 first changes to High (the state 2) and further the flag signal FLG1 becomes Low (the state 1).

[0052] FIG. 3 is a circuit diagram showing a specific example of the frequency changing circuit 120. The frequency changing circuit 120 is provided with a frequency-dividing circuit 130 which divides the frequency w of the clock input signal CLKIN into w/2 to output this frequency-divided signal as the clock signal 2*CLK. The frequency-dividing circuit 130 includes transfer gates T1 to T4, as shown in FIG. 3. The frequency w of clock input signal CLKIN can be frequency-divided into w/2 by alternate switching between the transfer gates T1 and T4 and the transfer gates T2 and T3. The transfer gates T1 to T4 are, for example, respectively constituted by parallel connections of N-type MOS transistors and P-type MOS transistors.

[0053] The frequency changing circuit 120 is further provided with NAND gates G30, G40 and G50. The NAND gate G30 is inputted with the reversed signal of the frequency changing signal CLKCHG and the clock input signal CLKIN. The NAND gate G40 is inputted with the frequency changing signal CLKCHG and the clock signal 2*CLK from the frequency-dividing circuit 130. The NAND gate G50 is inputted with outputs of the NAND gates G30 and G40.

[0054] Therefore, when the frequency changing signal CLKCHG is inactive (Low), the clock output signal CLKOUT becomes the clock input signal CLKIN with the frequency w. On the other hand, when the frequency changing signal CLKCHG is active (High), the clock output signal CLKOUT becomes the clock signal 2*CLK obtained by frequency-dividing the frequency w of the clock input signal CLKIN into w/2.

[0055] FIG. 4 is a timing chart showing a relationship between the frequency changing signal CLKCHG and the clock output signal CLKOUT. When the frequency changing signal CLKCHG is Low (time points t₀ to t₁), the clock output signal CLKOUT is the clock input signal CLKIN. When the frequency changing signal CLKCHG becomes High (time points t₁ to t₂), the clock output signal CLKOUT becomes the clock signal 2*CLK. Further, the frequency changing signal CLKCHG returns to Low (time point t₂ and thereafter), the clock output signal CLKOUT returns to the clock input signal CLKIN.

[0056] FIG. 5 is a circuit diagram showing a specific example of the booster circuit 112. FIG. 6 is a timing chart showing signal levels of clock signals Φ and Φbar. The booster circuit 112 is inputted with a supply potential Vin, and it boosts the supply potential Vin by the clock signals Φ and Φbar whose phases are reversed to each other, as shown in FIG. 6. The booster circuit 112 outputs the boosted supply potential Vin as an output potential Vout.

[0057] FIG. 7 is a graph showing an output potential Vout of this embodiment. FIG. 8 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB, a clock output signal CLKOUT and a clock signal Φ. In this connection, since the clock input signal CLKIN and the clock signal 2*CLK are respective signals with fixed frequencies of w and w/2, as illustrated in FIG. 4, they will be omitted in FIG. 8.

[0058] The output potential Vout when the monitor potential MON1 is equal to the reference potential Vref is defined as an expected potential value 1, and the output potential Vout when the monitor potential MON2 is equal to the reference potential Vref is defined as an expected potential value 2. As described with reference to FIG. 2, when the output potential Vout is raised, since the monitor potential MON1 exceeds the reference potential Vref prior to the monitor potential MON2, the expected potential value 2 becomes a potential higher than the expected potential value 1.

[0059] With reference to FIG. 7 and FIG. 8, operation and advantage of the semiconductor device 100 shown in FIG. 2 will be explained. In this connection, this embodiment serves so as to hold the output potential Vout in the expected potential value 2.

[0060] First, when the booster circuit 112 starts boosting operation, the output potential Vout rises from zero (time points t₁₀ to t₁₁). At this time, since both the monitor potential MON1 and the monitor potential MON2 are smaller than the reference potential Vref, the frequency changing signal CLKCHG (flag signal FLG1) is Low and the enabling signal CLKENB (flag signal FLG2) is active (High). Therefore, the frequency changing circuit 120 outputs the clock input signal CLKIN as the clock output signal CLKOUT without changing the frequency w of the clock input signal CLKIN. Further, the AND gates G10 and G20 output the clock output signals CLKOUT as the clock signals Φ and Φbar. Thereby, the booster circuit 112 can boost a supply voltage (not shown) in a short time.

[0061] Next, when the output potential Vout exceeds the expected potential value 1 (time point t₁₁), the monitor potential MON1 exceeds the reference potential Vref and the monitor potential MON2 remains smaller than the reference potential Vref. Therefore, the frequency changing signal CLKCHG becomes active (High) and the enabling signal CLKENB holds its active (High) state. Thereby, the frequency changing circuit 120 frequency-divides the frequency w of the clock input signal CLKIN to w/2 to output the same as the clock output signal CLKOUT. The AND gates G10 and G20 output the clock output signals CLKOUT with the frequency w/2 as the clock signal Φ or Φbar. Accordingly, the boosting ability of the booster circuit 112 is reduced to ½ to the clock signals Φ and Φbar with the frequency w.

[0062] Next, when the output potential Vout exceeds the expected potential value 2 (time point t₁₂), the monitor potential MON2 exceeds the reference potential Vref. Therefore, the enabling signal CLKENB becomes inactive (Low). Thereby, the AND gates G10 and G20 interrupt the clock output signals CLKOUT. Thereby, the clock signals Φ and Φbar become low. That is, the boosting operation of the booster circuit 112 stops and the output potential Vout gradually lowers due to the current I_R. In this connection, after the output potential (voltage) Vout exceeds the expected potential value 2, it is delayed, so that the enabling signal CLKENB is changed. This is because the potential detecting circuit 114 has a RC time constant, and the RC delay of the potential detecting circuit 114 causes overshoot or ripple.

[0063] Further, when the output potential Vout lowers below the expected potential value 2 (time point t₁₃), the monitor potential MON2 decreases below the reference potential Vref. Thereby, the enabling potential CLKENB becomes active (High). At this time, the frequency changing signal CLKCHG holds its active (High) state. Therefore, the frequency changing circuit 120 outputs the clock signal CLKOUT with the frequency w/2 CLKOUT, and the AND gates G10 and G20 output the clock signals CLKOUT with the frequency w/2 CLKOUT as the clock signal Φ or Φbar. Accordingly, the booster circuit 112 restarts the boosting operation. However, since the frequency of the clock signal Φ or Φbar is w/2, the boosting ability of the booster circuit is about one half to the boosting ability obtained by the clock signal Φ or Φbar with the frequency w. Incidentally, since the current I_R is very small, a lowering speed of the output potential Vout is slow. Thereby, the undershoot ordinarily becomes smaller than the overshoot. Accordingly, the output potential Vout does not lower below the expected potential value 1 and it is held in the expected potential value 2.

[0064] Thereafter, when the output potential Vout exceeds the expected potential value 2 (time t₁₄), the same operation as that at the time point t₁₂ is conducted in this embodiment. The operations of the semiconductor device 100 at the time points t₁₃ and t₁₄ are repeated at time points t₁₅ and t₁₆ and time points t₁₇ and t₁₈. Thereby, the semiconductor device 100 serves so as to hold the output potential Vout in the expected potential value 2.

[0065] When the output of the booster circuit 112 is connected with a new load (not shown), there occurs a possibility that the output potential Vout lowers rapidly. In such a case, since the output potential Vout lowers below the expected potential value 1, the booster circuit 112 is driven by the clock signals Φ and Φbar with the frequency w like the case at the time points t₁₀ to t₁₁. Thereby, the booster circuit 112 can boost the output voltage (potential) Vout in a short time by a High boosting ability thereof.

[0066] According to this embodiment, since the booster circuit 112 is driven by the clock signals Φ and Φbar with the frequency “w” in an initial stage of the boosting operation, the boosting speed of the output potential Vout is fast. On the other hand, when the output potential Vout is boosted up to approximately the expected potential value 2, the frequencies of the clock signals Φ and Φbar are frequency-divided to w/2. Thereby, since the boosting ability of the booster circuit 112 lowers, the overshoot can be suppressed to a smaller value as compared with the conventional case.

[0067] Further, when the output potential Vout is held in an expected potential value 2, booster circuits 112 repeats the boosting operation and stopping operation of the boosting operation by the clock signals Φ and Φbar frequency-divided to w/2.

[0068] In this embodiment, because the regulator circuit 113 changes the frequency of the clock signal for each of the booster circuits 112, the regulator circuit 113 are respectively provided so as to correspond to the plurality of booster circuits 112 (refer to FIG. 1). Thereby, the plurality of booster circuits 112 can be driven by using clock signals from the same or one clock generating circuit 111.

[0069] In this embodiment, the frequency changing circuit 120 must be provided for each of the booster circuits 112. However, the frequency changing circuit 120 can be realized with a simple frequency-dividing circuit, such as shown in FIG. 3. Further, the frequency changing circuit 120 only frequency-divides the clock signal. Therefore, fluctuation of the amplitude or frequency of the clock signal due to process variations or the like can be relatively small without making the size of the semiconductor memory device significantly large.

[0070] On the other hand, according to a conventional semiconductor device described in Patent Literature 2 and the like, a clock generating circuit must be provided for each booster circuit in order to change the frequency of the clock signal. Since the clock generating circuit is complicated as compared with the frequency changing circuit 120 according to this embodiment, provision of the clock generating circuit for each booster circuit makes the size of the semiconductor device large. Further, there is a case that the clock generating circuit is provided with a circuit which trims a clock frequency using a fuse or the like in order to suppress fluctuation of the clock frequency. In this case, when the clock generating circuit is provided for each booster circuit, the semiconductor memory device becomes complicated and its size becomes large.

[0071] In this embodiment, the frequency changing circuit 120 frequency-divides the frequency of the clock input signal CLKIN to ½. However, the frequency changing circuit 120 shown in FIG. 3 is only one specific example, and the frequency changing circuit 120 may divide the frequency of the clock input signal CLKIN to n/m of the frequency. Incidentally, n and m are natural numbers, where n<m.

[0072] In order to adjust the expected potential value 1 and the expected potential value 2, the values of the resistors R10, R20 and R30 may be changed. Thereby, the expected potential value 1 or the expected potential value 2 can be fitted to a required specification of the semiconductor memory device. The expected potential value 1 may be lower than the expected potential value 2, and it is not limited to a specific value. However, in order to reduce overshoot or ripple while holding a high boosting ability, it is preferable that the expected potential value 1 is set such that the output potential Vout does not become lower than the expected potential value 1, and it is preferable that the expected potential value 1 approximates to the expected potential value 2, when holding the output potential Vout in approximately the expected potential value 2.

[0073] A block diagram of a boosting section of a semiconductor device 200 according to a second embodiment is similar to that in FIG. 1. In this embodiment, a regulator circuit 213 is provided in place of the regulator circuit 113.

[0074] FIG. 9 is a circuit diagram showing a clock generating circuit 111, one of booster circuits 112 and one of regulator circuit 213.

[0075] The regulator circuit 213 includes resistor s R10, R20, R30 and R40, differential amplifiers AMP10, AMP20 and AMP30, a frequency changing circuit 220, a latch circuit 215, and inverters In10, In20, In30 and In40.

[0076] The resistors R10, R20, R30 and R40 are connected in series between an output of the booster circuit 112 and the ground GND. The resistors R10, R20, R30 and R40 may be either fixed resistors or variable resistors. The resistors R10, R20, R30 and R40 potential-divides the output potential Vout to produce a monitor potential MON1 from a node N1 between the resistor R10 and the resistor R20, a monitor potential MON2 from a node N2 between the resistors R20 and the resistor R30, and a monitor potential MON3 from a node N3 between the resistor R30 and the resistor R40, respectively. Since the monitor potentials MON1, MON2 and MON3 change in proportion to the output potential Vout, the output potential Vout can be monitored.

[0077] One inputs of the differential amplifiers AMP10, AMP20 and AMP30 are respectively connected to the nodes N1, N2 and N3, and the other inputs thereof are connected to the reference potential Vref. Outputs of the differential amplifiers AMP10, AMP20 and AMP30 are respectively connected with the inverters In10, In20 and In30.

[0078] The differential amplifiers AMP10, AMP20 and AMP30 respectively compare the monitor potentials MON1, MON2 and MON3 with the reference potential Vref to output signals based upon the comparison results. The inverters In10, In20 and In30 reverse respective outputs of the differential amplifiers AMP10, AMP20 and AMP30 and output these reversed outputs as flag signals FLG1, FLG2 and FLG2.

[0079] In details, when the monitor potentials MON1, MON2 and MON3 are lower than the reference potential Vref, the flag signals FLG1, FLG2 and FLG3 become High, respectively. When the monitor potentials MON1, MON2 and MON3 exceed the reference potential Vref, the flag signals FLG1, FLG2 and FLG3 become Low, respectively.

[0080] The flag signals FLG1 and FLG2 are supplied to the latch circuit 215. The latch circuit 215 outputs a frequency changing signal CLKCHG on the basis of the flag signals FLG1 and FLG2. In this embodiment, when the flag signals FLG1 and FLG2 are changed to low, the frequency changing signal CLKCHG is latched to an active (High) state. When both the flag signals FLG1 and FLG2 are changed to Low, the frequency changing signal CLKCHG is latched to an inactive (Low) state. When only one of the flag signals FLG1 and FLG2 is changed, the state of the frequency changing signal CLKCHG does not change.

[0081] The flag signal FLG3 is supplied to the frequency changing circuit 220 as an enabling signal CLKENB.

[0082] The frequency changing circuit 220 is connected between the clock generating circuit 111 and the booster circuit 112. The frequency changing circuit 220 is inputted with a clock input signal CLKIN, a frequency changing signal CLKCHG and an enabling signal CLKENB. The frequency changing circuit 220 changes the frequency of the clock input signal CLKIN on the basis of the frequency changing signal CLKCHG. Further, the frequency changing signal 220 allows passing-through of the clock input signal CLKIN or interrupts the clock input signal CLKIN on the basis of the enabling signal CLKENB.

[0083] An operation of the frequency changing circuit 220 to the flag signals FLG1, FLG2 and FLG3 will be explained. When the output potential Vout is boosted from a low potential, the monitor potentials MON1, MON2 and MON3 exceed the reference potential Vref in the order of the monitor potentials MON1, MON2 and MON3. Therefore, the flag signals FLG1, FLG2 and FLG3 sequentially change from respective High, High and High states (state 10) to Low, High and High states (state 11), Low, Low and High states (state 12), and Low, Low and Low states (state 13).

[0084] During the state 10, the frequency changing signal CLKCHG is inactive (Low) and the enabling signal CLKENB becomes active (High). At this time, the frequency changing circuit 220 outputs the clock input signal CLKIN as the clock output signal CLKOUT without changing the frequency w of outputs the clock input signal CLKIN.

[0085] During the state 11, since the frequency changing circuit 220 and the latch circuit 215 do not change, the state 11 is similar to the state 10.

[0086] During the state 12, the latch circuit 215 latches the frequency changing signal CLKCHG in an active (High) and the enabling signal CLKENB holds its active (High) state. At this time, the frequency changing circuit 220 changes the clock input signal CLKIN to a clock signal 4*CLK with a frequency of w/4 to output the same as a clock output signal CLKOUT.

[0087] During the state 13, the frequency switching signal CLKCHG is active (High) and the enabling signal CLKENB becomes inactive (Low). At this time, the frequency switching circuit 220 interrupts the clock input signal CLKIN and the clock signal 4*CLK.

[0088] In case that the output potential Vout falls below a high potential, the monitor potentials MON3, MON2 and MON1 lower below the reference potential Vref in this order. Therefore, the flag signals FLG1, FLG2 and FLG3 transit from the state 13 to the state 12, the state 11 and the state 10. In this connection, when both the flag signals FLG1 and FLG2 change, namely, the state transit from the state 11 to the state 10, the latch circuit 215 changes the frequency changing signal CLKCHG.

[0089] FIG. 10 is a circuit diagram showing a specific example of the frequency changing circuit 220. The frequency changing circuit 220 is provided with frequency-dividing circuits 231 and 232. The frequency-dividing circuit 231 frequency-divides the frequency w of the clock input signal CLKIN to w/2 to output the same as a clock signal 2*CLK. The frequency-dividing circuit 232 frequency-divides the frequency w/2 of the clock signal 2*CLK to w/4 to output the same as a clock signal 4*CLK.

[0090] The frequency-dividing circuit 231 includes transfer gates T1 to T4. The frequency w of the clock input signal CLKIN can be frequency-divided to ½ by switching the transfer gates T1, T4 and the transfer gates T2, T3 alternately. The frequency-dividing circuit 232 includes transfer gates T5 to T8. The frequency of the clock signal 2*CLK can be further frequency-divided to ½ thereof by alternately switching the transfer gates T5, T8 and the transfer gates T6, T7. The transfer gates T5, T8 are respectively constituted by parallel connections of N-type MOS transistors and P-type MOS transistors.

[0091] The frequency changing circuit 220 is further provided with an AND gate G60, and NAND gates G70, G80 and G90. The AND gate G60 is inputted with a clock input signal CLKIN and an enabling signal CLKENB. The NAND gate G70 is inputted with an output of the NAND gate G60 and a reversed signal of a frequency changing signal CLKCHG. The NAND gate G80 is inputted with the frequency changing signal CLKCHG and a clock signal 4*CLK from the frequency-dividing circuit 232. The NAND gate G90 is inputted with outputs of the NAND gates G70 and G80.

[0092] The AND gate G60 allows passing-through of a clock input signal CLKIN, when the enabling signal CLKENB is active (High), while it interrupts the clock input signal CLKIN, when the enabling signal CLKENB is inactive (Low). Incidentally, in this embodiment, the AND gate G60 is included in the frequency changing circuit 220 as a gate circuit for allowing a clock input signal CLKIN to pass through or interrupts the same.

[0093] Further, when the frequency changing signal CLKCHG is active (High), the clock output signal CLKOUT becomes a clock signal 4*CLK. On the other hand, when the frequency changing signal CLKCHG is inactive (Low), the clock output signal CLKOUT becomes an output signal of the AND gate G60.

[0094] FIG. 11 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB and a clock output signal CLKOUT. When the enabling signal CLKENB is High and the frequency changing signal CLKCHG is Low (time points t₀ to t₁), the frequency changing circuit 220 outputs the clock input signal CLKIN as a clock output signal CLKOUT. When both the enabling signal CLKENB and the frequency changing signal CLKCHG are High (time points t₁ to t₂), the frequency changing circuit 220 outputs the clock signal 4*CLK as the clock output signal CLKOUT. When the enabling signal CLKENB becomes Low (time points t₂ to t₃), the frequency changing circuit 220 interrupts the clock input signal CLKIN and the clock signal 4*CLK. Operations of the frequency changing circuit 220 during time points t₃ to t₄ and time points t₅ to t₆ are similar to the operation of the frequency changing circuit 220 during the time points t₁ to t₂. Operations of the frequency changing circuit 220 during time points t₄ to t₅ and during time point t₆ to time point subsequent thereto are similar to the operations of the frequency changing circuit 220 during the time points t₂ to t₃ and during the time points t₀ to t₁.

[0095] FIG. 12 is a graph showing an output potential Vout of this embodiment. FIG. 13 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB, a clock output signal CLKOUT and clock signal Φ. Incidentally, since the clock input signal CLKIN and the clock signal 4*CLK are a signal with a fixed frequency of w and a signal with a fixed frequency of w/4, they will be omitted in FIG. 13.

[0096] An output potential Vout obtained when the monitor potential MON1 is equal to the reference potential is defined as an expected potential value 1, an output potential Vout obtained when the monitor potential MON2 is equal to the reference potential is defined as an expected potential value 2, and an output potential Vout obtained when the monitor potential MON3 is equal to the reference potential is defined as an expected potential value 3. As explained with reference to FIG. 9, when the output potential Vout is boosted, the monitor potentials MON1, MON2 and MON3 exceed the reference potential Vref in this order, so that the potential of the expected potential value 3 is the highest and the expected potential values lower in the order of the expected potential values 2 and the expected potential value 1.

[0097] With reference to FIG. 12 and FIG. 13, an operation and an advantage of the semiconductor device 200 shown in FIG. 9 will be explained. Incidentally, this embodiment serves to hold the output potential Vout in the expected potential value 3. When the booster circuit 112 first starts an boosting operation, the output potential Vout rise from zero (during time points t₂₀ to t₂₁). At this time, the monitor potentials MON1 to MON3 are lower than the reference potential Vref. Alternatively, only the monitor potential MON1 exceeds the reference potential Vref. Therefore, all the flag signals FLG1 to FLG3 become High or only the flag signal FLG1 becomes Low. At this time, the frequency changing signal is inactive (Low) and the enabling signal CLKENB is active (High). Therefore, frequency changing circuit 220 outputs the clock input signal CLKIN as the clock output signal CLKOUT without changing the frequency w of the clock input signal CLKIN. The clock output signal CLKOUT and a reversed signal thereof become clock signals Φ and Φbar. Thereby, the booster circuit 112 can boost the output voltage Vout in a short time with its high boosting ability.

[0098] Next, when the output potential Vout exceeds the expected potential value 2 (time point t₂₁), the monitor potentials MON1 and MON2 exceed the reference potential Vref, while the monitor potential MON3 remains lower than the reference potential Vref. Therefore, the frequency changing signal CLKCHG is latched in an active (High) state and the enabling signal CLKENB holds its active (High) state. Therefore, the frequency changing circuit 220 outputs the clock signal 4*CLK with the frequency w/4 as the clock output signal CLKOUT. The clock signal 4*CLK and its reversed signal become clock signals Φ and Φbar. Therefore, the boosting ability of the booster circuit 112 lowers to ¼ to the clock signals Φ and Φbar with the frequency w.

[0099] Next, when the output potential Vout exceeds the expected potential value 3 (time point t₂₂), the monitor potential MON3 exceeds the reference potential Vref. Therefore, the enabling signal CLKENB becomes inactive (Low). Therefore, the frequency changing circuit 220 interrupts the clock output signal CLKOUT. Thereby, the clock signals Φ and Φbar become Low. That is, the boosting operation of the booster circuit 112 stops and the output voltage Vout gradually lowers due to a current I_R.

[0100] When the output potential Vout lowers below the expected potential value 3 (time point t₂₃), the monitor potential MON3 lowers below the reference potential Vref. Therefore, the enabling signal CLKENB becomes active (High). At this time, the frequency changing signal CLKCHG is latched in an active (High) state by the latch circuit 215. Therefore, the frequency changing circuit 120 outputs the clock signal 4*CLK with the frequency w/4 as a clock signal Φ or Φbar. Thus, the booster circuit 112 restarts its boosting operation. However, since the frequency of the clock signal Φ or Φbar is w/4, the boosting ability is about ¼ to the clock signal Φ or Φbar with the frequency w. In this connection, since the current I_R is very small, a lowering speed of the output potential Vout is slow. Thereby, undershoot becomes smaller than overshoot. Accordingly, the output potential Vout does not lower below the expected potential value 1 and it can be held in the expected potential value 3.

[0101] Therefore, when the output potential Vout exceeds the expected potential value 3 (time point t₂₄), the semiconductor device 200 performs the same operation as the operation at the time point t₂₂. An operation of the semiconductor device 200 during the time points t₂₅ to t₂₆ is the same at the operation of the semiconductor device 200 during the time points t₂₃ to t₂₄.

[0102] Further, when an output of the booster circuit 112 is connected with a new load (time point t₂₇), such a possibility may occur that the output voltage Vout lowers urgently. In such a case, since the output voltage Vout lowers below the expected value voltage (potential) 1, the latch circuit 215 is reset, and the booster circuit 112 is driven by the clock signal Φ or Φbar with the frequency w like the case during time points t₂₀ to t₂₁. Thereby, the booster circuit 112 can boost the output voltage Vout in a short time. An operation of the semiconductor device 200 during the time points t₂₈ to t₂₉ is the same as the operation of the semiconductor device during the time points t₂₁ to t₂₂.

[0103] This embodiment has an advantage or merit similar to the first embodiment. Further, this embodiment has the latch circuit 215, where three expected potential values have been set. Thereby, the output potential Vout can be boosted with a high boosting ability until the output potential Vout is boosted up to the expected potential value 2 approximating to the expected potential value 3. On the other hand, even if the output potential Vout lowers below the expected potential value 2, the frequencies of the clock signals Φ and Φbar are held in the frequency w/4 by operation of the latch circuit 215. Unless the output potential Vout lowers below the expected potential value 1 lower than the expected potential value 2, the frequencies do not return back to the frequency w. That is, it is made possible to boost the output potential Vout with a high boosting ability just before the expected potential value 3 by causing the expected potential value 2 to approach to the expected potential value 3 sufficiently. In addition thereto, when the output potential Vout is held at the expected potential value 3, the frequencies of the clock signals Φ and Φbar with the frequency w/4 are w/4 and they are not reset to w, so that the output potential Vout is not boosted with an excessive boosting ability. As a result, this embodiment can boosts the output potential Vout in an initial stage of boosting very quickly, and a ripple may be made small.

[0104] In this embodiment, the frequency changing circuit 220 frequency-divides the frequency w of the clock input signal CLKIN to ¼. However, the frequency changing circuit 220 shown in FIG. 10 is merely one specific example, and the frequency changing circuit 220 may frequency-divide the clock input signal CLKIN to n/m. Incidentally n and m are natural numbers, where n<m.

[0105] In order to adjust the expected potential value 1, the expected potential value 2 and the expected potential value 3, values of the resistors R10, R20, R30 and R40 may be changed. Thereby, the values of the expected potential value 1, the expected potential value 2 and the expected potential value 3 can be fitted to their specifications. The expected potential value 2 is not limited to a specific value as long as it is equal to or less than the expected value 3. In this connection, it is preferable that the expected potential value 2 further approximates to the expected potential value 3 for holding a fast boosting speed. Further, the expected potential value 1 is not limited to a specific value as long as it is equal to or less than the expected potential value 2. In this connection, it is preferable that, when the output potential Vout is held in a value approximating to the expected potential value 3, the output potential Vout is set such that it does not lower below the expected potential value 1 for preventing the output potential Vout from being boosted with an excessive boosting ability.

[0106] A block diagram of a boosting section of a semiconductor device 300 according to a third embodiment is similar to that in FIG. 1. Incidentally, in this embodiment, a regulator circuit 313 is provided in place of the regulator circuit 313.

[0107] FIG. 14 is a circuit diagram of a clock generating circuit 111, one of booster circuits 112 and one of regulator circuits 313. The regulator circuit 313 is different from the regulator circuit 113 in that the former is provided with one differential amplifier and it includes a latch circuit 315.

[0108] Resistors R10 and R20 is connected in series between an output of the booting circuit 112 and the ground GND. The resistors R10 and R20 potential-divide an output potential Vout to produce a monitor potential MON1 from a node N1 between the resistor R10 and the resistor R20. Since the monitor potential MON1 changes in proportion to the output potential Vout, the output potential Vout can be monitored.

[0109] One input of a differential amplifier AMP10 is connected to the node N1, and the other input thereof is connected to the reference potential Vref. An output of the differential amplifier AMP10 is connected with an inverter In10.

[0110] The differential amplifier AMP10 compares the monitor potential MON1 and the reference potential Vref to each other to output a signal on the basis of the comparison result. The inverter In10 reverses an output of the differential amplifier AMP10 to output the same as a flag signal FLG1.

[0111] In details, when the monitor potential MON1 is lower than the reference potential Vref, the flag signal FLG1 becomes High. When the monitor potential MON1 exceeds the reference potential Vref, the flag signal FLG1 becomes Low.

[0112] The flag signal FLG1 is supplied to the latch circuit 315, and AND gates G10 and G20. The latch circuit 315 outputs a frequency changing signal CLKCHG on the basis of the flag signal FLG1. In this embodiment, after the flag signal FLF1 has been once changed to Low, the frequency changing signal CLKCHG is always latched in a active (High) state. Thereafter, even if the flag signal FLG1 is changed to High, the state of the frequency changing signal CLKCHG does not change.

[0113] Operations of the frequency changing circuit 120 and the AND gates G10 and G20 to the flag signal FLG1 will be explained. When the flag signal FLG1 is High, the enabling signal CLKENB is active (High) and the frequency changing signal CLKCHG is inactive (Low). Therefore, the frequency changing circuit 120 outputs a clock output signal CLKOUT with a frequency w, and the AND gates G10 and G20 cause the clock output signal CLKOUT and its reversed signal to pass through as clock signals Φ and Φbar.

[0114] When the flag signal FLG1 becomes Low, the enabling signal CLKENB becomes inactive (Low) and the latch circuit 315 latches the frequency changing signal CLKCHG in an active (High) state. Thereby, the frequency changing circuit 120 outputs a clock output signal CLKOUT with a frequency of w/2, and the AND gates G10 and G20 interrupt the clock output signals CLKOUT.

[0115] When the flag signal FLG1 becomes High again, the enabling signal CLKENB becomes active (High), but the frequency changing signal CLKCHG is held at an active (High) state by the latch circuit 315. Thereby, the frequency changing circuit 120 outputs the clock output signal CLKOUT with the frequency of w/2, and the AND gates G10 and G20 allows the clock output signal CLKOUT and its reversed signal to pass as the clock signals Φ and Φbar, respectively.

[0116] FIG. 15 is a graph showing an output potential Vout in this embodiment. FIG. 16 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB, a clock output signal CLKOUT and a clock signal Φ. The output potential Vout obtained when the monitor potential MON1 is equal to the reference potential is defined as an expected potential value 1. The semiconductor device 300 serves to hold the output potential Vout in the expected potential value 1.

[0117] With reference to FIG. 15 and FIG. 16, an operation and an advantage of the semiconductor device 300 will be explained. First, when the booster circuit 112 starts a boosting operation, the output potential Vout is boosted (time points t₃₀ to t₃₁). At this time, the monitor potential MON1 is smaller than the reference potential Vref, so that the frequency changing signal CLKCHG is inactive (Low) and the enabling signal CLKENG is active (High). Therefore, the frequency changing circuit 120 outputs the clock input signal CLKIN as a clock output signal CLKOUT without changing the frequency w of the clock input signal CLKIN. Further, the AND gates G10 and G20 output the clock output signals CLKOUT as the clock signal Φ or Φbar. Thereby, the booster circuit 112 can boost a supply voltage in a short time.

[0118] Next, when the output potential Vout exceeds the expected potential value 1 (time point t₃₁), the monitor potential MON1 exceeds the reference potential Vref. Therefore, the latch circuit 315 latches the frequency changing signal CLKCHG in an active (High) state and the enabling signal CLKENB becomes inactive (Low). Thereby, the frequency changing circuit 120 frequency-divides the frequency of the clock input signal CLKIN to w/2, but the AND gates G10 and G20 interrupt the clock output signals CLKOUT with the frequency w/2. Accordingly, the booster circuit 112 stops its boosting operation and the output potential Vout gradually lowers due to a current I_R.

[0119] Next, when the output potential Vout lowers below the expected potential value 1 (time point t₃₃), the monitor potential MON1 lowers below the reference potential Vref. Thereby, the enabling signal CLKENB becomes active (High). At this time, the frequency changing signal CLKCHG is held in an active (High) state by the latch circuit 315. Thereby, the frequency changing circuit 120 outputs the clock output signal CLKOUT with the frequency w/2, and the AND gates G10 and G20 outputs the clock output signals CLKOUT with the frequency w/2 as the clock signal Φ or Φbar. Accordingly, the booster circuit 112 restarts its boosting operation. However, since the frequency of the clock signal Φ or Φbar is w/2, its boosting ability is about one half to the boosting ability by the clock signal Φ or Φbar.

[0120] Thereafter, when the output potential Vout exceeds the expected potential value 1 (time point t₃₄), this embodiment performs the same operation as at the time point t32. The operations of the semiconductor device 300 at the time points of t₃₃ and t₃₄ are repeated at the time points t₃₅, t₃₆ and time points t₃₇, t₃₈. Thereby, the semiconductor device 300 serves to hold the output potential Vout in the expected potential value 1.

[0121] This embodiment has an advantage or merit similar to the first embodiment. However, when the output of the booster circuit 112 is connected with a new load, there may occurs a possibility that the output potential Vout lowers rapidly. In such a case, since the frequency changing signal CLKCHG is remained in an active (High) state by the latch circuit 315, the booster circuit 112 performs a boosting operation by the clock signal Φ or Φbar with the frequency w/2. Therefore, a time elapsed until the output potential Vout returns back to the expected potential value 1 becomes longer than a time elapsed in the case that boosting is performed by the clock signal Φ or Φbar. Accordingly, this embodiment is unsuitable for a case that, after the output potential Vout has reached the expected potential value 1, the output of the booster circuit 112 is connected with a new load. However, since the circuit configuration of the semiconductor device 300 is simpler than the circuit configuration of the semiconductor device 100, the size of the apparatus can be further reduced.

[0122] FIG. 17 is a block diagram of a semiconductor device 400 according to an embodiment of the present invention. The semiconductor device 400 may be, for example, a NAND type EEPROM or a NAND type flash memory.

[0123] A bit line control circuit 2 for performing writing/reading of data in the memory cell array 1 as the memory means is provided. The bit line control circuit 2 are connected to a data input buffer 6 and receives an output of a column decoder 3 receiving an address signal from an address buffer 4 as an input. Further, a row decoder 5 is provided for controlling a control gate and a selection gate to the memory cell array 1, and a substrate potential control circuit 7 for controlling a potential of a p-type substrate (or a p-type well) on which the memory cell array 1 is formed is provided.

[0124] Further, the semiconductor device 400 is provided with a clock generating circuit 111, a regulator circuit and a booster circuit 112. The regulator circuit may be either one of the regulator circuits 113, 213 and 313 in the first to third embodiments. The booster circuit 112 supplies an output voltage Vout to the bit line control circuit 2, the row decoder 5 and the substrate potential control circuit 7 at reading/writing/erasing times of the memory cell array 1. The booster circuit 112 can supply a stable output potential Vout with reduced overshoot or ripple by the regulator circuit 113.