Dual semiconductor die package with reverse lead form

[0001] This application is based on and claims the benefit of U.S. Provisional Application No. 60/519,586, filed Nov. 12, 2003, entitled Dual Semiconductor Die Package with Reverse Lead Form to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.

[0002] Referring to FIG. 1, a half-bridge configuration 10 is routinely incorporated in ballast circuits, audio class D amplifier circuits, synchronous buck circuit, and the like. A half-bridge configuration includes two power semiconductor devices connected in series. FIG. 1 shows a conventional half-bridge arrangement which includes a low side N-channel power MOSFET 12 and a high side N-channel power MOSFET 14. As is conventionally known, the source of high side power MOSFET 14 is electrically connected to the drain of low side power MOSFET 12. Furthermore, the source of low side power MOSFET 12 is connected to the ground GND while the drain of the high side power MOSFET 14 is connected to the power bus V₊. The output 13 of the half-bridge is taken from the connection between high side power MOSFET 14 and low side power MOSFET 12.

[0003] It is commercially desirable to package high side power MOSFET 14 and low side power MOSFET 12 in a common package to reduce cost and save space. Referring to FIG. 2, it is known to package high side power MOSFET 14 and low side power MOSFET 12 in a common small outline eight lead (S08) package 16. To accommodate two power MOSFETs 12, 14 and S08 includes two die pads 18, each having a receiving area for a respective power MOSFET 12, 14. According to a conventional design, each power MOSFET 12, 14 is electrically connected to a respective die pad 18 at its drain side by a conductive adhesive such as solder, conductive epoxy, or the like. Four of the eight leads in an S08 package are disposed at one side thereof, and the other four at another opposing side thereof. According to a known design, two of the leads, drain leads 20, on each side of the package are electrically connected to the drain of a respective power MOSFET 12, 14 through a die pad 18. Specifically, for example, leads 20 may be integral with a respective die pad 18. In addition, one of the leads, source lead 22, on each side of the package is electrically connected to the source 24 of a respective power MOSFET 12, 14 by wire bonds 26 or the like, while the other lead, gate lead 28 is electrically connected to the gate 30 of a respective power MOSFET 12, 14 by a single wire bond 32. A polymer-based mold compound is usually used to form a molded housing which encapsulates at least the die, the wirebonds, portions of the leads and portions of the die pads. In FIG. 2, the molded housing is removed to better illustrate the components of the package, but the outline of the molded housing 33 is shown by the dotted line surrounding die pads 18.

[0004] A problem often encountered in package design is creepage. Creepage is the current that may travel on the surface of the molded housing of the package between two leads if the two leads are close enough. Creepage becomes particularly important when leads that are at different potential become closer to one another. As semiconductor die become smaller, it becomes possible to use smaller packages. Such packages have shorter lead distances, which pose a creepage problem when smaller, but higher voltage die are used.

[0005] To adapt smaller package outlines to smaller die, a package according to the present invention has one lead removed to increase the tracking distance between leads of high potential difference. Specifically, a drain lead 20 may be removed from a prior art package (see FIG. 2) to increase the tracking distance between source lead 22 and the other drain lead 20.

[0006] According to a first embodiment of the present invention, only one drain lead is removed from one side of the package.

[0007] According to a second embodiment, a drain lead is removed from each side of the package.

[0008] According to another embodiment, the bottom portion of each die pad is exposed for better thermal performance.

[0009] According to another aspect of the invention, the leads of the package extend in the same direction faced by the die, thereby improving the thermal characteristics of the package.

[0010] The semiconductor devices in a package according to the present invention are not limited to N-channel type power MOSFETs. Rather, P-channel power MOSFETs, IGBTs, power diodes, and non-silicon-based power device such as SiC-based and GaN-based power devices may be used instead of N-channel power MOSFETs without deviating from the scope and the spirit of the present invention.

[0011] In addition, a package according to the present invention is not limited to having two identical semiconductor devices. For example, one of the devices may be a power MOSFET and the other a diode.

[0012] Moreover, a package according to the present invention need not be limited to use in a half-bridge configuration. The package can be used in other circuit configurations.

[0013] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

[0014] FIG. 1 shows a half-bridge configuration according to the prior art.

[0015] FIG. 2 shows a schematic of a prior art package.

[0016] FIG. 3 shows a schematic of a package according to the first embodiment of the present invention.

[0017] FIG. 4 shows a schematic of a package according to the first embodiment prior to the removal of the tie bars that connect the leads of the lead frame.

[0018] FIG. 5 shows a schematic of a package according to the second embodiment of the present invention.

[0019] FIG. 6 shows a side plan view of a package according to the present invention.

[0020] FIG. 7 shows a side plan view of a package according to the present invention as incorporated in an electronic apparatus.

[0021] FIG. 8 shows a side plan view of another variation of a package according to the present invention.

[0022] FIGS. 9-11 illustrate alternative embodiments in which diverse semiconductor devices are incorporated in a package according to the present invention.

[0023] FIGS. 12 and 13 illustrate alternative circuit arrangements for a package according to the present invention that includes two power switching devices.

[0024] Referring to FIG. 3, in which like numerals identify like elements, a package according to the present invention includes four leads at one side thereof, and three leads at another opposing side thereof. Specifically, one drain lead 20 is eliminated from one side of the package in order to increase tracking distance 34 between at least one drain lead 20′ and the next closest lead on the same side, i.e. source lead 22′. The increased tracking distance 34, which is made possible by the present invention, allows for the use of a package with a smaller outline but a higher voltage compared to prior art devices of the same outline. Specifically, lead 20′ may be used to connect the drain electrode of high side power MOSFET 14 to the power bus and source lead 22′ can be used to connect source electrode 24 of low side power semiconductor MOSFET 12 to the ground. It should be noted that to better illustrate the components of the package molded housing 35, which encapsulates the die, the wirebonds and the die pads, is only shown by an outline.

[0025] Referring to FIG. 4, according to one aspect of the present invention, one of the drain leads 20 is removed as part of the lead frame design. That is, drain lead 20 is not removed after the lead frame is over molded with mold compound. Rather, the lead frame is designed to be missing one drain lead 20. Thus, as seen in FIG. 4 a tie bar 21′ between drain lead 20′ and source lead 22″ is longer than tie bar 21″ between source lead 22″ and gate lead 28.

[0026] Referring now to FIG. 5, according to a second embodiment of the present invention, tracking distance 34 between drain leads 20′ and source leads 22′ is increased on both sides of the package.

[0027] Referring now to FIG. 6, the leads in a package according to the present invention extend in the same direction that is faced by the die receiving surface of die pads 18. Thus, as seen in FIG. 7, a package according to the present invention can be mounted to the underside of a circuit board 36. Furthermore, less mold compound is necessary to cover the die pad surfaces opposite the die receiving surfaces of die pads 18. As a result, the thermal resistance of a package according to the present invention is improved. In addition, a package according to the present invention can form a base for the circuit board 36 to space the same from an external casing or enclosure 38. A thermal interface 42 such as thermal grease or the like between the package and casing 38 can be used to use the casing as a heat spreader or heatsink.

[0028] Also, a package according to the present invention can be mounted in a conventional manner on the top surface of a circuit board. An insulation layer can be disposed atop the package and a heatsink can be glued to the insulation layer.

[0029] Referring now to FIG. 8, mold compound can be removed to expose the free surface of die pads 18 (the surface opposite to the die receiving surface) to further improve the thermal resistance of the package. A package as modified according to FIG. 8, would exhibit better thermal characteristics, particularly in an environment, such as the one shown by FIG. 7, in that heat may be transferred without hindrance from the mold compound.

[0030] In a package according to the preferred embodiment of the present invention the lead frame (die pads, and leads) are formed from copper, although other materials can be used without deviating from the present invention. In addition, the mold compound for forming the molded housing can be any known molding polymer, however, a high K polymer is preferred if better thermal performance is desired.

[0031] A conventional package can have an Rth J-C through the top of the package of about 160 C/W, when the package has the following characteristics:

• • [0032] 15 mils MP8000AN mold compound (0.67 W/mK)
  • [0033] Rth is for 1 die only (e.g. each die will have 160 C./W)
  • [0034] Die size 85×65 mils

[0035] When a thickness of the mold compound is reduced to about ten mills Rth J-C can be reduced to 110 C/W. Using a high K mold compound can reduce this value by 50 to 75 C/W base on k=11 W/mK.

[0036] The semiconductor devices in a package according to the present invention are not limited to N-channel type power MOSFETs. Rather, P-channel power MOSFETs, IGBTs, power diodes, and non-silicon-based power device such as SiC-based and GaN-based power devices may be used instead of N-channel power MOSFETs without deviating from the scope and the spirit of the present invention.

[0037] In addition, a package according to the present invention is not limited to having two identical semiconductor devices. Referring to FIGS. 9-11, for example, one of the devices may be a power MOSFET and the other a diode. As seen in FIG. 9, the anode electrode of diode 44 can be electrically connected to the drain electrode of MOSFET 46. Such a configuration may be useful in power factor correction circuits. Also, the anode electrode of diode 44 can be electrically connected to the source electrode of MOSFET 46. Such a configuration may be used in a buck converter circuit. In addition, the cathode electrode of diode 44 may be electrically connected to the drain electrode of MOSFET 46. It should be noted that FIGS. 9-11 only illustrate examples of how a diode 44 and a MOSFET 46 contained within a package according to the present invention can be connected and thus adapted for a specific configuration. The present invention, however, is not limited to the specific subject matter shown by FIGS. 9-11.

[0038] Moreover, a package according to the present invention need not be limited to use in a half-bridge configuration. Referring, for example, to FIG. 12, two power MOSFETs, or IGBTs can be co-packaged in a package according to the present invention and then parallel-connected. Also, referring to FIG. 13, two power MOSFETs or IGBTs can be co-package in a package according to the present invention and then connected to form a bidirectional switch. Specifically, for example, if power MOSFETs are used, the drain electrode of one power switch can be connected to the source electrode of the other, and the drain electrode of the other connected to the source electrode of the one power MOSFET to form a bidirectional switch.

[0039] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.