System & method of linking separately compiled simulations

[0001] Modern high performance microprocessors have an ever-increasing number of circuit elements and an ever-rising clock frequency. Also, as the number of circuits that can be used in a central processing unit (CPU) has increased, the number of parallel operations has risen. Examples of efforts to create more parallel operations include increased pipeline depth and an increase in the number of functional units in super-scalar and very-long-instruction-word architectures. As CPU performance continues to increase, the result has been a larger number of circuits switching at faster rates. Thus, from a design perspective, important considerations such as the time needed to complete a simulation and the time needed to compile a CPU design is taken into account.

[0002] As a result, high performance, massively parallel processed environments are used to perform CPU design simulation. FIG. 1 shows a block diagram of a typical computer system (100) used to control and monitor execution of a CPU design simulation. A host computer (114), with associated data store (105), controls the simulation of the CPU design that executes on a simulation hardware (116).

[0003] The host computer (114) includes such hardware and software mechanisms as are needed to manage simulation, e.g., loading execution processor code onto a processor array, transferring test interface files, transferring design symbol files, etc. The data store (105) may contain several kinds of data including hardware definition source code files, clock file data, test interface files, programmable input files, circuit object files, design symbol information (or design database), etc. A general purpose computer (112) with a human interface (110), such as a GUI or a command line interface, together with the host computer (114) support common functions of the simulation environment. A simulation control program (118) executes on the host computer (114) and interacts with the simulation hardware (116) via a test interface (120). The test interface (120) facilitates data transfer between the host computer (114) and the simulation hardware (116).

[0004] The simulation control program (118) controls and monitors simulations executing on the simulation hardware (116). The simulation control program (118) also allows a user to interact with the simulation (and the simulation hardware (116)) between complete simulation cycles. The simulation control program (118) supports important functions of the simulation environment (100). These functions include interactive display and modification of the simulation state, setting of execution breakpoints based on simulation times and states, use of test vector files and trace files, use of hardware definition language (HDL) modules that execute on the host computer (114). The functions are called from the simulation hardware (116), check pointing and restoration of running simulations, the generation of value change dump (VCD) files compatible with waveform analysis tools, and tracing the origin of bad signal states using backtracking techniques.

[0005] The test interface (120) supports the visibility into simulations running on the simulation hardware (116) by applying user-defined input stimuli to selected nodes in the running simulation. The output of the user-defined stimuli may be recorded as a trace of specific signals in the simulation and viewed using post-simulation analysis programs. Alternatively, the output of the user-defined stimuli may be compared to expected output values for signals in the design.

[0006] Prior to executing on the simulation hardware (116), the logic design is verified for accuracy and then compiled. During compilation, the compiler decomposes a logic design into execution processor code that may be executed in parallel on a processor array of the simulation hardware (116) by one or more execution processors. The compiler also produces routing tables and other information, such as routing processor code, control code and a design symbol file. The design symbol file involves recording physical locations where the values of nets and registers have been stored, so that test interface (120) and routines called by the simulation control program (118) may access values of nets and registers.

[0007] Compilation as described above may use a single processor compilation system as shown in FIG. 2. FIG. 2 shows a block diagram of a typical compilation system. The compilation system (130) includes compiler (134), an assembler (138), and a linker (142). The compiler (134) receives as input one or more header files (131) and various source code files (132 A, 132 B). The input files are decomposed by the compiler (134) into an assembly code (136). The assembler (138) receives as input the assembly code (136) and generates an object code (140). The linker (142) then accepts the object code as input and generates an executable file (144). Compiling the source files together, as shown in FIG. 2, results in compile times that increase substantially as the number of source files increase.

[0008] In general, one aspect of the invention relates to a compilation system. The compilation system includes a logic design comprising a plurality of modules, a plurality of compilers arranged to accept as input the logic design and an input file and to separately compile the logic design into a plurality of object files, and a linker arranged to link the plurality of object files to execute the logic design.

[0009] In general, one aspect of the invention relates to a method for compiling a logic design. The method includes inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, compiling separately the plurality of modules into a plurality of object files, and linking the plurality of object files to execute the logic design.

[0010] In general, one aspect of the invention relates to an apparatus for compiling a logic design. The apparatus includes means for inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, means for compiling separately the plurality of modules into a plurality of object files, and means for linking the plurality of object files to execute the logic design.

[0011] Other aspects and advantages of the invention will be apparent from the following description and the appended claims.

[0012] FIG. 1 shows a block diagram of a typical computer system.

[0013] FIG. 2 shows a block diagram of a typical compilation system.

[0014] FIG. 3 shows a block diagram of a massively parallel processed system in accordance with one or more embodiments of the present invention.

[0015] FIG. 4 shows a block diagram of a system board of the system in FIG. 3 in accordance with one or more embodiments of the present invention.

[0016] FIG. 5 shows a flow diagram of preparing a simulation of a cycle-based logic design to execute on a cycle-based system in accordance with one or more embodiments of the present invention.

[0017] FIG. 6 shows a block diagram of a logic design in accordance with one or more embodiments of the present invention.

[0018] FIG. 7 shows a tree diagram of a logic design in accordance with one or more embodiments of the present invention.

[0019] FIG. 8 shows a block diagram of a combinational logic component in accordance with one or more embodiments of the present invention.

[0020] FIG. 9 shows a block diagram of an object file in accordance with one or more embodiment of the present invention.

[0021] FIG. 10 shows a block diagram of a separate compilation system in accordance with one or more embodiments of the present invention.

[0022] FIG. 11 shows a flow diagram of compiling and linking a logic design in accordance with one or more embodiments of the present invention.

[0023] FIG. 12 shows a flow diagram of executing an executable file in accordance with one or more embodiments of the present invention.

[0024] Specific embodiments of the present invention will now be described in detail with reference to the accompanying figures. Like elements in the various figures are denoted by like reference numerals for consistency.

[0025] The present invention involves a method and apparatus for linking separately compiled simulations in a cycle-based system, e.g., a cycle-based simulation system. In the following detailed description of embodiments of the present invention, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the present invention. Embodiments of the present invention may be implemented on any type of computer system or processing environment such as those described above in the Background of the Invention.

[0026] Before describing in further detail the method and apparatus for linking separately compiled simulations, a computer execution environment and a class of simulation systems (e.g., multiple instruction, multiple data (MIMD)) used with one or more embodiments of the present invention is described below.

[0027] In an embodiment of the present invention, the computer execution environment may use execution processors to execute execution processor code on a general purpose computer, such as a SPARC workstation produced by Sun Microsystems, Inc., or specialized hardware for performing cycle-based computations.

[0028] Those skilled in the art will appreciate that the computer systems described herein are merely exemplary embodiments of the present invention may be implemented on any type of computer system or programming or processing environment.

[0029] The specialized hardware is a massively parallel, cycle-based computing system. The system uses an array of execution processors arranged to perform cycle-based computations. One example of cycle-based computation is simulation of a cycle-based design written in a computer readable language, such as HDL (e.g., Verilog, etc.), or a high-level language (e.g., Occam, Modula, C, etc.).

[0030] FIG. 3 shows exemplary elements of a system (200) in accordance with one or more embodiments of the present invention. Cycle-based computation, such as a logic simulation on the system (200), involves one or more host computers (202, 204) managing the logic simulation(s) executing on one or more system boards (220, 222, 224). Each system board contains one or more Application Specific Integrated Circuits (ASIC). Each ASIC contains multiple execution processors. The host computers (202, 204) may communicate with the system boards (220, 222, 224) using one of several pathways. The host computers (202, 204) include interface hardware and software as needed to manage a logic simulation.

[0031] A high speed switch (210) connects the host computers (202, 204) to the system boards (220, 222, 224). The high speed switch (210) is used for loading and retrieval of state information from the execution processors located on ASICs on each of the system boards (220, 222, 224). The connection between the host computers (202, 204) and system boards (220, 222, 224) also includes an Ethernet connection (203). The Ethernet connection (203) is used for service functions, such as loading a program and debugging. The system also includes a backplane (207). The backplane (207) allows the ASICs on one system board to communicate with the ASICs of another system board (220, 222, 224) without having to communicate with an embedded controller located on each system board. Additional system boards may be added to the system by connecting more system boards to the backplane (207).

[0032] FIG. 4 shows a block diagram of a system board in accordance with one or more embodiments of the present invention. The system board is representative of any of the system boards (e.g., system boards (220, 222, 224)) shown in FIG. 2. The system board may include multiple ASICs (e.g., 312, 316, 310, 318, 320, etc.). Each ASIC is connected via a two-dimensional mesh. Each ASIC has four input/output buffers referenced as North (N), South (S), East (E), and West (W). For example, an ASIC (312) has four input/output buffers N (358), S (356), E (360), and W (354). Each ASIC connects to other ASICs using the four input/output buffers, one for each neighboring ASIC. An edge ASIC may connect to other edge ASIC to create a secondary connection. For example, ASIC (312) and ASIC (316) connect using the E and W input/output buffers, respectively, and using their respective S input/output buffers. Another possible connection for edge ASICs is a connection to the backplane (207), which connects to other system boards. For example, ASICs (312, 318, 320) connect to the backplane, each using their respective W input/output buffers. Each ASIC may also connect to external memory in the form of static random access memory (SRAM) through an SRAM interface. For example, ASIC (312) connects to SRAM (314) through SRI (SRAM interface) (362).

[0033] One ASIC on each system board is used as an operative connection to an embedded controller. For example, ASIC (310) uses its S input/output buffer to connect to an embedded controller (304) through a host bridge (308). The embedded controller (304) connects to an Ethernet network (203), associated memory in the form of a synchronous dynamic random access memory (SDRAM) (306), and a high speed switch interface (302). The high speed switch interface (302) connects to the high speed switch (210). The SDRAM (306) may store instructions for the embedded controller (304).

[0034] In accordance with one or more embodiments of the present invention, FIG. 5 shows a process of preparing a simulation of a cycle-based logic design to run on a cycle-based system, e.g., the Phaser System. The process includes three separate phases. The first phase is a verification phase (624). This phase includes a style checker (626), which parses and checks high level design code of a program (629) representing the cycle-based design. The program is checked for adherence to a cycle-based design standard, e.g., synchronous logic design, no combinational logic loops are included, etc. An error action during this phase results from nonconformance to the defined cycle-based design standards. A clock file input (628) defines clocks cycles for the simulation. The output of the verification phase (624) produces a verified cycle-based design.

[0035] The second phase is a compilation phase (630), which receives the verified cycle-based design as input from the verification phase (624). The compilation phase (630) uses a translation component, such as a compiler (632), to compile the verified cycle-based design of the verification phase (624). The compiler (632) decomposes the verified cycle-based design into execution processor code that may be executed in parallel on a processor array of the cycle-based system by one or more execution processors.

[0036] The compiler also produces routing tables and other information, such as routing processor code, interface code, and an annotated symbol table. Routing tables enable static routing of messages sent during execution. An annotation symbol table involves recording physical locations where the values of nets and registers have been stored, so that user interface and Programming Language Interface (PLI) routines may access values of nets and registers during runtime. Input files (634), e.g., PLI and TVI files, etc., provide functionality for items such as system task calls and trace vectors.

[0037] Errors in cycle-based designs input into the compiler (632) cause an error action. The compiler and code generation includes a scheme for routing of messages and placement of compiled execution processor code so that there is some optimization in the choice of which of the parallel execution processors of the simulation hardware to use for certain tasks. This is because the time required for delivery of a message from one processor to another depends upon the data connection component between those execution processors, (i.e., the number of hops the message takes in traversing the data connection component from source processor to destination processor). One skilled in the art can appreciate that compilation of a program may be targeted to a specific execution environment and/or platform, e.g., Phaser system hardware or an appropriate computer, such as a SPARC workstation produced by Sun Microsystems, Inc.

[0038] The third phase is the simulation phase (636), which receives input in the form of execution processor code from the compilation phase (630). A Phaser simulator driver (638) (PHSIM) typically runs on a host computer and controls and monitors execution of simulations executing on the cycle-based system.

[0039] The host computer includes such hardware and software mechanisms as are needed to manage simulation, e.g., loading execution processor code onto a processor array. PHSIM (638) enables user interaction with a simulation using a graphical user interface (GUI) or with a command line interface, interactive modification of simulation state, break-pointing, test vector use, system task functionality, signal tracing, single-stepping on clock cycles, and other functionalities. A simulation cycle begins with one or more simultaneous clock edges and completes when every dependent event has completed evaluation. The simulation phase (636) may run on system hardware (640), which is designed for cycle-based computation, or on an appropriate computer, such as a SPARC workstation (642) produced by Sun Microsystems, Inc.

[0040] The present invention involves a compilation system that enables the linking of separately compiled modules in a massively parallel processor environment. In one embodiment of the present invention, referring to FIG. 5, a verified cycle-based logic design enters the verification phase (624), typically with numerous modules representing various granularity of logic (i.e., top-level modules or sub-modules). These modules may be written in a computer readable language, such as HDL (e.g., Verilog, etc.). In one or more embodiments, the verified logic design may include several top-level modules.

[0041] FIG. 6 shows a block diagram of a logic design in accordance with one or more embodiments of the present invention. Likewise, FIG. 7 shows a tree diagram of a logic design in accordance with one or more embodiment of the present invention. Both figures show a logic design (701) that includes a top-level module (700) and sub-modules (702, 704).

[0042] After the logic design (701) exits the verification phase in FIG. 5, the modules (700, 702, 704) are compiled. The modules (700, 702, 704) that are compiled define a compilation space (703). At compile time, input files e.g., Verilog parameters, clock file, port description file, etc., associated with the logic design should be specified.

[0043] In one or more embodiments, a port description file describes the specification of clocking characteristics of the signals within the logic design. FIG. 8 shows a block diagram of a combinational logic component in accordance with one or more embodiments of the present invention. The sub-module (702) represents the combinational logic component (750) with two input ports (752, 754) and one output port (756). The port description file describes characteristics of signals input to ports (752, 754) and output of port (756).

[0044] In one or more embodiments, a module (700) may be equivalent to a logic design (701). Alternatively, in one or more embodiments, a module is a subset of a logic design (701). For example, only several top-level modules (i.e., modules with multiple sub-modules) may be independently compiled together or a top-level module may be independently compiled together with several sub-modules. Optionally, only selected modules may be compiled independently. For example, FIGS. 6 and 7 only show modules (700, 702, 704) (shaded circles in FIG. 7), however modules (700, 702, 704) represent only a subset of the logic design (701).

[0045] In one or more embodiments, each port is either a clock port or a logical port whose clock phase is specified. Moreover, logical ports may have several communication instructions divided across an execution processor. The logical port may be uni-directional or bi-directional, e.g., in port, out port, in/out port. Additionally, an arbitrary number of entries are also used to describe the physical port; these entries describe the physical communication instructions.

[0046] The modules (700, 702, 704) are separately compiled. Separate compilation is a technique that allows parts of a system to be compiled individually into object code and combined later by a linker to create an executable file or execute on the system. In one or more embodiments of the invention, each part of the logic design may be compiled completely independent of all other modules of the logic design.

[0047] FIG. 10 shows a block diagram of a separate compilation system in accordance with one or more embodiments of the present invention. The separate compilation system (801) includes a plurality of instances of a compilers (632 A, 632 B, 632 C) and a linker (806). The modules (700, 702, 704) of the logic design are input to respective compilers (632 A, 632 B, 632 C). In addition to the modules (700, 702, 704), input files (634 in FIG. 9) (e.g., PLI files, TVI files, clock files, port description files, etc.) are also input to the compilers (632 A, 632 B, 632 C). The compilers (632 A, 632 B, 632 C) separately compile the modules (700, 702, 704) to generate object files (800, 802, 804). A linker (806) links the object files (800, 802, 804) to generate an executable file (808) to execute the logic design.

[0048] The object files (800, 802, 804) that are produced by the compilers (632 A, 632 B, 632 C) and linked by the linker (806) may be maintained in a particular format. FIG. 9 shows a block diagram of an object file in accordance with one or more embodiments of the present invention. The object file (800, 802, 804) includes a body code section (900) and an external linkage information section (902). The body code section (900) includes the fixed instructions (e.g., execution processor code and routing processor code) used during the computation of the logic design, and the external linkage information section (902) provides information regarding how the module communicates with the other modules in the logic design. The code in the body code section (900) is resolved at compile time, however the code (or data) in the external linkage information section (902) is not.

[0049] In one or more embodiments, modules having the same body code sections may be replicated, while the external linkage information section of each module is stored individually. In one or more embodiments, a body code section in an object file may include instructions for execution processors, an index for the execution processors, instructions for routing processors, an index for the routing processors, initial values for registers, an index for initial values of registers, etc. Additionally, in one or more embodiments, an external linkage information section in an object file may include data regarding the external linkage to ports in top-level modules.

[0050] Additionally, in one or more embodiments, after linking object code information, the overall structure of the logic design may be encapsulated in an additional section, i.e., module description section. In one or more embodiments, the module description section is used to load the same body of code into more than one execution processor.

[0051] One skilled in the art will appreciate that an object file with a body code section and linkage code section may be compiled and linked for any module, i.e., source file, that communicates with other modules via statically scheduled message routing system as described in FIGS. 3-4.

[0052] The object files (800, 802, 804) are linked by the linker (806) to execute the logic design (701). In one embodiment, an executable file (808) is created. The executable file (808) may be embodied in variety of data structures, e.g., a hierarchical table, a linked list, an array, etc. In one or more embodiments, a data structure of the executable file lends to execution in a massively parallel processor environment. If external communication is required by a compiled module, the linker may insert a wait instruction in the body code section of the executable file (808). Accordingly, during execution, the wait instruction stalls the module until the complete execution of the module from which a computed value is required. In an alternative embodiment, the object files (800, 802, 804) are linked during execution of the logic design. In this case, the individually compiled object files (800, 802, 804) are linked and loaded during execution.

[0053] FIG. 11 shows a flow diagram of compiling and linking a compilation space in accordance with one or more embodiments of the invention. Initially, a plurality of modules, i.e., a logic design, and input files are input to a plurality of instances of compilers, respectively (Step 1000). The plurality of modules represent how the functionality of various logic components and how the logic components communicate. In the modules, the communication between logic components is accomplished with statically scheduled messages.

[0054] The modules are compiled separately to generate a plurality of object files (Step 1002). The plurality of object files contain two sections: a body code section and an external linkage information section. The body code section includes the functionality and/or data embodied by the logic components. The external linkage information section houses the information required for modules to communicate properly. The plurality of object files are linked to execute the logic design (Step 1004). In one or more embodiments, an executable file is generated. The executable file may be modified, for example, by directives or wait instructions being inserted, such that during execution the modules communicate properly. In one or more embodiments, during execution the plurality of object files are linked and loaded. Consequently, an executable file produced by the abovementioned linking method and apparatus is executed in two portions of a major cycle that is newly calculated.

[0055] FIG. 12 shows a flow diagram of executing an executable file in accordance with one or more embodiments of the present invention. Initially, a new major cycle is calculated by adding a longest cycle produced by a body code section and a cycle produced by an external linkage information section (Step 2000). The external linkage information section is relatively small.

[0056] In a first portion (or computation portion) of the new major cycle, the body sections of code of the executable file are executed (Step 2002). The body sections of code are entirely computational and do not require communication with external modules. In a second portion (or linkage portion) of the new major cycle, the external linkage information section is resolved. Meaning, the values input to external modules are resolved (i.e., located in known registers) before the beginning of the cycle and the value output to external modules are resolved at the end of the cycle of the current cycle.

[0057] In one or more embodiments of the present invention, the linkage portion is executed after the computation portion, however one skilled in the art will appreciate that the linkage may occur first.

[0058] In one or more embodiments of the present invention, linking a plurality of object files requires a portion of code to be relocated. Relocation is achieved using the infrastructure provided by the message routing system. Further, in one embodiment, the relocation may occur at the lowest level of a hardware compute hierarchy, e.g., a processor level. An example of a hardware computer hierarchy (in descending order) includes a system, a board, a chip, a sub-cluster, and a processor. Accordingly, operations, e.g., rotation, translation, mirror image, may result in an optimization of a critical path, thereby minimizing the number of processors used after the linking. The critical path is the longest path of an intermediate form graph derived from a logic design that determines the number of major and minor cycles. One of ordinary skill in the art will appreciate that minimizing relocation of code during linking avoids an expensive routing (and re-routing procedure).

[0059] Advantages of embodiments of the present invention may include one or more of the following. In one or more embodiments, the present invention improves the compilation speed. Because modules, i.e., source files, may be compiled separately, compilation time may be decreased. In other words, a compiler is not required to handle multiple source files simultaneously. In some instances, compilation time may be reduced in the order of hours with the present invention. Consequently, there is no need to transmit source trees and elaborate make files and minimal copies of commonly used libraries may be used providing storage savings and easing the distribution of files. Additionally, linking in this manner increases the security, because capturing a logic design from individually compiled object files is substantially more difficult.

[0060] In one or more embodiments, the present invention allows for a compilation space that is a subset of a simulation space to be compiled. Advantageously, this allows particular modules to be modified and compiled without necessitating the compilation of an entire simulation space thereby reducing overall compile time.

[0061] In one or more embodiments, the present invention allows an object file to be generated having a body code section and an external linkage information section. Accordingly, during execution, instructions within the body code section may be executed in one portion of a major cycle and communication may be executed in a remaining portion of a major cycle thereby effectively reducing input/output communication time. One skilled in the art can appreciate that these portions of a major cycle may overlap during execution.

[0062] While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.