US 2004/0142527 A1Application
High voltage tolerant ESD design for analog and RF applications in deep submicron CMOS technologies
Publication Date:2004-07-22
•41 Claims
•6 Drawing Sheets
Abstract
The invention describes structures and a process for providing ESD semiconductor protection with reduced input capacitance that has special advantages for high frequency analog pin I/O applications. The structures consist of a first and second NMOS serial pair whose capacitance is shielded from the I/O pins by a serial diode. The first serial pair provides an ESD voltage clamp between the I/O pin and the Vcc voltage source. The second pair provides an ESD voltage clamp between the I/O pin and Vss, or ground voltage source. A NMOS device whose gate is dynamically coupled to the ESD energy through capacitance and a RC network enhances the triggering of both pairs. The serial pairs can be used separately to match specific application requirements or used together.
Metadata
Inventor
- Chung-Hui Chen
Application Information
Application Number:US 10/348,388
Filing Date:2003-01-21
Priority Date:2003-01-21
Patent Drawings (6 sheets)
Description
(1) FIELD OF THE INVENTION
[0001] The present invention relates generally to the structure and process for an ESD protection arrangement for high voltage tolerant ESD protection for analog applications requiring low capacitance such as radio frequency and high speed analog transceivers.
(2) DESCRIPTION OF PRIOR ART
[0002] Because of high input impedance and thin oxide gate structures, the problem of electrostatic discharge damage (ESD) with field effect transistor (FET) devices can be severe. Therefore the input/output (I/O) circuit locations or pins usually have a protective device connected between the I/O pin and the internal circuits which allows the ESD current to be shunted to an alternative voltage source, typically ground, protecting the active internal circuits from damage.
[0003] There can be several different types of device structures used for these protective devices, such as single diodes, stacked diodes, field effect transistor devices, and silicon controlled rectifiers (SCR).
[0004] With prior art devices, the capacitance associated with the ESD protection device on the active circuit input pin can be a concern as circuit speeds increase. A typical prior art protection circuit scheme is represented in FIG. 1 . The active circuit input-output (110) terminal or pin 10 is connected to a current limiting resistor R and then to the secondary ESD clamp or protection circuit device NMOS Mn12. A complimentary MOS (CMOS) inverter buffer 14 with Mp and Mn precede the input to the internal active logic circuits 16.
[0005] The secondary ESD clamp 12, is typically a gate-grounded short channel NMOS shown in FIG. 1 as Mn12. This clamps the ESD overstress voltage represented by the generator element 20 to a safe voltage for the internal circuits 16. To provide a high ESD protection level, a robust device such as a SCR, field thick-oxide device, or long channel NMOS is used as the primary ESD clamp 18 to bypass ESD current Iesd to a secondary voltage source, Vss or ground.
[0006] The primary clamp element 18 must be triggered on before the secondary clamping device 12 is damaged by the overstress Iesd current. The resistor R is required to limit the ESD current flowing in the secondary clamp 12. This resistor can be in the order of thousands of ohms.
[0007] The large junction capacitance of the clamp devices connected in an electrical parallel configuration together with the resistor R can cause a long RC delay. For current mode input signal applications, high frequency applications and analog applications this RC input loading cannot be tolerated. For this application a configuration is required that minimizes the input capacitance and eliminates the series resistor R.
[0008] The invention provides a unique structure and method, which minimizes the capacitance on the I/O pin while still providing appropriate high voltage tolerant (HVT) ESD protection without the need for current limiting resistance.
[0009] The following patents and reports pertain to ESD protection.
[0010] U.S. Pat. No. 6,606,752 (Williams) shows an ESD circuit for RF and analog applications.
[0011] U.S. Pat. No. 6,284,616B1 (Smith) Discusses an ESD circuit with a high voltage tolerance.
[0012] U.S. Pat. No. 5, 477,414 (Li et al.) shows an ESD protection circuit.
[0013] U.S. Pat. No. 6,008,970 (Maloney et al.) reveals a power supply clamp circuit for ESD protection.
[0014] The following technical reports discuss ESD protection methods.
[0015] Richier et al., Investigation on Different ESD Protection Strategies Devoted to 3.3 V RF Applications (2 Ghz) in a 0.18 um CMOS Process. EOS/ESD Symposium 2000, PP 252 to 259.
[0016] Paul Leroux, et al., A 0.8 dB NF ESD Protected 9 Mw CMOS LNA. Proceedings of the 2001 ISSC PP 410 to 411.
[0017] Ming-Dou Ker, et al., ESD Protection Design on Analog Pin with Very Low Input Capacitance for High Frequency or Current-Mode Applications IEEE Journal of Solid-State Circuits, Volume 35; Issue 8; August 2000, PP 1194 to 1199.
[0018] Ming-Dou Ker, et al, Dynamic-Floating-Gate Design for Output ESD Protection in a 0.35 um CMOS cell library, Proceedings of the 1998 ISCAS Volume 2; 1998, PP 216 to 219.
SUMMARY OF THE INVENTION
[0019] Accordingly, it is the primary objective of the invention to provide an effective structure and manufacturable method for providing an effective ESD clamping protection element while at the same time reducing the capacitive loading on the I/O circuits.
[0020] It is a further objective of the invention to improve ESD protection for high frequency and analog applications by providing a low input capacitance structure that will have minimum impact on device performance while maintaining robust ESD protection levels.
[0021] A still additional objective of the invention is to provide the ESD protection with reduced capacitance without changing the characteristics of the internal circuits being protected and by using a process compatible with the process of integrated MOS device manufacturing.
[0022] The above objectives are achieved in accordance with the methods of the invention that describes a structure and a manufacturing process for semiconductor ESD protection devices with reduced input capacitance.
[0023] One embodiment of the invention utilizes two NMOS series devices as a ESD energy clamp from I/O pin to Vcc, shielded from the I/O pin by a diode. The source of the second or top NMOS comprising the clamp is connected to Vcc while its gate is connected to the drain of an ESD trigger enhancing NMOS. The gate of the trigger enhancing NMOS is connected to the midpoint of an RC string between Vcc and ground. The drain of the second series NMOS is connected to the drain of the first series NMOS whose gate is connected to Vcc and whose source is connected to the cathode of the top or second diode of a series diode string.
[0024] The second diode anode is connected to the cathode of the first or bottom diode in the string and also connected to the I/O pin. The configuration protects against ESD charge flow from pin to Vcc. The relatively small second diode capacitance is stacked in series with the larger capacitance of the NMOS pair which provides an effective reduced capacitance from pin to Vcc of approximately the junction capacitance of the diode.
[0025] Another embodiment of the invention utilizes two series NMOS devices as a ESD clamp from I/O pin to Vss or ground. The clamp is shielded from the input pin by a series diode and with the source of the top or second NMOS connected to ground. This embodiment protects against any ESD charge from pin to ground. Because of the parasitic junction diode between the first NMOS source and substrate, the capacitance between pin and ground is essentially that of the two small diodes in parallel, which is smaller than that of the NMOS pair.
[0026] Yet another embodiment of the invention incorporates both the series NMOS device clamp to Vcc and the series NMOS device clamp to Vss or ground. Both pairs of devices are shielded from the I/O pin by a diode to reduce the capacitance seen by the I/O pin. This embodiment protects against ESD charge energy both from pin to Vcc and from pin to ground.
[0027] All embodiments utilize a a trigger enhancing NMOS whose gate is dynamically coupled to the ESD energy and to a RC circuit. The source of the trigger enhancing NMOS is typically connected to a gate of an NMOS in the clamp circuits to control the conduction duration.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] FIG. 1 shows a schematic representation of a prior art ESD protection scheme.
[0029] FIGS. 2A through 2D shows the configurations for ESD testing on Analog Input/Output Pins. FIGS. 2A and 2C illustrates the test case of positive voltage to Vss/Gnd. (PS Mode), FIGS. 2B and 2D is negative voltage to Vss/Gnd. (NS Mode).
[0030] FIG. 3A shows the test configuration for Positive Mode differential ESD voltage and FIG. 3B shows the test configuration for Negative Mode ESD differential voltage.
[0031] FIG. 4A shows a simplified schematic of one embodiment of the invention for ESD protection for I/O Pin to Vcc while FIG. 4B shows the detailed schematic.
[0032] FIG. 5A shows a simplified schematic of one embodiment of the invention for ESD protection for I/O Pin to Vss or ground while FIG. 5B shows the detailed schematic. ESD protection for Pin to Vss Or ground.
[0033] FIG. 6A shows a simplified schematic of one embodiment of the invention for ESD protection for I/O Pin to Vcc and I/O pin protection to Vss or ground. FIG. 6B shows the detailed schematic.
[0034] FIG. 7 is a flow chart of the process of forming the protection devices for ESD protection from I/O pin to Vcc and I/O pin to Vss or ground.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0035] FIG. 4A shows a simplified schematic of the invention embodiment for ESD protection from I/O pin to Vcc. The ESD energy is clamped to Vcc by the NMOS string 120. Since capacitance elements in series add like resistors in parallel, the diode D2 shields the NMOS ESD clamp string 120 capacitance from the I/O pin 110 and internal active circuits. The capacitance of the diode is much less than the capacitance of the NMOS series string ESD clamp 120, and therefore the capacitance seen by the I/O pin 110 is essentially the relatively small capacitance of the diode D2.
[0036] The detailed schematic is shown in FIG. 4B . The cathode of the first diode D1 is connected to the I/O pin 10 while the anode is connected to a second voltage source, Vss, typically ground.
[0037] Diode D1 provides a shunt path for negative ESD energy to ground.
[0038] The cathode of the second diode D2 is connected to the source of NMOS Mn1 while the anode of D2 is connected to the I/O pin 110 and the cathode of diode D1. Diode D2 shields the I/O pin 110 from the relatively large capacitance of the series NMOS ESD clamp string 120. The gate of Mn1 is tied to a first voltage source Vcc while the drain is connected to the drain of Mn2. The gate of Mn2 is connected to the drain of a trigger enhancing NMOS Mn0 while the source of Mn2 is connected to Vcc.
[0039] The source of the trigger enhancing NMOS Mn0 is connected to the second voltage source, Vss, typically ground, as is the channel substrate for all the NMOS devices. The gate of Mn0 is connected to the first end of a resistor R whose second end is connected to a first voltage source, Vcc. The first end of resistor R and the gate of Mn0 are also connected to the first end of a capacitor whose other end is connected to a second voltage source, Vss or ground.
[0040] When a positive ESD event takes place at the I/O pin 110 with respect to Vcc, the energy is transferred through diode D2 and through the parasitic drain to gate capacitance of Mn1 turning it on. The energy then appears on Vcc which enables Mn0 to turn on after a time delay determined by the RC time constant. This grounds the gate of Mn2 after a suitable delay turning it off to complete the discharge cycle.
[0041] FIG. 5A is a simplified schematic of the embodiment of the invention clamping ESD energy to the second voltage source, Vss, or ground by means of the ESD clamping element 130. The clamp is again shielded from the input pin by diode D2.
[0042] FIG. 5B illustrates the schematic details of this embodiment of the invention. The I/O pin 110 is connected to the anode of D2 and cathode of D1 with the anode of D1 connected to a second voltage source, Vss, typically ground. The cathode of diode D2 is connected to the source of NMOS Mn3. The gate of Mn3 is connected to the first voltage source, Vcc, and the drain to the drain of the NMOS Mn4. The gate of Mn4 is connected to the drain of NMOS Mn0 and the source is connected to the second voltage source, or ground.
[0043] The source of Mn0 is connected to the second voltage source, Vss or ground, while the gate is again connected to the first end of a resistor R and the first end of a capacitor C. The second end of the resistor R is connected to the first voltage source, Vcc, and the second end of the capacitor is connected to the second voltage source Vss, typically ground.
[0044] Since the device substrate is grounded, the parasitic Mn3 source to substrate diode D3 is noticed effectively in electrical parallel with diodes D1 and D2 as shown in FIG. 5B . The combined diode effect on I/O pin loading is still substantially lower than for the ESD clamp 130 if it were unshielded.
[0045] The circuit turn on is similar to that described above, but with the ESD energy being shunted to Vss or ground through Mn3 and Mn4 until Mn4 is turned off by the dynamic gate action of Mn0.
[0046] Another embodiment of the invention is shown in FIGS. 6A and 6B . FIG. 6A shows the ESD clamp 120 to the first voltage source, Vcc, and the ESD clamp 130 to the second voltage source or ground. This embodiment incorporates the protection elements of ESD energy from I/O pin 110 to Vcc and from the I/O pin 110 to the second voltage source, Vss or ground. Both ESD clamps are shielded from the I/O pin 110 by diode D2 which essentially reduces the capacitance seen at the I/O pin 110.
[0047] The schematic details are shown in FIG. 6B . This embodiment has the anode of D2 connected to the I/O pin 110 and to the cathode of diode D1. The anode of diode D1 is connected to a second voltage source, Vss, typically ground. The cathode of diode D2 is connected to the source of NMOS Mn1 and the source of NMOS Mn3.
[0048] Since the device substrate is tied to the second voltage source, Vss or ground, the parasitic junction diode D3 of the source to substrate junction of NMOS Mn3 is essentially in parallel with diodes D1 and D2. The cathode of parasitic diode D3 is essentially connected to the cathode of D2, and the anode of D3 is essentially connected to the second voltage source or ground.
[0049] The drain of NMOS Mn1 is connected to the drain of NMOS Mn2, the second NMOS in the series string of the ESD clamp 120. The gate of Mn1 is tied to the first voltage source Vcc, as is the drain of Mn2, and the gate of NMOS Mn2 is tied to the drain of NMOS Mn0. The gate of NMOS Mn0 is tied to the junction of R and C elements with the second side of the resistor R tied to Vcc and the second side of the capacitor C is tied to the second voltage source Vss or ground.
[0050] The ESD clamp 130 consists of an NMOS series string Mn3 and Mn4. As previously mentioned, the source of Mn3 is connected to the cathode of diode D2 and the source of NMOS Mn1. The gate of Mn3 is tied to the first voltage source, Vcc, and the drain of Mn3 is connected to the drain of NMOS Mn4. The source of Mn4 is connected to the second voltage source, Vss or ground. The gate of NMOS Mn4 is connected to the gate of NMOS Mn0.
[0051] The process for creating the embodiment of the invention with clamps to both the first voltage source, Vcc, and to the second voltage source, Vss or ground, is illustrated in FIG. 7 .
[0052] Element 60 of the process flow chart of FIG. 7 illustrates the initiation of the process by creating on a semiconductor substrate the first series pair Mn1 and Mn2 and the second series pair Mn3 and Mn4. It also describes the creation of diodes D1, D2, and D3. The diode D3 is created from the parasitic elements of the third NMOS, Mn3, source to substrate junction. FIG. 7 element 60 also describes the creation of the resistor R and capacitor C components of the RC network, and the trigger enhancing NMOS device Mn0, on the same substrate.
[0053] Continuing with element 62 of FIG. 7 , the diode network is formed by connecting the anode of the second diode D2 to the cathode of the first diode D1 and to the semiconductor I/O circuit 110. The cathodes of the second and third diodes are connected together and to the source elements of the first and third NMOS elements, Mn1 and Mn3. The process continues by connecting the anodes of the first and third diodes to a second voltage source, Vss, typically ground.
[0054] Element 64 describes the connection of the source of the special trigger enhancing NMOS Mn0 as well as the substrate to a second voltage source, Vss or ground, and the gate of Mn0 to the first ends of the resistor and capacitor.
[0055] The process continues by connecting the first side of the resistor R to the first side of the capacitor C as well as to the gate of the trigger enhancing NMOS Mn0 as indicated in FIG. 7 element 66. The second side of the resistor R is connected to a first voltage source Vcc and connecting the second side of the capacitor C to a second voltage source Vss or ground completes the RC circuit.
[0056] Element 68 describes the connecting of the drain of NMOS Mn1 to the drain of the second NMOS, Mn2, and the gate of Mn1 and source of Mn2 to a first voltage source, Vcc. The gate of NMOS Mn2 is connected to the source trigger enhancing NMOS Mn0.
[0057] FIG. 7 element 70 illustrates the formation of the second ESD clamp element 130 by connecting the gate of the third NMOS Mn3 to a first voltage source, Vcc, connecting the drain of the third NMOS Mn3 to the drain of the fourth NMOS Mn4, connecting the source of the fourth NMOS device Mn4 to the second voltage source, Vss, typically ground, and connecting the gate of NMOS Mn4 to the gate of the trigger enhancing NMOS Mn0.
[0058] The test results of the high voltage capability device are shown in table 1 which compares the normal protection device to the invention device. The test conditions are shown in schematic form in FIGS. 2A through 2C and FIGS. 3A and 3B .
[0059] As can be seen from table 1, the invention device affords the same degree of protection from ESD as indicated by the machine model (MM) and human body model (fBM) test results. The invention provides the additional advantage of shielding the relatively high capacitance of the clamp circuits from the I/O circuits. This enables the invention to be beneficial in applications requiring reduced capacitance such as radio frequency applications and analog transceivers.
Table 1: Measured Human Body Model (HBM) and Machine Model (MM) Protection for Traditional Analog Pin Versus Invention High Voltage Tolerance (HVT) Analog Pin
[0060]
| TABLE 1 | ||||||
|---|---|---|---|---|---|---|
| Positive | ||||||
| Pin to | Negative | |||||
| PS | NS | PD | ND | Pin | Pin to Pin | |
| Mode | Mode | Mode | Mode | Mode | Mode | |
| Non- | 7 KV | 6 KV | 7 KV | 6 KV | 7 KV | 6 KV |
| HVT | ||||||
| pin | ||||||
| HBM | ||||||
| HVT | 6.5 KV | 6 KV | 7 KV | 7 KV | 7.5 KV | 6 KV |
| pin | ||||||
| HBM | ||||||
| Non- | 600 V | 550 V | 600 V | 500 V | 600 V | 550 V |
| HVT | ||||||
| pin MM | ||||||
| HVT | 550 V | 550 V | 600 V | 650 V | 650 V | 550 V |
| pin | ||||||
| MM | ||||||
[0061] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
Claims
1. A low capacitance sericonductor 110 ESD protection structure on a substrate comprising:
a first and second NMOS in series on said substrate with said second NMOS connected to a first voltage source;
a first and second diode on said substrate connecting to said semiconductor 1/o;
a trigger enhancing NMOS on said substrate connecting to said second NMOS; and
a resistor and capacitor element on said substrate connecting with said trigger enhancing NMOS.
2. The protection structure of claim 1 wherein said second diode cathode is connected to the source of said first NMOS and said second diode anode is connected to said first diode cathode and to said semiconductor I/O pin.
3. The protection structure of claim 1 wherein said first diode anode and said substrate are connected to a second voltage source.
4. The protection structure of claim 1 wherein said first NMOS drain is connected to said second NMOS drain, and said first NMOS gate and said second NMOS source are connected to a first voltage source.
5. The protection structure of claim 1 wherein said second NMOS gate is connected to said trigger enhancing NMOS drain.
6. The protection structure of claim 1 wherein said trigger enhancing NMOS source is connected to a second voltage source and said NMOS gate is connected to the first end of said resistor and the first end of said capacitor.
7. The protection structure of claim 1 wherein the second end of said resistor is connected to the first voltage source.
8. The protection structure of claim 1 wherein the second end of said capacitor is connected to the second voltage source.
9. The protection structure of claim 1 wherein said first and said second NMOS devices form an ESD energy clamp between said semiconductor I/O and said first voltage source.
10. The protection structure of claim 1 wherein said second diode shields said I/O pin from said capacitance of said ESD energy clamp thereby presenting a lower capacitance to said I/O pin.
11. A low capacitance semiconductor I/O ESD protection structure on a substrate comprising:
a first and second NMOS in series on said substrate whereby said second NMOS is connected to a second voltage source;
a first and second diode on said substrate connecting to said semiconductor I/O, and a third diode connected to said second diode;
a trigger enhancing NMOS on said substrate connecting to said second NMOS; and
a resistor and capacitor element on said substrate connecting with said trigger enhancing NMOS.
12. The protection structure of claim 11 wherein said second diode cathode is connected to the source of said first NMOS and to the cathode of said third diode, and said second diode anode is connected to said first diode cathode and to said semiconductor I/O.
13. The protection structure of claim 11 wherein said first and said third diode anodes and said substrate and said second NMOS source are connected to said second voltage source.
14. The protection structure of claim 11 wherein said first NMOS gate is connected to a first voltage source and said first and said second NMOS drains are connected together.
15. The protection structure of claim 11 wherein said second NMOS gate is connected to said trigger enhancing NMOS drain.
16. The protection structure of claim 11 wherein said trigger enhancing NMOS source is connected to said second voltage source and said NMOS gate is connected to the first end of said resistor and the first end of said capacitor.
17. The protection structure of claim 11 wherein the second end of said resistor is connected to said first voltage source.
18. The protection structure of claim 11 wherein the second end of said capacitor is connected to aid second voltage source.
19. The protection structure of claim 11 wherein said first and said second NMOS devices form an ESD energy clamp between said semiconductor I/O and said second voltage source.
20. The protection structure of claim 11 wherein said second diode shields said semiconductor I/O from said capacitance of said ESD energy clamp thereby presenting a lower capacitance to said semiconductor 110.
21. A low capacitance semiconductor I/O ESD protection structure on a substrate comprising:
a first, second, third and fourth NMOS device on said substrate;
a first and a second diode device connected to said semiconductor 110, and a third diode connected between said second diode and a second voltage source;
a trigger enhancing NMOS device on said substrate connecting to said second and fourth NMOS device; and
a resistor and capacitor element on said substrate connected with said trigger enhancing NMOS device.
22. The protection structure of claim 21 wherein said second diode cathode is connected to the source of said first and said third NMOS and to the cathode of said third diode and said second diode anode is connected to said first diode cathode and to said semiconductor I/O.
23. The protection structure of claim 21 wherein said first and said third diode anodes and said substrate and said fourth NMOS source are connected to said second voltage source.
24. The protection structure of claim 21 wherein said first NMOS gate and said second NMOS source and said third NMOS gate are connected to a first voltage source and said first and said second NMOS drains are connected together.
25. The protection structure of claim 21 wherein said second NMOS gate is connected to said trigger enhancing NMOS drain.
26. The protection structure of claim 21 wherein said trigger enhancing NMOS source is connected to said second voltage source and said NMOS gate is connected to the first end of said resistor and the first end of said capacitor.
27. The protection structure of claim 21 wherein the second end of said resistor is connected to said first voltage source.
28. The protection structure of claim 21 wherein the second end of said capacitor is connected to said second voltage source.
29. The protection structure of claim 21 wherein the drain of said third NMOS and the drain of said fourth NMOS are connected together.
30. The protection structure of claim 21 wherein the gate of said fourth NMOS is connected to the gate of said trigger enhancing NMOS.
31. The protection structure of claim 21 wherein said first and said second NMOS devices form an ESD energy clamp between said semiconductor I/O and said first voltage source and said third and said fourth NMOS form an ESD energy clamp between said semiconductor I/O and said second voltage source.
32. The protection structure of claim 21 wherein said second diode shields said I/O pin from said capacitance of said ESD energy clamp thereby presenting a lower capacitance to said I/O pin.
33. A method of forming a low capacitance semiconductor I/O ESD protection structure on a substrate comprising:
creating a first, second, third and fourth NMOS device on said substrate;
creating a first, second and third diode on said substrate with said second diode connected to said first and third NMOS device;
creating a trigger enhancing NMOS on said substrate connected to said second and said fourth NMOS device; and
creating a resistor and capacitor element on said substrate connected to said trigger enhancing NMOS.
34. The method according to claim 33 whereby said third diode is formed by the parasitic junction characteristics of the source to substrate junction of said third NMOS device.
35. The method according to claim 33 whereby said diode elements form part of said protection structure by connecting the anode of said second diode to the cathode of said first diode and to said semiconductor I/O, and connecting the cathodes of said second and third diodes to the source of said first and third NMOS, and connecting the anode of said first and third diodes to a second voltage source.
36. The method according to claim 33 whereby said trigger enhancement NMOS forms part of said protection structure by connecting the source of said NMOS and said substrate to said second voltage source, and connecting the gate of said NMOS to the first ends of said resistor and said capacitor.
37. The method according to claim 33 whereby said resistor and capacitor form part of said protection structure by connecting the second end of said resistor to a first voltage source, connecting the first end of said resistor to said first end of said capacitor, and connecting the second end of said capacitor to said second voltage source.
38. The method according to claim 33 whereby said first and second NMOS devices form part of said protection structure by connecting the drain of said first NMOS to the drain of said second NMOS and connecting the gate of said first NMOS and the source of said second NMOS to said first voltage source and the gate of said second NMOS to the source of said trigger enhancing NMOS.
39. The method according to claim 33 whereby said third and said fourth NMOS device form part of said protection device by connecting the gate of said third NMOS to said first voltage source, connecting the drain of said third NMOS to the drain of said fourth NMOS, connecting the source of said fourth NMOS to said second voltage source, and connecting the gate of said fourth NMOS to said gate of said trigger enhancement NMOS.
40. The method according to claim 33 whereby the connection of said first and second NMOS devices form an ESD voltage clamp for ESD voltages between said semiconductor I/O and said first voltage source.
41. The method according to claim 33 whereby the connection of said third and fourth NMOS devices form an ESD voltage clamp for ESD voltages between said semiconductor I/O and said second voltage source.