Semiconductor integrated circuit device and a method of manufacturing the same

[0001] The present invention relates to a semiconductor device and a manufacturing technique thereof. More particularly, it relates to a technique effectively applicable for a system IC (Integrated Circuit) having a nonvolatile storage element, and a capacitor element or a resistor element.

[0002] As a semiconductor integrated circuit device, for example, a nonvolatile storage device designated as, for example, a flash memory or an EEPROM (Electrically Erasable Programmable Read Only Memory) is known. For the flash memory, there is known a memory cell of a one-transistor system in which the memory cell is composed of one nonvolatile storage element, or a memory cell of a two-transistor system in which one nonvolatile storage element and one selecting MISFET (Metal Insulator Semiconductor Field Effect Transistor) are connected in series. Whereas, for the nonvolatile storage element, there is known a floating gate type in which information is stored in a floating gate electrode between a semiconductor substrate and a control gate electrode, a MNOS (Metal Nitride Oxide Semiconductor) in which a NO (Nitride/Oxide) film is used as a gate insulating film between a semiconductor substrate and a gate electrode, so that information is stored in this gate insulating film, a MONOS (Metal Oxide Nitride Oxide Semiconductor) type in which an ONO (Oxide/Nitride/Oxide) film is used as a gate insulating film between a semiconductor substrate and a gate electrode, so that information is stored in this gate insulating film, or the like. Further, for the floating gate type, there is also known the one using an ONO film for an interlayer insulating film between a floating gate electrode and a control gate electrode.

[0003] On the other hand, in the semiconductor integrated circuit device, not only active elements such as MISFETs but also passive elements such as resistor elements and capacitor elements are generally present in a large number. These are used in, for example, a delay circuit, a load element, an oscillation circuit, and a bypass capacitor for stabilizing power supply. Also for resistor elements and capacitor elements, the ones of various structures are known. For example, as resistor elements, there are known a diffused resistor element formed by doping impurities into the semiconductor substrate and a polycrystal silicon resistor element formed of a polycrystal silicon film. As capacitor elements, there are known a capacitor element in which a semiconductive region (impurity diffused region) formed by doping impurities into a semiconductor substrate serves as a lower electrode, and a conductive film disposed over the lower electrode via a dielectric film interposed therebetween serves as an upper electrode, a capacitor element in which a conductive film disposed over an element isolation region of a principal surface of a semiconductor substrate serves as a lower electrode, and a conductive film disposed over the lower electrode via a dielectric film interposed therebetween serves as an upper electrode, and the like. Whereas, for the capacitor element, a capacitor element using the ONO film described above as a dielectric film is also known.

[0004] Incidentally, the known documents regarding the present invention include the following Patent Document 1 (Japanese Unexamined Patent Publication No. 2000-269449) and Patent Document 2 (Japanese Unexamined Patent Publication No. 2000-164835). Patent Document 1 discloses a manufacturing technique of a semiconductor integrated circuit device having a nonvolatile memory of a floating gate structure, and a capacitor element. Patent Document 2 discloses a manufacturing technique of an integrated circuit having a nonvolatile memory of a floating gate structure, a high breakdown voltage transistor, and a low breakdown voltage transistor.

[0005] Patent Document 1

[0006] Japanese Unexamined Patent Publication No. 2000-269449

[0007] Patent Document 1

[0008] Japanese Unexamined Patent Publication No. 2000-164835

[0009] In recent years, in the frontiers of technology such as multimedia or information communication, a system on chip structure in which a microcomputer, a DRAM, an ASIC (Application Specific Integrated Circuit), a flash memory, and the like are merged in one chip has been implemented. This has been stepping up the move to achieve the increase in data transfer speed, the space-saving (improvement in packaging density), and the reduction in power consumption.

[0010] For a system on chip incorporating therein a flash memory array, and a logic operational circuit such as a microcomputer, for example, an external power supply of 3.3 V is used, which necessitates a plurality of MISFETs to be driven at the external power supply of 3.3 V, and a first internal power supply voltage of 1.8 V is generated by a voltage reduction circuit for lower power consumption and higher speed, which necessitates a plurality of MISFETs to be driven at the first internal power supply voltage. Further, a second internal power supply voltage of 10 V to 12 V is generated by a booster circuit, which necessitates a plurality of MISFETs to be driven at the second internal power supply voltage (10 to 12 V) for writing into selected memory cells in the flash memory array, or for other purposes. Hereinafter, the former MISFETs to be driven at a voltage of 3.3 V or 1.8 V are referred to as low breakdown voltage MISFETs. The latter MISFETs to be driven at 10 to 12 V are referred to as high breakdown voltage MISFETs. The low breakdown voltage MISFETs and the high breakdown voltage MISFETs are each incorporated in one semiconductor substrate (semiconductor chip) in the form of a CMOS (a pair of a p-type MISFET and an n-type MISFET).

[0011] On the other hand, a system LSI to be mounted in a portable card is composed of a regulator, a CPU (Central Processing Unit), an input/out circuit (I/O), a system controller, a watch dog timer, a random-number generator, a ROM (Read Only Memory), a RAM (Random Access Memory), an EEPROM, and the like. In the regulator, the I/O, and the EEPROM, a plurality of high breakdown voltage MISFETs are used. Whereas, in the watch dog timer and the timer in the EEPROM, a plurality of resistor elements are used. Further, a plurality of bypass capacitors are used for stabilizing the power supply voltage.

[0012] The present inventors have conducted a study on the system LSI, and as a result, they have found the following problems.

[0013] A lower electrode of a capacitor element is formed of a first-layer polycrystal silicon film. Whereas, an upper electrode of the capacitor element, the gate electrodes of the low breakdown voltage and the high breakdown voltage MISFETs are formed of a second-layer polycrystal silicon film. In this case, the lower electrode is formed over an element isolation region of a principal surface of a substrate, and then a heat treatment is conducted to form a gate insulating film comprised of a silicon oxide film. During the formation of the gate insulating film, a bird's beak comprised of a silicon oxide film is formed extending from the side of the lower electrode along the interface between the lower electrode and the element isolation region. The element isolation region of the principal surface of the substrate is generally formed of a silicon oxide film. An oxidant such as O₂ or H₂O for the heat treatment passes through the silicon oxide film. Therefore, a bird's beak of a silicon oxide film extending from the side of the lower electrode along the interface between the lower electrode and the element isolation region is formed during the formation of the gate insulating film.

[0014] The edge of the lower electrode is lifted by the formation of the bird's beak, so that warping resulting in a convex bottom surface of the lower electrode is caused in the lower electrode. For this reason, the lower electrode becomes more likely to be peeled off from the element isolation region. Such a deficiency becomes more noticeable as the miniaturization of the capacitor element proceeds in association with the trend toward a high-integration and multifunction system LSI. This makes difficult the reduction in size of the capacitor element. Further, this also causes the reduction of yield and the reduction of the reliability of the system LSI.

[0015] Also in the case where a resistor element is formed of a first-layer polycrystal silicon film over the element isolation region of the substrate, and the gate electrodes of the low breakdown voltage and high breakdown voltage MISFETs are formed of a second-layer polycrystal silicon film, the bird's beak is formed. The variations in resistance value of the resistor element are caused by the formation of the bird's beak. The variation in resistance value of the resistor element due to the bird's beak becomes noticeable with the miniaturization of the resistor element. This makes difficult the formation of the high resistive resistor element with a narrowed width.

[0016] The channel length of the MISFET becomes shorter with advances of miniaturization due to the increase in scale of integration. The reduction in channel length causes the depletion layers from the source region and the drain region to extend under the gate electrode. This results in the reduction of the potential barrier of the channel formation region. As a result, the threshold value voltage (Vth) is reduced, so that only a little increase in voltage (Vds) between the source region/the drain region increases the drain current (Ids). This makes it impossible to obtain a constant current region. Further, an increase in voltage Vds results in the punch through state in which the depletion layers from the drain region and the source region come in contact with each other, leading to a rapid increase in drain current Ids. Namely, the breakdown voltage between the drain region/the source region is reduced. Further, since the drain current (sub-threshold current) flowing with a gate voltage (Vg) lower than the threshold value voltage Vth increases, the leakage current in the OFF state increases.

[0017] Such degradation in breakdown voltage between the drain region/the source region and increase in leakage current in the OFF state can be suppressed by raising the impurity concentration of the well regions in which MISFETs are to be formed, i.e., the impurity concentration of the channel formation regions. Therefore, the surface impurity concentration of a low voltage system well region in which a low breakdown voltage MISFET is to be formed is set higher than the surface impurity concentration of a high voltage system well region in which a high breakdown voltage MISFET is to be formed.

[0018] The well regions are generally formed before the step of forming a gate insulating film. On the other hand, the gate insulating film of an ONO type nonvolatile storage element is generally formed by the thermal oxidation of the lower-layer and upper-layer oxide films. Therefore, in the case where the low voltage system well region is formed before the step of forming the gate insulating film of the ONO type nonvolatile storage element, the number of times the low voltage system well region is heat treated increases. The surface impurity concentration of the low voltage system well region is higher than the surface impurity concentration of the high voltage system well region. For this reason, an increase in number of times the heat treatment is conducted results in a reduction of the surface impurity concentration of the low voltage system well region. Accordingly, the characteristics of the low breakdown voltage MISFET are changed.

[0019] It is an object of the present invention to provide a technique capable of implementing a capacitor element with a small occupying area and a large capacitance.

[0020] It is another object of the present invention to provide a technique capable of implementing a high resistive resistor element.

[0021] It is a still other object of the present invention to provide a technique capable of forming a high breakdown voltage MISFET without affecting the characteristics of a low breakdown voltage MISFET.

[0022] It is a still further object of the present invention to provide a technique capable of improving the yield in manufacturing of a semiconductor integrated circuit device.

[0023] The foregoing and other objects, and the novel features of the present invention will be apparent through the description of this specification and the accompanying drawings.

[0024] Out of the inventions disclosed in this application, the outlines of the typical ones will be briefly described as follows.

[0025] (1) A semiconductor integrated circuit device, comprising: a semiconductor substrate having an element isolation region in a principal surface thereof; and a capacitor element having a lower electrode provided over the element isolation region of the principal surface of the semiconductor substrate, a dielectric film over the lower electrode, and an upper electrode provided over the lower electrode via the dielectric film interposed therebetween,

[0026] the semiconductor integrated circuit device, comprising oxidation resistant films (e.g., silicon nitride films) between the element isolation region of the principal surface of the semiconductor substrate and the lower electrode, and between the lower electrode and the upper electrode.

[0027] (2) A method of manufacturing a semiconductor integrated circuit device which comprises: a MISFET including a gate electrode provided over an element formation region of a principal surface of a semiconductor substrate via a gate insulating film interposed therebetween; and a capacitor element having a lower electrode provided over an element isolation region of the principal surface of the semiconductor substrate, and an upper electrode over the lower electrode via a dielectric film interposed therebetween,

[0028] the method comprising a step of conducting a heat treatment with the lower electrode being provided over the element isolation region of the principal surface of the semiconductor substrate via a first oxidation resistant film (e.g., a silicon nitride film) interposed therebetween, and with the top surface of the lower electrode being covered with a second oxidation resistant film (e.g., a silicon nitride film) so as to form the gate insulating film comprised of a silicon oxide film in the element formation region of the principal surface of the semiconductor substrate.

[0029] (3) A method of manufacturing a semiconductor integrated circuit device which comprises: a nonvolatile storage element formed in a first region of a principal surface of a semiconductor substrate; a MISFET formed in a second region of the principal surface of the semiconductor substrate; and a capacitor element formed over an element isolation region of the principal surface of the semiconductor substrate,

[0030] the method, comprising the steps of:

[0031] (a) conducting a heat treatment, and forming a silicon oxide film in the first region of the principal surface of the semiconductor substrate;

[0032] (b) after the step (a), forming a first silicon nitride film in such a manner as to cover the silicon oxide film, and the element isolation region of the principal surface of the semiconductor substrate;

[0033] (c) after the step (b), forming a first silicon film over the first silicon nitride film in such a manner as to cover the first region of the principal surface of the semiconductor substrate, and the element isolation region of the principal surface of the semiconductor substrate;

[0034] (d) after the step (c), forming a second silicon nitride film over the first silicon film in such a manner as to cover the element isolation region of the principal surface of the semiconductor substrate;

[0035] (e) after the step (d), patterning the second silicon nitride film and the first silicon film, and forming a gate electrode of the nonvolatile storage element over the first region of the principal surface of the semiconductor substrate and forming a lower electrode, of the capacitor element, having its top surface covered with the second silicon nitride film over the first silicon nitride film over the element isolation region of the principal surface of the semiconductor substrate;

[0036] (f) after the step (e), conducting a heat treatment, and forming a gate insulating film comprised of a silicon oxide film in the second region of the principal surface of the semiconductor substrate;

[0037] (g) after the step (f), forming a second silicon film in such a manner as to cover the gate insulating film, and the second silicon nitride film over the lower electrode; and

[0038] (h) after the step (g), patterning the second silicon film, and forming a gate electrode of the MISFET over the gate insulating film and forming an upper electrode of the capacitor element over the second silicon nitride film over the lower electrode.

[0039] (4) A semiconductor integrated circuit device, comprising: a semiconductor substrate having an element isolation region in a principal surface thereof; and a resistor element provided over the element isolation region of the principal surface of the semiconductor substrate,

[0040] the semiconductor integrated circuit device, comprising oxidation resistant films (e.g., silicon nitride films) between the element isolation region of the principal surface of the semiconductor substrate and the resistor element, and over the resistor element.

[0041] (5) A method of manufacturing a semiconductor integrated circuit device which comprises: a MISFET including a gate electrode provided over an element formation region of a principal surface of a semiconductor substrate via a gate insulating film interposed therebetween; and a resistor element provided over an element isolation region of the principal surface of the semiconductor substrate,

[0042] the method comprising a step of conducting a heat treatment with the resistor element being provided over the element isolation region of the principal surface of the semiconductor substrate via a first oxidation resistant film (e.g., a silicon nitride film) interposed therebetween, and with the top surface of the resistor element being covered with a second oxidation resistant film (e.g., a silicon nitride film) so as to form the gate insulating film comprised of a silicon oxide film in the element formation region of the principal surface of the semiconductor substrate.

[0043] (6) A method of manufacturing a semiconductor integrated circuit device which comprises: a nonvolatile storage element formed in a first region of a principal surface of a semiconductor substrate; a MISFET formed in a second region of the principal surface of the semiconductor substrate; and a resistor element formed over an element isolation region of the principal surface of the semiconductor substrate,

[0044] the method, comprising:

[0045] (a) conducting a heat treatment, and forming a silicon oxide film in the first region of the principal surface of the semiconductor substrate;

[0046] (b) after the step (a), forming a first silicon nitride film in such a manner as to cover the silicon oxide film and the element isolation region of the principal surface of the semiconductor substrate;

[0047] (c) after the step (b), forming a first silicon film over the first silicon nitride film in such a manner as to cover the first region of the principal surface of the semiconductor substrate, and the element isolation region of the principal surface of the semiconductor substrate;

[0048] (d) after the step (c), forming a second silicon nitride film over the first silicon film in such a manner as to cover the element isolation region of the principal surface of the semiconductor substrate;

[0049] (e) after the step (d), patterning the second silicon nitride film and the first silicon film, and forming a gate electrode of the nonvolatile storage element over the first region of the principal surface of the semiconductor substrate and forming the resistor element having its top surface covered with the second silicon nitride film over the first silicon nitride film over the element isolation region of the principal surface of the semiconductor substrate;

[0050] (f) after the step (e), conducting a heat treatment, and forming a gate insulating film comprised of a silicon oxide film in the second region of the principal surface of the semiconductor substrate;

[0051] (g) after the step (f), forming a second silicon film in such a manner as to cover the gate insulating film; and

[0052] (h) after the step (g), patterning the second silicon film, and forming a gate electrode of the MISFET over the gate insulating film.

[0053] (7) A method of manufacturing a semiconductor integrated circuit device which comprises:

[0054] a MISFET including a gate electrode provided over an element formation region of a principal surface of a semiconductor substrate via a gate insulating film interposed therebetween;

[0055] a capacitor element including a lower electrode provided over an element isolation region of the principal surface of the semiconductor substrate, and an upper electrode provided over the lower electrode via a dielectric film interposed therebetween; and

[0056] a resistor element provided over the element isolation region of the principal surface of the semiconductor substrate,

[0057] the method comprising a step of conducting a heat treatment with the lower electrode and the resistor element being provided over the element isolation region of the principal surface of the semiconductor substrate via a first oxidation resistant film (e.g., a silicon nitride film) interposed therebetween, and with the top surface of the lower electrode and the top surface of the resistor element being covered with a second oxidation resistant film (e.g., a silicon nitride film) so as to form the gate insulating film comprised of a silicon oxide film in the element formation region of the principal surface of the semiconductor substrate.

[0058] (8) A method of manufacturing a semiconductor integrated circuit device which comprises:

[0059] a nonvolatile storage element formed in a first region of a principal surface of a semiconductor substrate;

[0060] a MISFET formed in a second region of the principal surface of the semiconductor substrate;

[0061] a capacitor element formed over a first element isolation region of the principal surface of the semiconductor substrate; and

[0062] a resistor element formed over a second element isolation region of the principal surface of the semiconductor substrate, the method, comprising:

[0063] (a) conducting a heat treatment, and forming a silicon oxide film in the first region of the principal surface of the semiconductor substrate;

[0064] (b) after the step (a), forming a first silicon nitride film in such a manner as to cover the silicon oxide film, and the first and second element isolation regions of the principal surface of the semiconductor substrate;

[0065] (c) after the step (b), forming a first silicon film over the first silicon nitride film in such a manner as to cover the first region of the principal surface of the semiconductor substrate, and the first and second element isolation regions of the principal surface of the semiconductor substrate;

[0066] (d) after the step (c), forming a second silicon nitride film over the first silicon film in such a manner as to cover the first and second element isolation regions of the principal surface of the semiconductor substrate;

[0067] (e) after the step (d), patterning the second silicon nitride film and the first silicon film, and forming a gate electrode of the nonvolatile storage element over the first region of the principal surface of the semiconductor substrate, a lower electrode, of the capacitor element, having its top surface covered with the second silicon nitride film over the first silicon nitride film over the first element isolation region of the principal surface of the semiconductor substrate, and the resistor element having its top surface covered with the second silicon nitride film over the first silicon nitride film over the second element isolation region of the principal surface of the semiconductor substrate;

[0068] (f) after the step (e), conducting a heat treatment, and forming a gate insulating film comprised of a silicon oxide film in the second region of the principal surface of the semiconductor substrate;

[0069] (g) after the step (f), forming a second silicon film in such a manner as to cover the second silicon nitride film over the lower electrode and the resistor element, and the gate insulating film; and

[0070] (h) after the step (g), patterning the second silicon film, and forming a gate electrode of the MISFET over the gate insulating film, and an upper electrode of the capacitor element over the second silicon nitride film over the lower electrode.

[0071] (9) A method of manufacturing a semiconductor integrated circuit device which comprises:

[0072] a nonvolatile storage element formed in a first region of a principal surface of a semiconductor substrate;

[0073] a first MISFET provided in a second region of the principal surface of the semiconductor substrate; and

[0074] a second MISFET having a lower operating voltage than that of the first MISFET, and provided in a third region of the principal surface of the semiconductor substrate;

[0075] the method, comprising the steps of:

[0076] forming a gate insulating film including a thermal oxide film in the first region of the principal surface of the semiconductor substrate;

[0077] forming a gate electrode over the gate insulating film;

[0078] forming a first well region in the second region of the principal surface of the semiconductor substrate; and

[0079] forming a second well region in the third region of the principal surface of the semiconductor substrate,

[0080] wherein the step of forming the second well region is carried out after forming the gate electrode.

[0081] FIG. 1 is a schematic cross sectional view showing a general configuration of a semiconductor integrated circuit device which is one embodiment of the present invention;

[0082] FIG. 2 is a schematic cross sectional view on an enlarged scale showing a part (a memory cell part) of FIG. 1;

[0083] FIG. 3 is a schematic cross sectional view on an enlarged scale showing a part (a high breakdown voltage pMIS part and a resistor element part) of FIG. 1;

[0084] FIG. 4 is a schematic cross sectional view on an enlarged scale showing a part (a low breakdown voltage pMIS part and a capacitor element part) of FIG. 1;

[0085] FIG. 5 is a circuit block diagram configured in the semiconductor integrated circuit device which is one embodiment of the present invention;

[0086] FIG. 6 is a circuit diagram showing a general configuration of an EEPROM of FIG. 5;

[0087] FIG. 7 is a schematic illustrative view of a bypass capacitor in FIG. 5;

[0088] FIG. 8 is a graph for showing the leakage current characteristics when a positive voltage is applied to an upper electrode in a capacitor element which is one embodiment of the present invention;

[0089] FIG. 9 is a graph for showing the leakage current characteristics when a negative voltage is applied to the upper electrode in the capacitor element which is one embodiment of the present invention;

[0090] FIG. 10 is a graph showing the upper electrode voltage dependency of the capacitor element of one embodiment of the present invention;

[0091] FIG. 11 is a graph showing the polycrystal silicon width dependency of the resistance value in the resistor element of one embodiment of the present invention;

[0092] FIG. 12 is a schematic cross sectional view of the semiconductor integrated circuit device during a manufacturing step, which is one embodiment of the present invention;

[0093] FIG. 13 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that shown in FIG. 12;

[0094] FIG. 14 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that of FIG. 13;

[0095] FIG. 15 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that shown in FIG. 14;

[0096] FIG. 16 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that of FIG. 15;

[0097] FIG. 17 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that shown in FIG. 16;

[0098] FIG. 18 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that of FIG. 17;

[0099] FIG. 19 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that shown in FIG. 18;

[0100] FIG. 20 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that of FIG. 19;

[0101] FIG. 21 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that of FIG. 20;

[0102] FIG. 22 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that shown in FIG. 21;

[0103] FIG. 23 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that of FIG. 22;

[0104] FIG. 24 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that shown in FIG. 23;

[0105] FIG. 25 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that of FIG. 24;

[0106] FIG. 26 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that of FIG. 25;

[0107] FIG. 27 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that shown in FIG. 26; and

[0108] FIG. 28 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step subsequent to that of FIG. 27.

[0109] Below, the present invention will be described in details by way of embodiments with reference to the accompanying drawings. Incidentally, throughout the drawings for describing the embodiments of the invention, the elements having the same function are represented by the same reference numerals and characters, and the repeated description thereof is omitted. Whereas, in cross sectional views, hatching indicating cross sections may be partially omitted for convenient reference of the drawings.

[0110] In this embodiment, a description will be given to the case where the present invention is applied to a system LSI to be incorporated in, for example, an IC card, and used, as a semiconductor integrated circuit device.

[0111] FIG. 1 is a schematic cross sectional view showing a general configuration of the system LSI of this embodiment.

[0112] FIG. 2 is a schematic cross sectional view on an enlarged scale showing a part (a memory cell part) of FIG. 1.

[0113] FIG. 3 is a schematic cross sectional view on an enlarged scale showing a part (a high breakdown voltage pMIS part and a resistor element part) of FIG. 1.

[0114] FIG. 4 is a schematic cross sectional view on an enlarged scale showing a part (a low breakdown voltage pMIS part and a capacitor element part) of FIG. 1.

[0115] FIG. 5 is a circuit block diagram showing a general configuration of the system LSI of this embodiment.

[0116] FIG. 6 is a circuit diagram showing a general configuration of an EEPROM of FIG. 5;

[0117] FIG. 7 is a block diagram showing one example of the form of use of a capacitor element of FIG. 1.

[0118] As shown in FIG. 5, the system LSI of this embodiment is configured such that a regulator, a central processing unit (CPU), an input/output circuit (I/O), a system controller, a watch dog timer, a random-number generator, a ROM, a RAM, an EEPROM, and the like are mounted on a semiconductor chip 1A.

[0119] The EEPROM constituting the system LSI is used as, for example, a data memory of an IC card, and is configured to be applied with a high voltage (Vpp) for rewriting (erasing and writing) via a booster circuit as shown in FIG. 6 mounted in the semiconductor chip 1A. The booster circuit boosts 1.5 V generated by stepping down the external power supply voltage of 1.8 to 5 V through a regulator for low voltage logics other than the EEPROM to generate 10.5 V. At this step, it supplies a high voltage to an output node via a multistage charge pump circuit using several tens-pF capacitor elements.

[0120] Besides, in the semiconductor chip 1A, as shown in FIG. 7, a large number of capacitor elements C referred to as bypass capacitors are connected for stabilizing the internal power supply voltage between the internal power supply Vdd generated by regulating the external power supply Vcc , and Vss (0V). The capacitor elements C are often located under wiring in a wiring channel region between respective circuit blocks (modules).

[0121] Incidentally, the system LSI is basically formed in a CMIS device configuration in which n-channel conductive type MISFETs and p-channel conductive type MISFETs are combined. The CMIS device is generally referred to as a CMOS.

[0122] Further, a MISFET to be driven at a relatively low voltage such as a MISFET to be driven at 1.8 V or a MISFET to be driven at 3.3 V is also miniaturized in device configuration for higher speed. Therefore, such a MISFET is also low in gate breakdown voltage. Hereinafter, such a MISFET is referred to as a low breakdown voltage MISFET.

[0123] Whereas, a MISFET to be driven at a relatively high voltage such as a MISFET to be driven at 12 V is also high in gate breakdown voltage. Hereinafter, such a MISFET is referred to as a high breakdown voltage MISFET.

[0124] Then, a specific configuration of the system LSI will be described with reference to FIGS. 1 to 4. FIG. 1 shows a memory cell Me, a low breakdown voltage p-type MISFET-QLp, a resistor element 10b, a high breakdown voltage p-MISFET-QHp, and a capacitor element C. The memory cell Me is used in the memory cell array of the EEPROM; the low breakdown voltage p-type MISFET-QLP is used in the CPU, or the like; the resistor element 10b is used in the watch dog timer, or the like; the high breakdown voltage p-type MISFET-QHp is used in the regulator, the I/O, the peripheral circuit of the EEPROM, or the like; and the capacitor element C is used as the bypass capacitor.

[0125] As shown in FIGS. 1 to 4, the system LSI is mainly composed of a semiconductor substrate 1 (hereinafter, simply referred to as a substrate) made of, for example, a p-type single crystal silicon as a semiconductor substrate. In a principal surface of the substrate 1, a plurality of element formation regions defined by element isolation regions 5 are provided. The element formation regions include a memory cell formation region, a low breakdown voltage MIS formation region, a high breakdown voltage MIS formation region, and the like. The element isolation regions 5 are formed by, for example, a known STI (Shallow Trench Isolation) technique. The element isolation regions 5 by the STI technique are formed in the following manner. Shallow trenches (e.g., trenches with a depth of about 300 nm) are formed in the principal surface of the substrate 1. Then, an insulating film composed of, for example, a silicon oxide film is formed over the principal surface of the substrate 1 by a CVD (Chemical Vapor Deposition) process. Subsequently, planarization is carried out by a CMP (Chemical Mechanical Polishing) process so that the insulating film is selectively left inside the shallow trenches.

[0126] As shown in FIGS. 1 and 2, n-type well regions 2 are formed in the memory cell formation region of the principal surface of the substrate 1. In the n-type well regions 2, high voltage system p-type well regions 4 are formed. Further, in the memory cell formation region in the principal surface of the substrate 1, the memory cell Me is formed. The memory cell Me is composed of one nonvolatile storage element Qm, and one selecting MISFET-Qs connected in series to the nonvolatile storage element Qm.

[0127] As shown in FIGS. 1 and 3, in a low voltage pMIS formation region in the principal surface of the substrate 1, an n-type well region 2 is formed. In the n-type well region 2, a low voltage system n-type well region 14 is formed. Further, in the low voltage pMIS formation region of the principal surface of the substrate 1, the low breakdown voltage p-type MISFET-QLp is formed.

[0128] As shown in FIGS. 1 and 3, over the element isolation region 5 of the principal surface of the substrate 1, the resistor element 10b is formed. Under the element isolation region 5 over which the resistor element 10b is formed, a low voltage system p-type well region 15 is formed. Hereinafter, the element isolation region 5 over which the resistor element 10b is formed is referred to as a first element isolation region.

[0129] As shown in FIGS. 1 to 4, in the high voltage pMIS formation region of the principal surface of the substrate 1, the n-type well region 2 is formed. In the n-type well region 2, a high voltage system n-type well region 3 is formed. Further, in the high voltage pMIS formation region in the substrate 1, the high breakdown voltage p-type MISFET-QHp is formed.

[0130] As shown in FIGS. 1 to 4, over the element isolation region 5 of the principal surface of the substrate 1, a capacitor element C is formed. Under the element isolation region 5 over which the capacitor element C is formed, a high voltage system p-type well region 4 is formed. Hereinafter, the element isolation region 5 over which the capacitor element C is formed is referred to as a second element isolation region.

[0131] Incidentally, for preventing the parasitic channel, n-type well regions 3a are formed between the high voltage system p-type well region 4 and the low voltage system n-type well region 14, between the high voltage system n-type well region 3 and the high voltage system p-type well region 4, and the like.

[0132] As shown in FIG. 2, the nonvolatile storage element Qm mainly comprises a channel formation region, a gate insulating film 16, a gate electrode (memory gate electrode) 10a, and a source region and a drain region. The gate insulating film 16 is provided in the principal surface of the substrate 1; the gate electrode 10a is provided over the principal surface of the substrate 1 via the gate insulating film 16 interposed therebetween; and the channel formation region is provided in the surface layer portion of the substrate immediately under the gate electrode 10a, specifically, in the surface layer portion of the high voltage system p-type well region 4. The source region and the drain region are provided on opposite sides along the direction of channel length of the channel formation region in such a manner as to sandwich the channel formation region therebetween.

[0133] The source region and the drain region of the nonvolatile storage element Qm comprises a pair of n-type semiconductive regions 21 which are extension regions, and a pair of n-type semiconductive regions 25 which are contact regions. The n-type semiconductive regions 21 are formed in alignment with the gate electrode 10a. The n-type semiconductive regions 25 are formed in alignment with a sidewall spacer 24 disposed on the sidewall of the gate electrode 10a, and have a higher impurity concentration than that of the n-type semiconductive regions 21.

[0134] The nonvolatile storage element Qm is configured in the form of MONOS (Metal Oxide Nitride Oxide Semiconductor) in which an ONO (oxide/nitride/oxide) film is used as the gate insulating film 16 between the high voltage system p-type well region 4 (substrate) and the gate electrode 10a, and information is stored in this gate insulating film 16. The nonvolatile storage element Qm of this embodiment uses an ONO film composed of silicon oxide film/silicon nitride film/silicon oxide film as the gate insulating film 16.

[0135] As shown in FIG. 2, the selecting MISFET-Qs mainly comprises a channel formation region, a gate insulating film 17, a gate electrode 19a, and a source region and a drain region. The gate insulating film 17 is provided in the principal surface of the substrate 1. The gate electrode 19a is disposed over the principal surface of the substrate 1 via the gate insulating film 17 interposed therebetween; and the channel formation region is provided in the surface layer portion of the substrate immediately under the gate electrode 19a, specifically, in the surface layer portion of the high voltage system p-type well region 4. The source region and the drain region are provided on opposite sides along the direction of channel length of the channel formation region in such a manner as to sandwich the channel formation region therebetween.

[0136] The source region and the drain region of the selecting MISFET-Qs comprises a pair of n-type semiconductive regions 21 which are extension regions, and a pair of n-type semiconductive regions 25 which are contact regions. The n-type semiconductive regions 21 are formed in alignment with the gate electrode 19a. The n-type semiconductive regions 25 are formed in alignment with a sidewall spacer 24 disposed on the sidewall of the gate electrode 19a.

[0137] The threshold value voltage of the nonvolatile storage element Qm is high if a large number of electrons are captured by the traps in the silicon nitride film of the gate insulating film 16. Accordingly, even if the electric potential of a word line integrally formed with the gate electrode 10a becomes high, the transistor will not go into the ON state. If electrons vanish from the traps in the silicon nitride film of the gate insulating film 16, the threshold value voltage is reduced, so that the transistor goes into the ON state. Injection of electrons into the silicon nitride film of the gate insulating film 16 (writing) is accomplished in the following manner. A positive voltage (e.g., 1.5 V) is applied to the gate electrode 10a, and a negative high voltage (e.g., 10.5 V) is applied to the high voltage system p-type well region 4. Thus, tunneling is caused from the channel formation region (high voltage system p-type well region 4) through the silicon oxide film of the gate insulating film 16. Conversely, for erasing, a negative high voltage (e.g., 8.5 V) is applied to the gate electrode 10a, and a positive voltage (e.g., 1.5 V) is applied to the high voltage system p-type well region 4. Thus, the electrons in the silicon nitride film of the gate insulating film 16 are emitted into the channel formation region (high voltage system p-type well region 4) by the tunneling effect, and positive holes are tunnel injected from the channel formation region into the silicon nitride film.

[0138] As shown in FIG. 3, the low breakdown voltage p-type MISFET-QLP mainly comprises a channel formation region, a gate insulating film 18, a gate electrode 19b, and a source region and a drain region. The gate insulating film 18 is provided in the principal surface of the substrate 1; the gate electrode 19b is provided over the principal surface of the substrate 1 via the gate insulating film 18 interposed therebetween; and the channel formation region is provided in the surface layer portion of the substrate immediately under the gate electrode 19b, specifically, in the surface layer portion of the low voltage system n-type well region 14. The source region and the drain region are provided on opposite sides along the direction of channel length of the channel formation region in such a manner as to sandwich the channel formation region therebetween.

[0139] The source region and the drain region of the low breakdown voltage p-type MISFET-QLp comprises a pair of p-type semiconductive regions 23 which are extension regions, and a pair of p-type semiconductive regions 26 which are contact regions. The p-type semiconductive regions 23 are formed in alignment with the gate electrode 19b. The p-type semiconductive regions 26 are formed in alignment with a sidewall spacer 24 disposed on the sidewall of the gate electrode 19b, and have a higher impurity concentration than that of the n-type semiconductive regions 23.

[0140] As shown in FIG. 3, the resistor element 10b includes contact regions for establishing connection to an upper-layer wiring, respectively provided on the one edge and the other edge positioned on mutually opposite sides. The resistor element 10b is mainly composed of, for example, a polycrystal silicon film.

[0141] As shown in FIG. 4, the high breakdown voltage p-type MISFET-QHp mainly comprises a channel formation region, a gate insulating film 17, a gate electrode 19d, and a source region and a drain region. The gate insulating film 17 is provided in the principal surface of the substrate 1; the gate electrode 19d is provided over the principal surface of the substrate 1 via the gate insulating film 17 interposed therebetween; and the channel formation region is provided in the surface layer portion of the substrate immediately under the gate electrode 19d, specifically, in the surface layer portion of the high voltage system n-type well region 3. The source region and the drain region are provided on opposite sides along the direction of channel length of the channel formation region in such a manner as to sandwich the channel formation region therebetween.

[0142] The source region and the drain region of the high breakdown voltage p-type MISFET-QHP comprises a pair of p-type semiconductive regions 22 which are extension regions, and a pair of p-type semiconductive regions 26 which are contact regions. The p-type semiconductive regions 22 are formed in alignment with the gate electrode 19d. The p-type semiconductive regions 26 are formed in alignment with a sidewall spacer 24 disposed on the sidewall of the gate electrode 19d, and have a higher impurity concentration than that of the p-type semiconductive regions 22.

[0143] As shown in FIG. 4, the capacitor element C comprises a lower electrode 10c provided over the second element isolation region of the principal surface of the substrate 1, and an upper electrode 19c provided over the lower electrode 10c via a dielectric film interposed therebetween. The capacitor element C of this embodiment uses an ONO film composed of silicon oxide film 11/silicon nitride film 12/silicon oxide film 13 as the dielectric film. The high voltage system p-type well region 4 under the second element isolation region is fixed at a given electric potential (e.g., 0V) so that the capacitor element C is not affected thereby.

[0144] The gate electrode 10a of the nonvolatile storage element Qm, the resistor element 10b, and the lower electrode 10c of the capacitor element C are mainly formed of, for example, a first-layer polycrystal silicon film. The gate electrode 19a of the selecting MISFET-Qs, the gate electrode 19b of the low breakdown voltage p-type MISFET-QLP, the upper electrode 19c of the capacitor element C, and the gate electrode 19d of the high breakdown voltage p-type MISFET-QHp are mainly formed of, for example, a second-layer polycrystal silicon film. To these first-layer and second-layer polycrystal silicon films, impurities for reducing the resistance value have been doped.

[0145] In the gate insulating film 16 of the nonvolatile storage element Qm, the lower-layer silicon oxide film has a thickness of, for example, about 1.8 nm; the silicon nitride film has a thickness of, for example, about 15 nm; and the upper-layer silicon oxide film has a thickness of, for example, about 3 nm. These upper-layer and lower-layer silicon oxide films are formed by, for example, a thermal oxidation process.

[0146] The gate insulating film 17 of the selecting MISFET-Qs and the high breakdown voltage p-type MISFET-QHP is formed with a thickness of, for example, about 18 nm; and the gate insulating film 17 of the low breakdown voltage p-type MISFET-QLp is formed with a thickness of, for example, about 3.7 nm. These gate insulating films 16 and 17 are formed by, for example, a thermal oxidation process.

[0147] The gate length of the nonvolatile storage element Qm is, for example, about 500 nm; the gate length of the selecting MISFET-Qs is, for example, about 400 nm; the gate length of the low breakdown voltage p-type MISFET-QLp is, for example, about 160 nm; and the gate length of the high breakdown voltage p-type MISFET-QHp is, for example, about 900 nm.

[0148] As shown in FIGS. 2, 3, and 4, in the nonvolatile storage element Qm, the selecting MISFET-Qs, the low breakdown voltage p-type MISFET-QLP, the high breakdown voltage p-type MISFET-QHP, the capacitor element C, and the resistor element 10b, a silicide layer 28 which is a metal/semiconductor reaction layer is formed for achieving the reduction in resistance over the surfaces of the gate electrodes (10a, 19a, 19b, and 19d), the surfaces of the semiconductor regions (25 and 26), the surface of the upper electrode 19c, the surface of the contact region of the lower electrode 10c, and the surfaces of the two contact regions positioned on mutually opposite sides of the resistor elements 10b. Each portion of the silicide layer 28 is formed in alignment with the sidewall spacer 24 by, for example, a salicide (self aligned silicide) technique.

[0149] Over the principal surface of the substrate 1, an interlayer insulating film 29 composed of, for example, a silicon oxide film is provided in such a manner as to cover the foregoing active elements and passive elements. Over the semiconductive regions 25 and 26, contact holes for the sources/the drains, which reach from the surface of the interlayer insulating film 29 to the silicide layer 28 are provided. Conductive plugs 30 are embedded inside the contact holes for the sources/the drains. The semiconductive regions 25 and 26 are electrically connected to a wiring 31 extending over the interlayer insulating film 29 via the silicide layer 28 and the conductive plugs 30.

[0150] On the gate electrodes 19a, 19b, and 19d, although not shown, contact holes for the gates reaching from the surface of the interlayer insulating film 29 to the silicide layer 28 are provided. The conductive plugs 30 are embedded inside the contact holes for the gates. The gate electrodes 19a, 19b, and 19d are electrically connected to the wiring 31 extending over the interlayer insulating film 29 via the silicide layer 28 and the conductive plugs 30.

[0151] On the upper electrode 19c, a contact hole for the upper electrode reaching from the surface of the interlayer insulating film 29 to the silicide layer 28 is provided. The conductive plug 30 is embedded inside the contact hole for the upper electrode. The upper electrode 19c is electrically connected to the wiring 31 extending over the interlayer insulating film 29 via the silicide layer 28 and the conductive plug 30 interposed therebetween.

[0152] On the contact region of the lower electrode 10c, a contact hole for the lower electrode reaching from the surface of the interlayer insulating film 29 to the silicide layer 28 is provided. A conductive plug 30 is embedded inside the contact hole for the lower electrode. The lower electrode 10c is electrically connected to the wiring 31 extending over the interlayer insulating film 29 via the silicide layer 28 and the conductive plug 30 interposed therebetween.

[0153] On the one and the other contact regions of the resistor element 10b, contact holes for the resistor reaching from the surface of the interlayer insulating film 29 to the silicide layer 28 are respectively provided. Conductive plugs 30 are embedded inside the contact holes for the resistor. The one and the other contact regions of the resistor element 10b are electrically connected to the wiring 31 extending over the interlayer insulating film 29 via the silicide layer 28 and the conductive plugs 30 interposed therebetween.

[0154] As shown in FIG. 4, for example, a silicon nitride film 8 is provided as an oxidation resistant film between the lower electrode 10c of the capacitor element C and the second element isolation region (element isolation insulating film) of the principal surface of the substrate 1. Between the silicon nitride film 8 and the lower electrode 10c, for example, a silicon oxide film 9 is provided. Namely, the lower electrode 10c of the capacitor element C is provided over the second element isolation region of the principal surface of the substrate 1 via the oxidation resistant film composed of the silicon nitride film 8 interposed therebetween. In this embodiment, the silicon nitride film 8 is formed by the same process as with the silicon nitride film of the gate insulating film 16 of the nonvolatile storage element Qm. The silicon oxide film 9 is formed by the same process as with the upper-layer silicon oxide film of the gate insulating film 16 of the nonvolatile storage element Qm.

[0155] In the capacitor element C, as shown in FIG. 4, the lower electrode 10c is formed with a larger planar size than that of the upper electrode 19c. This is for convenience of connection of the upper-layer wiring to the lower electrode 10c. Therefore, a contact region for establishing a connection to the upper-layer wiring is provided in the lower electrode 10c. Whereas, the area occupied by the capacitor element C is determined by the planar size of the lower electrode 10c.

[0156] The dielectric film of the capacitor element C is, as described above, formed of an ONO film composed of silicon oxide film 11/silicon nitride film 12/silicon oxide film 13. Therefore, an oxidation resistant film composed of the silicon nitride film 12 is provided between the lower electrode 10c and the upper electrode 19c.

[0157] The silicon nitride film 8 has a thickness of, for example, about 15 nm; the silicon oxide film 9 has a thickness of, for example, about 3 nm; the silicon oxide film 11 has a thickness of, for example, about 6 nm; the silicon nitride film 12 has a thickness of, for example, about 26 nm; and the silicon oxide film 13 has a thickness of, for example, about 1 nm. The capacitance per unit area in this case is about 1.9 fF/m², and 19 pF for 100 m square.

[0158] It is desirable that the leakage current flowing through the dielectric film of the capacitor element C is sufficiently small. FIG. 8 is a graph for showing the leakage current characteristics when a positive voltage is applied to the upper electrode in the capacitor element C in which the area of the dielectric film between the upper electrode and the lower electrode is 18000 m². The thickness of the silicon nitride film 12 is taken as a parameter. As shown in FIG. 8, the leakage current decreases with an increase in thickness of the silicon nitride film 12, and the leakage current becomes remarkable from about 10 V.

[0159] FIG. 9 is a graph for showing the leakage current characteristics when a negative voltage is applied to the upper electrode in the capacitor element C having the same area as with FIG. 8. The silicon nitride film 12 is taken as a parameter. As shown in FIG. 9, when the thickness of the silicon nitride film 12 is 26 nm, the leakage current hardly flows until 14 V. Since the absolute voltage of the high voltage for the EEPROM of FIGS. 5 and 6 is 12 V, the upper electrode is desirably held at a negative voltage, and thus used. When it is used as a bypass capacitor for stabilizing power supply, either polarity is acceptable. The leakage current has a polarity dependence because of the asymmetry resulting from the fact that the thickness of the silicon oxide film 11 is 6 nm, and the thickness of the silicon oxide film 13 is 1 nm.

[0160] FIG. 10 is a graph showing the upper electrode voltage dependency of the capacitor element C. As shown in FIG. 10, the capacitance value decreases on the negative voltage side because the lower electrode is depleted. The smaller the thickness of the silicon nitride film 12 is, the more the capacitance value decreases on the negative voltage side. This is also because the lower electrode is more susceptible to depletion. As compared with a MOS type capacitor element in which a semiconductive region formed in a substrate serves as a lower electrode, the capacitor element C is characterized by its very small applied voltage dependency.

[0161] As shown in FIG. 3, for example, the silicon nitride film 8 is provided as the oxidation resistant film between the resistor element 10b and the first element isolation region of the principal surface of the substrate 1. Between the silicon nitride film 8 and the resistor element 10b, for example, the silicon oxide film 9 is provided. Namely, the resistor element 10b is provided over the first element isolation region of the principal surface of the substrate 1 via the oxidation resistant film composed of the silicon nitride film 8 interposed therebetween. In this embodiment, the silicon nitride film 8 is formed by the same process as with the silicon nitride film of the gate insulating film 16 of the nonvolatile storage element Qm. The silicon oxide film 9 is formed by the same process as with the upper-layer silicon oxide film of the gate insulating film 16 of the nonvolatile storage element Qm.

[0162] As shown in FIGS. 1 to 4, the low voltage system n-type well region 14 is formed with a shallower depth than that of the high voltage system n-type well region 3. The surface concentration of the low voltage system n-type well region 14 is higher (more dense) than the surface concentration of the high voltage system n-type well region 3. The low voltage system p-type well region 15 is formed with a shallower depth than that of the high voltage system p-type well region 4. The surface concentration of the low voltage system p-type well region 15 is higher (more dense) than the surface concentration of the high voltage system p-type well region 4.

[0163] Then, manufacturing of a semiconductor integrated circuit device of this embodiment will be described by reference to FIGS. 12 to 28. FIGS. 12 to 28 are schematic cross sectional diagrams of the semiconductor integrated circuit device in respective manufacturing steps.

[0164] First, the substrate 1 composed of single crystal silicon having a specific resistance of 10 cm is prepared. Thereafter, as shown in FIG. 12, the element isolation regions 5 defining the element formation regions are formed in the principal surface of the substrate 1. The element isolation regions 5 are formed using, for example, a known STI technique. Specifically, the element isolation regions 5 are formed in the following manner. Shallow trenches (trenches with a depth of, for example, about 300 nm) are formed in the principal surface of the substrate 1. Subsequently, an insulating film composed of, for example, silicon oxide, is formed over the principal surface of the substrate 1 by a CVD process. Then, planarization is carried out by a CMP process so that the insulating film is selectively left inside the shallow trenches. In this step, a buffer insulating film 6 composed of, for example, a silicon oxide film is formed in the element formation regions of the principal surface of the substrate 1.

[0165] Then, an impurity for forming well regions is selectively ion-implanted into the principal surface of the substrate 1. Subsequently, a heat treatment for activating the impurity is carried out. As shown in FIG. 13, this results in the formation of the n-type well regions 2, the high voltage system n-type well regions 3, the n-type well regions 3a for preventing the parasitic channel, and the high voltage type p-type well regions 4.

[0166] As the impurity for forming the n-type well regions 2, for example, phosphorus (P) is used. The phosphorus is ion-implanted under the conditions of an accelerating energy of 2 MeV and a dose amount of 5.010¹² atoms/cm².

[0167] As the impurities for forming the high voltage system n-type well regions 3, for example, phosphorus (P) and boron difluroride (BF₂) are used.

[0168] The ion implantation of phosphorus is carried out under the conditions as follows:

[0169] The accelerating energy is 1 MeV, and the dose amount is 8.010¹² atoms/cm²;

[0170] The accelerating energy is 460 KeV, and the dose amount is 5.010¹¹ atoms/cm²; or

[0171] The accelerating energy is 180 KeV, and the dose amount is 1.010¹² atoms/cm².

[0172] Whereas, the ion implantation of boron difluoride is carried out under the conditions of an energy of 100 KeV and a dose amount of 1.510¹² atoms/cm².

[0173] As the impurities for forming the high voltage system p-type well regions 4, for example, boron (B) and boron difluroride (BF₂) are used.

[0174] The ion implantation of boron is carried out under the conditions as follows:

[0175] The accelerating energy is 500 KeV, and the dose amount is 8.010¹² atoms/cm²;

[0176] The accelerating energy is 150 KeV, and the dose amount is 1.810¹² atoms/cm²; or

[0177] The accelerating energy is 50 KeV, and the dose amount is 1.210¹² atoms/cm².

[0178] Whereas, the ion implantation of boron difluoride is carried out under the conditions of an accelerating energy of 100 KeV and a dose amount of 2.510¹² atoms/cm².

[0179] The boron difluoride for forming the high voltage system n-type and p-type well regions is implanted for controlling the threshold value voltage.

[0180] In this step, the n-type well regions 2 and the high voltage system p-type well regions 4 are formed in the memory cell formation region of the principal surface of the substrate 1. Further, the n-type well regions 2 are formed under the low breakdown voltage pMIS formation region and the first element isolation region of the principal surface of the substrate 1. Whereas, the n-type well region 2 and the high voltage system n-type well region 3 are formed in the high breakdown voltage pMIS formation region of the principal surface of the substrate 1. Whereas, the n-type well region 2, and the high voltage system p-type well region 4 are formed under the second element isolation region of the principal surface of the substrate 1. Further, the n-type well regions 3a for preventing the parasitic channel are formed in the principal surface of the substrate 1.

[0181] Then, a portion (a region where a nonvolatile storage element is to be formed) of the buffer insulating film 6 in the memory cell formation region of the principal surface of the substrate 1 is selectively removed by etching. Thereafter, the substrate 1 is subjected to a heat treatment in an oxygen atmosphere diluted with nitrogen. As shown in FIG. 14, this results in the formation of a silicon oxide film 7 with a thickness as very thin as, for example, about 1.8 nm in the nonvolatile storage element formation region formed by removing a portion of the buffer insulating film 6.

[0182] Then, as shown in FIG. 15, the silicon nitride film 8 with a thickness of, for example, about 18 nm is formed entirely over the principal surface of the substrate 1, including over the silicon oxide film 7 and over the first and second element isolation regions by a CVD process. Thereafter, the substrate 1 is subjected to a heat treatment in a steam atmosphere. As a result, as shown in FIG. 15, the silicon oxide film 9 with a thickness of, for example, about 3 nm is formed in the surface of the silicon nitride film 8. In this step, the thickness of the silicon nitride film 8 decreases from about 18 nm to 15 nm. Further, in this step, an ONO film (silicon oxide film 7/silicon nitride film 8/silicon oxide film 9) is formed as the gate insulating film of the nonvolatile storage element Qm over the high voltage system p-type well region 4 of the memory cell formation region.

[0183] Then, as shown in FIG. 16, a first-layer polycrystal silicon film 10 with a thickness of, for example, about 200 nm is formed by a CVD process entirely over the silicon oxide film 9 including over the memory cell formation region, and over the first and second element isolation regions. Thereafter, an impurity (e.g., phosphorus (P)) for reducing the resistance value is ion-implanted into the polycrystal silicon film 10, followed by a heat treatment for activating the impurity.

[0184] Then, as shown in FIG. 17, the silicon oxide film 11, the silicon nitride film 12, and the silicon oxide film 13 are formed sequentially from the surface of the polycrystal silicon film 10 by a CVD process entirely over the polycrystal silicon film 10 including over the first and second element isolation regions. The silicon oxide film 11 is formed with a thickness of, for example, about 6 nm; the silicon nitride film 12, with a thickness of, for example, about 26 nm; and the silicon oxide film 13, with a thickness of, for example, about 70 nm.

[0185] Then, the silicon oxide film 13, the silicon nitride film 12, the silicon oxide film 11, and the polycrystal silicon film 10 are sequentially patterned. As a result, as shown in FIG. 18, the gate electrode 10a of the nonvolatile storage element Qm is formed in the memory cell formation region; the resistor element 10b, over the first element isolation region; and the lower electrode 10c of the capacitor element C, over the second element isolation region. The patterning of the silicon oxide film 13, the silicon nitride film 12, and the silicon oxide film 11 is sequentially carried out by forming a mask composed of, for example, a photoresist film over the silicon oxide film 13, and then using the mask. The patterning of the polycrystal silicon film 10 is carried out by using the ONO film composed of the silicon oxide film 13, the silicon nitride film 12, and the silicon oxide film 11 as a mask.

[0186] In this step, the gate electrode 10a of the nonvolatile storage element Qm is formed over the memory cell formation region of the principal surface of the substrate 1 via the gate insulating film 16 composed of the ONO film (the silicon oxide film 7/the silicon nitride film 8/the silicon oxide film 9) interposed therebetween.

[0187] Whereas, the resistor element 10b having its top surface covered with the oxidation resistant film composed of the silicon nitride film 12 is formed over the first element isolation region of the principal surface of the substrate 1 via the oxidation resistant film composed of the silicon nitride film 9 interposed therebetween.

[0188] Further, the lower electrode 10c of the capacitor element C having its top surface covered with the oxidation resistant film composed of the silicon nitride film 12 is formed over the second element isolation region of the principal surface of the substrate 1 via the oxidation resistant film composed of the silicon nitride film 9 interposed therebetween.

[0189] Still further, the ONO film (the silicon oxide film 11/the silicon nitride film 12/the silicon oxide film 13) for use as the dielectric film of the capacitor element C is formed over the lower electrode 10c by overetching for the patterning of the polycrystal silicon film 10.

[0190] Whereas, in this step, each thickness of the portions of the silicon oxide film 13 over the resistor element 10b and over the lower electrode 10c, and the portions of the silicon oxide film 9 in the peripheries of the resistor element 10b and the lower electrode 10c is reduced.

[0191] Then, as shown in FIG. 19, the portions of the silicon nitride film 8 in the peripheries of the gate electrode 10a, the resistor element 10b, and the lower electrode 10c are removed. Thereafter, an impurity for forming the low voltage system well regions is selectively ion-implanted into the principal surface of the substrate 1, followed by a heat treatment for activating the impurity. As shown in FIG. 20, this results in the formation of the low voltage system n-type well region 14 in the low breakdown voltage pMIS formation region, and the low voltage system p-type well region 15 under the first element isolation region.

[0192] As the impurity for forming the low voltage system n-type well region 14, for example, phosphorus (P) is used.

[0193] The ion implantation of phosphorus is carried out under the conditions as follows:

[0194] The accelerating energy is 360 KeV, and the dose amount is 2.010¹³ atoms/cm²;

[0195] The accelerating energy is 100 KeV, and the dose amount is 1.510¹² atoms/cm²; or

[0196] The accelerating energy is 40 MeV, and the dose amount is 8.010¹² atoms/cm².

[0197] As the impurities for forming the low voltage system p-type well region 15, for example, boron (B) and boron difluroride (BF₂) are used.

[0198] The ion implantation of boron is carried out under the conditions as follows:

[0199] The accelerating energy is 200 KeV, and the dose amount is 1.510¹³ atoms/cm²;

[0200] The accelerating energy is 120 KeV, and the dose amount is 5.010¹² atoms/cm²; or

[0201] The accelerating energy is 50 MeV, and the dose amount is 1.510¹² atoms/cm².

[0202] Whereas, the ion implantation of boron difluoride is carried out under the conditions of an accelerating energy of 60 KeV and a dose amount of 2.010¹³ atoms/cm².

[0203] The boron difluoride for forming the low voltage system p-type well region is implanted for controlling the threshold value voltage.

[0204] Herein, the formation of the low voltage type well regions (14 and 15) is carried out after forming the gate insulating film of the nonvolatile storage element Qm. Therefore, the low voltage system well regions will not be subjected to the heat treatment for the formation of the silicon oxide film 7, and the heat treatment for the formation of the silicon oxide film 9. Accordingly, it is possible to reduce the number of times the low voltage system well regions are heat-treated.

[0205] Then, the portions of the buffer insulating film 6 over the high voltage system p-type well region 4, over the low voltage system n-type well region 14, and over the high voltage system n-type well region 3 are removed. Subsequently, the substrate 1 is subjected to a heat treatment. As shown in FIG. 21, this results in the formation of the gate insulating film 17 composed of a thick silicon oxide film with a thickness of, for example, about 18 nm over the high voltage system p-type well region 4, over the low voltage system n-type well region 14, and over the high voltage system n-type well region 3. The removal of the portions of the buffer insulating film 6 reduces the thickness of the portions of the silicon oxide film 13 over the resistor element 10b and over the lower electrode 10c.

[0206] In this step, the oxidation resistant film composed of the silicon nitride film 8 is provided between the lower electrode 10c and the second element isolation region. Therefore, it is possible to suppress the oxidation of the bottom surface of the lower electrode 10c. Whereas, the top surface of the lower electrode 10c is covered with the oxidation resistant film composed of the silicon nitride film 12 in the dielectric film. Therefore, it is possible to suppress the oxidation of the lower electrode 10c.

[0207] Whereas, in this step, the oxidation resistant film composed of the silicon nitride film 8 is provided between the resistor element 10b and the first element isolation region. Therefore, it is possible to suppress the oxidation of the bottom surface of the resistor element 10b. Whereas, the top surface of the resistor element 10b is covered with the oxidation resistant film composed of the silicon nitride film 12. Therefore, it is possible to suppress the oxidation of the resistor element 10b.

[0208] Then, the gate insulating film 17 over the low voltage system n-type well region 14 is selectively removed. Subsequently, the substrate 1 is subjected to a heat treatment. As shown in FIG. 22, this results in the formation of the gate insulating film 18 composed of a thin silicon oxide film with a thickness of, for example, about 3.7 nm over the low voltage system n-type well region 14. With this heat treatment, the thickness of the gate insulating film 17 becomes from 18 nm to 19 nm, and the thickness of the portions of the silicon oxide film 13 over the resistor element 10b and over the lower electrode 10c becomes 1 nm.

[0209] In this step, the oxidation resistant film composed of the silicon nitride film 8 is provided between the lower electrode 10c and the second element isolation region. Therefore, it is possible to suppress the oxidation of the bottom surface of the lower electrode 10c. Whereas, the top surface of the lower electrode 10c is covered with the oxidation resistant film composed of the silicon nitride film 12 in the dielectric film. Therefore, it is possible to suppress the oxidation of the lower electrode 10c.

[0210] Whereas, in this step, the oxidation resistant film composed of the silicon nitride film 8 is provided between the resistor element 10b and the first element isolation region. Therefore, it is possible to suppress the oxidation of the bottom surface of the resistor element 10b. Whereas, the top surface of the resistor element 10b is covered with the oxidation resistant film composed of the silicon nitride film 12. Therefore, it is possible to suppress the oxidation of the resistor element 10b.

[0211] Then, as shown in FIG. 23, a second-layer polycrystal silicon film 19 with a thickness of, for example, about 250 nm is formed entirely over the principal surface of the substrate 1 including over the gate insulating films 17 and 18, and over the silicon oxide film 13 over the lower electrode 10c by a CVD process. Subsequently, an impurity for reducing the resistance value is ion-implanted into the polycrystal silicon film 19, followed by a heat treatment for activating the impurity. Then, as shown in FIG. 23, a silicon oxide film 20 with a thickness of, for example, about 70 nm is formed entirely over the polycrystal silicon film 19 by a CVD process.

[0212] Then, the silicon oxide film 20 and the polycrystal silicon film 19 are sequentially patterned. As shown in FIG. 24, this results in the formation of the gate electrode 19a of the selecting MISFET-Qs over the gate insulating film 17 of the memory cell formation region, the gate electrode 19b of the low breakdown voltage p-type MISFET-QLP over the gate insulating film 18 of the low breakdown voltage MIS formation region, the gate electrode 19d of the high breakdown voltage p-type MISFET-QHP over the gate insulating film 17 of the high breakdown voltage pMIS formation region, and the upper electrode 19c over the ONO film over the lower electrode 10c.

[0213] Then, an impurity (e.g., phosphorus), impurities (e.g., boron difluoride, and phosphorus for punch through stopper), and an impurity (e.g., boron difluoride) are selectively ion-implanted into the high voltage system p-type well region 4 of the memory cell formation region, the low voltage system n-type well region 14 of the low breakdown voltage pMIS formation region, and the high voltage system n-type well region 3 of the high breakdown voltage pMIS formation region, respectively. As shown in FIG. 25, these result in the formation of the n-type semiconductive regions (extension regions) 21 in alignment with the gate electrode 10a and the n-type semiconductive regions (extension regions) 21 in alignment with the gate electrode 19a in the high voltage system p-type well region 4 of the memory cell formation region, the p-type semiconductive regions (extension regions) 23 in alignment with the gate electrode 19b in the low voltage system n-type well region 14 of the low breakdown voltage pMIS formation region, and the p-type semiconductive regions (extension regions) 22 in alignment with the gate electrode 19d in the high voltage system n-type well region 3 of the high breakdown voltage pMIS formation region.

[0214] Then, as shown in FIG. 26, the sidewall spacers 24 are formed on the respective sidewalls of the gate electrodes 10a, 19a, 19b, and 19d. The sidewall spacers 24 are formed in the following manner. An insulating film composed of, for example, a silicon oxide film is formed entirely over the principal surface of the substrate 1 by a CVD process. Subsequently, the insulating film is subjected to anisotropic etching such as RIE (Reactive Ion Etching). In this step, each sidewall spacer 24 is formed in alignment with its corresponding gate electrode. Further, the sidewall spacers 24 are also formed on the respective sidewalls of the resistor element 10b, the lower electrode 10c, and the upper electrode 19c.

[0215] Then, impurities (e.g., phosphorus and arsenic) are selectively ion-implanted into the high voltage system p-type well region 4 of the memory cell formation region. As shown in FIG. 27, this results in the formation of the n-type semiconductive regions (contact regions) 25 in alignment with the sidewall spacer 24 in the high voltage system p-type well region 4 of the memory cell formation region. Whereas, impurities (e.g., boron difluoride and boron) are selectively ion-implanted into the low voltage system n-well region 14 of the low breakdown voltage pMIS formation region, and the high voltage system n-type well region of the high breakdown voltage pMIS formation region. As shown in FIG. 27, this results in the formation of the p-type semiconductive regions (contact regions) 26 in alignment with the sidewall spacer 24 in the low voltage system n-type well region 14 of the low breakdown voltage pMIS formation region and the high voltage system n-type well region of the high breakdown voltage pMIS formation region.

[0216] Then, a natural oxide film, and the like are removed to expose the surfaces of the gate electrodes (10a, 19a, 19b, and 19d), the surfaces of the contact regions of the resistor element 10b, the surface of the contact region of the lower electrode 10c, and the surface of the upper electrode 19c. Then, entirely over the principal surface of the substrate 1 including over these surfaces, for example, a cobalt film 27 is formed as a refractory metal film by a sputtering process. Subsequently, a heat treatment for causing the reaction of the silicon (Si) of the semiconductive regions (25 and 26), the Si in the gate electrodes (10a, 19a, 19b, and 19d), the Si in the contact regions of the resistor element 10b, the Si in the contact region in the lower electrode 10c, and the Si in the upper electrode 19c with the Co in the cobalt film 27 is conducted. As shown in FIG. 28, this results in the formation of a silicide (CoSi) layer 28 which is a metal/semiconductor reaction layer in the surfaces of the semiconductive regions (25 and 26), the surfaces of the gate electrodes (10a, 19a, 19b, and 19d), the surfaces of the contact regions of the resistor element 10b, the surface of the contact region of the lower electrode 10c, and the surface of the upper electrode 19c. The silicide layer 28 is formed in alignment with the sidewall spacers 24.

[0217] Then, the unreacted cobalt film 27 in a region other than the region in which the silicide layer 28 has been formed is selectively removed, followed by a heat treatment for activating the silicide layer 28 (to CoSi₂).

[0218] With this step, the nonvolatile storage element Qm, the selecting MISFET-Qs, the low breakdown voltage p-type MISFET-QLp, the high breakdown voltage p-MISFET-QHp, the resistor element 10b, and the capacitor element C are almost completed.

[0219] Then, the interlayer insulating film 29 composed of, for example, a silicon oxide film is formed entirely over the principal surface of the substrate 1 including over the foregoing active elements and passive elements by a CVD process. Subsequently, the surface of the interlayer insulating film 29 is planarized by a CVD process.

[0220] Then, the contact holes for the sources/the drains, the contact holes for the gates, the contact holes for the resistor element, the contact hole for the lower electrode, and the contact hole for the upper electrode, reaching from the surface of the interlayer insulating film 29 to the silicide layer 28 are formed. Subsequently, a conductive substance such as a metal is embedded inside the contact holes to form the conductive plugs 30. Thereafter, the wiring 31 is formed over the interlayer insulating film 29, results in the configuration shown in FIGS. 1 to 4.

[0221] FIG. 11 is a graph showing the polycrystal silicon width dependency of the resistance value in the resistor element 10b. The thickness of the silicon nitride film 12 when deposited over the resistor element 10b is taken as a parameter. As shown in FIG. 11, as the silicon nitride film 12 increases in thickness, the oxidation from the sides of the polycrystal silicon film during the step is more suppressed, and the thin wire effect is suppressed. When the width of the polycrystal silicon film is reduced to 1 m or less, the thickness of the silicon nitride film 12 when deposited is desirably 24 nm or more.

[0222] Thus, in accordance with this embodiment, the following effects are obtainable.

[0223] The oxidation resistant film composed of the silicon nitride film 8 is provided between the second element isolation region of the principal surface of the substrate 1 and the lower electrode 10c. Whereas, the top surface of the lower electrode 10c is covered with the oxidation resistant film composed of the silicon nitride film 12. In this state, a heat treatment is carried out to form the gate insulating films 17 and 18 composed of the silicon oxide film in the principal surface of the substrate 1. As a result, it is possible to suppress the oxidation of the bottom surface and the top surface of the lower electrode 10c. Further, it is possible to suppress the formation of bird's beaks each extending from the side of the lower electrode 10c along the interface between the lower electrode 10c and the second element isolation region. Accordingly, it is possible to suppress the warp of the lower electrode 10c caused by the birds beaks. This can suppress the deficiency that the lower electrode 10c is peeled off. As a result, it is possible to implement the capacitor element C with a small occupying area and a large capacitance.

[0224] Further, it is possible to manufacture a system LSI mounting therein a capacitor element C with a small occupying area and a large capacitance at a high yield.

[0225] Whereas, the oxidation resistant film between the second element isolation region and the lower electrode 10c is formed by the same process as with the silicon nitride film 8 in the gate insulating film of the nonvolatile storage element Qm. The oxidation resistant film over the lower electrode 10c is the silicon nitride film 12 in the dielectric film of the capacitor element C. Therefore, it is possible to implement the capacitor element C with a small occupying area and a large capacitance without increasing the number of manufacturing steps, and it is possible to manufacture a system LSI mounting therein a capacitor element C with a large capacitance at a high yield.

[0226] The oxidation resistant film composed of the silicon nitride film 8 is provided between the first element isolation region of the principal surface of the substrate 1 and the resistor element 10b. Whereas, the top surface of the resistor element 10b is covered with the oxidation resistant film composed of the silicon nitride film 12. In this state, a heat treatment is carried out to form the gate insulating films 17 and 18 composed of the silicon oxide film over the principal surface of the substrate 1. As a result, it is possible to suppress the oxidation of the bottom surface and the top surface of the resistor element 10b. Therefore, even if the resistor element 10b is formed of the first-layer polycrystal silicon film 10, it is possible to form the high resistive resistor element 10b with stability.

[0227] Whereas, the oxidation resistant film between the first element isolation region and the resistor element 10b is formed by the same process as with the silicon nitride film 8 in the gate insulating film of the nonvolatile storage element Qm. The oxidation resistant film over the lower electrode 10c is formed by the same process as with the silicon nitride film 12 in the dielectric film of the capacitor element C. Therefore, it is possible to stably form the high resistive resistor element 10b without increasing the number of manufacturing steps.

[0228] After the formation of the gate insulating film 16 composed of the ONO film of the nonvolatile storage element Qm, the low voltage system well regions (14 and 15) are formed. This can reduce the number of times the low voltage system well regions are heat treated. Therefore, it is possible to suppress the reduction in surface impurity concentration of the low voltage system well regions. As a result, it is possible to form a high breakdown voltage MISFET without affecting the characteristics of a general low breakdown voltage MISFET.

[0229] Up to this point, the invention completed by the present inventors has been specifically described based on the embodiment. However, the present invention is not limited to the foregoing embodiment, and various modifications may be naturally made in the scope not departing from the gist thereof.

[0230] The effects obtainable with the typical ones out of the inventions disclosed in this application will be briefly described as follows.

[0231] In accordance with the present invention, it is possible to implement a capacitor element with a small occupying area and a large capacitance.

[0232] In accordance with the present invention, it is possible to implement a high resistive resistor element.

[0233] In accordance with the present invention, it is possible to form a high breakdown voltage MISFET without affecting the characteristics of a low breakdown voltage MISFET In accordance with the present invention, it is possible to improve the yield in manufacturing of a semiconductor integrated circuit device.