Multi-service packet network interface

[0001] The applicants claim priority based on provisional application Ser. No. 60/419,865, Multi-Service Ethernet-Over-SONET Silicon Platform, filed Oct. 21, 2002, the complete subject matter of which is incorporated herein by reference in its entirety.

[0002] This application is a continuation in part of U.S. application Ser. No. 10/318,444, Multi-Service Ethernet-Over-SONET Silicon Platform, filed on Dec. 13, 2002, which is incorporated herein by reference in its entirety.

[0003] Not Applicable

[0004] Not Applicable

[0005] Certain embodiments of the present invention relate to providing access to broadband communication systems. More specifically, certain embodiments relate to an apparatus which provides an interface to connect to broadband synchronous optical networks in order to provide a variety of synchronous and packet network connections. Additional embodiments described relate to an apparatus that may provide a packet network interface operating at a higher bit rate using a group of communications links operating at a lower bit rate as the transport mechanism.

[0006] In the past, a variety of transmission technologies have been used to electronically transfer large amounts of digital information, including both terrestrial and satellite links. Terrestrial facilities that have commonly been used include both buried and above-ground cable, microwave radio and most recently, optical fiber, which offers the largest bandwidth. Networks used for such high capacity data transport systems are typically synchronous networks.

[0007] A synchronous network is one example of what is traditionally referred to as a circuit-switched network. In a synchronous network, data is transmitted from one location to another as a continuous stream of digital information moving from the source to the destination at a constant rate. The stream is organized as a sequence of frames, each frame containing a fixed number of fields in a defined order, each field of the same length. An end-to-end connection or circuit in a synchronous network exists as a collection of individual segments which are assigned when the circuit is built or provisioned. At the time that a circuit is provisioned it is assigned the use of one or more of the fields in the frames exchanged across a given segment, and a circuit may be assigned a different field within the frames carried on different segments. The transfer of data at the point of connection of one segment to another is time synchronized, and does not add significant delay. Because the data on any segment moves at a constant rate, and no delay occurs at the connections between segments, the time needed to travel from one end to the other end of a circuit is fixed. The Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH) are the principal synchronous optical network standards currently in use. In the SONET standard, the term circuit in the above discussion corresponds to the SONET term path, and the term segment corresponds to the SONET term link. An example of a path in a SONET network is shown in FIG. 1.

[0008] In most cases, no single user needs all of the capacity of an optical fiber-based transmission system, so the standards have been designed to provide a means to share the bandwidth. For example, SONET networks typically operate at data rates of between 51.84 megabits per second (Mbps) and 10 gigabits per second (Gbps). Within that range, a device called an add/drop multiplexer (ADM) can be used to insert or extract a lower bit rate stream to or from one of a higher bit rate. A diagram showing the SONET hierarchy and the relationships between bits rates is illustrated in FIG. 2.

[0009] In contrast to circuit switched networks, packet networks consist of a mesh of nodes interconnected by links, and data is exchanged in bursts called packets. The use of packet networks is growing in popularity due to the flexibility offered by the ability of a packet network to efficiently handle multiple data streams of widely varying bandwidth. This flexibility is one of the factors helping to bring about a convergence of data and voice networks. The packet contents include the address of its destination, and it is the function of each node to direct each packet that it receives to a link that will send it closer to its destination. In general, a packet is queued at a node before being forwarded to the next node in the path, because it may have to wait for the outgoing link to become available. Packets may contain voice, data, or video information, and can be of varying length. The amount of time that a packet takes to travel from the source to the destination varies based upon a number of factors including the number of nodes, the speed of the links, and the queuing delay that occurred at each node. Each of the services supported on a packet network has its own set of requirements including, for example, end-to-end delay, packet loss, and privacy. Designers of packet networks take those requirements into consideration.

[0010] Synchronous optical networks are the primary transport mechanism for long distance transmission of information, and are becoming increasingly important in metropolitan areas. At the same time, the use of packet networks is growing rapidly due to their ability to efficiently carry multiple data streams of widely varying bandwidth. With the passage of time, the number and variety of data services, the number of users, and the total bandwidth required at any particular user location will grow. Some legacy equipment requires lower speed synchronous network connections, while other equipment requires a packet network interface. In some applications, more than one synchronous optical link may be needed to support the total bandwidth required. As user demand for higher bandwidth connections grows and synchronous optical networks expand, support for connections of varying bandwidth will become increasingly important. The result is an ever-growing need for high-capacity, highly-functional, cost-effective systems for the connection of synchronous optical networks to packet networks and to lower speed synchronous networks.

[0011] The functionality that may be needed to connect a SONET or SDH synchronous optical network and a packet network includes that of an Add-Drop Multiplexer (ADM) or terminal, a Digital Cross-Connect (DCC), and a Multi-Service Provisioning Platform (MSPP). ADMs are used to transport SONET or SDH traffic on network ring topologies. An example of such a SONET ring is shown in FIG. 3. The most popular of these ring topologies are Unidirectional Protected Switched Rings (UPSR) and Bidirectional Line Switched Rings (BLSR). In this arrangement, the nodes on the ring are linked by two optical fiber connections that transmit data in opposite directions. Should one of the optical fibers experience a failure, the nodes in the ring are still able to communicate using the other optical fiber. The ADMs are nodes on such rings that are used to arbitrate (add or drop) traffic to or from the ring. Rings are interconnected by gateways, as illustrated in FIG. 4. The client traffic on the ADM (the traffic that is added or dropped from the network ring) is normally transmitted at a lesser data rate than the network traffic (the traffic on the ring). Typical ring traffic rates for both SONET and SDH are 155 Mbps, 622 Mbps, 2488 Mbps and 9953 Mbps. These correspond to OC-3, OC-12, OC-48 and OC-192 rates for SONET respectively, and to STM-1, STM-4, STM-16 and STM-64 rates for SDH respectively. Client traffic on the ADM can either be a lower SONET or SDH rate than the ring rate, or it can be a PDH rate (Plesiochronous Digital Hierarchy), such as DS1, DS2 or DS3 or E1, E2 and E3. The DS1 rate is 1.544 Mbps, DS2 is 6.312 Mbps, DS3 is 44.736 Mbps, E1 is 2.048 Mbps, E2 is 8.448 Mbps, and E3 is 34.368 Mbps.

[0012] A SONET/SDH terminal performs a function similar to that of an ADM except that the network connection is not in a ring configuration. A terminal terminates a high speed point-to-point SONET path, and hands off a number of lower rate lines and paths on the client side. For example, an OC-3 terminal could be used to terminate an OC-3 path and hand off three DS3 lines on the client side.

[0013] The DCCs are used to switch and groom traffic between different lines and paths. A network may include several ADMs and terminals to arbitrate or terminate traffic along rings or point-to-point connections, and a DCC will be used to switch the traffic between all the paths. A DCC is a circuit switch, which means that all connections are provisioned statically.

[0014] The Multi-Service Provisioning platform combines the function of the DCC, the ADM, and the terminal along with the ability to support data protocols such as Ethernet to the client users. In all instances today, these MSPPs are scalable platforms based on a chassis. This means that to build a useful system, a user needs to install a specific circuit card supporting each function. The purpose of the chassis is to hold the required circuit cards, provide an electrical interconnect or backplane to connect signals from one card to another, and to supply power for system operation. For example, separate cards are needed for switching, supporting the ADM function, supporting and mapping DS1 traffic, supporting and mapping DS3 traffic, and supporting and mapping Ethernet traffic. FIG. 5 illustrates an example chassis arrangement of an MSPP 500, showing Ethernet interface card 502, cross-point switch card 504, synchronous optical interface cards 506 and 508, and processor card 510. The silicon devices developed to support these platforms tend to implement an ever increasing but still small portion of the needed functionality. For instance, there are devices on the market supporting SONET framing, DS1 framing and mapping, DS3 framing and mapping, DS1 mapping into DS3 (known as M13 mappers), Ethernet-over-SONET mappers, and digital cross-connects. Building a system is complex and costly due to the number of cards and/or individual integrated circuit devices required. The variety and number of network connections that can be supported by the MSPP system is limited by several factors, including the level of functionality and number of connections on each integrated circuit device, the number of circuit cards that can be contained within the chassis, and the number of signals that must be carried by the backplane.

[0015] Situations exist where Ethernet packet network service is desired and where optical connectivity is not available or is not cost effective, but where there are available multiple lower bit-rate circuit-switched communications links. For example, synchronous time division multiplex service such as DS1 has been in widespread use for many years. Some subscribers may have multiple DS1 or digital subscriber loop (DSL) lines available on site, but have a need for 10 Mbps Ethernet packet connectivity. Many subscribers that may need Ethernet packet network connectivity cannot make effective use of even the lowest level of SONET/SDH capacity. A low-cost solution to provide a packet network interface via multiple lower speed links is needed.

[0016] As can be seen from the above discussion, there is a fundamental disconnect between the packet network environment and core optical networks such as SONET and SDH. There is also a need for systems able to provide packet network connectivity using available lower speed facilities. The relatively high cost of the technology typically used to fill these gaps hinders network growth and further expansion of support for metropolitan optical networks and packet network service. Accordingly there is a need for a more compact, cost-effective, and more flexible solution to providing packet network over legacy facilities as well as newer SONET and SDH-based optical networks.

[0017] Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

[0018] Aspects of the present invention relate to a device that permits the interconnection of circuit-switched and packet networks. More specifically, one embodiment of the present invention may be a single integrated circuit that includes the functionality that may be required to provide Ethernet packet service using a group of lower-speed, time division multiplex connections.

[0019] An embodiment in accordance with the present invention may comprise a hashing processor for selecting a transmit data channel and for designating a receive packet interface and a transmit packet interface. In addition, it may comprise a packet mapper for processing at least one transmit packet from the designated transmit packet interface operating at a first bit rate, the packet mapper transferring the contents of the at least one transmit packet to the selected transmit data channel, and may process data from at least one receive data channel, producing at least one receive packet for transmission on the designated receive packet interface operating at the first bit rate. Further, it may comprise at least one communication interface for serializing data from the transmit data channel to form a transmit data stream, and for passing to the receive data channel data deserialized from a receive data stream, the transmit data stream and receive data stream operating at a second bit rate. A packet format of the at least one receive packet and the at least one transmit packet may be compliant with at least one of the Institute of Electrical and Electronic Engineers 802.3 family of Ethernet standards. In such an embodiment, the first bit rate may be greater than the second bit rate.

[0020] An embodiment may also comprise at least one optical carrier framer for performing transmit framing on data from at least one transmit data channel producing a transmit data sequence, and for performing receive framing on a receive data sequence producing data for at least one receive data channel. The packet mapper may be compatible with the American National Standards Institute T1X1.5 Generic Framing Procedure, the International Telecommunications Union X.86 Ethernet over SONET recommendation, or the Internet Engineering Task Force RFC 1662 point-to-point protocol specification. In addition, a format of the transmit data sequence and the receive data sequence may be compatible with the Synchronous Optical Network or Synchronous Digital Hierarchy optical carrier standard.

[0021] Another embodiment of the present invention may comprise a bus interface for connecting additional communications interface devices where the bus interface is a telecom bus compatible interface. The at least one communication interface of an embodiment may comprise at least one T/E carrier framer for receiving and transmitting data in time division multiplexed format which may comprise a DS1 or E1 format framer and a DS3 or E3 format framer. It may further comprise an M13 multiplexer for converting DS1 format time division multiplex data streams to and from DS3 format.

[0022] A further embodiment in accordance with the present invention may comprise at least one embedded microprocessor core arranged in order to receive signals from the hashing processor, and an embedded memory for storing information to be accessed by the at least one embedded microprocessor core. It may comprise an external memory interface arranged to allow the at least one embedded microprocessor core to access information stored in an external memory device, and the functionality of the embodiment may be contained within a single integrated circuit.

[0023] Another aspect of the present invention is a method of operating a data communication device, the method comprising receiving a first packet from a first packet stream at a higher bit rate, selecting a first data link from a predefined group of data links, depacketizing the first packet to a first data stream, transmitting the first data stream on the first data link at a lower bit rate, receiving a second data stream on a second data link at the lower bit rate, packetizing the second data stream into a second packet, designating a second packet stream on which to send the second packet, and transmitting the second packet on the second packet stream at the higher bit rate. A packet format of the first packet stream and the second packet stream may be compliant with at least one of the Institute of Electrical and Electronic Engineers 802.3 family of Ethernet standards. The first data link and the second data link may use a time division multiplex format where the time division multiplex format is DS1 or E1 compliant. The first data link and the second data link may also be a type of digital subscriber line.

[0024] Another aspect of the invention may include machine-readable storage, having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the foregoing.

[0025] These and other advantages, aspects, and novel features of the present invention, as well as details of illustrated embodiments, thereof, will be more fully understood from the following description and drawings.

[0026] FIG. 1 is a block diagram showing the elements along the path in a SONET network.

[0027] FIG. 2 is a hierarchy diagram showing the names and relationships of the various link capacities available within the SONET hierarchy.

[0028] FIG. 3 is a block diagram showing the structure of a exemplary SONET ring, and the elements and interconnections that may be present.

[0029] FIG. 4 is a block diagram illustrating an exemplary interconnection of two SONET ring structures, and the gateway which connects them.

[0030] FIG. 5 is an illustration of the chassis of an exemplary multi-service provisioning platform, showing the arrangement of the individual circuit cards that may be used to support various communications services.

[0031] FIG. 6 is network diagram showing an exemplary network configuration in which a SONET network and a packet network are interconnected to provide a variety of services, in accordance with an embodiment of the present invention.

[0032] FIG. 7 is a high-level block diagram illustrating a single-chip embodiment of the present invention.

[0033] FIG. 7a shows an embodiment of the present invention which is contained within one or more integrated circuits on a single circuit card having a single connector.

[0034] FIG. 7b illustrates an embodiment in accordance with the present invention where the functionality shown in FIG. 7 is incorporated on a single circuit card having two connectors.

[0035] FIG. 8 is a block diagram showing functionality that may be present in one embodiment according to the present invention.

[0036] FIG. 8a shows an exemplary embodiment illustrating the bonding of seven DS1 synchronous time division multiplex circuits into a bonded group that transports the traffic from a first 10 Mbps Ethernet link to a second 10 Mbps Ethernet link, in accordance with the present invention.

[0037] FIG. 8b is a block diagram showing functionality that supports the use of bonded links in an embodiment of the present invention.

[0038] FIG. 9 is a high-level flow diagram showing a method of operating an embodiment of the present invention.

[0039] FIG. 9a is a high-level flow diagram illustrating a method of operating another embodiment in accordance with the present invention.

[0040] FIG. 9b illustrates a network architecture in which two bonded groups are used in sequence, in accordance with the present invention.

[0041] FIG. 9c shows an exemplary network architecture using multiple embodiments of the present invention to interface a packet link to a SONET optical link.

[0042] FIG. 10 is a high-level flow diagram showing another method of operating an embodiment in accordance with the present invention.

[0043] Aspects of the present invention may be seen in FIG. 6, which illustrates the interconnections in an example of a data communications network. As shown in the diagram, portions of the network, such as SONET optical link 606, metropolitan area network connection 616, and SONET ADM Network 602, are synchronous optical network links. Other portions, such as packet connection 618 linking ADM 608 to users 614, and Core IP Network and Public Internet 604, are constructed using a packet network. The fundamental difference in these two forms of data transport may require a means at several points along the transmission path to adapt packetized data for transmission via a synchronous link, and synchronous data for packet transport. For example, packet data traffic from service provider 620 destined for users 612 may be sent in Ethernet packet format from service provider 620 through Core IP Network 604 and directed onto packet-over-SONET link 606. The broadband traffic may then pass through SONET ADM Network 602 onto metropolitan area network 616 to multi-service provisioning platform 610, where it would be mapped into one or more Ethernet packet connections to users 612. Packets flowing from users 612 back to service provider 620 would require similar data format adjustments. An embodiment of the present invention may provide the functionality needed to allow a broadband synchronous optical network to serve a variety of synchronous and packet network connections in a flexible manner at lower cost than existing alternatives, and may be incorporated into a circuit card in add/drop multiplexer 608. It may also be used to offer Ethernet services in metropolitan markets by leveraging the SONET infrastructure. To support such an application, an embodiment of the present invention may be contained within multi-service provisioning platform 610. In such applications, it may support the use of Ethernet private lines, and advanced Internet protocol (IP) services such as Voice-over-IP (VoIP) telephony. The present invention may also be used to provide advanced remote troubleshooting features on subscriber connections 618.

[0044] An embodiment of the present invention may combine all of the functionality that may be needed to provide client-side support for a variety of interfaces, including 10 Mbps/100 Mbps and gigabit Ethernet, DS1/E1 and DS3/E3 time-division-multiplexed synchronous links, and network or trunk-side interfaces for one or more synchronous optical links or DS3/E3 time-division-multiplexed synchronous links in a single integrated circuit, or in a multi-chip configuration. A high-level block diagram illustrating an exemplary embodiment of the present invention is shown in FIG. 7. In this embodiment, incoming signals from SONET line 704 are converted by SONET-to-Ethernet/TDM Conversion block 710 into one or more packet streams 725 and one or more TDM data streams 730. In the reverse direction, the functionality of Ethernet/TDM-to-SONET Conversion block 720 receives one or more packet streams 735 and one or more TDM data streams 740, and converts them into a format suitable for transmission via SONET line 715. The functionality shown in FIG. 7 for inclusion in an embodiment of the present invention permits the realization of a single-chip device. For example, it is possible to eliminate the Optical Internetworking Forum System Packet Interface (SPI) typically used to interconnect some of the illustrated functionality. Removing the need for this interface not only frees the chip area that would typically be used for the interface components, it enables an embodiment of the present invention to incorporate a significantly larger number of virtual channel connections between the packet processing and network interface (SONET/TDM) blocks. This increases device capacity and performance, and permits the integration of the functionality of FIG. 7 into a single integrated circuit device or a multi-chip solution of lower cost and higher performance than prior art solutions.

[0045] FIG. 7a shows an embodiment of the present invention in which the above functionality is contained within one or more integrated circuits on a single circuit card 705a. In such an embodiment, both the SONET and packet data streams are directed through a single connector 715a. The high level of functionality present on circuit card 705a eliminates the need for many other circuit cards in the MSPP 500 of FIG. 5, freeing card slots for additional circuit cards 705a, or for the inclusion of other functionality in MSPP 500. FIG. 7b illustrates another embodiment in accordance with the present invention where the functionality shown in FIG. 7 is incorporated on a single circuit card 705b having two connectors. Connector 715b may, for example, carry SONET receive and transmit signals 710b and 720b, respectively. Connector 725b may, for example, carry Ethernet receive and transmit signals 730b and 740b, respectively, and time division multiplex receive and transmit signals 750b and 760b, respectively. Such an embodiment eliminates the need for the backplane typically present in systems with this level of functionality, and permits the development of a relatively small, SONET-to-Ethernet interface device. Additional details of the functionality that may be present in embodiments such as these follows.

[0046] FIG. 8 shows a block diagram illustrating further detail of functionality that may be present in a single-chip embodiment according to the present invention. Such an embodiment may incorporate a channelized framer 802, which may support the Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH) protocol specifications of optical link 834. The incoming and outgoing paths of optical link 834 of FIG. 8 correspond to, for example, optical links 704 and 715 of FIG. 7, respectively. Channelized framer 802 may support Uni-directional Protected Switched Rings (UPSR) with protected ADM uplinks via OC-12/48 optical lines. In such an arrangement, automatic protection switching (APS) control 820 supports switching from the main to the protection line. An embodiment may also support a Bi-directional Line Switched Ring (BLSR) ring topology. Channelized framer 802 may incorporate a full-capacity, non-blocking Synchronous Transport Signal (STS)/Synchronous Transport Module (STM) and Virtual Tributary (VT)/Tributary Unit (TU) cross-connect which may be used to switch channelized data streams between the optical line 834 and packet mapper 804, subscriber-side DS1/E1 and DS3/E3 framers 814 and 816, and telecom bus interface 822. An embodiment may support complete line and path overhead processing, including full STS/STM and VT/TU pointer processing. In addition, an embodiment may interface with a time-division-multiplexed (TDM) DS3/E3 uplink 836 via DS3/E3 framer 818.

[0047] Packet mapper 804 may support virtual concatenation (VC) for compatibility with the installed SONET/SDH network infrastructure, and may enable the use of various traffic segregation methods, for example, stacked virtual local area networks (VLANs), multi-protocol label switching (MPLS) labels, and VT1.5 and/or STS-1 Ethernet-over-SONET (EoS) mapping. Mapping of VLAN/MPLS groups to create a link-layer tunnel that may be supported by VLAN Engine 808. The use of provisioned tunnels with MPLS or VLANs may ensure that the bandwidth provisioned for subscriber access to Internet Protocol (IP) services is maintained, and that high-priority traffic will have the bandwidth resources needed to be passed unconstrained through the network during times of congestion & restoration. In one embodiment, packet mapper 804 may support Ethernet mapping to SONET using, for example, the ANSI T1X1.5 Generic Framing Procedure (GFP), the ITU X.86 EoS recommendation, or the Internet Engineering Task Force (IETF) RFC 1662 point-to-point protocol (PPP) specification. These procedures may be used for the Ethernet-to-SONET mapping functions, while 802.3x may be used for flow control at a subscriber line interface. Internet access traffic may be mapped into a shared concatenated channel, and both high order (STS-1-Xv) and low order (VT1.5-Xv) virtual concatenation may be supported. This capability may enable mapping to a channel of any size with 1.5 Mbps granularity. Each subscriber channel may be mapped to its own SONET channel. The subscriber may have multiple channels per physical port, for example, a private line channel and a channel for Internet access, and may also have multiple private lines on the same port. VLAN/MPLS tags may be mapped to physical ports, via media access control (MAC) addresses as well as logical channels.

[0048] Ethernet service on packet links 830 may be 10 megabit per second (Mbps), 100 Mbps, or 1000 Mbps. (gigabit) Ethernet (GigE/GbE) connections which may be supported by 10 Mbps/100 Mbps MAC 810 and Gig-E MAC 812. Both MAC 810 and MAC 812 may connect to external physical layer (PHY) interface devices (not shown). Support for TDM DS1/E1 and DS3/E3 interfaces may be provided by DS1/E1 framer 814 and DS3/E3 framer 816 via synchronous connections 832, the specifications of which may be designed to interface with appropriate external physical interface devices (not shown). An embodiment may allow the connection of additional communications interfaces such as additional DS1/E1 or DS3/E3 framers, through the use of telecom bus interface 822. The present invention may support full duplex operation at full rate for all frame sizes for 10BaseT, 100BaseTX, 1000BaseLX/SX. For telephone grade subscriber loop cabling, an Ethernet-to-DSL bridging chip may be used.

[0049] An embodiment of the present invention may support services such as Ethernet Private Lines, which provide secure local area network (LAN) interconnections between corporate sites, Internet access over Ethernet physical service links, and packet voice. An embodiment of the present invention may provide support for delay-sensitive traffic, such as IP telephony over Ethernet, which generally requires guaranteed minimum latency. IP-based interoffice telephony allows a single access line for data & interoffice voice, permitting cheaper interoffice voice calls using the IP network. This also allows re-use of an existing private branch exchange (PBX) infrastructure. Access to the public switched telephone network (PSTN) may be possible via a service provider's gateway. In such an arrangement, the subscriber pays only for data access service.

[0050] An embodiment of the present invention may support Ethernet private line service, which provides point-to-point transparent transport using Ethernet. Private line service implies that all attributes of the subscriber's Ethernet channel are preserved throughout the transport network, e.g. VLANs, etc. This capability allows a subscriber to connect two corporate LANs together, leveraging the SONET investment by making use of SONET DCS network. Ethernet traffic may be mapped into SONET containers, for example, STS and VT groups using the capabilities of channelized framer 802 and packet mapper 806. The mapping may be transparent. In such an application, privacy is typically of paramount importance.

[0051] The present invention may include traffic shaping, which may be supported by the policing, shaping, flow control and subscriber management functionality represented by functional block 806. This functionality may allow Ethernet subscriber ports to be rate limited with a 1 Mbps granularity up to gigabit rate or be shut off entirely, and may permit the service provider to offer Internet access provisioned as metered, tiered or burst-able service. For example, with tiered service the subscriber may choose a specific capacity tier to set the maximum allowable capacity they may access. Those limits may be set with, for example, a 10% granularity for 10/100 Ethernet and a 5% granularity for gigabit Ethernet. An embodiment may also allow a service provider to offer metered service in which subscribers pay only for the bandwidth they use on a per-use basis. In such an arrangement, the only bandwidth limit is the port speed (10 Mbps/100 Mbps/GbE). In addition, the service provider may offer burst-able service, which may be viewed as a combination of tiered and metered service. With burst-able service the subscriber operates within a specific bandwidth tier, allowing the subscriber to obtain a fixed amount of bandwidth. The allowed bandwidth limit might be set with, for example, a 10% granularity for 10 Mbps/100 Mbps Ethernet and with a 5% granularity for gigabit Ethernet service. The subscriber may then burst at up to the physical port speed.

[0052] In addition, the policing, shaping, flow control and subscriber management functionality represented by block 806 may support intelligent traffic shaping, which may guarantee minimum latency for delay-sensitive traffic such as packet voice. The present invention may provide subscriber port shaping/policing capabilities configurable to support IP Differentiated Services Code Point (DSCP) prioritized and/or weighted queuing enabling, for example, eight different link layer traffic priority levels as per 802.1D(p). It may also reprioritize 802.1D(p) priorities in the 802.1Q tag for traffic that exceeds the subscriber's provisioned bandwidth. An embodiment of the present invention may issue PAUSE frames when a subscriber attempts to burst beyond its provisioned bandwidth. However, the present invention may support intelligent traffic shaping that extends the PAUSE frame concept so that only certain flows (e.g. Internet access flows) are throttled. The intelligent traffic shaping approach is in addition to DSCP and 802.1D(p) priorities, because it guarantees a traffic shaping procedure going beyond priorities. This may provide enhanced traffic management, because priorities are irrelevant if the physical port is paused. An embodiment of the present invention may support a policing & congestion control mechanism similar to Frame Relay's Discard Eligible (DE) standard, marking traffic that is above the traffic profile and treating such traffic with a higher discard probability when network congestion occurs. Discretionary traffic shaping may be based on flow/priority type, and may permit traffic shaping at a physical port to be honored as may be required by a service level agreement (SLA). For example, an embodiment in accordance with the present invention may support system performance characteristics that meet the standard service provider's SLA's such as, for example, a one-way delay of 65 msec, data loss of 1%, and 100% availability. The functionality in block 806 supports the reality that some flows, however, should not be shaped. In general, Voice-over-Internet Protocol (VoIP) flows should not be paused, so that minimum latency to the MPLS IP network can be guaranteed for voice connections, for example.

[0053] The functionality represented by block 806 may also permit the collection of usage statistics based on class-of-service (CoS)/quality of service (QoS) for network management and SLA conformance purposes. Key benchmarks in such agreements may be latency, latency variation and data loss, and such parameters may be measured by an embodiment of the present invention. Other statistics that may be collected include port, VLAN, and 802.1D(p) traffic statistics, and available resources (bandwidth, buffer space, protection bandwidth, etc). An embodiment may also support the gathering of traffic statistics on subscriber ports independently. This information may be reported to operating personnel or systems at a remote location by embedded microprocessor core 824, using the SONET data communications channel (DCC).

[0054] An embodiment of the present invention may protect 100% of allocated subscriber access bandwidth to IP service within the network, and may also provide different levels of protection. In a fiber cut or port failure scenario, the traffic restoration mechanism contained within block 820 may use SONET UPSR ring technology for fault discovery, traffic switchover and alarm propagation. Channelized framer 802 may have, for example, two STS-48 ports to connect either to the ring or to a redundant backplane link. On the subscriber side, an embodiment of the present invention may provision protected links between itself and the CPE. Each subscriber may have, for example, two connections, and the protected connection may switch over if the main connection goes down. Software stored in embedded memory 826 may direct embedded microprocessor core 824 to use VLAN mapping to different 802.1D(p) priorities as a way to protecting subscriber traffic at different levels of protection.

[0055] An embodiment of the present invention may support advanced maintenance and operations support functionality, due in part to the immediate and broad access by embedded microprocessor core 824 to status information and operating parameters contained within, for example, channelized framer 802, MACs 810 and 812, packet mapper 804, DS1/DS3 framers 814, 816, and 818, and policing/shaping/flow control/subscriber management functionality 806. To support such functionality, an embodiment of the present invention may provide for creation of a subscriber demarcation point in the same facility as the CPE, and may permit remote loop-back at both the line and MAC levels. This capability may enable the monitoring and isolation of physical problems on the subscriber link from a remote location up to the CPE. In addition, MAC 810 and MAC 812 may support time-domain-reflectometry (TDR) functionality on ports to isolate break points for copper-based subscriber loops. Software instructions contained within embedded memory 826 or external memory connected to external memory interface 828 may permit processor 824 to report the illustrated failure conditions, locations, and other diagnostic information to the operator of the system either through control frames (dedicated VLAN) or via the SONET DCC channel. An embodiment may also have the mechanisms to identify and geographically locate network degradation using alarms from the equipment, and may be able to distinguish between layer 0/1 and layer 2 degradation or faults.

[0056] An embodiment in accordance with the present invention may include external memory that may be accessed by embedded microprocessor core 824 via external memory interface 828. This functionality may allow software instructions stored in embedded memory 826 or external memory connected to external memory interface 828 to use the SONET DCC channel for remote management & provisioning. Software programs stored in embedded memory 826 may permit embedded microprocessor core 824 to receive via a private Ethernet tunnel in-the-field downloadable software upgrades to be stored in a flash memory connected to external memory interface 828. It will be clear to those skilled in the art that the ability to remotely upgrade software is of great value in operating and maintaining networking equipment. In addition, the instructions for an algorithm comparable to admission control may be contained within embedded memory 826 or external memory connected to external memory interface 828 and implemented by embedded microprocessor core 824, to disallow provisioning changes which would adversely affect customer traffic and/or the level of traffic protection within the network.

[0057] An embodiment of the present invention may support the logical bonding of lower capacity communications circuits to effectively form a link of higher capacity such as that illustrated in FIG. 8a. Bonding may make a group of lower capacity circuits appear as a higher capacity path, by spreading or inverse multiplexing the source traffic on the higher capacity link over the lower capacity circuits belonging to the bonded group of circuits. At the other end of the bonded segment, the traffic on each of the lower capacity circuits may be merged into a higher capacity link, or it may be carried over another bonded group of circuits of different types or capacities. The provisioning information needed to identify the lower speed circuits to be bonded may be provided either at the equipment site, or from a remote location.

[0058] FIG. 8a shows an exemplary embodiment illustrating the bonding of seven DS1 synchronous time division multiplex circuits into a bonded group 830a that transports the traffic from 10 Mbps Ethernet link 805a to 10 Mbps Ethernet link 815a, in accordance with the present invention. Although the illustration shows seven DS1 circuits bonded for transport of a single 10 Mbps Ethernet packet link, lower-speed circuits other than DS1 may be used to transport traffic from higher-speed network connections without departing from the spirit of the invention. In FIG. 8a, a group of circuits are bonded as a transport mechanism by identifying to Ethernet/TDM bonding function 810a and 820a the circuits in the group, and the packet interface to which they connect. Ethernet/TDM bonding function 810a and 820a may be implemented by the functionality shown in FIG. 8b. An algorithm may be implemented within hashing processor 838b of FIG. 8b, located at a first location, allowing it to cooperate with a distant hashing processor 838b, located at a second location, to bond or aggregate the communications circuits such as those in bonded group 830a of FIG. 8a, which connect the two locations. The communication circuits within bonded group 830a may be, for example, communication circuits such as those shown in FIG. 8b as trunk-side DS1 circuits 846b connected to DS1 framer 819b. In the exemplary embodiment, hashing processor 838b determines which of the lower speed circuits contained in bonded group 830a should be used to carry the next of the packets received from the higher speed link. The algorithm used by hashing processor 838b in selecting the circuit within bonded group 830a to be used to transport a given packet may take into consideration, among other things, the size of the packet, the priority of the packet, the allowable latency or maximum delay allowed in getting the packet to its destination, and the occupancy of each of the lower speed circuits in bonded group 830a. Information from the policing/shaping/flow-control/subscriber-management block 806b, MACs 810b and 812b, VLAN engine 808b, and embedded memory 826b may be used by hashing processor 838b and embedded microprocessor core 824b in the management of bonded group 830a. Performance measurements and diagnostic information regarding the operation of bonded group 830a may be gathered and distributed by embedded microprocessor core 824b.

[0059] An embodiment of the present invention may also include an M13 multiplexer (mux), which is illustrated as block 844b in FIG. 8b. M13 mux 844b may be used to combine a number of DS1/E1 streams from DS1/E1 framer 814b into a single DS3/E3 stream transported via DS3/E3 framer 816b. The DS3/E3 stream may be switched to channelized framer 802b for transport via optical link 834b, or it may be carried on a DS3/E3 trunk. This permits voice traffic from multiple DS1/E1 circuits to be carried via one DS3/E3 link. Management and monitoring of the operation of M13 mux 844b may be provided by embedded microprocessor core 824b executing program instructions stored in embedded memory 826b. Performance and diagnostic information may be provided either locally, or remotely via a dedicated VLAN connection or the SONET DCC.

[0060] Another embodiment in accordance with the present invention may include system packet interface (SPI) 840b of FIG. 8b, to permit expansion of the packet network interface capacity. System packet interface 840b is not required for operation of an embodiment of the present invention, but may be incorporated if MACs 810b and 812b do not provide sufficient packet interface capacity for a particular application of the invention.

[0061] FIG. 9 is a high-level flow diagram of a method of operating an embodiment of the present invention. In such an embodiment, the incoming SONET data stream is received (block 902) from a synchronous optical network, for example, and converted into a packet formatted stream (block 904). The packet stream is then transmitted (block 906) to an Ethernet packet network, for example. In the reverse direction, an incoming packet stream is received (block 908) from an Ethernet packet network, for example, and converted to a SONET compatible format (block 910). The resulting SONET data stream is then transmitted (block 912) to a synchronous optical network, for example.

[0062] FIG. 9a shows a high-level flow diagram illustrating a method of operating another embodiment in accordance with the present invention. The blocks shown in FIG. 9a represent the functions that are performed by blocks 810a and 820a as shown in FIG. 8a. In the exemplary embodiment, the contents of a packet received from a designated packet interface (block 908a) is converted to a stream of data (block 910a) for transmission over a lower-speed communications circuit selected from the bonded group of circuits for the designated packet interface (block 912a). The particular circuit to be used may be selected from the bonded group based upon, for example, the amount of data contained within the packet, the amount of data remaining to be transmitted on each of the circuits in the bonded group, the delay requirements of the subscriber being served by the packet interface, the priority of the packet, or one of a number of other criteria. Once the circuit has been selected, the stream of data is transmitted on the selected lower-speed circuit (block 914a) to the far end of the bonded group.

[0063] At the far end of the bonded group, the data is received from the lower-speed communications circuit (block 902a) and converted to packet format (block 904a). The formatted packet is then transmitted on the higher-speed packet interface that has been designated for use with the bonded group of lower-speed communications circuits (block 906a). The bonded group of lower speed communications circuits might be, for example, seven DS1 time division multiplex connections each operating at 1.544 Mbps, while the packet interface may be a 10 Mbps IEEE 802.3 Ethernet compliant connection.

[0064] FIG. 9b illustrates a network architecture in which, for example, two bonded groups are used in sequence, in accordance with one embodiment of the present invention. In FIG. 9b, packet traffic on Ethernet link 905b is transferred by Ethernet/DSL bonding function 910b to a bonded group of digital subscriber lines (DSL) 930b. Bonded group 930b connects to DSL/DS1 conversion function 915b, which transfers the data from the circuits of bonded group 930b to bonded group 940b made of DS1 circuits. The data from bonded group 940b is then converted back to Ethernet packet format and transmitted on Ethernet link 925b by DS1/Ethernet bonding functionality 920b.

[0065] FIG. 9c shows an example network architecture using, for example, multiple embodiments 910c, 915c, and 920c of the present invention to interface a packet link to a SONET optical link. In FIG. 9c, an Ethernet packet link is carried over two successive bonded groups for eventual transport over a SONET optical link. Ethernet/DSL bonding function 910c connects Ethernet packet link 905c to a bonded group of DSL links 930c. Data traffic on bonded group 930c is then transferred to a bonded group of DS1 circuits 940c by DSL/DS1 conversion function 915c. Bonded group 940c is then mapped for transport via a SONET or SDH optical link by DS1/SONET mapping function 920c. Although the embodiments described reference specific packet and circuit standards, speeds, and parameters, the present invention is not so limited and can be applied in yet further embodiments without departing from the spirit of the invention.

[0066] FIG. 10 is a high-level flow diagram of a further method of operating an embodiment according to the present invention. In such an embodiment, embedded microprocessor core 824 of FIG. 8, or 824b of FIG. 8b may collect operational statistics from, for example, the SONET receive processing (block 1002), the SONET transmit processing (block 1004), the packet receive processing (block 1006), and the packet transmit processing (block 1008) functional blocks. It may also gather statistics regarding the operation of hashing processor 838b of FIG. 8b. The gathered statistics may then be analyzed (block 1010) and embedded microprocessor core 824 or 824b may then determine, the actions or adjustments that may be needed for desired system operation. Embedded microprocessor core 824 or 824b may then adjust the operation (block 1012) of the functional blocks in the embodiment, and may report troubles and performance (block 1014) to a predetermined location. Many improvements in the level of diagnostics, performance, and control become available by closely integrating the functionality shown in FIG. 7 in the form of, for example, a single chip or multi-chip embodiment.

[0067] Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

[0068] The present invention also may be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.

[0069] Notwithstanding, the invention and its inventive arrangements disclosed herein may be embodied in other forms without departing from the spirit or essential attributes thereof. Accordingly, reference should be made to the following claims, rather than to the foregoing specification, as indicating the scope of the invention. In this regard, the description above is intended by way of example only and is not intended to limit the present invention in any way, except as set forth in the following claims.

[0070] While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.