Programmable camera system with software interpreter

[0001] Continuation Application of U.S. Ser. No. 09/113,071 filed on Jul. 10, 1998

[0002] The following Australian provisional patent applications are hereby incorporated by cross-reference. For the purposes of location and identification, US patent applications identified by their US patent application serial numbers (USSN) are listed alongside the Australian applications from which the US patent applications claim the right of priority.

CROSS-REFERENCED	US PATENT/
AUSTRALIAN	PATENT APPLICATION
PROVISIONAL	(CLAIMING RIGHT OF
PATENT	PRIORITY FROM AUSTRALIAN	DOCKET
APPLICATION NO.	PROVISIONAL APPLICATION)	NO.
PO7991	09/113,060	ART01
PO8505	09/113,070	ART02
PO7988	09/113,073	ART03
PO9395	09/112,748	ART04
PO8017	09/112,747	ART06
PO8014	09/112,776	ART07
PO8025	09/112,750	ART08
PO8032	09/112,746	ART09
PO7999	09/112,743	ART10
PO7998	09/112,742	ART11
PO8031	09/112,741	ART12
PO8030	09/112,740	ART13
PO7997	09/112,739	ART15
PO7979	09/113,053	ART16
PO8015	09/112,738	ART17
PO7978	09/113,067	ART18
PO7982	09/113,063	ART19
PO7989	09/113,069	ART20
PO8019	09/112,744	ART21
PO7980	09/113,058	ART22
PO8018	09/112,777	ART24
PO7938	09/113,224	ART25
PO8016	09/112,804	ART26
PO8024	09/112,805	ART27
PO7940	09/113,072	ART28
PO7939	09/112,785	ART29
PO8501	09/112,797	ART30
PO8500	09/112,796	ART31
PO7987	09/113,071	ART32
PO8022	09/112,824	ART33
PO8497	09/113,090	ART34
PO8020	09/112,823	ART38
PO8023	09/113,222	ART39
PO8504	09/112,786	ART42
PO8000	09/113,051	ART43
PO7977	09/112,782	ART44
PO7934	09/113,056	ART45
PO7990	09/113,059	ART46
PO8499	09/113,091	ART47
PO8502	09/112,753	ART48
PO7981	09/113,055	ART50
PO7986	09/113,057	ART51
PO7983	09/113,054	ART52
PO8026	09/112,752	ART53
PO8027	09/112,759	ART54
PO8028	09/112,757	ART56
PO9394	09/112,758	ART57
PO9396	09/113,107	ART58
PO9397	09/112,829	ART59
PO9398	09/112,792	ART60
PO9399	6,106,147	ART61
PO9400	09/112,790	ART62
PO9401	09/112,789	ART63
PO9402	09/112,788	ART64
PO9403	09/112,795	ART65
PO9405	09/112,749	ART66
PP0959	09/112,784	ART68
PP1397	09/112,783	ART69
PP2370	09/112,781	DOT01
PP2371	09/113,052	DOT02
PO8003	09/112,834	Fluid01
PO8005	09/113,103	Fluid02
PO9404	09/113,101	Fluid03
PO8066	09/112,751	IJ01
PO8072	09/112,787	IJ02
PO8040	09/112,802	IJ03
PO8071	09/112,803	IJ04
PO8047	09/113,097	IJ05
PO8035	09/113,099	IJ06
PO8044	09/113,084	IJ07
PO8063	09/113,066	IJ08
PO8057	09/112,778	IJ09
PO8056	09/112,779	IJ10
PO8069	09/113,077	IJ11
PO8049	09/113,061	IJ12
PO8036	09/112,818	IJ13
PO8048	09/112,816	IJ14
PO8070	09/112,772	IJ15
PO8067	09/112,819	IJ16
PO8001	09/112,815	IJ17
PO8038	09/113,096	IJ18
PO8033	09/113,068	IJ19
PO8002	09/113,095	IJ20
PO8068	09/112,808	IJ21
PO8062	09/112,809	IJ22
PO8034	09/112,780	IJ23
PO8039	09/113,083	IJ24
PO8041	09/113,121	IJ25
PO8004	09/113,122	IJ26
PO8037	09/112,793	IJ27
PO8043	09/112,794	IJ28
PO8042	09/113,128	IJ29
PO8064	09/113,127	IJ30
PO9389	09/112,756	IJ31
PO9391	09/112,755	IJ32
PP0888	09/112,754	IJ33
PP0891	09/112,811	IJ34
PP0890	09/112,812	IJ35
PP0873	09/112,813	IJ36
PP0993	09/112,814	IJ37
PP0890	09/112,764	IJ38
PP1398	09/112,765	IJ39
PP2592	09/112,767	IJ40
PP2593	09/112,768	IJ41
PP3991	09/112,807	IJ42
PP3987	09/112,806	IJ43
PP3985	09/112,820	IJ44
PP3983	09/112,821	IJ45
PO7935	09/112,822	IJM01
PO7936	09/112,825	IJM02
PO7937	09/112,826	IJM03
PO8061	09/112,827	IJM04
PO8054	09/112,828	IJM05
PO8065	6,071,750	IJM06
PO8055	09/113,108	IJM07
PO8053	09/113,109	IJM08
PO8078	09/113,123	IJM09
PO7933	09/113,114	IJM10
PO7950	09/113,115	IJM11
PO7949	09/113,129	IJM12
PO8060	09/113,124	IJM13
PO8059	09/113,125	IJM14
PO8073	09/113,126	IJM15
PO8076	09/113,119	IJM16
PO8075	09/113,120	IJM17
PO8079	09/113,221	IJM18
PO8050	09/113,116	IJM19
PO8052	09/113,118	IJM20
PO7948	09/113,117	IJM21
PO7951	09/113,113	IJM22
PO8074	09/113,130	IJM23
PO7941	09/113,110	IJM24
PO8077	09/113,112	IJM25
PO8058	09/113,087	IJM26
PO8051	09/113,074	IJM27
PO8045	6,111,754	IJM28
PO7952	09/113,088	IJM29
PO8046	09/112,771	IJM30
PO9390	09/112,769	IJM31
PO9392	09/112,770	IJM32
PP0889	09/112,798	IJM35
PP0887	09/112,801	IJM36
PP0882	09/112,800	IJM37
PP0874	09/112,799	IJM38
PP1396	09/113,098	IJM39
PP3989	09/112,833	IJM40
PP2591	09/112,832	IJM41
PP3990	09/112,831	IJM42
PP3986	09/112,830	IJM43
PP3984	09/112,836	IJM44
PP3982	09/112,835	IJM45
PP0895	09/113,102	IR01
PP0870	09/113,106	IR02
PP0869	09/113,105	IR04
PP0887	09/113,104	IR05
PP0885	09/112,810	IR06
PP0884	09/112,766	IR10
PP0886	09/113,085	IR12
PP0871	09/113,086	IR13
PP0876	09/113,094	IR14
PP0877	09/112,760	IR16
PP0878	09/112,773	IR17
PP0879	09/112,774	IR18
PP0883	09/112,775	IR19
PP0880	6,152,619	IR20
PP0881	09/113,092	IR21
PO8006	6,087,638	MEMS02
PO8007	09/113,093	MEMS03
PO8008	09/113,062	MEMS04
PO8010	6,041,600	MEMS05
PO8011	09/113,082	MEMS06
PO7947	6,067,797	MEMS07
PO7944	09/113,080	MEMS09
PO7946	6,044,646	MEMS10
PO9393	09/113,065	MEMS11
PP0875	09/113,078	MEMS12
PP0894	09/113,075	MEMS13

[0003] Not applicable.

[0004] The present invention relates to a data processing method and apparatus and, in particular, discloses a programmable camera system with software Interpreter.

[0005] Recently, digital camera technology has become increasingly popular. In this form of technology, an image is normally imaged by CCD array. Subsequently, the images are stored on the camera on storage media such as a semiconductor memory array. At a later stage, the images are downloaded from the CCD camera device to a computer or the like where upon they go subsequent manipulation and printing in the course of requirements. The printing normally includes various image processing steps to enhance certain aspects of the image.

[0006] For details on the operation of CCD devices and cameras, reference is made to a standard text in this field such as CCD arrays, cameras and displays by Gerald C Holst, published 1996 by SPE Optical Engineering Press Bellingham, Wash., USA.

[0007] Recently, there has been proposed by the present applicant, a camera system having a integral inbuilt printer that is able to produce full colour, high quality output images. Further, it is known to apply a filter to a digital image to produce various effects. The number of filters able to be utilized being totally arbitrary with the expectation that further filters will be discovered or created in future.

[0008] Unfortunately, changing digital imaging technologies and changing filter technologies result in onerous system requirements in that cameras produced today obviously are unable to take advantages of technologies not yet available nor are they able to take advantage of filters which have not, as yet, been created or conceived.

[0009] It is an object of the present invention to provide a system which readily is able to take advantage of updated technologies in addition to taking advantage of new filters being created and, in addition, providing a readily adaptable form of image processing of digitally captured images for printing out.

[0010] According to the invention there is provided a portable camera with inbuilt printer device, and input means for uploading software, said camera including:

[0011] (a) digital image capture device for the capturing of digital images;

[0012] (b) an inbuilt programming language interpreter means internally connected to said digital image capture device for the manipulation of a digital image captured by said capture device;

[0013] (c) a script input means for inputting a self documenting program script for the manipulation and filtering of said captured digital image to produce visual alterations thereof, said script input means comprising a card reader for optically reading a script printed as an array of dots on one surface of a portable card, there being a visual example of the likely effect of said script on a second surface of the card;

[0014] wherein said script is interpreted and executed by said interpreter means to modify said captured digital image in accordance with said script to produce a digital image modified from said captured digital image, in the manner visually exemplified on said second surface of said card, and to provide a printout of said image on said inbuilt printer device.

[0015] Notwithstanding any other forms which may fall within the scope of the present invention, preferred forms of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

[0016] FIG. 1 illustrates an Artcam device constructed in accordance with the preferred embodiment;

[0017] FIG. 2 is a schematic block diagram of the main Artcam electronic components;

[0018] FIG. 3 is a schematic block diagram of the Artcam Central Processor;

[0019] FIG. 3(a) illustrates the VLIW Vector Processor in more detail;

[0020] FIG. 4 illustrates the Processing Unit in more detail;

[0021] FIG. 5 illustrates the ALU 188 in more detail;

[0022] FIG. 6 illustrates the In block in more detail;

[0023] FIG. 7 illustrates the Out block in more detail;

[0024] FIG. 8 illustrates the Registers block in more detail;

[0025] FIG. 9 illustrates the Crossbar1 in more detail;

[0026] FIG. 10 illustrates the Crossbar2 in more detail;

[0027] FIG. 11 illustrates the read process block in more detail;

[0028] FIG. 12 illustrates the read process block in more detail;

[0029] FIG. 13 illustrates the barrel shifter block in more detail;

[0030] FIG. 14 illustrates the adder/logic block in more detail;

[0031] FIG. 15 illustrates the multiply block in more detail;

[0032] FIG. 16 illustrates the I/O address generator block in more detail;

[0033] FIG. 17 illustrates a pixel storage format;

[0034] FIG. 18 illustrates a sequential read iterator process;

[0035] FIG. 19 illustrates a box read iterator process;

[0036] FIG. 20 illustrates a box write iterator process;

[0037] FIG. 21 illustrates the vertical strip read/write iterator process;

[0038] FIG. 22 illustrates the vertical strip read/write iterator process;

[0039] FIG. 23 illustrates the generate sequential process;

[0040] FIG. 24 illustrates the generate sequential process;

[0041] FIG. 25 illustrates the generate vertical strip process;

[0042] FIG. 26 illustrates the generate vertical strip process;

[0043] FIG. 27 illustrates a pixel data configuration;

[0044] FIG. 28 illustrates a pixel processing process;

[0045] FIG. 29 illustrates a schematic block diagram of the display controller;

[0046] FIG. 30 illustrates the CCD image organization;

[0047] FIG. 31 illustrates the storage format for a logical image;

[0048] FIG. 32 illustrates the internal image memory storage format;

[0049] FIG. 33 illustrates the image pyramid storage format;

[0050] FIG. 34 illustrates a time line of the process of sampling an Artcard;

[0051] FIG. 35 illustrates the super sampling process;

[0052] FIG. 36 illustrates the process of reading a rotated Artcard;

[0053] FIG. 37 illustrates a flow chart of the steps necessary to decode an Artcard;

[0054] FIG. 38 illustrates an enlargement of the left hand corner of a single Artcard;

[0055] FIG. 39 illustrates a single target for detection;

[0056] FIG. 40 illustrates the method utilised to detect targets;

[0057] FIG. 41 illustrates the method of calculating the distance between two targets;

[0058] FIG. 42 illustrates the process of centroid drift;

[0059] FIG. 43 shows one form of centroid lookup table;

[0060] FIG. 44 illustrates the centroid updating process;

[0061] FIG. 45 illustrates a delta processing lookup table utilised in the preferred embodiment;

[0062] FIG. 46 illustrates the process of unscrambling Artcard data;

[0063] FIG. 47 illustrates a magnified view of a series of dots;

[0064] FIG. 48 illustrates the data surface of a dot card;

[0065] FIG. 49 illustrates schematically the layout of a single datablock;

[0066] FIG. 50 illustrates a single datablock;

[0067] FIG. 51 and FIG. 52 illustrate magnified views of portions of the datablock of FIG. 50;

[0068] FIG. 53 illustrates a single target structure;

[0069] FIG. 54 illustrates the target structure of a datablock;

[0070] FIG. 55 illustrates the positional relationship of targets relative to border clocking regions of a data region;

[0071] FIG. 56 illustrates the orientation columns of a datablock;

[0072] FIG. 57 illustrates the array of dots of a datablock;

[0073] FIG. 58 illustrates schematically the structure of data for Reed-Solomon encoding;

[0074] FIG. 59 illustrates an example Reed-Solomon encoding;

[0075] FIG. 60 illustrates the Reed-Solomon encoding process;

[0076] FIG. 61 illustrates the layout of encoded data within a datablock;

[0077] FIG. 62 illustrates the sampling process in sampling an alternative Artcard;

[0078] FIG. 63 illustrates, in exaggerated form, an example of sampling a rotated alternative Artcard;

[0079] FIG. 64 illustrates the scanning process;

[0080] FIG. 65 illustrates the likely scanning distribution of the scanning process;

[0081] FIG. 66 illustrates the relationship between probability of symbol errors and Reed-Solomon block errors;

[0082] FIG. 67 illustrates a flow chart of the decoding process;

[0083] FIG. 68 illustrates a process utilization diagram of the decoding process;

[0084] FIG. 69 illustrates the dataflow steps in decoding;

[0085] FIG. 70 illustrates the reading process in more detail;

[0086] FIG. 71 illustrates the process of detection of the start of an alternative Artcard in more detail;

[0087] FIG. 72 illustrates the extraction of bit data process in more detail;

[0088] FIG. 73 illustrates the segmentation process utilized in the decoding process;

[0089] FIG. 74 illustrates the decoding process of finding targets in more detail;

[0090] FIG. 75 illustrates the data structures utilized in locating targets;

[0091] FIG. 76 illustrates the Lancos 3 function structure;

[0092] FIG. 77 illustrates an enlarged portion of a datablock illustrating the clockmark and border region;

[0093] FIG. 78 illustrates the processing steps in decoding a bit image;

[0094] FIG. 79 illustrates the dataflow steps in decoding a bit image;

[0095] FIG. 80 illustrates the descrambling process of the preferred embodiment;

[0096] FIG. 81 illustrates one form of implementation of the convolver;

[0097] FIG. 82 illustrates a convolution process;

[0098] FIG. 83 illustrates the compositing process;

[0099] FIG. 84 illustrates the regular compositing process in more detail;

[0100] FIG. 85 illustrates the process of warping using a warp map;

[0101] FIG. 86 illustrates the warping bi-linear interpolation process;

[0102] FIG. 87 illustrates the process of span calculation;

[0103] FIG. 88 illustrates the basic span calculation process;

[0104] FIG. 89 illustrates one form of detail implementation of the span calculation process;

[0105] FIG. 90 illustrates the process of reading image pyramid levels;

[0106] FIG. 91 illustrates using the pyramid table for blinear interpolation;

[0107] FIG. 92 illustrates the histogram collection process;

[0108] FIG. 93 illustrates the color transform process;

[0109] FIG. 94 illustrates the color conversion process;

[0110] FIG. 95 illustrates the color space conversion process in more detail;

[0111] FIG. 96 illustrates the process of calculating an input coordinate;

[0112] FIG. 97 illustrates the process of compositing with feedback;

[0113] FIG. 98 illustrates the generalized scaling process;

[0114] FIG. 99 illustrates the scale in X scaling process;

[0115] FIG. 100 illustrates the scale in Y scaling process;

[0116] FIG. 101 illustrates the tessellation process;

[0117] FIG. 102 illustrates the sub-pixel translation process;

[0118] FIG. 103 illustrates the compositing process;

[0119] FIG. 104 illustrates the process of compositing with feedback;

[0120] FIG. 105 illustrates the process of tiling with color from the input image;

[0121] FIG. 106 illustrates the process of tiling with feedback;

[0122] FIG. 107 illustrates the process of tiling with texture replacement;

[0123] FIG. 108 illustrates the process of tiling with color from the input image;

[0124] FIG. 109 illustrates the process of applying a texture without feedback;

[0125] FIG. 110 illustrates the process of applying a texture with feedback;

[0126] FIG. 111 illustrates the process of rotation of CCD pixels;

[0127] FIG. 112 illustrates the process of interpolation of Green subpixels;

[0128] FIG. 113 illustrates the process of interpolation of Blue subpixels;

[0129] FIG. 114 illustrates the process of interpolation of Red subpixels;

[0130] FIG. 115 illustrates the process of CCD pixel interpolation with 0 degree rotation for odd pixel lines;

[0131] FIG. 116 illustrates the process of CCD pixel interpolation with 0 degree rotation for even pixel lines;

[0132] FIG. 117 illustrates the process of color conversion to Lab color space;

[0133] FIG. 118 illustrates the process of calculation of 1/{square root}X;

[0134] FIG. 119 illustrates the implementation of the calculation of 1/{square root}X in more detail;

[0135] FIG. 120 illustrates the process of Normal calculation with a bump map;

[0136] FIG. 121 illustrates the process of illumination calculation with a bump map;

[0137] FIG. 122 illustrates the process of illumination calculation with a bump map in more detail;

[0138] FIG. 123 illustrates the process of calculation of L using a directional light;

[0139] FIG. 124 illustrates the process of calculation of L using a Omni lights and spotlights;

[0140] FIG. 125 illustrates one form of implementation of calculation of L using a Omni lights and spotlights;

[0141] FIG. 126 illustrates the process of calculating the N.L dot product;

[0142] FIG. 127 illustrates the process of calculating the N.L dot product in more detail;

[0143] FIG. 128 illustrates the process of calculating the R.V dot product;

[0144] FIG. 129 illustrates the process of calculating the R.V dot product in more detail;

[0145] FIG. 130 illustrates the attenuation calculation inputs and outputs;

[0146] FIG. 131 illustrates an actual implementation of attenuation calculation;

[0147] FIG. 132 illustrates an graph of the cone factor;

[0148] FIG. 133 illustrates the process of penumbra calculation;

[0149] FIG. 134 illustrates the angles utilised in penumbra calculation;

[0150] FIG. 135 illustrates the inputs and outputs to penumbra calculation;

[0151] FIG. 136 illustrates an actual implementation of penumbra calculation;

[0152] FIG. 137 illustrates the inputs and outputs to ambient calculation;

[0153] FIG. 138 illustrates an actual implementation of ambient calculation;

[0154] FIG. 139 illustrates an actual implementation of diffuse calculation;

[0155] FIG. 140 illustrates the inputs and outputs to a diffuse calculation;

[0156] FIG. 141 illustrates an actual implementation of a diffuse calculation;

[0157] FIG. 142 illustrates the inputs and outputs to a specular calculation;

[0158] FIG. 143 illustrates an actual implementation of a specular calculation;

[0159] FIG. 144 illustrates the inputs and outputs to a specular calculation;

[0160] FIG. 145 illustrates an actual implementation of a specular calculation;

[0161] FIG. 146 illustrates an actual implementation of a ambient only calculation;

[0162] FIG. 147 illustrates the process overview of light calculation;

[0163] FIG. 148 illustrates an example illumination calculation for a single infinite light source;

[0164] FIG. 149 illustrates an example illumination calculation for a Omni light source without a bump map;

[0165] FIG. 150 illustrates an example illumination calculation for a Omni light source with a bump map;

[0166] FIG. 151 illustrates an example illumination calculation for a Spotlight light source without a bump map;

[0167] FIG. 152 illustrates the process of applying a single Spotlight onto an image with an associated bump-map;

[0168] FIG. 153 illustrates the logical layout of a single printhead;

[0169] FIG. 154 illustrates the structure of the printhead interface;

[0170] FIG. 155 illustrates the process of rotation of a Lab image;

[0171] FIG. 156 illustrates the format of a pixel of the printed image;

[0172] FIG. 157 illustrates the dithering process;

[0173] FIG. 158 illustrates the process of generating an 8 bit dot output;

[0174] FIG. 159 illustrates a perspective view of the card reader;

[0175] FIG. 160 illustrates an exploded perspective of a card reader;

[0176] FIG. 161 illustrates a close up view of the Artcard reader;

[0177] FIG. 162 illustrates a perspective view of the print roll and print head;

[0178] FIG. 163 illustrates a first exploded perspective view of the print roll;

[0179] FIG. 164 illustrates a second exploded perspective view of the print roll;

[0180] FIG. 165 illustrates the print roll authentication chip;

[0181] FIG. 166 illustrates an enlarged view of the print roll authentication chip;

[0182] FIG. 167 illustrates a single authentication chip data protocol;

[0183] FIG. 168 illustrates a dual authentication chip data protocol;

[0184] FIG. 169 illustrates a first presence only protocol;

[0185] FIG. 170 illustrates a second presence only protocol;

[0186] FIG. 171 illustrates a third data protocol;

[0187] FIG. 172 illustrates a fourth data protocol;

[0188] FIG. 173 is a schematic block diagram of a maximal period LFSR;

[0189] FIG. 174 is a schematic block diagram of a clock limiting filter;

[0190] FIG. 175 is a schematic block diagram of the tamper detection lines;

[0191] FIG. 176 illustrates an oversized nMOS transistor;

[0192] FIG. 177 illustrates the taking of multiple XORs from the Tamper Detect Line

[0193] FIG. 178 illustrate how the Tamper Lines cover the noise generator circuitry;

[0194] FIG. 179 illustrates the normal form of FET implementation;

[0195] FIG. 180 illustrates the modified form of FET implementation of the preferred embodiment;

[0196] FIG. 181 illustrates a schematic block diagram of the authentication chip;

[0197] FIG. 182 illustrates an example memory map;

[0198] FIG. 183 illustrates an example of the constants memory map;

[0199] FIG. 184 illustrates an example of the RAM memory map;

[0200] FIG. 185 illustrates an example of the Flash memory variables memory map;

[0201] FIG. 186 illustrates an example of the Flash memory program memory map;

[0202] FIG. 187 shows the data flow and relationship between components of the State Machine;

[0203] FIG. 188 shows the data flow and relationship between components of the I/O Unit.

[0204] FIG. 189 illustrates a schematic block diagram of the Arithmetic Logic Unit;

[0205] FIG. 190 illustrates a schematic block diagram of the RPL unit;

[0206] FIG. 191 illustrates a schematic block diagram of the ROR block of the ALU;

[0207] FIG. 192 is a block diagram of the Program Counter Unit;

[0208] FIG. 193 is a block diagram of the Memory Unit;

[0209] FIG. 194 shows a schematic block diagram for the Address Generator Unit;

[0210] FIG. 195 shows a schematic block diagram for the JSIGEN Unit;

[0211] FIG. 196 shows a schematic block diagram for the JSRGEN Unit.

[0212] FIG. 197 shows a schematic block diagram for the DBRGEN Unit;

[0213] FIG. 198 shows a schematic block diagram for the LDKGEN Unit;

[0214] FIG. 199 shows a schematic block diagram for the RPLGEN Unit;

[0215] FIG. 200 shows a schematic block diagram for the VARGEN Unit.

[0216] FIG. 201 shows a schematic block diagram for the CLRGEN Unit.

[0217] FIG. 202 shows a schematic block diagram for the BITGEN Unit.

[0218] FIG. 203 sets out the information stored on the print roll authentication chip;

[0219] FIG. 204 illustrates the data stored within the Artcam authorization chip;

[0220] FIG. 205 illustrates the process of print head pulse characterization;

[0221] FIG. 206 is an exploded perspective, in section, of the print head ink supply mechanism;

[0222] FIG. 207 is a bottom perspective of the ink head supply unit;

[0223] FIG. 208 is a bottom side sectional view of the ink head supply unit;

[0224] FIG. 209 is a top perspective of the ink head supply unit;

[0225] FIG. 210 is a top side sectional view of the ink head supply unit;

[0226] FIG. 211 illustrates a perspective view of a small portion of the print head;

[0227] FIG. 212 illustrates is an exploded perspective of the print head unit;

[0228] FIG. 213 illustrates a top side perspective view of the internal portions of an Artcam camera, showing the parts flattened out;

[0229] FIG. 214 illustrates a bottom side perspective view of the internal portions of an Artcam camera, showing the parts flattened out;

[0230] FIG. 215 illustrates a first top side perspective view of the internal portions of an Artcam camera, showing the parts as encased in an Artcam;

[0231] FIG. 216 illustrates a second top side perspective view of the internal portions of an Artcam camera, showing the parts as encased in an Artcam;

[0232] FIG. 217 illustrates a second top side perspective view of the internal portions of an Artcam camera, showing the parts as encased in an Artcam;

[0233] FIG. 218 illustrates the backing portion of a postcard print roll;

[0234] FIG. 219 illustrates the corresponding front image on the postcard print roll after printing out images;

[0235] FIG. 220 illustrates a form of print roll ready for purchase by a consumer;

[0236] FIG. 221 illustrates a layout of the software/hardware modules of the overall Artcam application;

[0237] FIG. 222 illustrates a layout of the software/hardware modules of the Camera Manager;

[0238] FIG. 223 illustrates a layout of the software/hardware modules of the Image Processing Manager;

[0239] FIG. 224 illustrates a layout of the software/hardware modules of the Printer Manager;

[0240] FIG. 225 illustrates a layout of the software/hardware modules of the Image Processing Manager;

[0241] FIG. 226 illustrates a layout of the software/hardware modules of the File Manager;

[0242] FIG. 227 illustrates a perspective view, partly in section, of an alternative form of printroll;

[0243] FIG. 228 is a left side exploded perspective view of the print roll of FIG. 227;

[0244] FIG. 229 is a right side exploded perspective view of a single printroll;

[0245] FIG. 230 is an exploded perspective view, partly in section, of the core portion of the printroll; and

[0246] FIG. 231 is a second exploded perspective view of the core portion of the printroll.

[0247] The digital image processing camera system constructed in accordance with the preferred embodiment is as illustrated in FIG. 1. The camera unit 1 includes means for the insertion of an integral print roll (not shown). The camera unit 1 can include an area image sensor 2 which sensors an image 3 for captured by the camera. Optionally, the second area image sensor can be provided to also image the scene 3 and to optionally provide for the production of stereographic output effects.

[0248] The camera 1 can include an optional color display 5 for the display of the image being sensed by the sensor 2. When a simple image is being displayed on the display 5, the button 6 can be depressed resulting in the printed image 8 being output by the camera unit 1. A series of cards, herein after known as Artcards 9 contain, on one surface encoded information and on the other surface, contain an image distorted by the particular effect produced by the Artcard 9. The Artcard 9 is inserted in an Artcard reader 10 in the side of camera 1 and, upon insertion, results in output image 8 being distorted in the same manner as the distortion appearing on the surface of Artcard 9. Hence, by means of this simple user interface a user wishing to produce a particular effect can insert one of many Artcards 9 into the Artcard reader 10 and utilize button 19 to take a picture of the image 3 resulting in a corresponding distorted output image 8.

[0249] The camera unit 1 can also include a number of other control button 13, 14 in addition to a simple LCD output display 15 for the display of informative information including the number of printouts left on the internal print roll on the camera unit. Additionally, different output formats can be controlled by CHP switch 17.

[0250] Turning now to FIG. 2, there is illustrated a schematic view of the internal hardware of the camera unit 1. The internal hardware is based around an Artcam central processor unit (ACP) 31.

[0251] Artcam Central Processor 31

[0252] The Artcam central processor 31 provides many functions which form the heart of the system. The ACP 31 is preferably implemented as a complex, high speed, CMOS system on-a-chip. Utilising standard cell design with some full custom regions is recommended. Fabrication on a 0.25 micron CMOS process will provide the density and speed required, along with a reasonably small die area.

[0253] The functions provided by the ACP 31 include:

[0254] 1. Control and digitization of the area image sensor 2. A 3D stereoscopic version of the ACP requires two area image sensor interfaces with a second optional image sensor 4 being provided for stereoscopic effects.

[0255] 2. Area image sensor compensation, reformatting, and image enhancement.

[0256] 3. Memory interface and management to a memory store 33.

[0257] 4. Interface, control, and analog to digital conversion of an Artcard reader linear image sensor 34 which is provided for the reading of data from the Artcards 9.

[0258] 5. Extraction of the raw Artcard data from the digitized and encoded Artcard image.

[0259] 6. Reed-Solomon error detection and correction of the Artcard encoded data. The encoded surface of the Artcard 9 includes information on how to process an image to produce the effects displayed on the image distorted surface of the Artcard 9. This information is in the form of a script, hereinafter known as a Vark script. The Vark script is utilised by an interpreter running within the ACP 31 to produce the desired effect.

[0260] 7. Interpretation of the Vark script on the Artcard 9.

[0261] 8. Performing image processing operations as specified by the Vark script.

[0262] 9. Controlling various motors for the paper transport 36, zoom lens 38, autofocus 39 and Artcard driver 37.

[0263] 10. Controlling a guillotine actuator 40 for the operation of a guillotine 41 for the cutting of photographs 8 from print roll 42.

[0264] 11. Half-toning of the image data for printing.

[0265] 12. Providing the print data to a print-head 44 at the appropriate times.

[0266] 13. Controlling the print head 44.

[0267] 14. Controlling the ink pressure feed to print-head 44.

[0268] 15. Controlling optional flash unit 56.

[0269] 16. Reading and acting on various sensors in the camera, including camera orientation sensor 46, autofocus 47 and Artcard insertion sensor 49.

[0270] 17. Reading and acting on the user interface buttons 6, 13, 14.

[0271] 18. Controlling the status display 15.

[0272] 19. Providing viewfinder and preview images to the color display 5.

[0273] 20. Control of the system power consumption, including the ACP power consumption via power management circuit 51.

[0274] 21. Providing external communications 52 to general purpose computers (using part USB).

[0275] 22. Reading and storing information in a printing roll authentication chip 53.

[0276] 23. Reading and storing information in a camera authentication chip 54.

[0277] 24. Communicating with an optional mini-keyboard 57 for text modification.

[0278] Quartz crystal 58

[0279] A quartz crystal 58 is used as a frequency reference for the system clock. As the system clock is very high, the ACP 31 includes a phase locked loop clock circuit to increase the frequency derived from the crystal 58.

[0280] Image Sensing

[0281] Area Image Sensor 2

[0282] The area image sensor 2 converts an image through its lens into an electrical signal. It can either be a charge coupled device (CCD) or an active pixel sensor (APS)CMOS image sector. At present, available CCD's normally have a higher image quality, however, there is currently much development occurring in CMOS imagers. CMOS imagers are eventually expected to be substantially cheaper than CCD's have smaller pixel areas, and be able to incorporate drive circuitry and signal processing. They can also be made in CMOS fabs, which are transitioning to 12 wafers. CCD's are usually built in 6 wafer fabs, and economics may not allow a conversion to 12 fabs. Therefore, the difference in fabrication cost between CCD's and CMOS imagers is likely to increase, progressively favoring CMOS imagers. However, at present, a CCD is probably the best option.

[0283] The Artcam unit will produce suitable results with a 1,5001,000 area image sensor. However, smaller sensors, such as 750500, will be adequate for many markets. The Artcam is less sensitive to image sensor resolution than are conventional digital cameras. This is because many of the styles contained on Artcards 9 process the image in such a way as to obscure the lack of resolution. For example, if the image is distorted to simulate the effect of being converted to an impressionistic painting, low source image resolution can be used with minimal effect. Further examples for which low resolution input images will typically not be noticed include image warps which produce high distorted images, multiple miniature copies of the of the image (eg. passport photos), textural processing such as bump mapping for a base relief metal look, and photo-compositing into structured scenes.

[0284] This tolerance of low resolution image sensors may be a significant factor in reducing the manufacturing cost of an Artcam unit 1 camera. An Artcam with a low cost 750500 image sensor will often produce superior results to a conventional digital camera with a much more expensive 1,5001,000 image sensor.

[0285] Optional Stereoscopic 3D Image Sensor 4

[0286] The 3D versions of the Artcam unit 1 have an additional image sensor 4, for stereoscopic operation. This image sensor is identical to the main image sensor. The circuitry to drive the optional image sensor may be included as a standard part of the ACP chip 31 to reduce incremental design cost. Alternatively, a separate 3D Artcam ACP can be designed. This option will reduce the manufacturing cost of a mainstream single sensor Artcam.

[0287] Print Roll Authentication Chip 53

[0288] A small chip 53 is included in each print roll 42. This chip replaced the functions of the bar code, optical sensor and wheel, and ISO/ASA sensor on other forms of camera film units such as Advanced Photo Systems film cartridges.

[0289] The authentication chip also provides other features:

[0290] 1. The storage of data rather than that which is mechanically and optically sensed from APS rolls

[0291] 2. A remaining media length indication, accurate to high resolution.

[0292] 3. Authentication Information to prevent inferior clone print roll copies.

[0293] The authentication chip 53 contains 1024 bits of Flash memory, of which 128 bits is an authentication key, and 512 bits is the authentication information. Also included is an encryption circuit to ensure that the authentication key cannot be accessed directly.

[0294] Print-Head 44

[0295] The Artcam unit 1 can utilize any color print technology which is small enough, low enough power, fast enough, high enough quality, and low enough cost, and is compatible with the print roll. Relevant printheads will be specifically discussed hereinafter.

[0296] The specifications of the ink jet head are:

	Image type	Bi-level, dithered
	Color	CMY Process Color
	Resolution	1600 dpi
	Print head length	Page-width (100 mm)
	Print speed	2 seconds per photo

[0297] Optional Ink Pressure Controller (Not Shown)

[0298] The function of the ink pressure controller depends upon the type of ink jet print head 44 incorporated in the Artcam. For some types of ink jet, the use of an ink pressure controller can be eliminated, as the ink pressure is simply atmospheric pressure. Other types of print head require a regulated positive ink pressure. In this case, the in pressure controller consists of a pump and pressure transducer.

[0299] Other print heads may require an ultrasonic transducer to cause regular oscillations in the ink pressure, typically at frequencies around 100 KHz. In the case, the ACP 31 controls the frequency phase and amplitude of these oscillations.

[0300] Paper Transport Motor 36

[0301] The paper transport motor 36 moves the paper from within the print roll 42 past the print head at a relatively constant rate. The motor 36 is a miniature motor geared down to an appropriate speed to drive rollers which move the paper. A high quality motor and mechanical gears are required to achieve high image quality, as mechanical rumble or other vibrations will affect the printed dot row spacing.

[0302] Paper Transport Motor Driver 60

[0303] The motor driver 60 is a small circuit which amplifies the digital motor control signals from the APC 31 to levels suitable for driving the motor 36.

[0304] Paper Pull Sensor

[0305] A paper pull sensor 50 detects a user's attempt to pull a photo from the camera unit during the printing process. The APC 31 reads this sensor 50, and activates the guillotine 41 if the condition occurs. The paper pull sensor 50 is incorporated to make the camera more foolproof in operation. Were the user to pull the paper out forcefully during printing, the print mechanism 44 or print roll 42 may (in extreme cases) be damaged. Since it is acceptable to pull out the pod from a Polaroid type camera before it is fully ejected, the public has been trained to do this. Therefore, they are unlikely to heed printed instructions not to pull the paper.

[0306] The Artcam preferably restarts the photo print process after the guillotine 41 has cut the paper after pull sensing.

[0307] The pull sensor can be implemented as a strain gauge sensor, or as an optical sensor detecting a small plastic flag which is deflected by the torque that occurs on the paper drive rollers when the paper is pulled. The latter implementation is recommendation for low cost.

[0308] Paper Guillotine Actuator 40

[0309] The paper guillotine actuator 40 is a small actuator which causes the guillotine 41 to cut the paper either at the end of a photograph, or when the paper pull sensor 50 is activated.

[0310] The guillotine actuator 40 is a small circuit which amplifies a guillotine control signal from the APC tot the level required by the actuator 41.

[0311] Artcard 9

[0312] The Artcard 9 is a program storage medium for the Artcam unit. As noted previously, the programs are in the form of Vark scripts. Vark is a powerful image processing language especially developed for the Artcam unit. Each Artcard 9 contains one Vark script, and thereby defines one image processing style.

[0313] Preferably, the VARK language is highly image processing specific. By being highly image processing specific, the amount of storage required to store the details on the card are substantially reduced. Further, the ease with which new programs can be created, including enhanced effects, is also substantially increased. Preferably, the language includes facilities for handling many image processing functions including image warping via a warp map, convolution, color lookup tables, posterizing an image, adding noise to an image, image enhancement filters, painting algorithms, brush jittering and manipulation edge detection filters, tiling, illumination via light sources, bump maps, text, face detection and object detection attributes, fonts, including three dimensional fonts, and arbitrary complexity pre-rendered icons. Further details of the operation of the Vark language interpreter are contained hereinafter.

[0314] Hence, by utilizing the language constructs as defined by the created language, new affects on arbitrary images can be created and constructed for inexpensive storage on Artcard and subsequent distribution to camera owners. Further, on one surface of the card can be provided an example illustrating the effect that a particular VARK script, stored on the other surface of the card, will have on an arbitrary captured image.

[0315] By utilizing such a system, camera technology can be distributed without a great fear of obsolescence in that, provided a VARK interpreter is incorporated in the camera device, a device independent scenario is provided whereby the underlying technology can be completely varied over time. Further, the VARK scripts can be updated as new filters are created and distributed in an inexpensive manner, such as via simple cards for card reading.

[0316] The Artcard 9 is a piece of thin white plastic with the same format as a credit card (86 mm long by 54 mm wide). The Artcard is printed on both sides using a high resolution ink jet printer. The inkjet printer technology is assumed to be the same as that used in the Artcam, with 1600 dpi (63 dpmm) resolution. A major feature of the Artcard 9 is low manufacturing cost. Artcards can be manufactured at high speeds as a wide web of plastic film. The plastic web is coated on both sides with a hydrophilic dye fixing layer. The web is printed simultaneously on both sides using a pagewidth color ink jet printer. The web is then cut and punched into individual cards. On one face of the card is printed a human readable representation of the effect the Artcard 9 will have on the sensed image. This can be simply a standard image which has been processed using the Vark script stored on the back face of the card.

[0317] On the back face of the card is printed an array of dots which can be decoded into the Vark script that defines the image processing sequence. The print area is 80 mm50 mm, giving a total of 15,876,000 dots.

[0318] This array of dots could represent at least 1.89 Mbytes of data. To achieve high reliability, extensive error detection and correction is incorporated in the array of dots. This allows a substantial portion of the card to be defaced, worn, creased, or dirty with no effect on data integrity. The data coding used is Reed-Solomon coding, with half of the data devoted to error correction. This allows the storage of 967 Kbytes of error corrected data on each Artcard 9.

[0319] Linear Image Sensor 34

[0320] The Artcard linear sensor 34 converts the aforementioned Artcard data image to electrical signals. As with the area image sensor 2, 4, the linear image sensor can be fabricated using either CCD or APS CMOS technology. The active length of the image sensor 34 is 50 mm, equal to the width of the data array on the Artcard 9. To satisfy Nyquist's sampling theorem, the resolution of the linear image sensor 34 must be at least twice the highest spatial frequency of the Artcard optical image reaching the image sensor. In practice, data detection is easier if the image sensor resolution is substantially above this. A resolution of 4800 dpi (189 dpmm) is chosen, giving a total of 9,450 pixels. This resolution requires a pixel sensor pitch of 5.3 m. This can readily be achieved by using four staggered rows of 20 m pixel sensors.

[0321] The linear image sensor is mounted in a special package which includes a LED 65 to illuminate the Artcard 9 via a light-pipe (not shown).

[0322] The Artcard reader light-pipe can be a molded light-pipe which has several function:

[0323] 1. It diffuses the light from the LED over the width of the card using total internal reflection facets.

[0324] 2. It focuses the light onto a 16 m wide strip of the Artcard 9 using an integrated cylindrical lens.

[0325] 3. It focuses light reflected from the Artcard onto the linear image sensor pixels using a molded array of microlenses.

[0326] The operation of the Artcard reader is explained further hereinafter.

[0327] Artcard Reader Motor 37

[0328] The Artcard reader motor propels the Artcard past the linear image sensor 34 at a relatively constant rate. As it may not be cost effective to include extreme precision mechanical components in the Artcard reader, the motor 37 is a standard miniature motor geared down to an appropriate speed to drive a pair of rollers which move the Artcard 9. The speed variations, rumble, and other vibrations will affect the raw image data as circuitry within the APC 31 includes extensive compensation for these effects to reliably read the Artcard data.

[0329] The motor 37 is driven in reverse when the Artcard is to be ejected.

[0330] Artcard Motor Driver 61

[0331] The Artcard motor driver 61 is a small circuit which amplifies the digital motor control signals from the APC 31 to levels suitable for driving the motor 37.

[0332] Card Insertion Sensor 49

[0333] The card insertion sensor 49 is an optical sensor which detects the presence of a card as it is being inserted in the card reader 34. Upon a signal from this sensor 49, the APC 31 initiates the card reading process, including the activation of the Artcard reader motor 37.

[0334] Card Eject Button 16

[0335] A card eject button 16 (FIG. 1) is used by the user to eject the current Artcard, so that another Artcard can be inserted. The APC 31 detects the pressing of the button, and reverses the Artcard reader motor 37 to eject the card.

[0336] Card Status Indicator 66

[0337] A card status indicator 66 is provided to signal the user as to the status of the Artcard reading process. This can be a standard bi-color (red/green) LED. When the card is successfully read, and data integrity has been verified, the LED lights up green continually. If the card is faulty, then the LED lights up red.

[0338] If the camera is powered from a 1.5 V instead of 3V battery, then the power supply voltage is less than the forward voltage drop of the greed LED, and the LED will not light. In this case, red LEDs can be used, or the LED can be powered from a voltage pump which also powers other circuits in the Artcam which require higher voltage.

[0339] 64 Mbit DRAM 33

[0340] To perform the wide variety of image processing effects, the camera utilizes 8 Mbytes of memory 33. This can be provided by a single 64 Mbit memory chip. Of course, with changing memory technology increased Dram storage sizes may be substituted.

[0341] High speed access to the memory chip is required. This can be achieved by using a Rambus DRAM (burst access rate of 500 Mbytes per second) or chips using the new open standards such as double data rate (DDR) SDRAM or Synclink DRAM.

[0342] Camera Authentication Chip

[0343] The camera authentication chip 54 is identical to the print roll authentication chip 53, except that it has different information stored in it. The camera authentication chip 54 has three main purposes:

[0344] 1. To provide a secure means of comparing authentication codes with the print roll authentication chip;

[0345] 2. To provide storage for manufacturing information, such as the serial number of the camera;

[0346] 3. To provide a small amount of non-volatile memory for storage of user information.

[0347] Displays

[0348] The Artcam includes an optional color display 5 and small status display 15. Lowest cost consumer cameras may include a color image display, such as a small TFT LCD 5 similar to those found on some digital cameras and camcorders. The color display 5 is a major cost element of these versions of Artcam, and the display 5 plus back light are a major power consumption drain.

[0349] Status display 15

[0350] The status display 15 is a small passive segment based LCD, similar to those currently provided on silver halide and digital cameras. Its main function is to show the number of prints remaining in the print roll 42 and icons for various standard camera features, such as flash and battery status.

[0351] Color display 5

[0352] The color display 5 is a full motion image display which operates as a viewfinder, as a verification of the image to be printed, and as a user interface display. The cost of the display 5 is approximately proportional to its area, so large displays (say 4 diagonal) unit will be restricted to expensive versions of the Artcam unit. Smaller displays, such as color camcorder viewfinder TFT's at around 1, may be effective for mid-range Artcams.

[0353] Zoom Lens (Not Shown)

[0354] The Artcam can include a zoom lens. This can be a standard electronically controlled zoom lens, identical to one which would be used on a standard electronic camera, and similar to pocket camera zoom lenses. A referred version of the Artcam unit may include standard interchangeable 35 mm SLR lenses.

[0355] Autofocus Motor 39

[0356] The autofocus motor 39 changes the focus of the zoom lens. The motor is a miniature motor geared down to an appropriate speed to drive the autofocus mechanism.

[0357] Autofocus Motor Driver 63

[0358] The autofocus motor driver 63 is a small circuit which amplifies the digital motor control signals from the APC 31 to levels suitable for driving the motor 39.

[0359] Zoom Motor 38

[0360] The zoom motor 38 moves the zoom front lenses in and out. The motor is a miniature motor geared down to an appropriate speed to drive the zoom mechanism.

[0361] Zoom Motor Driver 62

[0362] The zoom motor driver 62 is a small circuit which amplifies the digital motor control signals from the APC 31 to levels suitable for driving the motor.

[0363] Communications

[0364] The ACP 31 contains a universal serial bus (USB) interface 52 for communication with personal computers. Not all Artcam models are intended to include the USB connector. However, the silicon area required for a USB circuit 52 is small, so the interface can be included in the standard ACP.

[0365] Optional Keyboard 57

[0366] The Artcam unit may include an optional miniature keyboard 57 for customizing text specified by the Artcard. Any text appearing in an Artcard image may be editable, even if it is in a complex metallic 3D font. The miniature keyboard includes a single line alphanumeric LCD to display the original text and edited text. The keyboard may be a standard accessory.

[0367] The ACP 31 contains a serial communications circuit for transferring data to and from the miniature keyboard.

[0368] Power Supply

[0369] The Artcam unit uses a battery 48. Depending upon the Artcam options, this is either a 3V Lithium cell, 1.5 V AA alkaline cells, or other battery arrangement.

[0370] Power Management Unit 51

[0371] Power consumption is an important design constraint in the Artcam. It is desirable that either standard camera batteries (such as 3V lithium batters) or standard AA or AAA alkaline cells can be used. While the electronic complexity of the Artcam unit is dramatically higher than 35 mm photographic cameras, the power consumption need not be commensurately higher. Power in the Artcam can be carefully managed with all unit being turned off when not in use.

[0372] The most significant current drains are the ACP 31, the area image sensors 2, 4, the printer 44 various motors, the flash unit 56, and the optional color display 5 dealing with each part separately:

[0373] 1. ACP: If fabricated using 0.25 m CMOS, and running on 1.5V, the ACP power consumption can be quite low. Clocks to various parts of the ACP chip can be quite low. Clocks to various parts of the ACP chip can be turned off when not in use, virtually eliminating standby current consumption. The ACP will only fully used for approximately 4 seconds for each photograph printed.

[0374] 2. Area image sensor: power is only supplied to the area image sensor when the user has their finger on the button.

[0375] 3. The printer power is only supplied to the printer when actually printing. This is for around 2 seconds for each photograph. Even so, suitably lower power consumption printing should be used.

[0376] 4. The motors required in the Artcam are all low power miniature motors, and are typically only activated for a few seconds per photo.

[0377] 5. The flash unit 45 is only used for some photographs. Its power consumption can readily be provided by a 3V lithium battery for a reasonably battery life.

[0378] 6. The optional color display 5 is a major current drain for two reasons: it must be on for the whole time that the camera is in use, and a backlight will be required if a liquid crystal display is used. Cameras which incorporate a color display will require a larger battery to achieve acceptable batter life.

[0379] Flash Unit 56

[0380] The flash unit 56 can be a standard miniature electronic flash for consumer cameras.

[0381] Overview of the ACP 31

[0382] FIG. 3 illustrates the Artcam Central Processor (ACP) 31 in more detail. The Artcam Central Processor provides all of the processing power for Artcam. It is designed for a 0.25 micron CMOS process, with approximately 1.5 million transistors and an area of around 50 mm². The ACP 31 is a complex design, but design effort can be reduced by the use of datapath compilation techniques, macrocells, and IP cores. The ACP 31 contains:

[0383] A RISC CPU core 72

[0384] A 4 way parallel VLIW Vector Processor 74

[0385] A Direct RAMbus interface 81

[0386] A CMOS image sensor interface 83

[0387] A CMOS linear image sensor interface 88

[0388] A USB serial interface 52

[0389] An infrared keyboard interface 55

[0390] A numeric LCD interface 84, and

[0391] A color TFT LCD interface 88

[0392] A 4 Mbyte Flash memory 70 for program storage 70

[0393] The RISC CPU, Direct RAMbus interface 81, CMOS sensor interface 83 and USB serial interface 52 can be vendor supplied cores. The ACP 31 is intended to run at a clock speed of 200 MHz on 3V externally and 1.5V internally to minimize power consumption. The CPU core needs only to run at 100 MHz. The following two block diagrams give two views of the ACP 31:

[0394] A view of the ACP 31 in isolation

[0395] An example Artcam showing a high-level view of the ACP 31 connected to the rest of the Artcam hardware.

[0396] Image Access

[0397] As stated previously, the DRAM Interface 81 is responsible for interfacing between other client portions of the ACP chip and the RAMBUS DRAM. In effect, each module within the DRAM Interface is an address generator.

[0398] There are three logical types of images manipulated by the ACP. They are:

[0399] CCD Image, which is the Input Image captured from the CCD.

[0400] Internal Image formatthe Image format utilised internally by the Artcam device.

[0401] Print Imagethe Output Image format printed by the Artcam

[0402] These images are typically different in color space, resolution, and the output & input color spaces which can vary from camera to camera. For example, a CCD image on a low-end camera may be a different resolution, or have different color characteristics from that used in a high-end camera. However all internal image formats are the same format in terms of color space across all cameras.

[0403] In addition, the three image types can vary with respect to which direction is up. The physical orientation of the camera causes the notion of a portrait or landscape image, and this must be maintained throughout processing. For this reason, the internal image is always oriented correctly, and rotation is performed on images obtained from the CCD and during the print operation.

[0404] CPU Core (CPU) 72

[0405] The ACP 31 incorporates a 32 bit RISC CPU 72 to run the Vark image processing language interpreter and to perform Artcam's general operating system duties. A wide variety of CPU cores are suitable: it can be any processor core with sufficient processing power to perform the required core calculations and control functions fast enough to met consumer expectations. Examples of suitable cores are: MIPS R4000 core from LSI Logic, StrongARM core. There is no need to maintain instruction set continuity between different Artcam models. Artcard compatibility is maintained irrespective of future processor advances and changes, because the Vark interpreter is simply re-compiled for each new instruction set. The ACP 31 architecture is therefore also free to evolve. Different ACP 31 chip designs may be fabricated by different manufacturers, without requiring to license or port the CPU core. This device independence avoids the chip vendor lock-in such as has occurred in the PC market with Intel. The CPU operates at 100 MHz, with a single cycle time of 10 ns. It must be fast enough to run the Vark interpreter, although the VLIW Vector Processor 74 is responsible for most of the time-critical operations.

[0406] Program Cache 72

[0407] Although the program code is stored in on-chip Flash memory 70, it is unlikely that well packed Flash memory 70 will be able to operate at the 10 ns cycle time required by the CPU. Consequently a small cache is required for good performance. 16 cache lines of 32 bytes each are sufficient, for a total of 512 bytes. The program cache 72 is defined in the chapter entitled Program cache 72.

[0408] Data Cache 76

[0409] A small data cache 76 is required for good performance. This requirement is mostly due to the use of a RAMbus DRAM, which can provide high-speed data in bursts, but is inefficient for single byte accesses. The CPU has access to a memory caching system that allows flexible manipulation of CPU data cache 76 sizes. A minimum of 16 cache lines (512 bytes) is recommended for good performance.

[0410] CPU Memory Model

[0411] An Artcam's CPU memory model consists of a 32 MB area. It consists of 8 MB of physical RDRAM off-chip in the base model of Artcam, with provision for up to 16 MB of off-chip memory. There is a 4 MB Flash memory 70 on the ACP 31 for program storage, and finally a 4 MB address space mapped to the various registers and controls of the ACP 31. The memory map then, for an Artcam is as follows:

	Contents	Size
	Base Artcam DRAM	8 MB
	Extended DRAM	8 MB
	Program memory (on ACP 31 in Flash memory 70)	4 MB
	Reserved for extension of program memory	4 MB
	ACP 31 registers and memory-mapped I/O	4 MB
	Reserved	4 MB
	TOTAL	32 MB

[0412] A straightforward way of decoding addresses is to use address bits 23-24:

[0413] If bit 24 is clear, the address is in the lower 16-MB range, and hence can be satisfied from DRAM and the Data cache 76. In most cases the DRAM will only be 8 MB, but 16 MB is allocated to cater for a higher memory model Artcams.

[0414] If bit 24 is set, and bit 23 is clear, then the address represents the Flash memory 70 4 Mbyte range and is satisfied by the Program cache 72.

[0415] If bit 241 and bit 231, the address is translated into an access over the low speed bus to the requested component in the AC by the CPU Memory Decoder 68.

[0416] Flash Memory 70

[0417] The ACP 31 contains a 4 Mbyte Flash memory 70 for storing the Artcam program. It is envisaged that Flash memory 70 will have denser packing coefficients than masked ROM, and allows for greater flexibility for testing camera program code. The downside of the Flash memory 70 is the access time, which is unlikely to be fast enough for the 100 MHz operating speed (10 ns cycle time) of the CPU. A fast Program Instruction cache 77 therefore acts as the interface between the CPU and the slower Flash memory 70.

[0418] Program Cache 72

[0419] A small cache is required for good CPU performance. This requirement is due to the slow speed Flash memory 70 which stores the Program code. 16 cache lines of 32 bytes each are sufficient, for a total of 512 bytes. The Program cache 72 is a read only cache. The data used by CPU programs comes through the CPU Memory Decoder 68 and if the address is in DRAM, through the general Data cache 76. The separation allows the CPU to operate independently of the VLIW Vector Processor 74. If the data requirements are low for a given process, it can consequently operate completely out of cache. Finally, the Program cache 72 can be read as data by the CPU rather than purely as program instructions. This allows tables, microcode for the VLIW etc to be loaded from the Flash memory 70. Addresses with bit 24 set and bit 23 clear are satisfied from the Program cache 72.

[0420] CPU Memory Decoder 68

[0421] The CPU Memory Decoder 68 is a simple decoder for satisfying CPU data accesses. The Decoder translates data addresses into internal ACP register accesses over the internal low speed bus, and therefore allows for memory mapped I/O of ACP registers. The CPU Memory Decoder 68 only interprets addresses that have bit 24 set and bit 23 clear. There is no caching in the CPU Memory Decoder 68.

[0422] DRAM interface 81

[0423] The DRAM used by the Artcam is a single channel 64 Mbit (8 MB) RAMbus RDRAM operating at 1.6 GB/sec. RDRAM accesses are by a single channel (16-bit data path) controller. The RDRAM also has several useful operating modes for low power operation. Although the Rambus specification describes a system with random 32 byte transfers as capable of achieving a greater than 95% efficiency, this is not true if only part of the 32 bytes are used. Two reads followed by two writes to the same device yields over 86% efficiency. The primary latency is required for bus turn-around going from a Write to a Read, and since there is a Delayed Write mechanism, efficiency can be further improved. With regards to writes, Write Masks allow specific subsets of bytes to be written to. These write masks would be set via internal cache dirty bits. The upshot of the Rambus Direct RDRAM is a throughput of >1 GB/sec is easily achievable, and with multiple reads for every write (most processes) combined with intelligent algorithms making good use of 32 byte transfer knowledge, transfer rates of >1.3 GB/sec are expected. Every 10 ns, 16 bytes can be transferred to or from the core.

[0424] DRAM Organization

[0425] The DRAM organization for a base model (8 MB RDRAM) Artcam is as follows:

	Contents	Size
	Program scratch RAM	0.50 MB
	Artcard data	1.00 MB
	Photo Image, captured from CMOS Sensor	0.50 MB
	Print Image (compressed)	2.25 MB
	1 Channel of expanded Photo Image	1.50 MB
	1 Image Pyramid of single channel	1.00 MB
	Intermediate Image Processing	1.25 MB
	TOTAL	8 MB

[0426] Notes:

[0427] Uncompressed, the Print Image requires 4.5 MB (1.5 MB per channel). To accommodate other objects in the 8 MB model, the Print Image needs to be compressed. If the chrominance channels are compressed by 4:1 they require only 0.375 MB each).

[0428] The memory model described here assumes a single 8 MB RDRAM. Other models of the Artcam may have more memory, and thus not require compression of the Print Image. In addition, with more memory a larger part of the final image can be worked on at once, potentially giving a speed improvement.

[0429] Note that ejecting or inserting an Artcard invalidates the 5.5 MB area holding the Print Image, 1 channel of expanded photo image, and the image pyramid. This space may be safely used by the Artcard Interface for decoding the Artcard data.

[0430] Data cache 76

[0431] The ACP 31 contains a dedicated CPU instruction cache 77 and a general data cache 76. The Data cache 76 handles all DRAM requests (reads and writes of data) from the CPU, the VLIW Vector Processor 74, and the Display Controller 88. These requests may have very different profiles in terms of memory usage and algorithmic timing requirements. For example, a VLIW process may be processing an image in linear memory, and lookup a value in a table for each value in the image. There is little need to cache much of the image, but it may be desirable to cache the entire lookup table so that no real memory access is required. Because of these differing requirements, the Data cache 76 allows for an intelligent definition of caching. Although the Rambus DRAM interface 81 is capable of very high-speed memory access (an average throughput of 32 bytes in 25 ns), it is not efficient dealing with single byte requests. In order to reduce effective memory latency, the ACP 31 contains 128 cache lines. Each cache line is 32 bytes wide. Thus the total amount of data cache 76 is 4096 bytes (4 KB). The 128 cache lines are configured into 16 programmable-sized groups. Each of the 16 groups must be a contiguous set of cache lines. The CPU is responsible for determining how many cache lines to allocate to each group. Within each group cache lines are filled according to a simple Least Recently Used algorithm. In terms of CPU data requests, the Data cache 76 handles memory access requests that have address bit 24 clear. If bit 24 is clear, the address is in the lower 16 MB range, and hence can be satisfied from DRAM and the Data cache 76. In most cases the DRAM will only be 8 MB, but 16 MB is allocated to cater for a higher memory model Artcam. If bit 24 is set, the address is ignored by the Data cache 76.

[0432] All CPU data requests are satisfied from Cache Group 0. A minimum of 16 cache lines is recommended for good CPU performance, although the CPU can assign any number of cache lines (except none) to Cache Group 0. The remaining Cache Groups (1 to 15) are allocated according to the current requirements. This could mean allocation to a VLIW Vector Processor 74 program or the Display Controller 88. For example, a 256 byte lookup table required to be permanently available would require 8 cache lines. Writing out a sequential image would only require 2-4 cache lines (depending on the size of record being generated and whether write requests are being Write Delayed for a significant number of cycles). Associated with each cache line byte is a dirty bit, used for creating a Write Mask when writing memory to DRAM. Associated with each cache line is another dirty bit, which indicates whether any of the cache line bytes has been written to (and therefore the cache line must be written back to DRAM before it can be reused). Note that it is possible for two different Cache Groups to be accessing the same address in memory and to get out of sync. The VLIW program writer is responsible to ensure that this is not an issue. It could be perfectly reasonable, for example, to have a Cache Group responsible for reading an image, and another Cache Group responsible for writing the changed image back to memory again. If the images are read or written sequentially there may be advantages in allocating cache lines in this manner. A total of 8 buses 182 connect the VLIW Vector Processor 74 to the Data cache 76. Each bus is connected to an I/O Address Generator. (There are 2 I/O Address Generators 189, 190 per Processing Unit 178, and there are 4 Processing Units in the VLIW Vector Processor 74. The total number of buses is therefore 8.) In any given cycle, in addition to a single 32 bit (4 byte) access to the CPU's cache group (Group 0), 4 simultaneous accesses of 16 bits (2 bytes) to remaining cache groups are permitted on the 8 VLIW Vector Processor 74 buses. The Data cache 76 is responsible for fairly processing the requests. On a given cycle, no more than 1 request to a specific Cache Group will be processed. Given that there are 8 Address Generators 189, 190 in the VLIW Vector Processor 74, each one of these has the potential to refer to an individual Cache Group. However it is possible and occasionally reasonable for 2 or more Address Generators 189, 190 to access the same Cache Group. The CPU is responsible for ensuring that the Cache Groups have been allocated the correct number of cache lines, and that the various Address Generators 189, 190 in the VLIW Vector Processor 74 reference the specific Cache Groups correctly. The Data cache 76 as described allows for the Display Controller 88 and VLIW Vector Processor 74 to be active simultaneously. If the operation of these two components were deemed to never occur simultaneously, a total 9 Cache Groups would suffice. The CPU would use Cache Group 0, and the VLIW Vector Processor 74 and the Display Controller 88 would share the remaining 8 Cache Groups, requiring only 3 bits (rather than 4) to define which Cache Group would satisfy a particular request.

[0433] JTAG Interface 85

[0434] A standard JTAG (Joint Test Action Group) Interface is included in the ACP 31 for testing purposes. Due to the complexity of the chip, a variety of testing techniques are required, including BIST (Built In Self Test) and functional block isolation. An overhead of 10% in chip area is assumed for overall chip testing circuitry. The test circuitry is beyond the scope of this document.

[0435] Serial Interfaces

[0436] USB Serial Port Interface 52

[0437] This is a standard USB serial port, which is connected to the internal chip low speed bus, thereby allowing the CPU to control it.

[0438] Keyboard Interface 65

[0439] This is a standard low-speed serial port, which is connected to the internal chip low speed bus, thereby allowing the CPU to control it. It is designed to be optionally connected to a keyboard to allow simple data input to customize prints.

[0440] Authentication Chip Serial Interfaces 64

[0441] These are 2 standard low-speed serial ports, which are connected to the internal chip low speed bus, thereby allowing the CPU to control them. The reason for having 2 ports is to connect to both the on-camera Authentication chip, and to the print-roll Authentication chip using separate lines. Only using 1 line may make it possible for a clone print-roll manufacturer to design a chip which, instead of generating an authentication code, tricks the camera into using the code generated by the authentication chip in the camera.

[0442] Parallel Interface 67

[0443] The parallel interface connects the ACP 31 to individual static electrical signals. The CPU is able to control each of these connections as memory-mapped I/O via the low speed bus The following table is a list of connections to the parallel interface:

	Connection	Direction	Pins
	Paper transport stepper motor	Out	4
	Artcard stepper motor	Out	4
	Zoom stepper motor	Out	4
	Guillotine motor	Out	1
	Flash trigger	Out	1
	Status LCD segment drivers	Out	7
	Status LCD common drivers	Out	4
	Artcard illumination LED	Out	1
	Artcard status LED (red/green)	In	2
	Artcard sensor	In	1
	Paper pull sensor	In	1
	Orientation sensor	In	2
	Buttons	In	4
		TOTAL	36

[0444] VLIW Input and Output FIFOs 78, 79

[0445] The VLIW Input and Output FIFOs are 8 bit wide FIFOs used for communicating between processes and the VLIW Vector Processor 74. Both FIFOs are under the control of the VLIW Vector Processor 74, but can be cleared and queried (e.g. for status) etc by the CPU.

[0446] VLIW Input FIFO 78

[0447] A client writes 8-bit data to the VLIW Input FIFO 78 in order to have the data processed by the VLIW Vector Processor 74. Clients include the Image Sensor Interface, Artcard Interface, and CPU. Each of these processes is able to offload processing by simply writing the data to the FIFO, and letting the VLIW Vector Processor 74 do all the hard work. An example of the use of a client's use of the VLIW Input FIFO 78 is the Image Sensor Interface (ISI 83). The ISI 83 takes data from the Image Sensor and writes it to the FIFO. A VLIW process takes it from the FIFO, transforming it into the correct image data format, and writing it out to DRAM. The ISI 83 becomes much simpler as a result.

[0448] VLIW Output FIFO 79

[0449] The VLIW Vector Processor 74 writes 8-bit data to the VLIW Output FIFO 79 where clients can read it. Clients include the Print Head Interface and the CPU. Both of these clients is able to offload processing by simply reading the already processed data from the FIFO, and letting the VLIW Vector Processor 74 do all the hard work. The CPU can also be interrupted whenever data is placed into the VLIW Output FIFO 79, allowing it to only process the data as it becomes available rather than polling the FIFO continuously. An example of the use of a client's use of the VLIW Output FIFO 79 is the Print Head Interface (PHI 62). A VLIW process takes an image, rotates it to the correct orientation, color converts it, and dithers the resulting image according to the print head requirements. The PHI 62 reads the dithered formatted 8-bit data from the VLIW Output FIFO 79 and simply passes it on to the Print Head external to the ACP 31. The PHI 62 becomes much simpler as a result.

[0450] VLIW Vector Processor 74

[0451] To achieve the high processing requirements of Artcam, the ACP 31 contains a VLIW (Very Long Instruction Word) Vector Processor. The VLIW processor is a set of 4 identical Processing Units (PU e.g 178) working in parallel, connected by a crossbar switch 183. Each PU e.g 178 can perform four 8-bit multiplications, eight 8-bit additions, three 32-bit additions, I/O processing, and various logical operations in each cycle. The PUs e.g 178 are microcoded, and each has two Address Generators 189, 190 to allow full use of available cycles for data processing. The four PUs e.g 178 are normally synchronized to provide a tightly interacting VLIW processor. Clocking at 200 MHz, the VLIW Vector Processor 74 runs at 12 Gops (12 billion operations per second). Instructions are tuned for image processing functions such as warping, artistic brushing, complex synthetic illumination, color transforms, image filtering, and compositing. These are accelerated by two orders of magnitude over desktop computers.

[0452] As shown in more detail in FIG. 3(a), the VLIW Vector Processor 74 is 4 PUs e.g 178 connected by a crossbar switch 183 such that each PU e.g 178 provides two inputs to, and takes two outputs from, the crossbar switch 183. Two common registers form a control and synchronization mechanism for the PUs e.g 178. 8 Cache buses 182 allow connectivity to DRAM via the Data cache 76, with 2 buses going to each PU e.g 178 (1 bus per I/O Address Generator).

[0453] Each PU e.g 178 consists of an ALU 188 (containing a number of registers & some arithmetic logic for processing data), some microcode RAM 196, and connections to the outside world (including other ALUs). A local PU state machine runs in microcode and is the means by which the PU e.g 178 is controlled. Each PU e.g 178 contains two I/O Address Generators 189, 190 controlling data flow between DRAM (via the Data cache 76) and the ALU 188 (via Input FIFO and Output FIFO). The address generator is able to read and write data (specifically images in a variety of formats) as well as tables and simulated FIFOs in DRAM. The formats are customizable under software control, but are not microcoded. Data taken from the Data cache 76 is transferred to the ALU 188 via the 16-bit wide Input FIFO. Output data is written to the 16-bit wide Output FIFO and from there to the Data cache 76. Finally, all PUs e.g 178 share a single 8-bit wide VLIW Input FIFO 78 and a single 8-bit wide VLIW Output FIFO 79. The low speed data bus connection allows the CPU to read and write registers in the PU e.g 178, update microcode, as well as the common registers shared by all PUs e.g 178 in the VLIW Vector Processor 74. Turning now to FIG. 4, a closer detail of the internals of a single PU e.g 178 can be seen, with components and control signals detailed in subsequent hereinafter:

[0454] Microcode

[0455] Each PU e.g 178 contains a microcode RAM 196 to hold the program for that particular PU e.g 178. Rather than have the microcode in ROM, the microcode is in RAM, with the CPU responsible for loading it up. For the same space on chip, this tradeoff reduces the maximum size of any one function to the size of the RAM, but allows an unlimited number of functions to be written in microcode. Functions implemented using microcode include Vark acceleration, Artcard reading, and Printing. The VLIW Vector Processor 74 scheme has several advantages for the case of the ACP 31:

[0456] Hardware design complexity is reduced

[0457] Hardware risk is reduced due to reduction in complexity

[0458] Hardware design time does not depend on all Vark functionality being implemented in dedicated silicon

[0459] Space on chip is reduced overall (due to large number of processes able to be implemented as microcode)

[0460] Functionality can be added to Vark (via microcode) with no impact on hardware design time

[0461] Size and Content

[0462] The CPU loaded microcode RAM 196 for controlling each PU e.g 178 is 128 words, with each word being 96 bits wide. A summary of the microcode size for control of various units of the PU e.g 178 is listed in the following table:

	Process Block	Size (bits)
	Status Output	3
	Branching (microcode control)	11
	In	8
	Out	6
	Registers	7
	Read	10
	Write	6
	Barrel Shifter	12
	Adder/Logical	14
	Multiply/Interpolate	19
	TOTAL	96

[0463] With 128 instruction words, the total microcode RAM 196 per PU e.g 178 is 12,288 bits, or 1.5 KB exactly. Since the VLIW Vector Processor 74 consists of 4 identical PUs e.g 178 this equates to 6,144 bytes, exactly 6 KB. Some of the bits in a microcode word are directly used as control bits, while others are decoded. See the various unit descriptions that detail the interpretation of each of the bits of the microcode word.

[0464] Synchronization Between PUs e.g 178

[0465] Each PU e.g 178 contains a 4 bit Synchronization Register 197. It is a mask used to determine which PUs e.g 178 work together, and has one bit set for each of the corresponding PUs e.g 178 that are functioning as a single process. For example, if all of the PUs e.g 178 were functioning as a single process, each of the 4 Synchronization Register 197s would have all 4 bits set. If there were two asynchronous processes of 2 PUs e.g 178 each, two of the PUs e.g 178 would have 2 bits set in their Synchronization Register 197s (corresponding to themselves), and the other two would have the other 2 bits set in their Synchronization Register 197s (corresponding to themselves).

[0466] The Synchronization Register 197 is used in two basic ways:

[0467] Stopping and starting a given process in synchrony

[0468] Suspending execution within a process

[0469] Stopping and Starting Processes

[0470] The CPU is responsible for loading the microcode RAM 196 and loading the execution address for the first instruction (usually 0). When the CPU starts executing microcode, it begins at the specified address.

[0471] Execution of microcode only occurs when all the bits of the Synchronization Register 197 are also set in the Common Synchronization Register 197. The CPU therefore sets up all the PUs e.g 178 and then starts or stops processes with a single write to the Common Synchronization Register 197.

[0472] This synchronization scheme allows multiple processes to be running asynchronously on the PUs e.g 178, being stopped and started as processes rather than one PU e.g 178 at a time.

[0473] Suspending Execution within a Process

[0474] In a given cycle, a PU e.g 178 may need to read from or write to a FIFO (based on the opcode of the current microcode instruction). If the FIFO is empty on a read request, or full on a write request, the FIFO request cannot be completed. The PU e.g 178 will therefore assert its SuspendProcess control signal 198. The SuspendProcess signals from all PUs e.g 178 are fed back to all the PUs e.g 178. The Synchronization Register 197 is ANDed with the 4 SuspendProcess bits, and if the result is non-zero, none of the PU e.g 178's register WriteEnables or FIFO strobes will be set. Consequently none of the PUs e.g 178 that form the same process group as the PU e.g 178 that was unable to complete its task will have their registers or FIFOs updated during that cycle. This simple technique keeps a given process group in synchronization. Each subsequent cycle the PU e.g 178's state machine will attempt to re-execute the microcode instruction at the same address, and will continue to do so until successful. Of course the Common Synchronization Register 197 can be written to by the CPU to stop the entire process if necessary. This synchronization scheme allows any combinations of PUs e.g 178 to work together, each group only affecting its co-workers with regards to suspension due to data not being ready for reading or writing.

[0475] Control and Branching

[0476] During each cycle, each of the four basic input and calculation units within a PU e.g 178's ALU 188 (Read, Adder/Logic, Multiply/Interpolate, and Barrel Shifter) produces two status bits: a Zero flag and a Negative flag indicating whether the result of the operation during that cycle was 0 or negative. Each cycle one of those 4 status bits is chosen by microcode instructions to be output from the PU e.g 178. The 4 status bits (1 per PU e.g 178's ALU 188) are combined into a 4 bit Common Status Register 200. During the next cycle, each PU e.g 178's microcode program can select one of the bits from the Common Status Register 200, and branch to another microcode address dependant on the value of the status bit.

[0477] Status bit

[0478] Each PU e.g 178's ALU 188 contains a number of input and calculation units. Each unit produces 2 status bitsa negative flag and a zero flag. One of these status bits is output from the PU e.g 178 when a particular unit asserts the value on the 1-bit tri-state status bit bus. The single status bit is output from the PU e.g 178, and then combined with the other PU e.g 178 status bits to update the Common Status Register 200. The microcode for determining the output status bit takes the following form:

Bits	Description
2	Select unit whose status bit is to be output
	00 Adder unit
	01 Multiply/Logic unit
	10 Barrel Shift unit
	11 Reader unit
1	0 Zero flag
	1 Negative flag
3	TOTAL

[0479] Within the ALU 188, the 2-bit Select Processor Block value is decoded into four 1-bit enable bits, with a different enable bit sent to each processor unit block. The status select bit (choosing Zero or Negative) is passed into all units to determine which bit is to be output onto the status bit bus.

[0480] Branching Within Microcode

[0481] Each PU e.g 178 contains a 7 bit Program Counter (PC) that holds the current microcode address being executed. Normal program execution is linear, moving from address N in one cycle to address N1 in the next cycle. Every cycle however, a microcode program has the ability to branch to a different location, or to test a status bit from the Common Status Register 200 and branch. The microcode for determining the next execution address takes the following form:

Bits	Description
2	00 NOP (PC PC1)
	01 Branch always
	10 Branch if status bit clear
	11 Branch if status bit set
2	Select status bit from status word
7	Address to branch to (absolute address, 00-7F)
11	TOTAL

[0482] ALU 188

[0483] FIG. 5 illustrates the ALU 188 in more detail. Inside the ALU 188 are a number of specialized processing blocks, controlled by a microcode program. The specialized processing blocks include:

[0484] Read Block 202, for accepting data from the input FIFOs

[0485] Write Block 203, for sending data out via the output FIFOs

[0486] Adder/Logical block 204, for addition & subtraction, comparisons and logical operations

[0487] Multiply/Interpolate block 205, for multiple types of interpolations and multiply/accumulates

[0488] Barrel Shift block 206, for shifting data as required

[0489] In block 207, for accepting data from the external crossbar switch 183

[0490] Out block 208, for sending data to the external crossbar switch 183

[0491] Registers block 215, for holding data in temporary storage

[0492] Four specialized 32 bit registers hold the results of the 4 main processing blocks:

[0493] M register 209 holds the result of the Multiply/Interpolate block

[0494] L register 209 holds the result of the Adder/Logic block

[0495] S register 209 holds the result of the Barrel Shifter block

[0496] R register 209 holds the result of the Read Block 202

[0497] In addition there are two internal crossbar switches 213m 214 for data transport. The various process blocks are further expanded in the following sections, together with the microcode definitions that pertain to each block. Note that the microcode is decoded within a block to provide the control signals to the various units within.

[0498] Data Transfers Between PUs e.g 178

[0499] Each PU e.g 178 is able to exchange data via the external crossbar. A PU e.g 178 takes two inputs and outputs two values to the external crossbar. In this way two operands for processing can be obtained in a single cycle, but cannot be actually used in an operation until the following cycle.

[0500] In 207

[0501] This block is illustrated in FIG. 6 and contains two registers, In₁ and In₂ that accept data from the external crossbar. The registers can be loaded each cycle, or can remain unchanged. The selection bits for choosing from among the 8 inputs are output to the external crossbar switch 183. The microcode takes the following form:

Bits	Description
1	0 NOP
	1 Load In1 from crossbar
3	Select Input 1 from external crossbar
1	0 NOP
	1 Load In2 from crossbar
3	Select Input 2 from external crossbar
8	TOTAL

[0502] Out 208

[0503] Complementing In is Out 208. The Out block is illustrated in more detail in FIG. 7. Out contains two registers, Out₁ and Out₂, both of which are output to the external crossbar each cycle for use by other PUs e.g 178. The Write unit is also able to write one of Out₁ or Out₂ to one of the output FIFOs attached to the ALU 188. Finally, both registers are available as inputs to Crossbar1 213, which therefore makes the register values available as inputs to other units within the ALU 188. Each cycle either of the two registers can be updated according to microcode selection. The data loaded into the specified register can be one of D₀-D₃ (selected from Crossbar1 213) one of M, L, S, and R (selected from Crossbar2 214), one of 2 programmable constants, or the fixed values 0 or 1. The microcode for Out takes the following form:

Bits	Description
1	0 NOP
	1 Load Register
1	Select Register to load Out1 or Out2
4	Select input In1, In2, Out1, Out2, D0,
	D1, D2, D3, M, L, S, R, K1, K2, 0, 1
6	TOTAL

[0504] Local Registers and Data Transfers Within ALU 188

[0505] As noted previously, the ALU 188 contains four specialized 32-bit registers to hold the results of the 4 main processing blocks:

[0506] M register 209 holds the result of the Multiply/Interpolate block

[0507] L register 209 holds the result of the Adder/Logic block

[0508] S register 209 holds the result of the Barrel Shifter block

[0509] R register 209 holds the result of the Read Block 202

[0510] The CPU has direct access to these registers, and other units can select them as inputs via Crossbar2 214. Sometimes it is necessary to delay an operation for one or more cycles. The Registers block contains four 32-bit registers D₀-D₃ to hold temporary variables during processing. Each cycle one of the registers can be updated, while all the registers are output for other units to use via Crossbar1 213 (which also includes In₁, In₂, Out₁ and Out₂). The CPU has direct access to these registers. The data loaded into the specified register can be one of D₀-D₃ (selected from Crossbar1 213) one of M, L, S, and R (selected from Crossbar2 214), one of 2 programmable constants, or the fixed values 0 or 1. The Registers block 215 is illustrated in more detail in FIG. 8. The microcode for Registers takes the following form:

Bits	Description
1	0 NOP
	1 Load Register
2	Select Register to load D0-D3
4	Select input In1,In2,Out1,Out2,D0,D1,D2,
	D3,M,L,S,R,K1,K2,0,1
7	TOTAL

[0511] Crossbar1 213

[0512] Crossbar1 213 is illustrated in more detail in FIG. 9. Crossbar1 213 is used to select from inputs In₁, In₂, Out₁, Out₂, D₀-D₃. 7 outputs are generated from Crossbar1 213: 3 to the Multiply/Interpolate Unit, 2 to the Adder Unit, 1 to the Registers unit and 1 to the Out unit. The control signals for Crossbar1 213 come from the various units that use the Crossbar inputs. There is no specific microcode that is separate for Crossbar1 213.

[0513] Crossbar2 214

[0514] Crossbar2 214 is illustrated in more detail in FIG. 10. Crossbar2 214 is used to select from the general ALU 188 registers M, L, S and R. 6 outputs are generated from Crossbar1 213: 2 to the Multiply/Interpolate Unit, 2 to the Adder Unit, 1 to the Registers unit and 1 to the Out unit. The control signals for Crossbar2 214 come from the various units that use the Crossbar inputs. There is no specific microcode that is separate for Crossbar2 214.

[0515] Data Transfers Between PUs e.g 178 and DRAM or External Processes

[0516] Returning to FIG. 4, PUs e.g 178 share data with each other directly via the external crossbar. They also transfer data to and from external processes as well as DRAM. Each PU e.g 178 has 2 I/O Address Generators 189, 190 for transferring data to and from DRAM. A PU e.g 178 can send data to DRAM via an I/O Address Generator's Output FIFO e.g. 186, or accept data from DRAM via an I/O Address Generator's Input FIFO 187. These FIFOs are local to the PU e.g 178. There is also a mechanism for transferring data to and from external processes in the form of a common VLIW Input FIFO 78 and a common VLIW Output FIFO 79, shared between all ALUs. The VLIW Input and Output FIFOs are only 8 bits wide, and are used for printing, Artcard reading, transferring data to the CPU etc. The local Input and Output FIFOs are 16 bits wide.

[0517] Read

[0518] The Read process block 202 of FIG. 5 is responsible for updating the ALU 188's R register 209, which represents the external input data to a VLIW microcoded process. Each cycle the Read Unit is able to read from either the common VLIW Input FIFO 78 (8 bits) or one of two local Input FIFOs (16 bits). A 32-bit value is generated, and then all or part of that data is transferred to the R register 209. The process can be seen in FIG. 11. The microcode for Read is described in the following table. Note that the interpretations of some bit patterns are deliberately chosen to aid decoding.

Bits	Description
2	00 NOP
	01 Read from VLIW Input FIFO 78
	10 Read from Local FIFO 1
	11 Read from Local FIFO 2
1	How many significant bits
	0 8 bits (pad with 0 or sign extend)
	1 16 bits (only valid for Local FIFO reads)
1	0 Treat data as unsigned (pad with 0)
	1 Treat data as signed (sign extend when reading from FIFO)r
2	How much to shift data left by:
	00 0 bits (no change)
	01 8 bits
	10 16 bits
	11 24 bits
4	Which bytes of R to update (hi to lo order byte)
	Each of the 4 bits represents 1 byte WriteEnable on R
10	TOTAL

[0519] Write

[0520] The Write process block is able to write to either the common VLIW Output FIFO 79 or one of the two local Output FIFOs each cycle. Note that since only 1 FIFO is written to in a given cycle, only one 16-bit value is output to all FIFOs, with the low 8 bits going to the VLIW Output FIFO 79. The microcode controls which of the FIFOs gates in the value. The process of data selection can be seen in more detail in FIG. 12. The source values Out₁ and Out₂ come from the Out block. They are simply two registers. The microcode for Write takes the following form:

Bits	Description
2	00 NOP
	01 Write VLIW Output FIFO 79
	10 Write local Output FIFO 1
	11 Write local Output FIFO 2
1	Select Output Value Out1 or Out2
3	Select part of Output Value to write (32 bits 4 bytes ABCD)
	000 0D
	001 0D
	010 0B
	011 0A
	100 CD
	101 BC
	110 AB
	111 0
6	TOTAL

[0521] Computational Blocks

[0522] Each ALU 188 has two computational process blocks, namely an Adder/Logic process block 204, and a Multiply/Interpolate process block 205. In addition there is a Barrel Shifter block to provide help to these computational blocks. Registers from the Registers block 215 can be used for temporary storage during pipelined operations.

[0523] Barrel Shifter

[0524] The Barrel Shifter process block 206 is shown in more detail in FIG. 13 and takes its input from the output of Adder/Logic or Multiply/Interpolate process blocks or the previous cycle's results from those blocks (ALU registers L and M). The 32 bits selected are barrel shifted an arbitrary number of bits in either direction (with sign extension as necessary), and output to the ALU 188's S register 209. The microcode for the Barrel Shift process block is described in the following table. Note that the interpretations of some bit patterns are deliberately chosen to aid decoding.

Bits	Description
3	000 NOP
	001 Shift Left (unsigned)
	010 Reserved
	011 Shift Left (signed)
	100 Shift right (unsigned, no rounding)
	101 Shift right (unsigned, with rounding)
	110 Shift right (signed, no rounding)
	111 Shift right (signed, with rounding)
2	Select Input to barrel shift:
	00 Multiply/Interpolate result
	01 M
	10 Adder/Logic result
	11 L
5	bits to shift
1	Ceiling of 255
1	Floor of 0 (signed data)
12	TOTAL

[0525] Adder/Logic 204

[0526] The Adder/Logic process block is shown in more detail in FIG. 14 and is designed for simple 32-bit addition/subtraction, comparisons, and logical operations. In a single cycle a single addition, comparison, or logical operation can be performed, with the result stored in the ALU 188's L register 209. There are two primary operands, A and B, which are selected from either of the two crossbars or from the 4 constant registers. One crossbar selection allows the results of the previous cycle's arithmetic operation to be used while the second provides access to operands previously calculated by this or another ALU 188. The CPU is the only unit that has write access to the four constants (K₁-K₄). In cases where an operation such as (AB)4 is desired, the direct output from the adder can be used as input to the Barrel Shifter, and can thus be shifted left 2 places without needing to be latched into the L register 209 first. The output from the adder can also be made available to the multiply unit for a multiply-accumulate operation. The microcode for the Adder/Logic process block is described in the following table. The interpretations of some bit patterns are deliberately chosen to aid decoding. Microcode bit interpretation for Adder/Logic unit

Bits	Description
4	0000 AB (carry in 0)
	0001 AB (carry in carry out of previous operation)
	0010 AB1 (carry in 1)
	0011 A1 (increments A)
	0100 AB1 (carry in 0)
	0101 AB (carry in carry out of previous operation)
	0110 AB (carry in 1)
	0111 A1 (decrements A)
	1000 NOP
	1001 ABS(AB)
	1010 MIN(A, B)
	1011 MAX(A, B)
	1100 A AND B (both A & B can be inverted, see below)
	1101 A OR B (both A & B can be inverted, see below)
	1110 A XOR B (both A & B can be inverted, see below)
	1111 A (A can be inverted, see below)
1	If logical operation:
	0 AA
	1 ANOT(A)
	If Adder operation:
	0 A is unsigned
	1 A is signed
1	If logical operation:
	0 BB
	1 BNOT(B)
	If Adder operation
	0 B is unsigned
	1 B is signed
4	Select A In1,In2,Out1,Out2,D0,D1,D2,D3,M,L,S,R,
	K1,K2,K3,K4
4	Select B In1,In2,Out1,Out2,D0,D1,D2,D3,M,L,S,R,
	K1,K2,K3,K4
14	TOTAL

[0527] Multiply/Interpolate 205

[0528] The Multiply/Interpolate process block is shown in more detail in FIG. 15 and is a set of four 88 interpolator units that are capable of performing four individual 88 interpolates per cycle, or can be combined to perform a single 1616 multiply. This gives the possibility to perform up to 4 linear interpolations, a single bi-linear interpolation, or half of a tri-linear interpolation in a single cycle. The result of the interpolations or multiplication is stored in the ALU 188's M register 209. There are two primary operands, A and B, which are selected from any of the general registers in the ALU 188 or from four programmable constants internal to the Multiply/Interpolate process block. Each interpolator block functions as a simple 8 bit interpolator resultA(BA)f or as a simple 88 multiply resultA*B. When the operation is interpolation, A and B are treated as four 8 bit numbers A₀ thru A₃ (A₀ is the low order byte), and B₀ thru B₃. Agen, Bgen, and Fgen are responsible for ordering the inputs to the Interpolate units so that they match the operation being performed. For example, to perform bilinear interpolation, each of the 4 values must be multiplied by a different factor & the result summed, while a 1616 bit multiplication requires the factors to be 0. The microcode for the Adder/Logic process block is described in the following table. Note that the interpretations of some bit patterns are deliberately chosen to aid decoding.

Bits	Description
4	0000 (A10 * B10) V
	0001 (A0 * B0) (A1 * B1) V
	0010 (A10 * B10) V
	0011 V (A10 * B10)
	0100 Interpolate A0,B0 by f0
	0101 Interpolate A0,B0 by f0, A1,B1 by f1
	0110 Interpolate A0,B0 by f0, A1,B1 by f1, A2,B2 by f2
	0111 Interpolate A0,B0 by f0, A1,B1 by f1, A2,
	B2 by f2, A3,B3 by f3
	1000 Interpolate 16 bits stage 1 M A10 * f10
	1001 Interpolate 16 bits stage 2 M M (A10 * f10)
	1010 Tri-linear interpolate A by f stage 1 MA0f0A1f1
	A2f2A3f3
	1011 Tri-linear interpolate A by f stage 2 MMA0f0A1f1
	A2f2A3f3
	1100 Bi-linear interpolate A by f stage 1 MA0f0A1f1
	1101 Bi-linear interpolate A by f stage 2 MMA0f0A1f1
	1110 Bi-linear interpolate A by f complete MA0f0
	A1f1A2f2A3f3
	1111 NOP
4	Select A In1,In2,Out1,Out2,D0,D1,D2,
	D3,M,L,S,R,K1,K2,K3,K4
4	Select B In1,In2,Out1,Out2,D0,D1,D2,
	D3,M,L,S,R,K1,K2,K3,K4
If
Mult:
4	Select V In1,In2,Out1,Out2,D0,D1,D2,D3,K1,
	K2,K3,K4,Adder result,M,0,1
1	Treat A as signed
1	Treat B as signed
1	Treat V as signed
If
Interp:
4	Select basis for f In1,In2,Out1,Out2,D0,D1,D2,D3,
	K1,K2,K3,K4,X,X,X,X
1	Select interpolation f generation from P1 or P2
	Pn is interpreted as fractional bits in f
	If Pn0, f is range 0 . . . 255 representing 0 . . . 1
2	Reserved
19	TOTAL

[0529] The same 4 bits are used for the selection of V and f, although the last 4 options for V don't generally make sense as f values. Interpolating with a factor of 1 or 0 is pointless, and the previous multiplication or current result is unlikely to be a meaningful value for f.

[0530] I/O Address Generators 189, 190

[0531] The I/O Address Generators are shown in more detail in FIG. 16. A VLIW process does not access DRAM directly. Access is via 2 I/O Address Generators 189, 190, each with its own Input and Output FIFO. A PU e.g 178 reads data from one of two local Input FIFOs, and writes data to one of two local Output FIFOs. Each I/O Address Generator is responsible for reading data from DRAM and placing it into its Input FIFO, where it can be read by the PU e.g 178, and is responsible for taking the data from its Output FIFO (placed there by the PU e.g 178) and writing it to DRAM. The I/O Address Generator is a state machine responsible for generating addresses and control for data retrieval and storage in DRAM via the Data cache 76. It is customizable under CPU software control, but cannot be microcoded. The address generator produces addresses in two broad categories:

[0532] Image Iterators, used to iterate (reading, writing or both) through pixels of an image in a variety of ways

[0533] Table I/O, used to randomly access pixels in images, data in tables, and to simulate FIFOs in DRAM

[0534] Each of the I/O Address Generators 189, 190 has its own bus connection to the Data cache 76, making 2 bus connections per PU e.g 178, and a total of 8 buses over the entire VLIW Vector Processor 74. The Data cache 76 is able to service 4 of the maximum 8 requests from the 4 PUs e.g 178 each cycle. The Input and Output FIFOs are 8 entry deep 16-bit wide FIFOs. The various types of address generation (Image Iterators and Table I/O) are described in the subsequent sections.

[0535] Registers

[0536] The I/O Address Generator has a set of registers for that are used to control address generation. The addressing mode also determines how the data is formatted and sent into the local Input FIFO, and how data is interpreted from the local Output FIFO. The CPU is able to access the registers of the I/O Address Generator via the low speed bus. The first set of registers define the housekeeping parameters for the I/O Generator:

Register Name	bits	Description
Reset	0	A write to this register halts any operations,
		and writes 0s to all the data registers
		of the I/O Generator. The input
		and output FIFOs are not cleared.
Go	0	A write to this register restarts the counters
		according to the current setup. For example,
		if the I/O Generator is a Read Iterator, and the
		Iterator is currently halfway through the image,
		a write to Go will cause the reading to begin
		at the start of the image again. While the I/O
		Generator is performing, the Active bit of the
		Status register will be set.
Halt	0	A write to this register stops any current
		activity and clears the Active bit of the Status
		register. If the Active bit is already cleared,
		writing to this register has no effect.
Continue	0	A write to this register continues the I/O
		Generator from the current
		setup. Counters are not reset, and
		FIFOs are not cleared. A write to this
		register while the I/O Generator is active has no
		effect.
ClearFIFOsOnGo	1	0 Don't clear FIFOs on a write to the Go bit.
		1 Do clear FIFOs on a write to the Go bit.
Status	8	Status flags

[0537] The Status register has the following values

	Register Name	bits	Description
	Active	1	0 Currently inactive
			1 Currently active
	Reserved	7

[0538] Caching

[0539] Several registers are used to control the caching mechanism, specifying which cache group to use for inputs, outputs etc. See the section on the Data cache 76 for more information about cache groups.

Register Name	bits	Description
CacheGroup1	4	Defines cache group to read data from
CacheGroup2	4	Defines which cache group to write data to, and
		in the case of the ImagePyramidLookup I/O
		mode, defines the cache to use for reading the
		Level Information Table.

[0540] Image IteratorsSequential Automatic Access to pixels

[0541] The primary image pixel access method for software and hardware algorithms is via Image Iterators. Image iterators perform all of the addressing and access to the caches of the pixels within an image channel and read, write or read & write pixels for their client. Read Iterators read pixels in a specific order for their clients, and Write Iterators write pixels in a specific order for their clients. Clients of Iterators read pixels from the local Input FIFO or write pixels via the local Output FIFO.

[0542] Read Image Iterators read through an image in a specific order, placing the pixel data into the local Input FIFO. Every time a client reads a pixel from the Input FIFO, the Read Iterator places the next pixel from the image (via the Data cache 76) into the FIFO.

[0543] Write Image Iterators write pixels in a specific order to write out the entire image. Clients write pixels to the Output FIFO that is in turn read by the Write Image Iterator and written to DRAM via the Data cache 76.

[0544] Typically a VLIW process will have its input tied to a Read Iterator, and output tied to a corresponding Write Iterator. From the PU e.g 178 microcode program's perspective, the FIFO is the effective interface to DRAM. The actual method of carrying out the storage (apart from the logical ordering of the data) is not of concern. Although the FIFO is perceived to be effectively unlimited in length, in practice the FIFO is of limited length, and there can be delays storing and retrieving data, especially if several memory accesses are competing. A variety of Image Iterators exist to cope with the most common addressing requirements of image processing algorithms. In most cases there is a corresponding Write Iterator for each Read Iterator. The different Iterators are listed in the following table:

	Read Iterators	Write Iterators
	Sequential Read	Sequential Write
	Box Read
	Vertical Strip Read	Vertical Strip Write

[0545] The 4 bit Address Mode Register is used to determine the Iterator type:

	Bit	Address Mode
	3	0 This addressing mode is an Iterator
	2 to 0	Iterator Mode
		001 Sequential Iterator
		010 Box read only
		100 Vertical Strip
		remaining bit patterns are reserved

[0546] The Access Specific registers are used as follows:

Register Name	LocalName	Description
AccessSpecific1	Flags	Flags used for reading and writing
AccessSpecific2	XBoxSize	Determines the size in X of Box Read.
		Valid values are 3, 5, and 7.
AccessSpecific3	YBoxSize	Determines the size in Y of Box Read.
		Valid values are 3, 5, and 7.
AccessSpecific4	BoxOffset	Offset between one pixel center and
		the next during a Box Read only.
		Usual value is 1, but other useful
		values include 2, 4, 8. . .
		See Box Read for more details.

[0547] The Flags register (AccessSpecific₁) contains a number of flags used to determine factors affecting the reading and writing of data. The Flags register has the following composition:

Label	bits	Description
ReadEnable	1	Read data from DRAM
WriteEnable	1	Write data to DRAM not valid for Box mode
PassX	1	Pass X (pixel) ordinate back to Input FIFO
PassY	1	Pass Y (row) ordinate back to Input FIFO
Loop	1	0 Do not loop through data
		1 Loop through data
Reserved	11	Must be 0

[0548] Notes on ReadEnable and WriteEnable:

[0549] When ReadEnable is set, the I/O Address Generator acts as a Read Iterator, and therefore reads the image in a particular order, placing the pixels into the Input FIFO.

[0550] When WriteEnable is set, the I/O Address Generator acts as a Write Iterator, and therefore writes the image in a particular order, taking the pixels from the Output FIFO.

[0551] When both ReadEnable and WriteEnable are set, the I/O Address Generator acts as a Read Iterator and as a Write Iterator, reading pixels into the Input FIFO, and writing pixels from the Output FIFO. Pixels are only written after they have been readi.e. the Write Iterator will never go faster than the Read Iterator. Whenever this mode is used, care should be taken to ensure balance between in and out processing by the VLIW microcode. Note that separate cache groups can be specified on reads and writes by loading different values in CacheGroup1 and CacheGroup2.

[0552] Notes on PassX and PassY:

[0553] If PassX and PassY are both set, the Y ordinate is placed into the Input FIFO before the X ordinate.

[0554] PassX and PassY are only intended to be set when the ReadEnable bit is clear. Instead of passing the ordinates to the address generator, the ordinates are placed directly into the Input FIFO. The ordinates advance as they are removed from the FIFO.

[0555] If WriteEnable bit is set, the VLIW program must ensure that it balances reads of ordinates from the Input FIFO with writes to the Output FIFO, as writes will only occur up to the ordinates (see note on ReadEnable and WriteEnable above).

[0556] Notes on Loop:

[0557] If the Loop bit is set, reads will recommence at StartPixel, StartRow once it has reached EndPixel, EndRow. This is ideal for processing a structure such a convolution kernel or a dither cell matrix, where the data must be read repeatedly.

[0558] Looping with ReadEnable and WriteEnable set can be useful in an environment keeping a single line history, but only where it is useful to have reading occur before writing. For a FIFO effect (where writing occurs before reading in a length constrained fashion), use an appropriate Table I/O addressing mode instead of an Image Iterator.

[0559] Looping with only WriteEnable set creates a written window of the last N pixels. This can be used with an asynchronous process that reads the data from the window. The Artcard Reading algorithm makes use of this mode.

[0560] Sequential Read and Write Iterators

[0561] FIG. 17 illustrates the pixel data format. The simplest Image Iterators are the Sequential Read Iterator and corresponding Sequential Write Iterator. The Sequential Read Iterator presents the pixels from a channel one line at a time from top to bottom, and within a line, pixels are presented left to right. The padding bytes are not presented to the client. It is most useful for algorithms that must perform some process on each pixel from an image but don't care about the order of the pixels being processed, or want the data specifically in this order. Complementing the Sequential Read Iterator is the Sequential Write Iterator. Clients write pixels to the Output FIFO. A Sequential Write Iterator subsequently writes out a valid image using appropriate caching and appropriate padding bytes. Each Sequential Iterator requires access to 2 cache lines. When reading, while 32 pixels are presented from one cache line, the other cache line can be loaded from memory. When writing, while 32 pixels are being filled up in one cache line, the other can be being written to memory.

[0562] A process that performs an operation on each pixel of an image independently would typically use a Sequential Read Iterator to obtain pixels, and a Sequential Write Iterator to write the new pixel values to their corresponding locations within the destination image. Such a process is shown in FIG. 18. In most cases, the source and destination images are different, and are represented by 2 I/O Address Generators 189, 190. However it can be valid to have the source image and destination image to be the same, since a given input pixel is not read more than once. In that case, then the same Iterator can be used for both input and output, with both the ReadEnable and WriteEnable registers set appropriately. For maximum efficiency, 2 different cache groups should be usedone for reading and the other for writing. If data is being created by a VLIW process to be written via a Sequential Write Iterator, the PassX and PassY flags can be used to generate coordinates that are then passed down the Input FIFO. The VLIW process can use these coordinates and create the output data appropriately.

[0563] Box Read Iterator

[0564] The Box Read Iterator is used to present pixels in an order most useful for performing operations such as general-purpose filters and convolve. The Iterator presents pixel values in a square box around the sequentially read pixels. The box is limited to being 1, 3, 5, or 7 pixels wide in X and Y (set XBoxSize and YBoxSizethey must be the same value or 1 in one dimension and 3, 5, or 7 in the other). The process is shown in FIG. 19:

[0565] BoxOffset: This special purpose register is used to determine a sub-sampling in terms of which input pixels will be used as the center of the box. The usual value is 1, which means that each pixel is used as the center of the box. The value 2 would be useful in scaling an image down by 4:1 as in the case of building an image pyramid. Using pixel addresses from the previous diagram, the box would be centered on pixel 0, then 2, 8, and 10. The Box Read Iterator requires access to a maximum of 14 (27) cache lines. While pixels are presented from one set of 7 lines, the other cache lines can be loaded from memory.

[0566] Box Write Iterator

[0567] There is no corresponding Box Write Iterator, since the duplication of pixels is only required on input. A process that uses the Box Read Iterator for input would most likely use the Sequential Write Iterator for output since they are in sync. A good example is the convolver, where N input pixels are read to calculate 1 output pixel. The process flow is as illustrated in FIG. 20. The source and destination images should not occupy the same memory when using a Box Read Iterator, as subsequent lines of an image require the original (not newly calculated) values.

[0568] Vertical-Strip Read and Write Iterators

[0569] In some instances it is necessary to write an image in output pixel order, but there is no knowledge about the direction of coherence in input pixels in relation to output pixels. An example of this is rotation. If an image is rotated 90 degrees, and we process the output pixels horizontally, there is a complete loss of cache coherence. On the other hand, if we process the output image one cache line's width of pixels at a time and then advance to the next line (rather than advance to the next cache-line's worth of pixels on the same line), we will gain cache coherence for our input image pixels. It can also be the case that there is known block coherence in the input pixels (such as color coherence), in which case the read governs the processing order, and the write, to be synchronized, must follow the same pixel order.

[0570] The order of pixels presented as input (Vertical-Strip Read), or expected for output (Vertical-Strip Write) is the same. The order is pixels 0 to 31 from line 0, then pixels 0 to 31 of line 1 etc for all lines of the image, then pixels 32 to 63 of line 0, pixels 32 to 63 of line 1 etc. In the final vertical strip there may not be exactly 32 pixels wide. In this case only the actual pixels in the image are presented or expected as input. This process is illustrated in FIG. 21.

[0571] process that requires only a Vertical-Strip Write Iterator will typically have a way of mapping input pixel coordinates given an output pixel coordinate. It would access the input image pixels according to this mapping, and coherence is determined by having sufficient cache lines on the random-access reader for the input image. The coordinates will typically be generated by setting the PassX and PassY flags on the VerticalStripWrite Iterator, as shown in the process overview illustrated in FIG. 22.

[0572] It is not meaningful to pair a Write Iterator with a Sequential Read Iterator or a Box read Iterator, but a Vertical-Strip Write Iterator does give significant improvements in performance when there is a non trivial mapping between input and output coordinates.

[0573] It can be meaningful to pair a Vertical Strip Read Iterator and Vertical Strip Write Iterator. In this case it is possible to assign both to a single ALU 188 if input and output images are the same. If coordinates are required, a further Iterator must be used with PassX and PassY flags set. The Vertical Strip Read/Write Iterator presents pixels to the Input FIFO, and accepts output pixels from the Output FIFO. Appropriate padding bytes will be inserted on the write. Input and output require a minimum of 2 cache lines each for good performance.

[0574] Table I/O Addressing Modes

[0575] It is often necessary to lookup values in a table (such as an image). Table I/O addressing modes provide this functionality, requiring the client to place the index/es into the Output FIFO. The I/O Address Generator then processes the index/es, looks up the data appropriately, and returns the looked-up values in the Input FIFO for subsequent processing by the VLIW client.

[0576] 1D, 2D and 3D tables are supported, with particular modes targeted at interpolation. To reduce complexity on the VLIW client side, the index values are treated as fixed-point numbers, with AccessSpecific registers defining the fixed point and therefore which bits should be treated as the integer portion of the index. Data formats are restricted forms of the general Image Characteristics in that the PixelOffset register is ignored, the data is assumed to be contiguous within a row, and can only be 8 or 16 bits (1 or 2 bytes) per data element. The 4 bit Address Mode Register is used to determine the I/O type:

	Bit	Address Mode
	3	1 This addressing mode is Table I/O
	2 to 0	000 1D Direct Lookup
		001 1D Interpolate (linear)
		010 DRAM FIFO
		011 Reserved
		100 2D Interpolate (bi-linear)
		101 Reserved
		110 3D Interpolate (tri-linear)
		111 Image Pyramid Lookup

[0577] The access specific registers are:

Register Name	LocalName	bits	Description
AccessSpecific1	Flags	8	General flags for reading
			and writing. See below
			for more information.
AccessSpecific2	FractX	8	Number of fractional bits
			in X index
AccessSpecific3	FractY	8	Number of fractional bits
			in Y index
AccessSpecific4	FractZ	8	Number of fractional bits
			in Z index
(low 8 bits/next	ZOffset	12 or 24	See below
12 or 24 bits))

[0578] FractX, FractY, and FractZ are used to generate addresses based on indexes, and interpret the format of the index in terms of significant bits and integer/fractional components. The various parameters are only defined as required by the number of dimensions in the table being indexed. A 1D table only needs FractX, a 2D table requires FractX and FractY. Each Fract_value consists of the number of fractional bits in the corresponding index. For example, an X index may be in the format 5:3. This would indicate 5 bits of integer, and 3 bits of fraction. FractX would therefore be set to 3. A simple ID lookup could have the format 8:0, i.e. no fractional component at all. FractX would therefore be 0. ZOffset is only required for 3D lookup and takes on two different interpretations. It is described more fully in the 3D-table lookup section. The Flags register (AccessSpecific₁) contains a number of flags used to determine factors affecting the reading (and in one case, writing) of data. The Flags register has the following composition:

Label	bits	Description
ReadEnable	1	Read data from DRAM
WriteEnable	1	Write data to DRAM only valid for 1D direct
		lookup
DataSize	1	0 8 bit data
		1 16 bit data
Reserved	5	Must be 0

[0579] With the exception of the ID Direct Lookup and DRAM FIFO, all Table I/O modes only support reading, and not writing. Therefore the ReadEnable bit will be set and the WriteEnable bit will be clear for all I/O modes other than these two modes. The ID Direct Lookup supports 3 modes:

[0580] Read only, where the ReadEnable bit is set and the WriteEnable bit is clear

[0581] Write only, where the ReadEnable bit is clear and the WriteEnable bit is clear

[0582] Read-Modify-Write, where both ReadEnable and the WriteEnable bits are set

[0583] The different modes are described in the ID Direct Lookup section below. The DRAM FIFO mode supports only 1 mode:

[0584] Write-Read mode, where both ReadEnable and the WriteEnable bits are set

[0585] This mode is described in the DRAM FIFO section below. The DataSize flag determines whether the size of each data elements of the table is 8 or 16 bits. Only the two data sizes are supported. 32 bit elements can be created in either of 2 ways depending on the requirements of the process:

[0586] Reading from 2 16-bit tables simultaneously and combining the result. This is convenient if timing is an issue, but has the disadvantage of consuming 2 I/O Address Generators 189, 190, and each 32-bit element is not readable by the CPU as a 32-bit entity.

[0587] Reading from a 16-bit table twice and combining the result. This is convenient since only 1 lookup is used, although different indexes must be generated and passed into the lookup.

[0588] 1 Dimensional Structures

[0589] Direct Lookup

[0590] A direct lookup is a simple indexing into a 1 dimensional lookup table. Clients can choose between 3 access modes by setting appropriate bits in the Flags register:

[0591] Read only

[0592] Write only

[0593] Read-Modify-Write

[0594] Read Only

[0595] A client passes the fixed-point index X into the Output FIFO, and the 8 or 16-bit value at TableInt(X) is returned in the Input FIFO. The fractional component of the index is completely ignored. If the index is out of bounds, the DuplicateEdge flag determines whether the edge pixel or ConstantPixel is returned. The address generation is straightforward:

[0596] If DataSize indicates 8 bits, X is barrel-shifted right FractX bits, and the result is added to the table's base address ImageStart.

[0597] If DataSize indicates 16 bits, X is barrel-shifted right FractX bits, and the result shifted left 1 bit (bit0 becomes 0) is added to the table's base address ImageStart.

[0598] The 8 or 16-bit data value at the resultant address is placed into the Input FIFO. Address generation takes 1 cycle, and transferring the requested data from the cache to the Output FIFO also takes 1 cycle (assuming a cache hit). For example, assume we are looking up values in a 256-entry table, where each entry is 16 bits, and the index is a 12 bit fixed-point format of 8:4. FractX should be 4, and DataSize 1. When an index is passed to the lookup, we shift right 4 bits, then add the result shifted left 1 bit to ImageStart.

[0599] Write Only

[0600] A client passes the fixed-point index X into the Output FIFO followed by the 8 or 16-bit value that is to be written to the specified location in the table. A complete transfer takes a minimum of 2 cycles. 1 cycle for address generation, and 1 cycle to transfer the data from the FIFO to DRAM. There can be an arbitrary number of cycles between a VLIW process placing the index into the FIFO and placing the value to be written into the FIFO. Address generation occurs in the same way as Read Only mode, but instead of the data being read from the address, the data from the Output FIFO is written to the address. If the address is outside the table range, the data is removed from the FIFO but not written to DRAM.

[0601] Read-Modify-Write

[0602] A client passes the fixed-point index X into the Output FIFO, and the 8 or 16-bit value at TableInt(X) is returned in the Input FIFO. The next value placed into the Output FIFO is then written to TableInt(X), replacing the value that had been returned earlier. The general processing loop then, is that a process reads from a location, modifies the value, and writes it back. The overall time is 4 cycles:

[0603] Generate address from index

[0604] Return value from table

[0605] Modify value in some way

[0606] Write it back to the table

[0607] There is no specific read/write mode where a client passes in a flag saying read from X or write to X. Clients can simulate a read from X by writing the original value, and a write to X by simply ignoring the returned value. However such use of the mode is not encouraged since each action consumes a minimum of 3 cycles (the modify is not required) and 2 data accesses instead of 1 access as provided by the specific Read and Write modes.

[0608] Interpolate Table

[0609] This is the same as a Direct Lookup in Read mode except that two values are returned for a given fixed-point index X instead of one. The values returned are TableInt(X), and TableInt(X)1. If either index is out of bounds the DuplicateEdge flag determines whether the edge pixel or ConstantPixel is returned. Address generation is the same as Direct Lookup, with the exception that the second address is simply Address 11 or 2 depending on 8 or 16 bit data. Transferring the requested data to the Output FIFO takes 2 cycles (assuming a cache hit), although two 8-bit values may actually be returned from the cache to the Address Generator in a single 16-bit fetch.

[0610] DRAM FIFO

[0611] A special case of a read/write ID table is a DRAM FIFO. It is often necessary to have a simulated FIFO of a given length using DRAM and associated caches. With a DRAM FIFO, clients do not index explicitly into the table, but write to the Output FIFO as if it was one end of a FIFO and read from the Input FIFO as if it was the other end of the same logical FIFO. 2 counters keep track of input and output positions in the simulated FIFO, and cache to DRAM as needed. Clients need to set both ReadEnable and WriteEnable bits in the Flags register.

[0612] An example use of a DRAM FIFO is keeping a single line history of some value. The initial history is written before processing begins. As the general process goes through a line, the previous line's value is retrieved from the FIFO, and this line's value is placed into the FIFO (this line will be the previous line when we process the next line). So long as input and outputs match each other on average, the Output FIFO should always be full. Consequently there is effectively no access delay for this kind of FIFO (unless the total FIFO length is very smallsay 3 or 4 bytes, but that would defeat the purpose of the FIFO).

[0613] 2 Dimensional Tables

[0614] Direct Lookup

[0615] A 2 dimensional direct lookup is not supported. Since all cases of 2D lookups are expected to be accessed for bi-linear interpolation, a special bi-linear lookup has been implemented.

[0616] Bi-Linear Lookup

[0617] This kind of lookup is necessary for bi-linear interpolation of data from a 2D table. Given fixed-point X and Y coordinates (placed into the Output FIFO in the order Y, X), 4 values are returned after lookup. The values (in order) are:

[0618] TableInt(X), Int(Y)

[0619] TableInt(X)1, Int(Y)

[0620] TableInt(X), Int(Y)1

[0621] TableInt(X)1, Int(Y)1

[0622] The order of values returned gives the best cache coherence. If the data is 8-bit, 2 values are returned each cycle over 2 cycles with the low order byte being the first data element. If the data is 16-bit, the 4 values are returned in 4 cycles, 1 entry per cycle. Address generation takes 2 cycles. The first cycle has the index (Y) barrel-shifted right FractY bits being multiplied by RowOffset, with the result added to ImageStart. The second cycle shifts the X index right by FractX bits, and then either the result (in the case of 8 bit data) or the result shifted left 1 bit (in the case of 16 bit data) is added to the result from the first cycle. This gives us address Adraddress of TableInt(X), Int(Y): $\begin{array}{c}\mathrm{Adr}=\mathrm{ImageStart}+\\ \mathrm{ShiftRight}\left(Y,\mathrm{FractY}\right)*\mathrm{RowOffset})+\\ \mathrm{ShiftRight}\left(X,\mathrm{FractX}\right)\end{array}$

[0623] We keep a copy of Adr in AdrOld for use fetching subsequent entries.

[0624] If the data is 8 bits, the timing is 2 cycles of address generation, followed by 2 cycles of data being returned (2 table entries per cycle).

[0625] If the data is 16 bits, the timing is 2 cycles of address generation, followed by 4 cycles of data being returned (1 entry per cycle)

[0626] The following 2 tables show the method of address calculation for 8 and 16 bit data sizes:

Cycle	Calculation while fetching 2 8-bit data entries from Adr
1	Adr Adr RowOffset
2	<preparing next lookup>
Cycle	Calculation while fetching 1 16-bit data entry from Adr
1	Adr Adr 2
2	Adr AdrOld RowOffset
3	Adr Adr 2
4	<preparing next lookup>

[0627] In both cases, the first cycle of address generation can overlap the insertion of the X index into the FIFO, so the effective timing can be as low as 1 cycle for address generation, and 4 cycles of return data. If the generation of indexes is 2 steps ahead of the results, then there is no effective address generation time, and the data is simply produced at the appropriate rate (2 or 4 cycles per set).

[0628] 3 Dimensional Lookup

[0629] Direct Lookup

[0630] Since all cases of 2D lookups are expected to be accessed for tri-linear interpolation, two special tri-linear lookups have been implemented. The first is a straightforward lookup table, while the second is for tri-linear interpolation from an Image Pyramid.

[0631] Tri-Linear Lookup

[0632] This type of lookup is useful for 3D tables of data, such as color conversion tables. The standard image parameters define a single XY plane of the datai.e. each plane consists of ImageHeight rows, each row containing RowOffset bytes. In most circumstances, assuming contiguous planes, one XY plane will be ImageHeight x RowOffset bytes after another. Rather than assume or calculate this offset, the software via the CPU must provide it in the form of a 12-bit ZOffset register. In this form of lookup, given 3 fixed-point indexes in the order Z, Y, X, 8 values are returned in order from the lookup table:

[0633] TableInt(X), Int(Y), Int(Z)

[0634] TableInt(X)1, Int(Y), Int(Z)

[0635] TableInt(X), Int(Y)1, Int(Z)

[0636] TableInt(X)1, Int(Y)1, Int(Z)

[0637] TableInt(X), Int(Y), Int(Z)1

[0638] TableInt(X)1, Int(Y), Int(Z)1

[0639] TableInt(X), Int(Y)1, Int(Z)1

[0640] TableInt(X)1, Int(Y)1, Int(Z)1

[0641] The order of values returned gives the best cache coherence. If the data is 8-bit, 2 values are returned each cycle over 4 cycles with the low order byte being the first data element. If the data is 16-bit, the 4 values are returned in 8 cycles, 1 entry per cycle. Address generation takes 3 cycles. The first cycle has the index (Z) barrel-shifted right FractZ bits being multiplied by the 12-bit ZOffset and added to ImageStart. The second cycle has the index (Y) barrel-shifted right FractY bits being multiplied by RowOffset, with the result added to the result of the previous cycle. The second cycle shifts the X index right by FractX bits, and then either the result (in the case of 8 bit data) or the result shifted left 1 bit (in the case of 16 bit data) is added to the result from the second cycle. This gives us address Adraddress of TableInt(X), Int(Y), Int(Z): $\begin{array}{c}\mathrm{Adr}=\mathrm{ImageStart}+\\ \left(\mathrm{ShiftRight}\left(Z,\mathrm{FractZ}\right)*\mathrm{ZOffset}\right)+\\ \left(\mathrm{ShiftRight}\left(Y,\mathrm{FractY}\right)*\mathrm{RowOffset}\right)+\\ \mathrm{ShiftRight}\left(X,\mathrm{FractX}\right)\end{array}$

[0642] We keep a copy of Adr in AdrOld for use fetching subsequent entries.

[0643] If the data is 8 bits, the timing is 2 cycles of address generation, followed by 2 cycles of data being returned (2 table entries per cycle).

[0644] If the data is 16 bits, the timing is 2 cycles of address generation, followed by 4 cycles of data being returned (1 entry per cycle)

[0645] The following 2 tables show the method of address calculation for 8 and 16 bit data sizes:

Cycle	Calculation while fetching 2 8-bit data entries from Adr
1	Adr Adr RowOffset
2	Adr AdrOld ZOffset
3	Adr Adr RowOffset
4	<preparing next lookup>
Cycle	Calculation while fetching 1 16-bit data entries from Adr
1	Adr Adr 2
2	Adr AdrOld RowOffset
3	Adr Adr 2
4	Adr, AdrOld AdrOld Zoffset
5	Adr Adr 2
6	Adr AdrOld RowOffset
7	Adr Adr 2
8	<preparing next lookup>

[0646] In both cases, the cycles of address generation can overlap the insertion of the indexes into the FIFO, so the effective timing for a single one-off lookup can be as low as 1 cycle for address generation, and 4 cycles of return data. If the generation of indexes is 2 steps ahead of the results, then there is no effective address generation time, and the data is simply produced at the appropriate rate (4 or 8 cycles per set).

[0647] Image Pyramid Lookup

[0648] During brushing, tiling, and warping it is necessary to compute the average color of a particular area in an image. Rather than calculate the value for each area given, these functions make use of an image pyramid.

[0649] The description and construction of an image pyramid is detailed in the section on Internal Image Formats in the DRAM interface 81 chapter of this document. This section is concerned with a method of addressing given pixels in the pyramid in terms of 3 fixed-point indexes ordered: level (Z), Y, and X. Note that Image Pyramid lookup assumes 8 bit data entries, so the DataSize flag is completely ignored. After specification of Z, Y, and X, the following 8 pixels are returned via the Input FIFO:

[0650] The pixel at Int(X), Int(Y), level Int(Z)

[0651] The pixel at Int(X)1, Int(Y), level Int(Z)

[0652] The pixel at Int(X), Int(Y)1, level Int(Z)

[0653] The pixel at Int(X)1, Int(Y)1, level Int(Z)

[0654] The pixel at Int(X), Int(Y), level Int(Z)1

[0655] The pixel at Int(X)1, Int(Y), level Int(Z)1

[0656] The pixel at Int(X), Int(Y)1, level Int(Z)1

[0657] The pixel at Int(X)1, Int(Y)1, level Int(Z)1

[0658] The 8 pixels are returned as 416 bit entries, with X and X1 entries combined hi/lo. For example, if the scaled (X, Y) coordinate was (10.4, 12.7) the first 4 pixels returned would be: (10, 12), (11, 12), (10, 13) and (11, 13). When a coordinate is outside the valid range, clients have the choice of edge pixel duplication or returning of a constant color value via the DuplicateEdgePixels and ConstantPixel registers (only the low 8 bits are used). When the Image Pyramid has been constructed, there is a simple mapping from level 0 coordinates to level Z coordinates. The method is simply to shift the X or Y coordinate right by Z bits. This must be done in addition to the number of bits already shifted to retrieve the integer portion of the coordinate (i.e. shifting right FractX and FractY bits for X and Y ordinates respectively). To find the ImageStart and RowOffset value for a given level of the image pyramid, the 24-bit ZOffset register is used as a pointer to a Level Information Table. The table is an array of records, each representing a given level of the pyramid, ordered by level number. Each record consists of a 16-bit offset ZOffset from ImageStart to that level of the pyramid (64-byte aligned address as lower 6 bits of the offset are not present), and a 12 bit ZRowOffset for that level. Element 0 of the table would contain a ZOffset of 0, and a ZRowOffset equal to the general register RowOffset, as it simply points to the full sized image. The ZOffset value at element N of the table should be added to ImageStart to yield the effective ImageStart of level N of the image pyramid. The RowOffset value in element N of the table contains the RowOffset value for level N. The software running on the CPU must set up the table appropriately before using this addressing mode. The actual address generation is outlined here in a cycle by cycle description:

	Load	From
Cycle	Register	Address	Other Operations
0			ZAdr ShiftRight(Z, FractZ) ZOffset
			ZInt ShiftRight(Z, FractZ)
1	ZOffset	Zadr	ZAdr 2
			YInt ShiftRight(Y, FractY)
2	ZRowOffset	ZAdr	ZAdr 2
			YInt ShiftRight(YInt, ZInt)
			Adr ZOffset ImageStart
3	ZOffset	ZAdr	ZAdr 2
			Adr ZrowOffset * YInt
			XInt ShiftRight(X, FractX)
4	ZAdr	ZAdr	Adr ShiftRight(XInt, ZInt)
			ZOffset ShiftRight(XInt, 1)
5	FIFO	Adr	Adr ZrowOffset
			ZOffset ImageStart
6	FIFO	Adr	Adr (ZAdr * ShiftRight(Yint, 1))
			ZOffset
7	FIFO	Adr	Adr Zadr
8	FIFO	Adr	<Cycle 0 for next retrieval>

[0659] The address generation as described can be achieved using a single Barrel Shifter, 2 adders, and a single 1616 multiply/add unit yielding 24 bits. Although some cycles have 2 shifts, they are either the same shift value (i.e. the output of the Barrel Shifter is used two times) or the shift is 1 bit, and can be hard wired. The following internal registers are required: ZAdr, Adr, ZInt, YInt, XInt, ZRowOffset, and ZImageStart. The _Int registers only need to be 8 bits maximum, while the others can be up to 24 bits. Since this access method only reads from, and does not write to image pyramids, the CacheGroup2 is used to lookup the Image Pyramid Address Table (via ZAdr). CacheGroup1 is used for lookups to the image pyramid itself (via Adr). The address table is around 22 entries (depending on original image size), each of 4 bytes. Therefore 3 or 4 cache lines should be allocated to CacheGroup2, while as many cache lines as possible should be allocated to CacheGroup1. The timing is 8 cycles for returning a set of data, assuming that Cycle 8 and Cycle 0 overlap in operationi.e. the next request's Cycle 0 occurs during Cycle 8. This is acceptable since Cycle 0 has no memory access, and Cycle 8 has no specific operations.

[0660] Generation Of Coordinates Using VLIW Vector Processor 74

[0661] Some functions that are linked to Write Iterators require the X and/or Y coordinates of the current pixel being processed in part of the processing pipeline. Particular processing may also need to take place at the end of each row, or column being processed. In most cases, the PassX and PassY flags should be sufficient to completely generate all coordinates. However, if there are special requirements, the following functions can be used. The calculation can be spread over a number of ALUs, for a single cycle generation, or be in a single ALU 188 for a multi-cycle generation.

[0662] Generate Sequential X, Y

[0663] When a process is processing pixels in sequential order according to the Sequential Read Iterator (or generating pixels and writing them out to a Sequential Write Iterator), the following process can be used to generate X, Y coordinates instead of PassX/PassY flags as shown in FIG. 23. The coordinate generator counts up to ImageWidth in the X ordinate, and once per ImageWidth pixels increments the Y ordinate. The actual process is illustrated in FIG. 24, where the following constants are set by software:

	Constant	Value
	K1	ImageWidth
	K2	ImageHeight (optional)

[0664] The following registers are used to hold temporary variables:

	Variable	Value
	Reg1	X (starts at 0 each line)
	Reg2	Y (starts at 0)

[0665] The requirements are summarized as follows:

	Requirements	*		R	K	LU	Iterators
	General	0	3/4	2	1/2	0	0
	TOTAL	0	3/4	2	1/2	0	0

[0666] Generate Vertical Strip X,Y

[0667] When a process is processing pixels in order to write them to a Vertical Strip Write Iterator, and for some reason cannot use the PassX/PassY flags, the process as illustrated in FIG. 25 can be used to generate X, Y coordinates. The coordinate generator simply counts up to ImageWidth in the X ordinate, and once per ImageWidth pixels increments the Y ordinate. The actual process is illustrated in FIG. 26, where the following constants are set by software:

	Constant	Value
	K1	32
	K2	ImageWidth
	K3	ImageHeight

[0668] The following registers are used to hold temporary variables:

	Variable	Value
	Reg1	StartX (starts at 0, and is incremented
		by 32 once per vertical strip)
	Reg2	X
	Reg3	EndX (starts at 32 and is incremented
		by 32 to a maximum of ImageWidth) once
		per vertical strip)
	Reg4	Y

[0669] The requirements are summarized as follows:

	Requirements	*		R	K	LU	Iterators
	General	0	4	4	3	0	0
	TOTAL	0	4	4	3	0	0

[0670] The calculations that occur once per vertical strip (2 additions, one of which has an associated MIN) are not included in the general timing statistics because they are not really part of the per pixel timing. However they do need to be taken into account for the programming of the microcode for the particular function.

[0671] Image Sensor Interface (ISI 83)

[0672] The Image Sensor Interface (ISI 83) takes data from the CMOS Image Sensor and makes it available for storage in DRAM. The image sensor has an aspect ratio of 3:2, with a typical resolution of 750500 samples, yielding 375K (8 bits per pixel). Each 22 pixel block has the configuration as shown in FIG. 27. The ISI 83 is a state machine that sends control information to the Image Sensor, including frame sync pulses and pixel clock pulses in order to read the image. Pixels are read from the image sensor and placed into the VLIW Input FIFO 78. The VLIW is then able to process and/or store the pixels. This is illustrated further in FIG. 28. The ISI 83 is used in conjunction with a VLIW program that stores the sensed Photo Image in DRAM. Processing occurs in 2 steps:

[0673] A small VLIW program reads the pixels from the FIFO and writes them to DRAM via a Sequential Write Iterator.

[0674] The Photo Image in DRAM is rotated 90, 180 or 270 degrees according to the orientation of the camera when the photo was taken.

[0675] If the rotation is 0 degrees, then step 1 merely writes the Photo Image out to the final Photo Image location and step 2 is not performed. If the rotation is other than 0 degrees, the image is written out to a temporary area (for example into the Print Image memory area), and then rotated during step 2 into the final Photo Image location. Step 1 is very simple microcode, taking data from the VLIW Input FIFO 78 and writing it to a Sequential Write Iterator. Step 2's rotation is accomplished by using the accelerated Vark Affine Transform function. The processing is performed in 2 steps in order to reduce design complexity and to re-use the Vark affine transform rotate logic already required for images. This is acceptable since both steps are completed in approximately 0.03 seconds, a time imperceptible to the operator of the Artcam. Even so, the read process is sensor speed bound, taking 0.02 seconds to read the full frame, and approximately 0.01 seconds to rotate the image.

[0676] The orientation is important for converting between the sensed Photo Image and the internal format image, since the relative positioning of R, G, and B pixels changes with orientation. The processed image may also have to be rotated during the Print process in order to be in the correct orientation for printing. The 3D model of the Artcam has 2 image sensors, with their inputs multiplexed to a single ISI 83 (different microcode, but same ACP 31). Since each sensor is a frame store, both images can be taken simultaneously, and then transferred to memory one at a time.

[0677] Display Controller 88

[0678] When the Take button on an Artcam is half depressed, the TFT will display the current image from the image sensor (converted via a simple VLIW process). Once the Take button is fully depressed, the Taken Image is displayed. When the user presses the Print button and image processing begins, the TFT is turned off. Once the image has been printed the TFT is turned on again. The Display Controller 88 is used in those Artcam models that incorporate a flat panel display. An example display is a TFT LCD of resolution 240160 pixels. The structure of the Display Controller 88 isl illustrated in FIG. 29. The Display Controller 88 State Machine contains registers that control the timing of the Sync Generation, where the display image is to be taken from (in DRAM via the Data cache 76 via a specific Cache Group), and whether the TFT should be active or not (via TFT Enable) at the moment. The CPU can write to these registers via the low speed bus. Displaying a 240160 pixel image on an RGB TFT requires 3 components per pixel. The image taken from DRAM is displayed via 3 DACs, one for each of the R, G, and B output signals. At an image refresh rate of 30 frames per second (60 fields per second) the Display Controller 88 requires data transfer rates of:

[0679] 2401603303.5 MB per second

[0680] This data rate is low compared to the rest of the system. However it is high enough to cause VLIW programs to slow down during the intensive image processing. The general principles of TFT operation should reflect this.

[0681] Image Data Formats

[0682] As stated previously, the DRAM Interface 81 is responsible for interfacing between other client portions of the ACP chip and the RAMBUS DRAM. In effect, each module within the DRAM Interface is an address generator.

[0683] There are three logical types of images manipulated by the ACP. They are:

[0684] CCD Image, which is the Input Image captured from the CCD.

[0685] Internal Image formatthe Image format utilised internally by the Artcam device.

[0686] Print Imagethe Output Image format printed by the Artcam

[0687] These images are typically different in color space, resolution, and the output & input color spaces which can vary from camera to camera. For example, a CCD image on a low-end camera may be a different resolution, or have different color characteristics from that used in a high-end camera. However all internal image formats are the same format in terms of color space across all cameras.

[0688] In addition, the three image types can vary with respect to which direction is up. The physical orientation of the camera causes the notion of a portrait or landscape image, and this must be maintained throughout processing. For this reason, the internal image is always oriented correctly, and rotation is performed on images obtained from the CCD and during the print operation.

[0689] CCD Image Organization

[0690] Although many different CCD image sensors could be utilised, it will be assumed that the CCD itself is a 750500 image sensor, yielding 375,000 bytes (8 bits per pixel). Each 22 pixel block having the configuration as depicted in FIG. 30.

[0691] A CCD Image as stored in DRAM has consecutive pixels with a given line contiguous in memory. Each line is stored one after the other. The image sensor Interface 83 is responsible for taking data from the CCD and storing it in the DRAM correctly oriented. Thus a CCD image with rotation 0 degrees has its first line G, R, G, R, G, R . . . and its second line as B, G, B, G, B, G . . . If the CCD image should be portrait, rotated 90 degrees, the first line will be R, G, R, G, R, G and the second line G, B, G, B, G, B . . . etc.

[0692] Pixels are stored in an interleaved fashion since all color components are required in order to convert to the internal image format.

[0693] It should be noted that the ACP 31 makes no assumptions about the CCD pixel format, since the actual CCDs for imaging may vary from Artcam to Artcam, and over time. All processing that takes place via the hardware is controlled by major microcode in an attempt to extend the usefulness of the ACP 31.

[0694] Internal Image Organization

[0695] Internal images typically consist of a number of channels. Vark images can include, but are not limited to:

[0696] Lab

[0697] Lab

[0698] Lab

[0699]

[0700] L

[0701] L, a and b correspond to components of the Lab color space, is a matte channel (used for compositing), and is a bump-map channel (used during brushing, tiling and illuminating).

[0702] The VLIW processor 74 requires images to be organized in a planar configuration. Thus a Lab image would be stored as 3 separate blocks of memory:

[0703] one block for the L channel,

[0704] one block for the a channel, and

[0705] one block for the b channel

[0706] Within each channel block, pixels are stored contiguously for a given row (plus some optional padding bytes), and rows are stored one after the other.

[0707] Turning to FIG. 31 there is illustrated an example form of storage of a logical image 100. The logical image 100 is stored in a planar fashion having L 101, a 102 and b 103 color components stored one after another. Alternatively, the logical image 100 can be stored in a compressed format having an uncompressed L component 101 and compressed A and B components 105, 106.

[0708] Turning to FIG. 32, the pixels of for line n 110 are stored together before the pixels of for line and n1 (111). With the image being stored in contiguous memory within a single channel.

[0709] In the 8 MB-memory model, the final Print Image after all processing is finished, needs to be compressed in the chrominance channels. Compression of chrominance channels can be 4:1, causing an overall compression of 12:6, or 2:1.

[0710] Other than the final Print Image, images in the Artcam are typically not compressed. Because of memory constraints, software may choose to compress the final Print Image in the chrominance channels by scaling each of these channels by 2:1. If this has been done, the PRINT Vark function call utilised to print an image must be told to treat the specified chrominance channels as compressed. The PRINT function is the only function that knows how to deal with compressed chrominance, and even so, it only deals with a fixed 2:1 compression ratio.

[0711] Although it is possible to compress an image and then operate on the compressed image to create the final print image, it is not recommended due to a loss in resolution. In addition, an image should only be compressed onceas the final stage before printout. While one compression is virtually undetectable, multiple compressions may cause substantial image degradation.

[0712] Clip Image Organization

[0713] Clip images stored on Artcards have no explicit support by the ACP 31. Software is responsible for taking any images from the current Artcard and organizing the data into a form known by the ACP. If images are stored compressed on an Artcard, software is responsible for decompressing them, as there is no specific hardware support for decompression of Artcard images.

[0714] Image Pyramid Organization

[0715] During brushing, tiling, and warping processes utilised to manipulate an image it is often necessary to compute the average color of a particular area in an image. Rather than calculate the value for each area given, these functions make use of an image pyramid. As illustrated in FIG. 33, an image pyramid is effectively a multi-resolutionpixel-map. The original image 115 is a 1:1 representation. Low-pass filtering and sub-sampling by 2:1 in each dimension produces an image the original size 116. This process continues until the entire image is represented by a single pixel. An image pyramid is constructed from an original internal format image, and consumes of the size taken up by the original image ({fraction (1/16)}{fraction (1/64)}. . . ). For an original image of 15001000 the corresponding image pyramid is approximately MB. An image pyramid is constructed by a specific Vark function, and is used as a parameter to other Vark functions.

[0716] Print Image Organization

[0717] The entire processed image is required at the same time in order to print it. However the Print Image output can comprise a CMY dithered image and is only a transient image format, used within the Print Image functionality. However, it should be noted that color conversion will need to take place from the internal color space to the print color space. In addition, color conversion can be tuned to be different for different print rolls in the camera with different ink characteristics e.g. Sepia output can be accomplished by using a specific sepia toning Artcard, or by using a sepia tone print-roll (so all Artcards will work in sepia tone).

[0718] Color Spaces

[0719] As noted previously there are 3 color spaces used in the Artcam, corresponding to the different image types.

[0720] The ACP has no direct knowledge of specific color spaces. Instead, it relies on client color space conversion tables to convert between CCD, internal, and printer color spaces:

[0721] CCD:RGB

[0722] Internal:Lab

[0723] Printer:CMY

[0724] Removing the color space conversion from the ACP 31 allows:

[0725] Different CCDs to be used in different cameras

[0726] Different inks (in different print rolls over time) to be used in the same camera

[0727] Separation of CCD selection from ACP design path

[0728] A well defined internal color space for accurate color processing

[0729] Artcard Interface 87

[0730] The Artcard Interface (AI) takes data from the linear image Sensor while an Artcard is passing under it, and makes that data available for storage in DRAM. The image sensor produces 11,000 8-bit samples per scanline, sampling the Artcard at 4800 dpi. The AI is a state machine that sends control information to the linear sensor, including LineSync pulses and PixelClock pulses in order to read the image. Pixels are read from the linear sensor and placed into the VLIW Input FIFO 78. The VLIW is then able to process and/or store the pixels. The AI has only a few registers:

Register Name	Description
NumPixels	The number of pixels in a sensor line (approx 11,000)
Status	The Print Head Interface's Status Register
PixelsRemaining	The number of bytes remaining in the current line
Actions
Reset	A write to this register resets the AI, stops any
	scanning, and loads all registers with 0.
Scan	A write to this register with a non-zero value sets
	the Scanning bit of the Status register, and causes
	the Artcard Interface Scan cycle to start.
	A write to this register with 0 stops the scanning
	process and clears the Scanning bit in the Status
	register.
	The Scan cycle causes the AL to transfer NumPixels
	bytes from the sensor to the VLIW Input FIFO 78,
	producing the PixelClock signals appropriately.
	Upon completion of NumPixels bytes, a LineSync
	pulse is given and the Scan cycle restarts.
	The PixelsRemaining register holds the number of
	pixels remaining to be read on the current scanline.

[0731] Note that the CPU should clear the VLIW Input FIFO 78 before initiating a Scan. The Status register has bit interpretations as follows:

Bit Name	Bits	Description
Scanning	1	If set, the AI is currently scanning, with the number
		of pixels remaining to be transferred from the current
		line recorded in PixelsRemaining.
		If clear, the AI is not currently scanning, so is not
		transferring pixels to the VLIW Input FIFO 78.

[0732] Artcard Interface (AI) 87

[0733] The Artcard Interface (AI) 87 is responsible for taking an Artcard image from the Artcard Reader 34, and decoding it into the original data (usually a Vark script). Specifically, the AI 87 accepts signals from the Artcard scanner linear CCD 34, detects the bit pattern printed on the card, and converts the bit pattern into the original data, correcting read errors.

[0734] With no Artcard 9 inserted, the image printed from an Artcam is simply the sensed Photo Image cleaned up by any standard image processing routines. The Artcard 9 is the means by which users are able to modify a photo before printing it out. By the simple task of inserting a specific Artcard 9 into an Artcam, a user is able to define complex image processing to be performed on the Photo Image.

[0735] With no Artcard inserted the Photo Image is processed in a standard way to create the Print Image. When a single Artcard 9 is inserted into the Artcam, that Artcard's effect is applied to the Photo Image to generate the Print Image.

[0736] When the Artcard 9 is removed (ejected), the printed image reverts to the Photo Image processed in a standard way. When the user presses the button to eject an Artcard, an event is placed in the event queue maintained by the operating system running on the Artcam Central Processor 31. When the event is processed (for example after the current Print has occurred), the following things occur:

[0737] If the current Artcard is valid, then the Print Image is marked as invalid and a Process Standard event is placed in the event queue. When the event is eventually processed it will perform the standard image processing operations on the Photo Image to produce the Print Image.

[0738] The motor is started to eject the Artcard and a time-specific Stop-Motor Event is added to the event queue.

[0739] Inserting an Artcard

[0740] When a user inserts an Artcard 9, the Artcard Sensor 49 detects it notifying the ACP72. This results in the software inserting an Artcard Inserted event into the event queue. When the event is processed several things occur:

[0741] The current Artcard is marked as invalid (as opposed to none).

[0742] The Print Image is marked as invalid.

[0743] The Artcard motor 37 is started up to load the Artcard

[0744] The Artcard Interface 87 is instructed to read the Artcard The Artcard Interface 87 accepts signals from the Artcard scanner linear CCD 34, detects the bit pattern printed on the card, and corrects errors in the detected bit pattern, producing a valid Artcard data block in DRAM.

[0745] Reading Data from the Artcard CCDGeneral Considerations

[0746] As illustrated in FIG. 34, the Data Card reading process has 4 phases operated while the pixel data is read from the card. The phases are as follows:

[0747] Phase 1. Detect data area on Artcard

[0748] Phase 2. Detect bit pattern from Artcard based on CCD pixels, and write as bytes.

[0749] Phase 3. Descramble and XOR the byte-pattern

[0750] Phase 4. Decode data (Reed-Solomon decode)

[0751] As illustrated in FIG. 35, the Artcard 9 must be sampled at least at double the printed resolution to satisfy Nyquist's Theorem. In practice it is better to sample at a higher rate than this. Preferably, the pixels are sampled 230 at 3 times the resolution of a printed dot in each dimension, requiring 9 pixels to define a single dot. Thus if the resolution of the Artcard 9 is 1600 dpi, and the resolution of the sensor 34 is 4800 dpi, then using a 50 mm CCD image sensor results in 9450 pixels per column. Therefore if we require 2 MB of dot data (at 9 pixels per dot) then this requires 2 MB*8*9/945015,978 columnsapproximately 16,000 columns. Of course if a dot is not exactly aligned with the sampling CCD the worst and most likely case is that a dot will be sensed over a 16 pixel area (44) 231.

[0752] An Artcard 9 may be slightly warped due to heat damage, slightly rotated (up to, say 1 degree) due to differences in insertion into an Artcard reader, and can have slight differences in true data rate due to fluctuations in the speed of the reader motor 37. These changes will cause columns of data from the card not to be read as corresponding columns of pixel data. As illustrated in FIG. 36, a 1 degree rotation in the Artcard 9 can cause the pixels from a column on the card to be read as pixels across 166 columns:

[0753] Finally, the Artcard 9 should be read in a reasonable amount of time with respect to the human operator. The data on the Artcard covers most of the Artcard surface, so timing concerns can be limited to the Artcard data itself. A reading time of 1.5 seconds is adequate for Artcard reading.

[0754] The Artcard should be loaded in 1.5 seconds. Therefore all 16,000 columns of pixel data must be read from the CCD 34 in 1.5 second, i.e. 10,667 columns per second. Therefore the time available to read one column is 1/10667 seconds, or 93,747 ns. Pixel data can be written to the DRAM one column at a time, completely independently from any processes that are reading the pixel data. The time to write one column of data (9450/2 bytes since the reading can be 4 bits per pixel giving 24 bit pixels per byte) to DRAM is reduced by using 8 cache lines. If 4 lines were written out at one time, the 4 banks can be written to independently, and thus overlap latency reduced. Thus the 4725 bytes can be written in 11,840 ns (4725/128*320 ns). Thus the time taken to write a given column's data to DRAM uses just under 13% of the available bandwidth.

[0755] Decoding an Artcard

[0756] A simple look at the data sizes shows the impossibility of fitting the process into the 8 MB of memory 33 if the entire Artcard pixel data (140 MB if each bit is read as a 33 array) as read by the linear CCD 34 is kept. For this reason, the reading of the linear CCD, decoding of the bitmap, and the un-bitmap process should take place in real-time (while the Artcard 9 is traveling past the linear CCD 34), and these processes must effectively work without having entire data stores available.

[0757] When an Artcard 9 is inserted, the old stored Print Image and any expanded Photo Image becomes invalid. The new Artcard 9 can contain directions for creating a new image based on the currently captured Photo Image. The old Print Image is invalid, and the area holding expanded Photo Image data and image pyramid is invalid, leaving more than 5 MB that can be used as scratch memory during the read process. Strictly speaking, the 1 MB area where the Artcard raw data is to be written can also be used as scratch data during the Artcard read process as long as by the time the final Reed-Solomon decode is to occur, that 1 MB area is free again. The reading process described here does not make use of the extra 1 MB area (except as a final destination for the data).

[0758] It should also be noted that the unscrambling process requires two sets of 2 MB areas of memory since unscrambling cannot occur in place. Fortunately the 5 MB scratch area contains enough space for this process.

[0759] Turning now to FIG. 37, there is shown a flowchart 220 of the steps necessary to decode the Artcard data. These steps include reading in the Artcard 221, decoding the read data to produce corresponding encoded XORed scrambled bitmap data 223. Next a checkerboard XOR is applied to the data to produces encoded scrambled data 224. This data is then unscrambled 227 to produce data 225 before this data is subjected to Reed-Solomon decoding to produce the original raw data 226. Alternatively, unscrambling and XOR process can take place together, not requiring a separate pass of the data. Each of the above steps is discussed in further detail hereinafter. As noted previously with reference to FIG. 37, the Artcard Interface, therefore, has 4 phases, the first 2 of which are time-critical, and must take place while pixel data is being read from the CCD:

[0760] Phase 1. Detect data area on Artcard

[0761] Phase 2. Detect bit pattern from Artcard based on CCD pixels, and write as bytes.

[0762] Phase 3. Descramble and XOR the byte-pattern

[0763] Phase 4. Decode data (Reed-Solomon decode)

[0764] The four phases are described in more detail as follows:

[0765] Phase 1. As the Artcard 9 moves past the CCD 34 the AI must detect the start of the data area by robustly detecting special targets on the Artcard to the left of the data area. If these cannot be detected, the card is marked as invalid. The detection must occur in real-time, while the Artcard 9 is moving past the CCD 34.

[0766] If necessary, rotation invariance can be provided. In this case, the targets are repeated on the right side of the Artcard, but relative to the bottom right corner instead of the top corner. In this way the targets end up in the correct orientation if the card is inserted the wrong way. Phase 3 below can be altered to detect the orientation of the data, and account for the potential rotation.

[0767] Phase 2. Once the data area has been determined, the main read process begins, placing pixel data from the CCD into an Artcard data window, detecting bits from this window, assembling the detected bits into bytes, and constructing a byte-image in DRAM. This must all be done while the Artcard is moving past the CCD.

[0768] Phase 3. Once all the pixels have been read from the Artcard data area, the Artcard motor 37 can be stopped, and the byte image descrambled and XORed. Although not requiring real-time performance, the process should be fast enough not to annoy the human operator. The process must take 2 MB of scrambled bit-image and write the unscrambled/XORed bit-image to a separate 2 MB image.

[0769] Phase 4. The final phase in the Artcard read process is the Reed-Solomon decoding process, where the 2 MB bit-image is decoded into a 1 MB valid Artcard data area. Again, while not requiring real-time performance it is still necessary to decode quickly with regard to the human operator. If the decode process is valid, the card is marked as valid. If the decode failed, any duplicates of data in the bit-image are attempted to be decoded, a process that is repeated until success or until there are no more duplicate images of the data in the bit image.

[0770] The four phase process described requires 4.5 MB of DRAM. 2 MB is reserved for Phase 2 output, and 0.5 MB is reserved for scratch data during phases 1 and 2. The remaining 2 MB of space can hold over 440 columns at 4725 byes per column. In practice, the pixel data being read is a few columns ahead of the phase 1 algorithm, and in the worst case, about 180 columns behind phase 2, comfortably inside the 440 column limit.

[0771] A description of the actual operation of each phase will now be provided in greater detail.

[0772] Phase 1Detect Data Area on Artcard

[0773] This phase is concerned with robustly detecting the left-hand side of the data area on the Artcard 9. Accurate detection of the data area is achieved by accurate detection of special targets printed on the left side of the card. These targets are especially designed to be easy to detect even if rotated up to 1 degree.

[0774] Turning to FIG. 38, there is shown an enlargement of the left hand side of an Artcard 9. The side of the card is divided into 16 bands, 239 with a target eg. 241 located at the center of each band. The bands are logical in that there is no line drawn to separate bands. Turning to FIG. 39, there is shown a single target 241. The target 241, is a printed black square containing a single white dot. The idea is to detect firstly as many targets 241 as possible, and then to join at least 8 of the detected white-dot locations into a single logical straight line. If this can be done, the start of the data area 243 is a fixed distance from this logical line. If it cannot be done, then the card is rejected as invalid.

[0775] As shown in FIG. 38, the height of the card 9 is 3150 dots. A target (Target0) 241 is placed a fixed distance of 24 dots away from the top left corner 244 of the data area so that it falls well within the first of 16 equal sized regions 239 of 192 dots (576 pixels) with no target in the final pixel region of the card. The target 241 must be big enough to be easy to detect, yet be small enough not to go outside the height of the region if the card is rotated 1 degree. A suitable size for the target is a 3131 dot (9393 sensed pixels) black square 241 with the white dot 242.

[0776] At the worst rotation of 1 degree, a 1 column shift occurs every 57 pixels. Therefore in a 590 pixel sized band, we cannot place any part of our symbol in the top or bottom 12 pixels or so of the band or they could be detected in the wrong band at CCD read time if the card is worst case rotated.

[0777] Therefore, if the black part of the rectangle is 57 pixels high (19 dots) we can be sure that at least 9.5 black pixels will be read in the same column by the CCD (worst case is half the pixels are in one column and half in the next). To be sure of reading at least 10 black dots in the same column, we must have a height of 20 dots. To give room for erroneous detection on the edge of the start of the black dots, we increase the number of dots to 31, giving us 15 on either side of the white dot at the target's local coordinate (15, 15). 31 dots is 91 pixels, which at most suffers a 3 pixel shift in column, easily within the 576 pixel band.

[0778] Thus each target is a block of 3131 dots (9393 pixels) each with the composition:

[0779] 15 columns of 31 black dots each (45 pixel width columns of 93 pixels).

[0780] 1 column of 15 black dots (45 pixels) followed by 1 white dot (3 pixels) and then a further 15 black dots (45 pixels)

[0781] 15 columns of 31 black dots each (45 pixel width columns of 93 pixels)

[0782] Detect Targets

[0783] Targets are detected by reading columns of pixels, one column at a time rather than by detecting dots. It is necessary to look within a given band for a number of columns consisting of large numbers of contiguous black pixels to build up the left side of a target. Next, it is expected to see a white region in the center of further black columns, and finally the black columns to the left of the target center.

[0784] Eight cache lines are required for good cache performance on the reading of the pixels. Each logical read fills 4 cache lines via 4 sub-reads while the other 4 cache-lines are being used. This effectively uses up 13% of the available DRAM bandwidth.

[0785] As illustrated in FIG. 40, the detection mechanism FIFO for detecting the targets uses a filter 245, run-length encoder 246, and a FIFO 247 that requires special wiring of the top 3 elements (S1, S2, and S3) for random access.

[0786] The columns of input pixels are processed one at a time until either all the targets are found, or until a specified number of columns have been processed. To process a column, the pixels are read from DRAM, passed through a filter 245 to detect a 0 or 1, and then run length encoded 246. The bit value and the number of contiguous bits of the same value are placed in FIFO 247. Each entry of the FIFO 249 is in 8 bits, 7 bits 250 to hold the run-length, and 1 bit 249 to hold the value of the bit detected.

[0787] The run-length encoder 246 only encodes contiguous pixels within a 576 pixel (192 dot) region.

[0788] The top 3 elements in the FIFO 247 can be accessed 252 in any random order. The run lengths (in pixels) of these entries are filtered into 3 values: short, medium, and long in accordance with the following table:

Short	Used to detect white dot.	RunLength < 16
Medium	Used to detect runs of black	16 < Runlength < 48
	above or below the white dot
	in the center of the target.
Long	Used to detect run lengths of	RunLength > 48
	black to the left and right
	of the center dot in the target.

[0789] Looking at the top three entries in the FIFO 247 there are 3 specific cases of interest:

Case 1	S1 white long	We have detected a black column
	S2 black long	of the target to the left of or
	S3 white medium/long	to the right of the white center dot.
Case 2	S1 white long	If we've been processing a series of
	S2 black medium	columns of Case 1s, then we have
	S3 white short	probably detected the white dot in
	Previous 8 columns	this column. We know that the next
	were Case 1	entry will be black (or it would
		have been included in the white S3
		entry), but the number of black
		pixels is in question. Need to
		verify by checking after the next
		FIFO advance (see Case 3).
Case 3	Prev Case 2	We have detected part of the
	S3 black med	white dot. We expect around 3 of
		these, and then some more columns
		of Case 1.

[0790] Preferably, the following information per region band is kept:

	TargetDetected	1 bit
	BlackDetectCount	4 bits
	WhiteDetectCount	3 bits
	PrevColumnStartPixel	15 bits
	TargetColumn ordinate	16 bits (15:1)
	TargetRow ordinate	16 bits (15:1)
	TOTAL	7 bytes (rounded to 8 bytes
		for easy addressing)

[0791] Given a total of 7 bytes. It makes address generation easier if the total is assumed to be 8 bytes. Thus 16 entries requires 16*8128 bytes, which fits in 4 cache lines. The address range should be inside the scratch 0.5 MB DRAM area since other phases make use of the remaining 4 MB data area.

[0792] When beginning to process a given pixel column, the register value S2StartPixel 254 is reset to 0. As entries in the FIFO advance from S2 to S1, they are also added 255 to the existing S2StartPixel value, giving the exact pixel position of the run currently defined in S2. Looking at each of the 3 cases of interest in the FIFO, S2StartPixel can be used to determine the start of the black area of a target (Cases 1 and 2), and also the start of the white dot in the center of the target (Case 3). An algorithm for processing columns can be as follows:

	1	TargetDetected0-15 : 0
		BlackDetectCount0-15 : 0
		WhiteDetectCount0-15 : 0
		TargetRow0-15 : 0
		TargetColumn0-15 : 0
		PrevColStartPixel0-15 : 0
		CurrentColumn : 0
	2	Do ProcessColumn
	3	CurrentColumn
	4	If (CurrentColumn < LastValidColumn)
		Goto 2

[0793] The steps involved in the processing a column (Process Column) are as follows:

	1	S2StartPixel : 0
		FIFO : 0
		BlackDetectCount : 0
		WhiteDetectCount : 0
		ThisColumnDetected : FALSE
		PrevCaseWasCase2 : FALSE
	2	If ( TargetDetectedTarget) &
		( ColumnDetectedTarget)
		ProcessCases
		EndIf
	3	PrevCaseWasCase2 : Case 2
	4	Advance FIFO

[0794] The processing for each of the 3 (Process Cases) cases is as follows:

[0795] Case 1:

BlackDetectCounttarget < 8	: ABS(S2StartPixel PrevColStartPixelTarget)
OR	If (0<<2)
WhiteDetectCountTarget 0	BlackDetectCountTarget (max value 8)
	Else
	BlackDetectCountTarget : 1
	WhiteDetectCountTarget : 0
	EndIf
	PrevColStartPixelTarget : S2StartPixel
	ColumnDetectedTarget : TRUE
	BitDetected 1
BlackDetectCounttarget > 8	PrevColStartPixelTarget : S2StartPixel
WhiteDetectCountTarget 0	ColumnDetectedTarget : TRUE
	BitDetected 1
	TargetDetectedTarget : TRUE
	TargetColumnTarget : CurrentColumn 8
	(WhiteDetectCountTarget/2)

[0796] Case 2:

[0797] No special processing is recorded except for setting the PrevCaseWasCase2 flag for identifying Case 3 (see Step 3 of processing a column described above)

[0798] Case 3:

PrevCaseWasCase2 TRUE	If (WhiteDetectCountTarget < 2)
BlackDetectCountTarget > 8	TargetRowTarget S2StartPixel (S2RunLength/2)
WhiteDetectCount1	EndIf
	: ABS(S2StartPixel PrevColStartPixelTarget)
	If (0<<2)
	WhiteDetectCountTarget
	Else
	WhiteDetectCountTarget : 1
	EndIf
	PrevColStartPixelTarget : S2StartPixel
	ThisColumnDetected : TRUE
	BitDetected 0

[0799] At the end of processing a given column, a comparison is made of the current column to the maximum number of columns for target detection. If the number of columns allowed has been exceeded, then it is necessary to check how many targets have been found. If fewer than 8 have been found, the card is considered invalid.

[0800] Process targets

[0801] After the targets have been detected, they should be processed. All the targets may be available or merely some of them. Some targets may also have been erroneously detected.

[0802] This phase of processing is to determine a mathematical line that passes through the center of as many targets as possible. The more targets that the line passes through, the more confident the target position has been found. The limit is set to be 8 targets. If a line passes through at least 8 targets, then it is taken to be the right one.

[0803] It is all right to take a brute-force but straightforward approach since there is the time to do so (see below), and lowering complexity makes testing easier. It is necessary to determine the line between targets 0 and 1 (if both targets are considered valid) and then determine how many targets fall on this line. Then we determine the line between targets 0 and 2, and repeat the process. Eventually we do the same for the line between targets 1 and 2, 1 and 3 etc. and finally for the line between targets 14 and 15. Assuming all the targets have been found, we need to perform 151413. . . 90 sets of calculations (with each set of calculations requiring 16 tests1440 actual calculations), and choose the line which has the maximum number of targets found along the line. The algorithm for target location can be as follows:

	TargetA : 0
	MaxFound : 0
	BestLine : 0
	While (TargetA < 15)
	If (TargetA is Valid)
	TargetB: TargetA 1
	While (TargetB< 15)
	If (TargetB is valid)
	CurrentLine : line between TargetA and TargetB
	TargetC : 0;
	While (TargetC < 15)
	If (TargetC valid AND TargetC on line AB)
	TargetsHit
	EndIf
	If (TargetsHit > MaxFound)
	MaxFound : TargetsHit
	BestLine : CurrentLine
	EndIf
	TargetC
	EndWhile
	EndIf
	TargetB
	EndWhile
	EndIf
	TargetA
	EndWhile
	If (MaxFound < 8)
	Card is Invalid
	Else

[0804] Store expected centroids for rows based on BestLine

[0805] EndIf

[0806] As illustrated in FIG. 34, in the algorithm above, to determine a CurrentLine 260 from Target A 261 and target B, it is necessary to calculate row (264) & column (263) between targets 261, 262, and the location of Target A. It is then possible to move from Target 0 to Target 1 etc. by adding row and column. The found (if actually found) location of target N can be compared to the calculated expected position of Target N on the line, and if it falls within the tolerance, then Target N is determined to be on the line.

[0807] To calculate row & column:

[0808] Then we calculate the position of Target0:

[0809] And compare (row, column) against the actual row_Target0 and column_Target0. To move from one expected target to the next (e.g. from Target0 to Target1), we simply add row and column to row and column respectively. To check if each target is on the line, we must calculate the expected position of Target0, and then perform one add and one comparison for each target ordinate.

[0810] At the end of comparing all 16 targets against a maximum of 90 lines, the result is the best line through the valid targets. If that line passes through at least 8 targets (i.e. MaxFound>8), it can be said that enough targets have been found to form a line, and thus the card can be processed. If the best line passes through fewer than 8, then the card is considered invalid.

[0811] The resulting algorithm takes 180 divides to calculate row and column, 180 multiply/adds to calculate target0 position, and then 2880 adds/comparisons. The time we have to perform this processing is the time taken to read 36 columns of pixel data3,374,892 ns. Not even accounting for the fact that an add takes less time than a divide, it is necessary to perform 3240 mathematical operations in 3,374,892 ns. That gives approximately 1040 ns per operation, or 104 cycles. The CPU can therefore safely perform the entire processing of targets, reducing complexity of design.

[0812] Update Centroids Based on Data Edge Border and Clockmarks

[0813] Step 0: Locate the Data Area

[0814] From Target 0 (241 of FIG. 38) it is a predetermined fixed distance in rows and columns to the top left border 244 of the data area, and then a further 1 dot column to the vertical clock marks 276. So we use TargetA, row and column found in the previous stage (row and column refer to distances between targets) to calculate the centroid or expected location for Target0 as described previously.

[0815] Since the fixed pixel offset from Target0 to the data area is related to the distance between targets (192 dots between targets, and 24 dots between Target0 and the data area 243), simply add row/8 to Target0's centroid column coordinate (aspect ratio of dots is 1:1). Thus the top co-ordinate can be defined as:

[0816] Next row and column are updated to give the number of pixels between dots in a single column (instead of between targets) by dividing them by the number of dots between targets:

[0817] We also set the currentColumn register (see Phase 2) to be 1 so that after step 2, when phase 2 begins, the currentColumn register will increment from 1 to 0.

[0818] Step 1: Write out the Initial Centroid Deltas (A) and Bit History

[0819] This simply involves writing setup information required for Phase 2.

[0820] This can be achieved by writing 0s to all the row and column entries for each row, and a bit history. The bit history is actually an expected bit history since it is known that to the left of the clock mark column 276 is a border column 277, and before that, a white area. The bit history therefore is 011, 010, 011, 010 etc.

[0821] Step 2: Update the Centroids Based on Actual Pixels Read.

[0822] The bit history is set up in Step 1 according to the expected clock marks and data border. The actual centroids for each dot row can now be more accurately set (they were initially 0) by comparing the expected data against the actual pixel values. The centroid updating mechanism is achieved by simply performing step 3 of Phase 2.

[0823] Phase 2Detect Bit Pattern From Artcard Based on Pixels Read, and Write as Bytes.

[0824] Since a dot from the Artcard 9 requires a minimum of 9 sensed pixels over 3 columns to be represented, there is little point in performing dot detection calculations every sensed pixel column. It is better to average the time required for processing over the average dot occurrence, and thus make the most of the available processing time. This allows processing of a column of dots from an Artcard 9 in the time it takes to read 3 columns of data from the Artcard. Although the most likely case is that it takes 4 columns to represent a dot, the 4th column will be the last column of one dot and the first column of a next dot. Processing should therefore be limited to only 3 columns.

[0825] As the pixels from the CCD are written to the DRAM in 13% of the time available, 83% of the time is available for processing of 1 column of dots i.e. 83% of (93,747*3) 83% of 281,241 ns233,430 ns.

[0826] In the available time, it is necessary to detect 3150 dots, and write their bit values into the raw data area of memory. The processing therefore requires the following steps:

[0827] For each column of dots on the Artcard:

[0828] Step 0: Advance to the next dot column

[0829] Step 1: Detect the top and bottom of an Artcard dot column (check clock marks)

[0830] Step 2: Process the dot column, detecting bits and storing them appropriately

[0831] Step 3: Update the centroids

[0832] Since we are processing the Artcard's logical dot columns, and these may shift over 165 pixels, the worst case is that we cannot process the first column until at least 165 columns have been read into DRAM. Phase 2 would therefore finish the same amount of time after the read process had terminated. The worst case time is: 165*93,747 ns15,468,255 ns or 0.015 seconds.

[0833] Step 0: Advance to the Next Dot Column

[0834] In order to advance to the next column of dots we add row and column to the dotColumnTop to give us the centroid of the dot at the top of the column. The first time we do this, we are currently at the clock marks column 276 to the left of the bit image data area, and so we advance to the first column of data. Since row and column refer to distance between dots within a column, to move between dot columns it is necessary to add row to column_dotColumnTop and column to row_dotcolumnTop.

[0835] To keep track of what column number is being processed, the column number is recorded in a register called CurrentColumn. Every time the sensor advances to the next dot column it is necessary to increment the CurrentColumn register. The first time it is incremented, it is incremented from 1 to 0 (see Step 0 Phase 1). The CurrentColumn register determines when to terminate the read process (when reaching maxColumns), and also is used to advance the DataOut Pointer to the next column of byte information once all 8 bits have been written to the byte (once every 8 dot columns). The lower 3 bits determine what bit we're up to within the current byte. It will be the same bit being written for the whole column.

[0836] Step 1: Detect the Top and Bottom of an Artcard Dot Column.

[0837] In order to process a dot column from an Artcard, it is necessary to detect the top and bottom of a column. The column should form a straight line between the top and bottom of the column (except for local warping etc.). Initially dotColumnTop points to the clock mark column 276. We simply toggle the expected value, write it out into the bit history, and move on to step 2, whose first task will be to add the row and column values to dotColumnTop to arrive at the first data dot of the column.

[0838] Step 2: Process an Artcard's Dot Column

[0839] Given the centroids of the top and bottom of a column in pixel coordinates the column should form a straight line between them, with possible minor variances due to warping etc.

[0840] Assuming the processing is to start at the top of a column (at the top centroid coordinate) and move down to the bottom of the column, subsequent expected dot centroids are given as:

[0841] This gives us the address of the expected centroid for the next dot of the column. However to account for local warping and error we add another row and column based on the last time we found the dot in a given row. In this way we can account for small drifts that accumulate into a maximum drift of some percentage from the straight line joining the top of the column to the bottom.

[0842] We therefore keep 2 values for each row, but store them in separate tables since the row history is used in step 3 of this phase.

[0843] row and column (2 4 bits each1 byte)

[0844] row history (3 bits per row, 2 rows are stored per byte)

[0845] For each row we need to read a row and column to determine the change to the centroid. The read process takes 5% of the bandwidth and 2 cache lines:

[0846] Once the centroid has been determined, the pixels around the centroid need to be examined to detect the status of the dot and hence the value of the bit. In the worst case a dot covers a 44 pixel area. However, thanks to the fact that we are sampling at 3 times the resolution of the dot, the number of pixels required to detect the status of the dot and hence the bit value is much less than this. We only require access to 3 columns of pixel columns at any one time.

[0847] In the worst case of pixel drift due to a 1% rotation, centroids will shift 1 column every 57 pixel rows, but since a dot is 3 pixels in diameter, a given column will be valid for 171 pixel rows (3*57). As a byte contains 2 pixels, the number of bytes valid in each buffered read (4 cache lines) will be a worst case of 86 (out of 128 read).

[0848] Once the bit has been detected it must be written out to DRAM. We store the bits from 8 columns as a set of contiguous bytes to minimize DRAM delay. Since all the bits from a given dot column will correspond to the next bit position in a data byte, we can read the old value for the byte, shift and OR in the new bit, and write the byte back. The read/shift&OR/write process requires 2 cache lines.

[0849] We need to read and write the bit history for the given row as we update it. We only require 3 bits of history per row, allowing the storage of 2 rows of history in a single byte. The read/shift&OR/write process requires 2 cache lines.

The total bandwidth required for the bit detection and storage
is summarised in the following table:
	Read centroid	5%
	Read 3 columns of pixel data	19%
	Read/Write detected bits into byte buffer	10%
	Read/Write bit history	5%
	TOTAL	39%

[0850] Detecting a Dot

[0851] The process of detecting the value of a dot (and hence the value of a bit) given a centroid is accomplished by examining 3 pixel values and getting the result from a lookup table. The process is fairly simple and is illustrated in FIG. 42. A dot 290 has a radius of about 1.5 pixels. Therefore the pixel 291 that holds the centroid, regardless of the actual position of the centroid within that pixel, should be 100% of the dot's value. If the centroid is exactly in the center of the pixel 291, then the pixels above 292 & below 293 the centroid's pixel, as well as the pixels to the left 294 & right 295 of the centroid's pixel will contain a majority of the dot's value. The further a centroid is away from the exact center of the pixel 295, the more likely that more than the center pixel will have 100% coverage by the dot.

[0852] Although FIG. 42 only shows centroids differing to the left and below the center, the same relationship obviously holds for centroids above and to the right of center. center. In Case 1, the centroid is exactly in the center of the middle pixel 295. The center pixel 295 is completely covered by the dot, and the pixels above, below, left, and right are also well covered by the dot. In Case 2, the centroid is to the left of the center of the middle pixel 291. The center pixel is still completely covered by the dot, and the pixel 294 to the left of the center is now completely covered by the dot. The pixels above 292 and below 293 are still well covered. In Case 3, the centroid is below the center of the middle pixel 291. The center pixel 291 is still completely covered by the dot 291, and the pixel below center is now completely covered by the dot. The pixels left 294 and right 295 of center are still well covered. In Case 4, the centroid is left and below the center of the middle pixel. The center pixel 291 is still completely covered by the dot, and both the pixel to the left of center 294 and the pixel below center 293 are completely covered by the dot. The algorithm for updating the centroid uses the distance of the centroid from the center of the middle pixel 291 in order to select 3 representative pixels and thus decide the value of the dot:

[0853] Pixel 1: the pixel containing the centroid

[0854] Pixel 2: the pixel to the left of Pixel 1 if the centroid's X coordinate (column value) is <, otherwise the pixel to the right of Pixel 1.

[0855] Pixel 3: the pixel above pixel 1 if the centroid's Y coordinate (row value) is <, otherwise the pixel below Pixel 1.

[0856] As shown in FIG. 43, the value of each pixel is output to a pre-calculated lookup table 301. The 3 pixels are fed into a 12-bit lookup table, which outputs a single bit indicating the value of the doton or off.

[0857] The lookup table 301 is constructed at chip definition time, and can be compiled into about 500 gates. The lookup table can be a simple threshold table, with the exception that the center pixel (Pixel 1) is weighted more heavily.

[0858] Step 3: Update the Centroid s for Each Row in the Column

[0859] The idea of the s processing is to use the previous bit history to generate a perfect dot at the expected centroid location for each row in a current column. The actual pixels (from the CCD) are compared with the expected perfect pixels. If the two match, then the actual centroid location must be exactly in the expected position, so the centroid s must be valid and not need updating. Otherwise a process of changing the centroid s needs to occur in order to best fit the expected centroid location to the actual data. The new centroid s will be used for processing the dot in the next column.

[0860] Updating the centroid s is done as a subsequent process from Step 2 for the following reasons:

[0861] to reduce complexity in design, so that it can be performed as Step 2 of Phase 1 there is enough bandwidth remaining to allow it to allow reuse of DRAM buffers, and

[0862] to ensure that all the data required for centroid updating is available at the start of the process without special pipelining.

[0863] The centroid are processed as column row respectively to reduce complexity.

[0864] Although a given dot is 3 pixels in diameter, it is likely to occur in a 44 pixel area. However the edge of one dot will as a result be in the same pixel as the edge of the next dot. For this reason, centroid updating requires more than simply the information about a given single dot.

[0865] FIG. 44 shows a single dot 310 from the previous column with a given centroid 311. In this example, the dot 310 extend over 4 pixel columns 312-315 and in fact, part of the previous dot column's dot (coordinate(Prevcolumn, Current Row)) has entered the current column for the dot on the current row. If the dot in the current row and column was white, we would expect the rightmost pixel column 314 from the previous dot column to be a low value, since there is only the dot information from the previous column's dot (the current column's dot is white). From this we can see that the higher the pixel value is in this pixel column 315, the more the centroid should be to the right Of course, if the dot to the right was also black, we cannot adjust the centroid as we cannot get information sub-pixel. The same can be said for the dots to the left, above and below the dot at dot coordinates (PrevColumn, CurrentRow).

[0866] From this we can say that a maximum of 5 pixel columns and rows are required. It is possible to simplify the situation by taking the cases of row and column centroid s separately, treating them as the same problem, only rotated 90 degrees.

[0867] Taking the horizontal case first, it is necessary to change the column centroid s if the expected pixels don't match the detected pixels. From the bit history, the value of the bits found for the Current Row in the current dot column, the previous dot column, and the (previous-1)th dot column are known. The expected centroid location is also known. Using these two pieces of information, it is possible to generate a 20 bit expected bit pattern should the read be perfect. The 20 bit bit-pattern represents the expected values for each of the 5 pixels across the horizontal dimension. The first nibble would represent the rightmost pixel of the leftmost dot. The next 3 nibbles represent the 3 pixels across the center of the dot 310 from the previous column, and the last nibble would be the leftmost pixel 317 of the rightmost dot (from the current column).

[0868] If the expected centroid is in the center of the pixel, we would expect a 20 bit pattern based on the following table:

	Bit history	Expected pixels
	000	00000
	001	0000D
	010	0DFD0
	011	0DFDD
	100	D0000
	101	D000D
	110	DDFD0
	111	DDFDD

[0869] The pixels to the left and right of the center dot are either 0 or D depending on whether the bit was a 0 or 1 respectively. The center three pixels are either 000 or DFD depending on whether the bit was a 0 or 1 respectively. These values are based on the physical area taken by a dot for a given pixel. Depending on the distance of the centroid from the exact center of the pixel, we would expect data shifted slightly, which really only affects the pixels either side of the center pixel. Since there are 16 possibilities, it is possible to divide the distance from the center by 16 and use that amount to shift the expected pixels.

[0870] Once the 20 bit 5 pixel expected value has been determined it can be compared against the actual pixels read. This can proceed by subtracting the expected pixels from the actual pixels read on a pixel by pixel basis, and finally adding the differences together to obtain a distance from the expected values.

[0871] FIG. 45 illustrates one form of implementation of the above algorithm which includes a look up table 320 which receives the bit history 322 and central fractional component 323 and outputs 324 the corresponding 20 bit number which is subtracted 321 from the central pixel input 326 to produce a pixel difference 327.

[0872] This process is carried out for the expected centroid and once for a shift of the centroid left and right by 1 amount in column. The centroid with the smallest difference from the actual pixels is considered to be the winner and the column updated accordingly (which hopefully is no change). As a result, a column cannot change by more than 1 each dot column.

[0873] The process is repeated for the vertical pixels, and row is consequentially updated.

[0874] There is a large amount of scope here for parallelism. Depending on the rate of the clock chosen for the ACP unit 31 these units can be placed in series (and thus the testing of 3 different could occur in consecutive clock cycles), or in parallel where all 3 can be tested simultaneously. If the clock rate is fast enough, there is less need for parallelism.

[0875] Bandwidth Utilization

[0876] It is necessary to read the old of the s, and to write them out again. This takes 10% of the bandwidth:

[0877] It is necessary to read the bit history for the given row as we update its s. Each byte contains 2 row's bit histories, thus taking 2.5% of the bandwidth:

[0878] In the worst case of pixel drift due to a 1% rotation, centroids will shift 1 column every 57 pixel rows, but since a dot is 3 pixels in diameter, a given pixel column will be valid for 171 pixel rows (3*57). As a byte contains 2 pixels, the number of bytes valid in cached reads will be a worst case of 86 (out of 128 read). The worst case timing for 5 columns is therefore 31% bandwidth.

[0879] The total bandwidth required for the updating the centroid is summarised in the following table:

	Read/Write centroid	10%
	Read bit history	2.5%
	Read 5 columns of pixel data	31%
	TOTAL	43.5%

[0880] Memory Usage for Phase 2:

[0881] The 2 MB bit-image DRAM area is read from and written to during Phase 2 processing. The 2 MB pixel-data DRAM area is read.

[0882] The 0.5 MB scratch DRAM area is used for storing row data, namely:

Centroid array	24bits (16:8) * 2 * 3150 18,900 byes
Bit History array	3 bits * 3150 entries (2 per byte) 1575 bytes

[0883] Phase 3Unscramble and XOR the Raw Data

[0884] Returning to FIG. 37, the next step in decoding is to unscramble and XOR the raw data. The 2 MB byte image, as taken from the Artcard, is in a scrambled XORed form. It must be unscrambled and re-XORed to retrieve the bit image necessary for the Reed Solomon decoder in phase 4.

[0885] Turning to FIG. 46, the unscrambling process 330 takes a 2 MB scrambled byte image 331 and writes an unscrambled 2 MB image 332. The process cannot reasonably be performed in-place, so 2 sets of 2 MB areas are utilised. The scrambled data 331 is in symbol block order arranged in a 1616 array, with symbol block 0 (334) having all the symbol 0's from all the code words in random order. Symbol block 1 has all the symbol 1's from all the code words in random order etc. Since there are only 255 symbols, the 256^th symbol block is currently unused.

[0886] A linear feedback shift register is used to determine the relationship between the position within a symbol block eg. 334 and what code word eg. 355 it came from. This works as long as the same seed is used when generating the original Artcard images. The XOR of bytes from alternative source lines with 0AA and 055 respectively is effectively free (in time) since the bottleneck of time is waiting for the DRAM to be ready to read/write to non-sequential addresses.

[0887] The timing of the unscrambling XOR process is effectively 2 MB of random byte-reads, and 2 MB of random byte-writes i.e. 2*(2 MB*76 ns2 MB*2 ns)327,155,712 ns or approximately 0.33 seconds. This timing assumes no caching.

[0888] Phase 4Reed Solomon Decode

[0889] This phase is a loop, iterating through copies of the data in the bit image, passing them to the Reed-Solomon decode module until either a successful decode is made or until there are no more copies to attempt decode from.

[0890] The Reed-Solomon decoder used can be the VLIW processor, suitably programmed or, alternatively, a separate hardwired core such as LSI Logic's L64712. The L64712 has a throughput of 50 Mbits per second (around 6.25 MB per second), so the time may be bound by the speed of the Reed-Solomon decoder rather than the 2 MB read and 1 MB write memory access time (500 MB/sec for sequential accesses). The time taken in the worst case is thus 2/6.25sapproximately 0.32 seconds.

[0891] Phase 5 Running the Vark Script

[0892] The overall time taken to read the Artcard 9 and decode it is therefore approximately 2.15 seconds. The apparent delay to the user is actually only 0.65 seconds (the total of Phases 3 and 4), since the Artcard stops moving after 1.5 seconds.

[0893] Once the Artcard is loaded, the Artvark script must be interpreted, Rather than run the script immediately, the script is only run upon the pressing of the Print button 13 (FIG. 1). The taken to run the script will vary depending on the complexity of the script, and must be taken into account for the perceived delay between pressing the print button and the actual print button and the actual printing.

[0894] Alternative Artcard Fomat

[0895] Of course, other artcard formats are possible. There will now be described one such alternative artcard format with a number of preferable feature. Described hereinafter will be the alternative Artcard data format, a mechanism for mapping user data onto dots on an alternative Artcard, and a fast alternative Artcard reading algorithm for use in embedded systems where resources are scarce.

[0896] Alternative Artcard Overview