Internal package interconnect with electrically parallel vias

[0001] This disclosure relates to internal package interconnects with electrically parallel vias.

[0002] Microelectronics devices may contain many electronic components within an active semiconductor chip. To form a usable device, the semiconductor chip requires protection from the environment as well as electrical and mechanical connections to the surrounding components. The technology dealing with these requirements is called electronic packaging. The design of the chip provides access to terminals for input power and signal transmission and provides the electrical wiring for interconnections.

[0003] An electronic package may include a monolithic dielectric structure having a number of layers of insulating material which have conductor patterns, resistors and other electrical circuit elements on their surfaces. The layers may be thermally, mechanically or chemically fused together so that the circuit elements are buried within the structure. Vertical interconnects, also known as vias, may be formed through the insulating layers to provide interconnections between circuit elements in different layers.

[0004] An electronic package includes a multi-layer substrate module that includes multiple electrically parallel vias to carry an electrical data signal between two nodes. For example, the vias may be coupled between nodes of different metallization layers in or on the substrate module. Alternatively, the vias may be coupled between a node of one of the metallization layers and a signal transmission line that feeds or receives data signals or an interconnection that connects the multi-layer module to a next-higher level of the assembly, such as a printed circuit board. In other implementations, the vias may be coupled between a data signal transmission line and an interconnection to the next-higher level of the assembly.

[0005] The use of electrically parallel vias to carry the data signal(s) may help reduce the resistance and may reduce the effective layer-to-layer inductance. Such reductions may be particularly useful for carrying high frequency data signals through the multi-layer substrate module.

[0006] In various implementations, one or more of the following features may be present. The substrate module may include one or more capture pads which the vias intersect and may include a multi-layer ceramic substrate module. The vias may include a ceramic material, such as a low-temperature co-fired ceramic material. An electronic device may be mounted on and electrically coupled to the multi-layer substrate module.

[0007] A method also is disclosed in which an electrical data signal is passed from an electronic device to a multi-layer ceramic substrate module to which the device is mounted. The electrical data signal is carried simultaneously along electrically parallel vias in the multi-layer ceramic substrate module. The vias electrically couple a first node and a second node. The first node may be either on a data signal transmission line on the multi-layer substrate module or on a first electrically conductive layer in the multi-layer substrate module. The second node may be either on a second conductive layer in the multi-layer substrate module or an interconnection that electrically couples the multi-layer substrate module to a next-higher level assembly. The electrical data signal is passed from the multi-layer ceramic substrate module to a next-higher level assembly. In some implementations, the data signals may have a frequency greater than 9.9 Gigabits per second (Gbit/s).

[0008] Other features and advantages will be readily apparent from the following detailed description, the accompanying drawings and the claims.

[0009] FIG. 1 is a flow chart of a process for manufacturing a package for an electronic circuit.

[0010] FIG. 2 illustrates various steps in the manufacturing process.

[0011] FIG. 3 is a cross-section of an electronic package assembly.

[0012] FIG. 4 is a cross-section of the electronic package assembly showing additional details of a multi-layer ceramic substrate module according to one implementation.

[0013] FIG. 5 illustrates details of a turret via according to one implementation.

[0014] FIG. 6 is a cross-section of an electronic package assembly showing additional details of a multi-layer ceramic substrate module according to another implementation.

[0015] FIG. 7 is a partial cross-section of another example of an electronic assembly package that includes a turret via.

[0016] FIGS. 1 and 2 illustrate an example of an overall manufacturing process for making multi-layer electronic package assemblies. Other processes may include additional or different steps, or may differ in particular details.

[0017] Initially, unfired, flexible ceramic sheets may be tape cast 12 and cut 14. Via holes, cavities and other inside cutting may be punched 16 in the ceramic sheets layer-by-layer. The via holes may then be filled or coated 18 for electrical connection. Subsequent screen printing 20 may include the formation of conductor lines and various metallization pads. The ceramic sheets are then stacked according to the design sequence and bonded together during a lamination process 22.

[0018] Following lamination, a shaping process 24 may be used to cut the outside edge of the ceramic sheets to facilitate subsequent separation of the individual units from the master array. The ceramic and metallization layers then may be sintered simultaneously during a co-firing process 26 at a temperature, for example, in the range of about 1,500-1,600 F. To improve subsequent welding, pre-brazing nickel plating 28 may be performed. After assembly of the electrical leads and pins (block 30), metal parts such as lead frames, input/output (I/O) pins, seal rings and/or heat sinks may be bonded to metallized pads during a brazing process 32. During subsequent processing, exposed metal surfaces may be plated 34, for example, using gold with a nickel underplating.

[0019] The individual units then may be separated 36 from the master array. Final electrical testing 38 and quality assurance inspections 40 may be performed.

[0020] As shown in FIG. 3, the resulting electronic package assembly 50 may include a semiconductor flip-chip 52 or other electronic device mounted to the multi-layer ceramic substrate module 54, for example, through solder ball interconnections 56. The ceramic module 54 may be attached to the printed circuit board 58 through another set of solder ball interconnections 60.

[0021] FIG. 4 illustrates further details of a multi-layer ceramic substrate module 54. As shown, the substrate module 54 includes five conductive or metallization layers 62A, 62B, 62C, 62D and 62E, separated by layers of ceramic material. The metallization layers and the package interconnects may be coupled by thermal vias or data signal vias.

[0022] For example, some of the interconnections, metallization lines and vias may help dissipate heat. Solder balls connecting the flip-chip 52 to the substrate module 54, such as the solder ball 56A, may be coupled, for example, to the metallization layers 62C, 62D through thermal vias 64, 66. Additional thermal vias 68 may carry the heat to the printed circuit board interconnections 60B, 60C.

[0023] Other interconnections, metallization lines and vias may carry data signals. As shown, for example, in FIG. 4, the solder bump 56B connects a signal input/output pin (not shown) on the flip-chip 52 to the substrate module 54. The solder bump 56B may be coupled through a via 70 to the metallization layer 62B. The metallization layer 62B is coupled by a turret via 72 to the interconnect solder bump 60A. The turret via 72 includes multiple parallel vias that connect the metallization layer 62B to the interconnect solder bump 60A. Each of the vias in the turret via 72 contacts both the metallization layer 62B and the solder bump 60A.

[0024] Various materials, including low temperature co-fired ceramic materials, may be used for the electrically parallel vias. Other materials also may be used.

[0025] As shown in FIG. 5, capture pads 68A, 68B, 68C and 68D may be provided at one or more of the layers to help compensate for layer-to-layer misalignment. The capture pads may comprise the same material as the vias 72.

[0026] Electrically parallel vias, such as those shown in FIG. 5, may be used to carry data signals, for example, between nodes of two different metallization layers, between a node of one of the metallization layers and a signal transmission line that feeds or receives data signals, or between a node of one of the metallization layers and an interconnection that connects the multi-layer module to the next-higher level of the assembly (in this case, the printed circuit board 58). Each of the vias contacts both nodes. Using electrically parallel vias to carry data signals may help reduce the resistance and may reduce the effective layer-to-layer inductance of the signal. Reductions in resistance can be particularly important for data signals at high frequencies, such as signals with a frequency greater than 9.9 Gbits/s. The techniques may be particularly advantageous for data signals with frequencies in the range of about 9.9 to 80 Gigabits per second (Gbit/s). The techniques may, however, be used with data signals having higher or lower frequencies as well.

[0027] Although a solder ball 60A is shown in FIGS. 4 and 5 as the interconnection from the multi-layer ceramic module 54 to the next-higher level assembly (in this case, the printed circuit board 58), other types of package interconnections may be used instead, including land grid pads, brazen leads, coaxial launches, pins and/or columns. Similarly, instead of the flip-chip solder bump 56B, other types of connections may be provided between the semiconductor chip 52 and the multi-layer module 54. Such connections include, for example, wire bonds and ribbons.

[0028] FIG. 6 illustrates an electronic package assembly in which a turret via 72A provides the electrical data signal path from an interconnection to the chip 52 to a metallization or other conductive layer 62B in the multi-layer ceramic substrate module 54. The turret via 72A includes electrically parallel vias to carry a data signal from the chip interconnection to the metallization layer 62B.

[0029] FIG. 7 illustrates an example of a wire-bonded electronic package assembly 80 that includes a turret via 92. A semiconductor die 82 may be attached to a multi-layer ceramic module 86, for example, through use of an epoxy 84. Input/output connections to the die may be coupled electrically to a metal trace 90 on the surface of the ceramic module through a wire bond 88. The trace may be coupled electrically through a turret via 92 to a solder ball 98 that provides the interconnection from the multi-layer ceramic module to the next-higher level assembly (in this case, the printed circuit board 104). In this example, data signals may be carried from the die 82 through the multi-layer ceramic module 86 to the printed circuit board 104 by way of the turret via 92. The turret via 92 includes electrically parallel vias and may include one or more capture pads 94 to help compensate for layer-to-layer misalignment. The solder ball interconnection 98 may be sandwiched between metallization layers 96, 102, with the lower metallization layer providing the electrical connection to the printed circuit board 104. Optional solder masks 100, 101 may be present as well.

[0030] As discussed above, using parallel vias to carry data signals may help reduce the resistance and may reduce the effective layer-to-layer inductance of the signal. Use of the turret via may be particularly advantageous for data signals at high frequencies.

[0031] Other implementations are within the scope of the claims.