Magnetic random access memory

[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-365236, filed Nov. 29, 2001, the entire contents of which are incorporated herein by reference.

[0002] 1. Field of the Invention

[0003] The present invention relates to a magnetic random access memory (MRAM) which stores therein data of 1 and 0 by utilizing the magneto resistive effect.

[0004] 2. Description of the Related Art

[0005] In recent years, although many memories which store therein data based on the new principle have been proposed, one of such memories is a magnetic random access memory which stores therein data of 1 and 0 by utilizing the tunneling magneto resistive (which will be referred to as TMR hereinafter) effect.

[0006] As a proposal of the magnetic random access memory, there is known, for example, A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell by Roy Scheuerlein at. al, ISSCC2000 Technical Digest p. 128.

[0007] The magnetic random access memory stores therein data of 1 and 0 by using TMR elements. The basic structure of the TMR element has a cap insulator sandwiched between two magnetic layers (ferromagnetic layers).

[0008] Data stored in the TMR element is judged by whether the magnetizing states of the two magnetic layers are parallel or anti-parallel. Here, parallel means that magnetizing directions of the two magnetic layers are the same, and anti-parallel means that magnetizing directions of the two magnetic layers are opposed.

[0009] Usually, an anti-ferromagnetic layer is provided as one (fixed layer) of the two magnetic layers. The anti-ferromagnetic layer is a member which fixes the direction of magnetization of the fixed layer. Actually, therefore, data (1 or 0) stored in the TMR element is determined by the direction of magnetization of the other one (free layer) of the two magnetic layers.

[0010] When the magnetizing states of the TMR element are parallel, the resistance of the cap insulator (cap insulator) sandwiched between the two magnetic layers constituting the TMR element becomes lowest. For example, this state is determined as the state 1. Further, when the magnetizing states of the TMR element are anti-parallel, the resistance of the cap insulator (cap insulator) sandwiched between the two magnetic layers constituting the TMR element becomes highest. For example, this state is determined as the state 0.

[0011] In regard to a cell array structure of the magnetic random access memory, various structures are currently examined in view of realization of the high memory capacity, stabilization of the write/read operation and others.

[0012] For example, nowadays, there is known a cell array structure in which one memory cell is constituted by one MOS transistor and one TMR element (or MTJ (Magnetic Tunnel Junction) element). Furthermore, in order to realize stabilization of the read operation, there is known a magnetic random access memory which has such a cell array structure and stores one-bit data by using two memory cell arrays.

[0013] However, the memory capacity can be hardly increased by these magnetic random access memory. That is because one MOS transistor corresponds to one TMR element in these cell array structures.

[0014] (1) According to a first aspect of the present invention, there is provided a magnetic random access memory comprising: a plurality of memory cells which are connected to each other in series and store therein data by utilizing the magneto resistive effect; a bit line which is connected to one end of a plurality of the memory cells and extends in a first direction; and a read circuit connected to the bit line.

[0015] According to a second aspect of the present invention, there is provided a magnetic random access memory comprising: a plurality of memory cells which are connected to each other in parallel and store therein data by utilizing the magneto resistive effect; a bit line which is connected to one end of a plurality of the memory cells and extends in a first direction; and a read circuit connected to the bit line, wherein resistance values of a plurality of the memory cells are different from each other even if magnetizing states of a plurality of the memory cells are the same.

[0016] (2) According to a first aspect of the present invention, there is provided a read method of a magnetic random access memory, the magnetic random access memory having a plurality of memory cells which store therein data by utilizing the magneto resistive effect, resistance values of a plurality of the memory cells being different from each other, the read method comprising: passing a read current to a plurality of the memory cells when a plurality of the memory cells are connected to each other in series; subjecting the read current or a read potential generated from the read current to analog/digital conversion; and judging data values of a plurality of the memory cells based on data obtained by the analog/digital conversion.

[0017] According to a second aspect of the present invention, there is provided a read method of a magnetic random access memory, the magnetic random access memory having a plurality of memory cells which store therein data by utilizing the magneto resistive effect, resistance values of a plurality of the memory cells being different from each other, the read method comprising: passing a read current to a plurality of the memory cells when a plurality of the memory cells are connected to each other in parallel; subjecting the read current or a read potential generated from the read current to analog/digital conversion; and judging data values of a plurality of the memory cells based on data obtained by the analog/digital conversion.

[0018] (3) According to a first aspect of the present invention, there is provided a magnetic random access memory, the read circuit being applied to a magnetic random access memory having a plurality of memory cells which store therein data by utilizing the magneto resistive effect and are connected in series or parallel, the magnetic random access memory comprising: a current source which supplies a read current to a plurality of the memory cells; an analog/digital converter which compares the read current and a plurality of reference currents or a read potential generated from the read current with a plurality of reference potentials; and a logic circuit which judges data values of a plurality of the memory cells based on an output signal from the analog/digital converter.

[0019] According to a second aspect of the present invention, there is provided a magnetic random access memory, the read circuit being applied to a magnetic random access memory having a plurality of memory cells which store therein data by utilizing the magneto resistive effect and are connected to each other in series or parallel, the magnetic random access memory comprising: a current source which supplies a read current to a plurality of the memory cells; an analog/digital converter which compares the read current and a plurality of reference currents or a read potential generated from the read current with a plurality of reference potentials; and a logic circuit which judges data values of a plurality of the memory cells based on an output signal from the analog/digital converter.

[0020] (4) According to a first aspect of the present invention, there is provided a manufacturing method of a magnetic random access memory comprising: forming a read selection switch in a surface area of a semiconductor substrate; forming on the read selection switch a first write word line which extends in a first direction; forming a first MTJ element directly above the first write word line; forming directly above the first MTJ element a first write bit line which extends in a second direction crossing the first direction; forming a second MTJ element directly above the first MTJ element; forming directly above the second MTJ element a second write word line which extends in the first direction; forming a third MTJ element directly above the second MTJ element; forming directly above the third MTJ element a second write bit line which extends in the second direction; forming a fourth MTJ element directly above the third MTJ element; forming directly above the fourth MTJ element a third write word line which extends in the first direction; and forming on the fourth MTJ active regions a bit line which extends in the second direction.

[0021] According to a second aspect of the present invention, there is provided a manufacturing method of a magnetic random access memory comprising: forming a read selection switch in a surface area of a semiconductor substrate; forming N (N is a plural number) write word lines which extends in a first direction on the read selection switch; forming a lower electrode directly above the N write word lines; forming N MTJ elements which contact the lower element directly above the N write word lines; and a read bit line which contacts the N MTJ elements and extends in a second direction crossing the first direction.

[0022] FIG. 1 is a circuit diagram concerning Structure Example 1 of a magnetic random access memory according to the present invention;

[0023] FIG. 2 is a sectional view concerning Structure Example 1 of the magnetic random access memory according to the present invention;

[0024] FIG. 3 is a sectional view concerning Structure Example 1 of the magnetic random access memory according to the present invention;

[0025] FIG. 4 is a view showing a layout of an active regions and read word lines of Structure Example 1;

[0026] FIG. 5 is a view showing a layout of source lines and write word lines of Structure Example 1;

[0027] FIG. 6 is a view showing a layout of a first TMR element and its lower electrode of Structure Example 1;

[0028] FIG. 7 is a view showing a layout of the first TMR element and its upper electrode of Structure Example 1;

[0029] FIG. 8 is a view showing a layout of a second TMR element and its lower electrode of Structure Example 1;

[0030] FIG. 9 is a view showing a layout of the second TMR element and its upper electrode of Structure Example 1;

[0031] FIG. 10 is a view showing a layout of a third TMR element and its lower electrode of Structure Example 1;

[0032] FIG. 11 is a view showing a layout of the third TMR element and its upper electrode of Structure Example 1;

[0033] FIG. 12 is a view showing a layout of a fourth TMR element and its lower electrode of Structure Example 1;

[0034] FIG. 13 is a view showing a layout of a fourth TMR element and its upper electrode of Structure Example 1;

[0035] FIG. 14 is a view showing a layout of read bit lines of Structure Example 1;

[0036] FIG. 15 is a view showing a first modification of Structure Example 1;

[0037] FIG. 16 is a circuit diagram showing a second modification of Structure Example 1;

[0038] FIG. 17 is a sectional view showing the second modification of Structure Example 1;

[0039] FIG. 18 is a circuit diagram showing a third modification of Structure Example 1;

[0040] FIG. 19 is a sectional view showing the third modification of Structure Example 1;

[0041] FIG. 20 is a circuit diagram concerning Structure Example 2 of a magnetic random access memory according to the present invention;

[0042] FIG. 21 is a sectional view concerning Structure Example 2 of the magnetic random access memory according to the present invention;

[0043] FIG. 22 is a sectional view concerning Structure Example 2 of the magnetic random access memory according to the present invention;

[0044] FIG. 23 is a view showing a layout of an active regions and read word lines of Structure Example 2;

[0045] FIG. 24 is a view showing a layout of source lines and write word lines of Structure Example 2;

[0046] FIG. 25 is a view showing a layout of a first TMR element and its lower electrode of Structure Example 2;

[0047] FIG. 26 is a view showing a layout of the first TMR element and its upper electrode of Structure Example 2;

[0048] FIG. 27 is a view showing a layout of a second TMR element and its lower electrode of Structure Example 2;

[0049] FIG. 28 is a sectional view showing a layout of the second TMR element and its upper electrode of Structure Example 2;

[0050] FIG. 29 is a view showing a layout of a third TMR element and its lower electrode of Structure Example 2;

[0051] FIG. 30 is a view showing a layout of the third TMR element and its upper electrode of Structure Example 2;

[0052] FIG. 31 is a view showing a layout of a fourth TMR element and its lower electrode of Structure Example 2;

[0053] FIG. 32 is a view showing a layout of the fourth TMR element and its upper electrode of Structure Example 2;

[0054] FIG. 33 is a view showing a layout of read bit lines of Structure Example 2;

[0055] FIG. 34 is a view showing a first modification of Structure Example 2;

[0056] FIG. 35 is a view showing the first modification of Structure Example 2;

[0057] FIG. 36 is a circuit diagram showing a second modification of Structure Example 2;

[0058] FIG. 37 is a sectional view showing the second modification of Structure Example 2;

[0059] FIG. 38 is a circuit diagram showing a third modification of Structure Example 2;

[0060] FIG. 39 is a sectional view showing the third modification of Structure Example 2;

[0061] FIG. 40 is a circuit diagram concerning Structure Example 3 of a magnetic random access memory according to the present invention;

[0062] FIG. 41 is a sectional view concerning Structure Example 3 of the magnetic random access memory according to the present invention;

[0063] FIG. 42 is a view showing a layout of an active regions and read word lines of Structure Example 3;

[0064] FIG. 43 is a view showing a layout of source lines and write word lines of Structure Example 3;

[0065] FIG. 44 is a view showing a layout of a TMR element and its lower electrode of Structure Example 3;

[0066] FIG. 45 is a view showing a layout of the TMR element and its upper electrode of Structure Example 3;

[0067] FIG. 46 is a sectional view concerning Structure Example 3 of the magnetic random access memory according to the present invention;

[0068] FIG. 47 is a view showing a layout of an active regions and read word lines of Structure Example 3;

[0069] FIG. 48 is a view showing a layout of source lines and write word lines of Structure Example 3;

[0070] FIG. 49 is a view showing a layout of a TMR element and its lower electrode of Structure Example 3;

[0071] FIG. 50 is a view showing a layout of a TMR element and its upper electrode of Structure Example 3;

[0072] FIG. 51 is a view showing an equivalent circuit during a read operation in Structure Example 1;

[0073] FIG. 52 is a view showing an equivalent circuit during the read operation in Structure Examples 2 and 3;

[0074] FIG. 53 is a view showing an equivalent circuit during the read operation in the second modification of Structure Example 1;

[0075] FIG. 54 is a view showing an equivalent circuit during the read operation in the third modification of Structure Example 1;

[0076] FIG. 55 is a view showing an equivalent circuit during the read operation in the second modification of Structure Example 2;

[0077] FIG. 56 is a view showing an equivalent circuit during the read operation in the third modification of Structure Example 2;

[0078] FIG. 57 is a view showing a structure example of a first TMR element having a lowest resistance value;

[0079] FIG. 58 is a view showing a structure example of a second TMR element having a second lowest resistance value;

[0080] FIG. 59 is a view showing a structure example of a third TMR element having a third-lowest resistance value;

[0081] FIG. 60 is a view showing a structure example of a fourth TMR element having a highest resistance value;

[0082] FIG. 61 is a view showing a structure example of the first TMR element having the lowest resistance value;

[0083] FIG. 62 is a view showing a structure example of the second TMR element having the second lowest resistance value;

[0084] FIG. 63 is a view showing a structure example of the third TMR element having the third lowest resistance value;

[0085] FIG. 64 is a view showing a structure example of the fourth TMR element having the highest resistance value;

[0086] FIG. 65 is a view showing Circuit Example 1 of a read circuit concerning the present invention;

[0087] FIG. 66 is a view showing a logic circuit which judges a data value of the fourth TMR element;

[0088] FIG. 67 is a view showing a logic circuit which judges a data value of the third TMR element;

[0089] FIG. 68 is a view showing a logic circuit which judges a data value of the second TMR element;

[0090] FIG. 69 is a view showing a logic circuit which judges a data value of the first TMR element;

[0091] FIG. 70 is a view showing Circuit Example 2 of the read circuit concerning the present invention;

[0092] FIG. 71 is a view showing a concrete example of a reference current generation circuit;

[0093] FIG. 72 is a view showing a logic circuit which judges a data value of the first TMR element;

[0094] FIG. 73 is a view showing a logic circuit which judges a data value of the second TMR element;

[0095] FIG. 74 is a view showing a logic circuit which judges a data value of the third TMR element;

[0096] FIG. 75 is a view showing a logic circuit which judges a data value of the fourth TMR element;

[0097] FIG. 76 is a view showing a concrete example of a reference potential generation circuit;

[0098] FIG. 77 is a view showing a circuit example of a write word line driver/sinker;

[0099] FIG. 78 is a view showing a circuit example of a bit word line driver/sinker;

[0100] FIG. 79 is a view showing a circuit example of a read word line driver;

[0101] FIG. 80 is a view showing a circuit example of a column decoder;

[0102] FIG. 81 is a view showing a device structure to which a manufacturing method 1 according to the present invention is applied;

[0103] FIG. 82 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0104] FIG. 83 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0105] FIG. 84 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0106] FIG. 85 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0107] FIG. 86 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0108] FIG. 87 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0109] FIG. 88 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0110] FIG. 89 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0111] FIG. 90 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0112] FIG. 91 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0113] FIG. 92 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0114] FIG. 93 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0115] FIG. 94 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0116] FIG. 95 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0117] FIG. 96 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0118] FIG. 97 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0119] FIG. 98 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0120] FIG. 99 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0121] FIG. 100 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0122] FIG. 101 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0123] FIG. 102 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0124] FIG. 103 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0125] FIG. 104 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0126] FIG. 105 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0127] FIG. 106 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0128] FIG. 107 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0129] FIG. 108 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0130] FIG. 109 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0131] FIG. 110 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0132] FIG. 111 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0133] FIG. 112 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0134] FIG. 113 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0135] FIG. 114 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0136] FIG. 115 is a sectional view showing one step of the manufacturing method 1 according to the present invention;

[0137] FIG. 116 is a view showing a device structure to which a manufacturing method 2 according to the present invention is applied;

[0138] FIG. 117 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0139] FIG. 118 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0140] FIG. 119 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0141] FIG. 120 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0142] FIG. 121 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0143] FIG. 122 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0144] FIG. 123 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0145] FIG. 124 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0146] FIG. 125 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0147] FIG. 126 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0148] FIG. 127 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0149] FIG. 128 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0150] FIG. 129 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0151] FIG. 130 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0152] FIG. 131 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0153] FIG. 132 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0154] FIG. 133 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0155] FIG. 134 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0156] FIG. 135 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0157] FIG. 136 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0158] FIG. 137 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0159] FIG. 138 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0160] FIG. 139 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0161] FIG. 140 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0162] FIG. 141 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0163] FIG. 142 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0164] FIG. 142 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0165] FIG. 143 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0166] FIG. 144 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0167] FIG. 145 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0168] FIG. 146 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0169] FIG. 147 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0170] FIG. 148 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0171] FIG. 149 is a sectional view showing one step of the manufacturing method 2 according to the present invention;

[0172] FIG. 150 is a view showing a device structure to which a manufacturing method 3 according to the present invention is applied;

[0173] FIG. 151 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0174] FIG. 152 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0175] FIG. 153 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0176] FIG. 154 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0177] FIG. 155 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0178] FIG. 156 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0179] FIG. 157 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0180] FIG. 158 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0181] FIG. 159 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0182] FIG. 160 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0183] FIG. 161 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0184] FIG. 162 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0185] FIG. 163 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0186] FIG. 164 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0187] FIG. 165 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0188] FIG. 166 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0189] FIG. 167 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0190] FIG. 168 is a sectional view showing one step of the manufacturing method 3 according to the present invention;

[0191] FIG. 169 is a sectional view showing a modification of the device structure according to the present invention;

[0192] FIG. 170 is a sectional view showing the modification of the device structure according to the present invention;

[0193] FIG. 171 is a plane view showing the modification of the device structure according to the present invention;

[0194] FIG. 172 is a view showing a modification of a read circuit according to the present invention;

[0195] FIG. 173 is a view showing a modification of a reference current generation circuit according to the present invention; and

[0196] FIG. 174 is a view showing a modification of the read circuit according to the present invention.

[0197] A magnetic random access memory of an aspect of the present invention will be described below in detail with reference to the accompanying drawings.

[0198] 1. Cell Array Structure

[0199] First, a cell array structure of a magnetic random access memory of an aspect of the present invention will be described below in detail.

[0200] (1) Structure Example (1)

[0201] Structure example 1 concerns the cell array structure in which a plurality of TMR elements superposed in a plurality of stages are connected to each other in series.

[0202] {circle over (1)} Circuit Structure

[0203] The circuit structure will first be described.

[0204] FIG. 1 shows primary parts of a magnetic random access memory as Structure Example 1 according to the present invention.

[0205] The memory cell array 11 has a plurality of TMR elements 12 arranged in the form of an array in directions X, Y and Z. Here, the Z-direction means a direction which is orthogonal to the directions X and Y.

[0206] In this example, the memory cell array 11 has a cell array structure consisting of j1 TMR elements 12 arranged in the X-direction, n1 TMR elements 12 arranged in the Y-direction and four TMR elements 12 superposed in the Z-direction. Although a number of the TMR elements 12 superposed in the Z-direction is four in this example, it can be any number as long as it is a plural number.

[0207] The four TMR elements 12 superposed in the Z-direction are connected to each other in series and constitute one block BKik (i0, 1, . . . j, k0, 1, . . . n). The four TMR elements 12 in the block BKik are actually superposed each other in a direction vertical to the memory cell array plane (Z-direction).

[0208] One end of the four TMR elements 12 in the block BKik is connected to a ground point through a read selection switch (MOS transistor) RSW.

[0209] In this example, one row is constituted by j1 blocks BKik arranged in the X-direction. The memory cell array 11 has n1 rows. Further, one column is constituted by n1 blocks BKik arranged in the Y-direction. The memory cell array 11 has j1 columns.

[0210] A plurality of (three in this example) write word liens WWL3n, WWL3n1, WWL3n2 which extend in the X-direction and are superposed in the Z-direction are arranged in the vicinity of the four TMR elements 12 constituting the block BKik. However, n is a number of each row, and n0, 1, 2, . . .

[0211] In regard to the write word line extending in the X-direction, one write word line can be arranged on one stage in one row. In this case, a number of the write word lines in one row extending in the X-direction is four, namely, equal to a number of stages in which the TMR elements 12 are superposed.

[0212] Here, however, at least one of the write word lines in one row extending in the X-direction is shared by the two TMR elements (the upper TMR element and the lower TMR element). Specifically, in this example, the write word line WWL3n1 is shared by the TMR elements on the second and third stages. In this case, since a number of the write word lines is decreased, planation of the insulating film directly below the TMR elements 12 or reduction in the manufacturing cost can be realized.

[0213] In terms of the block structure, a number of the write word lines in one row extending in the X-direction can be two when one write word line is shared by the TMR elements on the first and second stages and one write word line is shared by the TMR elements on the third and fourth stages, as shown in FIGS. 169 and 170.

[0214] Nevertheless, a number of the write word lines in one row extending in the X-direction is determined as three in this example because positions of the write bit lines in one column extending in the Y-direction are taken into consideration.

[0215] That is, in this example, one write bit line BLj0 extending in the Y-direction is arranged between the TMR element 12 on the first stage and the TMR element 12 on the second stage, and one write bit line BLj1 extending in the Y-direction is arranged between the TMR element 12 on the third stage and the TMR element 12 on the fourth stage.

[0216] As a result, as to the write bit lines in one column extending in the Y-direction, the TMR elements on the first and second stages share one write bit line, and the TMR elements on the third and fourth stages share one write bit line. In this case, a number of write bit lines in one column extending in the Y-direction is two.

[0217] Incidentally, in FIG. 1, the two write bit lines BLj0 and BLj1 sandwich the four TMR elements 12 in the block BKjn there between in the drawing since the TMR elements 12 can not be three-dimensionally drawn. Actually, however, one write bit line BLj0 is arranged between the TMR element on the first stage and the TMR element on the second stage and one write bit line BLj1 is arranged between the TMR element on the third stage and the TMR element on the fourth stage as described above.

[0218] The concrete structures of the TMR elements in the block and those in the vicinity thereof will become apparent in explanation of the later-described device structure.

[0219] One end of the write word lines WWL3n, WWL3n1, WWL3n2 extending in the X-direction is connected to a write word line driver 23A-n, and the other end of the same is connected to a write word line sinker 24-n.

[0220] A gate of the read selection switch RSW is connected to read word lines RWLn (n0, 1, 2, . . . ) One read word line RWLn corresponds to one block BKjk in one column and is common to a plurality of blocks BKjk arranged in the X-direction.

[0221] For example, when one column is constituted by four blocks, a number of read word lines RWLn is four. The read word lines RWLn extend in the X-direction, and one end there of is connected to a read word line driver 23B-n.

[0222] A row decoder 25-n selects one of the write word lines WWL3n, WWL3n1 and WWL3n2 based on a row address signal during the write operation. The write word line driver 23A-n supplies a write current to the selected write word line. The write current flows through the selected word line and is absorbed into the write word line sinker 24-n.

[0223] The row decoder 25-n selects blocks in one row during the read operation based on, e.g., high order row address signals. The read word line driver 23B-n supplies a word line voltage to the read word line RWLn connected to the selected blocks BK0n, . . . BKjn. Since the read selection switch RSW enters the on state in the selected blocks BK0n, . . . BKjn, the read current flows to a ground point through a plurality of the TMR elements in the selected blocks BK0n, . . . BKjn.

[0224] The other end of the four TMR elements in the block BKik is connected to the read bit line BLj. One end of the read bit lines BLj is connected to a common data line 28 through a column selection switch (MOS transistor) SWA. The common data line 28 is connected to a read circuit (including a sense amplifier) 29B.

[0225] One end of the write bit lines BLj0 and BLj1 is connected to a circuit block 29A including the write bit line driver and the write bit line sinker.

[0226] The other end of the write bit lines BLj0 and BLj1 is connected to a circuit block 31 including the write bit line driver and the write bit line sinker.

[0227] A column selection line signal CSLj (j0, 1, . . . ) is inputted to a gate of a column selection switch SWA. A column decoder 32 outputs the column selection line signal CSLj.

[0228] In the magnetic random access memory of this example, one column is constituted by a plurality of blocks and performs reading in units of block. Furthermore, one block is constituted by a plurality of TMR elements which are superposed in a plurality of stages and connected to each other in series.

[0229] When such a cell array structure is adopted, the TMR elements can be three-dimensionally arranged on the semiconductor substrate, and associating one MOS transistor (read selection switch) with a plurality of the TMR elements can suffice. Thus, as a result, this can contribute to increase in the memory capacity.

[0230] {circle over (2)} By Device Structure 1

[0231] The device structure will now be described.

[0232] FIGS. 2 and 3 show the device structure of one block of the magnetic random access memory as Structure Example 1 according to the present invention.

[0233] FIG. 2 shows a cross section of one block of the magnetic random access memory in the Y-direction, and FIG. 3 shows a cross section of one block of the magnetic random access memory in the X-direction. Elements shown in FIGS. 2 and 3 are denoted by the same reference numerals as those in FIG. 1 so that they can correspond to the elements in the circuit of FIG. 1.

[0234] A read selection switch (MOS transistor) RSW is arranged in a surface area of a semiconductor substrate 41. A source of the read selection switch RSW is connected to a ground point through the source line SL. The source line SL extends straightway in, e.g., the X-direction.

[0235] A gate of the read selection switch (MOS transistor) RSW is a read word line RWLn. The read word line RWLn extends in the X-direction. Four TMR elements (MTJ (Magnetic Tunnel Junction) elements) MTJ1, MTJ2, MTJ3 and MTJ4 are superposed on the read selection switch RSW.

[0236] The respective TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are arranged between the lower electrodes 41A1, 41A2, 41A3 and 41A4 and the upper electrodes 41B1, 41B2, 41B3 and 41B4. Contact plugs 42B, 42C, 42D, 42E and 42F connects the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 to each other in series.

[0237] The lower electrode 41A1 of the TMR element MTJ1 on the lowermost stage is connected to a drain of the read selection switch (MOS transistor) RSW through the contact plugs 42A and 42B and an intermediate layer 43. The upper electrode 41B4 of the TMR element MTJ4 on the uppermost stage is connected to the read bit line BLj which extends in the Y direction through the contact plug 42F.

[0238] The write word line WWL3n is arranged directly below the TMR element MTJ1, the write word line WWL3n1 is arranged between the TMR element MTJ2 and the TMR element MTJ3, and the write word line WWL3n2 is arranged directly above the TMR element MTJ4. The write word lines WWL3n, WWL3n1 and WWL3n2 extend in the X-direction.

[0239] The write bit line BLj0 is arranged between the TMR element MTJ1 and the TMR element MTJ2, and the write bit line BLj1 is arranged between the TMR element MTJ3 and the TMR element MTJ4. The write bit lines BLj0 and BLj1 extend in the Y-direction.

[0240] According to such a device structure, a plurality of (four in this example) the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are provided with respect to one read selection switch RSW. Further, these TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are superposed on the read selection switch RSW and connected to each other in series.

[0241] Furthermore, in this case, providing only one read bit line BLj to, e.g., the uppermost layer can suffice. Moreover, at least one of the write word lines WWL3n, WWL3n1 and WWL3n2 and the write bit lines BLj0 and BLj1 can be shared by two TMR elements.

[0242] Therefore, according to such a device structure, the TMR elements can be arranged on the semiconductor substrate with the high density, which contributes to increase in the memory capacity. In addition, since a number of wirings arranged in the array of the TMR elements (for example, the write word lines, the write bit lines, the read bit lines or the like) can be reduced, planation of the insulating film directly below the TMR elements can be realized, thereby improving the characteristic of the TMR elements.

[0243] {circle over (3)} Device Structure 2

[0244] Description will now be given as to a plane layout in each stage (or each wiring layer) of the magnetic random access memory shown in FIGS. 2 and 3.

[0245] FIG. 4 shows a layout of the active regions and the read word lines.

[0246] The active regions 42 on the semiconductor substrate 41 is surrounded by an element separation area 43x. The active regions 42 means an area forming the read selection switch (MOS transistor).

[0247] The read word lines RWL0, RWL1 and RWL2 which extend in the X-direction and cut across the active regions 42 are arranged on the semiconductor substrate 41. Each read word lines of RWL0, RWL1 and RWL2 is a gate electrode of a group of the read selection switches (MOS transistors), respectively.

[0248] The active regions on one side of the read word lines RWL0, RWL1 and RWL2 becomes a source of the read selection switch, and the active regions on the other side of the read word lines RWL0, RWL1 and RWL2 becomes a drain of the read selection switch.

[0249] A contact portion 44A is a source contact portion with respect to the source of the read selection switch, and a contact portion 44B is a drain contact portion with respect to the drain of the read selection switch.

[0250] FIG. 5 shows a layout of the source lines SL and the write word lines WWL3n.

[0251] The source lines SL extend in the X-direction. The intermediate layer 43 is formed in the same wiring layer as the source line SL. The intermediate layer 43 serves to prevent a contact hole having a high aspect ratio from being formed. A contact portion 47 represents a contact portion relative to the intermediate layer 43 and the lower electrode of the TMR element on the first stage (lowermost stage).

[0252] The write word line WWL3n acts as a write word line with respect to the TMR element on the first stage. The write word line WWL3n is, as apparent from FIGS. 2 and 3, arranged above the source line SL and the intermediate layer 43 and directly below the TMR element MTJ1 on the first stage. The write word line WWL3n extends in the X-direction.

[0253] FIG. 6 shows a layout of the TMR element MTJ1 on the first stage and its lower electrode 41A1.

[0254] The lower electrode 41A1 is, for example, rectangular and regularly arranged. The TMR element MTJ1 on the first stage is arranged above the lower electrode 41A1. A position at which the TMR element MTJ1 is arranged is, for example, a position at which it does not overlap the contact portion 47.

[0255] FIG. 7 shows a layout of the upper electrode 41B1 of the TMR element MTJ1 on the first stage and the write bit lines BL00 and BL10.

[0256] The upper electrode 41B1 is, for example, rectangular and is arranged so as to overlap the lower electrode of the TMR element on the first stage. The contact portion 49 represents a contact portion with respect to the upper electrode 41B1 of the TMR element on the first stage and the lower electrode of the TMR element on the second stage.

[0257] The write bit lines BL00 and BL10 are arranged directly above the TMR element on the first stage and extend in the Y-direction. Additionally, as apparent from FIGS. 2 and 3, the write bit liens BL00 and BL10 are arranged directly below the TMR element on the second stage. The write bit lines BL00 and BL10 act as the write bit lines with respect to the TMR elements on the first and second stages.

[0258] FIG. 8 shows a layout of the TMR element MTJ2 on the second stage and its lower electrode 41A2.

[0259] The lower electrode 41A2 is, for example, rectangular and is regularly arranged. The TMR element on the second stage is arranged above the lower electrode 41A2. A position at which the TMR element MTJ2 is arranged is, for example, a position at which it does not overlap the contact portion 49.

[0260] FIG. 9 shows a layout of the upper electrode 41B2 of the TMR element MTJ2 on the second stage and the write word line WWL3n.

[0261] The upper electrode 41B2 is, for example, rectangular and is arranged so as to overlap the lower electrode of the TMR element on the second stage. The contact portion 50 represents a contact portion with respect to the upper electrode 41B2 of the TMR element on the second stage and the lower electrode of the TMR element on the third stage.

[0262] The write word line WWL3n1 acts as the write word line relative to the TMR elements on the second and third stages. As apparent from FIGS. 2 and 3, the write word line WWL3n1 is arranged between the TMR element MTJ2 on the second stage and the TMR element MTJ3 on the third stage and extends in the X-direction.

[0263] FIG. 10 shows a layout of the TMR element MTJ3 on the third stage and its lower electrode 41A3.

[0264] The lower electrode 41A3 is, for example, rectangular and is regularly arranged. The TMR element MTJ3 on the third stage is arranged on the lower electrode 41A3. A position at which the TMR element MTJ3 is arranged, for example, a position at which it does not overlap the contact portion 50.

[0265] FIG. 11 shows a layout of the upper electrode 41B3 of the TMR element MTJ3 on the third stage and the write bit lines BL01 and BL11.

[0266] The upper electrode 41B3 is, for example, rectangular and is arranged so as to overlap the lower electrode of the TMR element on the third stage. The contact portion 51 represents a contact portion with respect to the upper electrode 41B3 of the TMR element on the third stage and the lower electrode of the TMR element on the fourth stage.

[0267] The write bit lines BL01 and BL11 are arranged directly above the TMR element on the third stage and extend in the Y-direction. Further, as apparent from FIGS. 2 and 3, the write bit lines BL01 and BL11 are arranged directly below the TMR element on the fourth stage. The write bit lines BL01 and BL11 act as the write bit lines with respect to the TMR elements on the third and fourth stages.

[0268] FIG. 12 shows a layout of the TMR element MTJ4 on the fourth stage and its lower electrode 41A4.

[0269] The lower electrode 41A4 is, for example, rectangular and is regularly arranged. The TMR element MTJ4 on the fourth stage is arranged on the lower electrode 41A4. A position at which the TMR element MTJ4 is arranged is, for example, a position at which it does not overlap the contact portion 51.

[0270] FIG. 13 shows a layout of the upper electrode 41B4 of the TMR element MTJ4 on the fourth stage and the write word line WWL3n2.

[0271] The upper electrode 41B4 is, for example, rectangular and is arranged so as to overlap the lower electrode of the TMR element on the fourth stage. The contact portion 52 represents a contact portion between the upper electrode 41B4 of the TMR element on the fourth stage and the read bit line.

[0272] The write word line WWL3n2 acts as the write word line with respect to the TMR element on the fourth stage. The write word line WWL3n2 is, as apparent from FIGS. 2 and 3, arranged directly above the TMR element MTJ4 on the fourth stage and extends in the X-direction.

[0273] FIG. 14 shows a layout of the read bit lines BL0 and BL1.

[0274] The read bit lines BL0 and BL1 extend in the Y-direction. Each one of the read bit lines BL0 and BL1 is arranged in one column and commonly connected to the block in one column. The contact portion 52 represents a contact portion between the upper electrode of the TMR element on the fourth stage and the read bit liens BL0 and BL1.

[0275] {circle over (4)} Modifications

[0276] Modifications of Structure Example 1 will now be described.

[0277] FIG. 15 shows a first modification of Structure Example 1.

[0278] This drawing corresponds to FIG. 2. The device structure of this example is different from that in FIG. 2 in the positions at which the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are superposed.

[0279] That is, in the device structure shown in FIG. 2, the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are superposed directly above the gate electrode of the read selection switch (MOS transistor) RSW, i.e., the read word line RWLn. On the contrary, in the device structure of this example, the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are superposed directly above the source line SL connected to the source of the read selection switch (MOS transistor) RSW.

[0280] In order to realize high integration of the TMR elements, for example, sharing one source line SL by two blocks adjacent in the Y-direction is effective. When such sharing of the source line is taken into consideration, it can be said that the device structure shown in FIG. 2 is superior to the device structure illustrated in FIG. 15.

[0281] FIGS. 16 and 17 show a second modification of Structure Example 1.

[0282] The circuit diagram of FIG. 16 corresponds to the circuit diagram of FIG. 1, and a sectional view showing the device structure in FIG. 17 corresponds to a sectional view showing the device structure in FIG. 2. The structure of this example is different from the structures shown in FIGS. 1 and 2 in an element which realizes the read selection switch.

[0283] That is, in the structures shown in FIGS. 1 and 2, the read selection switch is constituted by the MOS transistor. On the other hand, in the structure of this example, the read selection switch is constituted by a diode DI. Herewith, the read word lines RWL0, . . . , RWLn are connected to a cathode of the diode DI.

[0284] When adopting the structure of this example, the read word line RWLi of the selected row is set to L, i.e., the ground potential during the read operation. At this moment, the read current can be caused to flow to a plurality of the TMR elements which constitute the block of the selected row and connected to each other in series.

[0285] FIGS. 18 and 19 show a third modification of Structure Example 1.

[0286] A circuit diagram of FIG. 18 corresponds to a circuit diagram of FIG. 1, and a sectional view showing the device structure in FIG. 19 corresponds to a sectional view showing the device structure in FIG. 2. The structure of this example is different from the structures in FIGS. 1 and 2 in types of the transistors constituting the memory cell array 11 and the peripheral circuit thereof.

[0287] That is, in the structures of FIGS. 1 and 2, the transistors constituting the memory cell array 11 and its peripheral circuit are the MOS transistors. On the contrary, in the structure of this example, the transistors constituting the memory cell array 11 and its peripheral circuit are bipolar transistors.

[0288] In case of the structure of this example, all of the transistors constituting the memory cell array 11 and its peripheral circuit may be bipolar transistors or some of them may be bipolar transistors.

[0289] (2) Structure Example 2

[0290] Structure example 2 concerns a cell array structure in which a plurality of TMR elements superposed in a plurality of stages are connected to each other in parallel.

[0291] {circle over (1)} Circuit Configuration

[0292] The circuit configuration will be first described.

[0293] FIG. 20 shows primary parts of the magnetic random access memory as Structure Example 2 according to the present invention.

[0294] The memory cell array 11 has a plurality of TMR elements 12 arranged in the form of an array in directions X, Y and Z. The Z-direction means a direction which is orthogonal to the directions X and Y.

[0295] The memory cell array 11 has a cell array structure consisting of j1 TMR elements 12 arranged in the X-direction, n1 TMR elements 12 arranged in the Y-direction and four TMR elements 12 superposed in the Z-direction. Although a number of the TMR elements 12 superposed in the Z-direction is four in this example, it may be any number as long as it is a plural number.

[0296] The four TMR elements 12 superposed in the Z-direction are connected to each other in parallel and constitute one block BKik (i0, 1, . . . , j, k0, 1, . . . n). The four TMR elements in the block BKik actually overlap each other in the direction vertical to the memory cell array plane (Z-direction).

[0297] One end of the four TMR elements in the block BKik is connected to the contact point through the read selection switch (MOS transistor) RSW.

[0298] In this example, one row is constituted by j1 blocks BKik arranged in the X-direction. The memory cell array 11 has n1 rows. Furthermore, one column is constituted by n1 blocks BKik arranged in the Y-direction. The memory cell array 11 has j1 columns.

[0299] In the vicinity of the four TMR elements 12 constituting the block BKik, a plurality of (three in this example) write word lines WWL3n, WWL3n1 and WWL3n2 which extend in the X-direction and are superposed in the Z-direction are arranged. However, n is a number of each row, and n0, 1, 2, . . .

[0300] In regard to the write word lines extending in the X-direction, one write word line can be arranged on one stage in one row. In this case, a number of the write word lines in one row which extend in the X-direction is four, namely, equal to a number of stages on which the TMR elements 12 are superposed. As described in connection with Structure Example 1, however, increase in number of the write word lines in one row which extend in the X-direction is disadvantageous in planation of the insulating film directly below the TMR elements 12 or reduction in the manufacturing cost.

[0301] Thus, in this example, at least one of the write word lines in one row which extend in the X-direction is shared by two TMR elements (the TMR element on the upper stage and the TMR element on the lower stage). Specifically, in this example, the write word line WWL3n1 is shared by the TMR element on the second stage and the TMR element on the third stage.

[0302] In terms of the block structure, if one write word line is shared by the TMR elements on the first and second stages and one write word line is shared by the TMR elements on the third and fourth stages, a number of the write word lines in one row which extend in the X-direction can be two. Nevertheless, a number of the write word lines in one row which extend in the X-direction is three in this example because positions of the write bit lines in one column which extend in the Y-direction are taken into consideration.

[0303] That is, in this example, one write bit line BLj0 which extends in the Y-direction is arranged between the TMR element 12 on the first stage and the TMR element on the second stage, and one write bit line BLj1 which extends in the Y-direction is arranged between the TMR element 12 on the third stage and the TMR element 12 on the fourth stage.

[0304] As a result, in regard to the write bit lines in one column which extend in the Y-direction, one write bit line is shared by the TMR elements on the first and second stages and one write bit line is shared by the TMR elements on the third and fourth stages. In this case, a number of the write bit lines in one column which extend in the Y-direction is two.

[0305] Incidentally, in FIG. 20, the two write bit lines BLj0 and BLj1 are illustrated so as to cross the four TMR elements in the block BKjn because the TMR elements 12 can not be three-dimensionally drawn. Practically, however, as described above, one write bit line BLj0 is arranged between the TMR element on the first stage and the TMR element on the second stage, and one write bit line BLj1 is arranged between the TMR element on the third stage and the TMR element on the fourth stage.

[0306] The concrete structure of the TMR elements in the block and in the vicinity thereof will be revealed in explanation of the later-described device structure.

[0307] One end of the write word lines WWL3n, WWL3n1 and WWL3n2 which extend in the X-direction is connected to the write word line driver 23A-n, and the other end of the same is connected to the write word line sinker 24-n.

[0308] A gate of the read selection switch RSW is connected to the read word line RWLn (n0, 1, 2, . . . ) One read word line RWLn corresponds to one block BKjk in one column and are common to a plurality of blocks BKjk arranged in the X-direction.

[0309] For example, when one column is constituted by four blocks, a number of the read word lines RWLn is four. The read word lines RWLn extend in the X-direction and one end thereof is connected to the read word line driver 23B-n.

[0310] The row decoder 25-n selects one of the write word lines WWL3n, WWL3n1, WWL3n2 based on a row address signal during the write operation. The write word line driver 23A-n supplies the write current to the selected write word line. The write current flows through the selected word line and is absorbed into the write word line sinker 24-n.

[0311] The row decoder 25-n selects blocks in one row based on, e.g., high order row address signals during the read operation. The read word line driver 23B-n supplies the read word line voltage to the read word line RWLn connected to the selected blocks BK0n, . . . BKjn. Since the read selection switch RSW enters the on state in the selected blocks BK0n, . . . BKjn, the read current passes through a plurality of the TMR elements in the selected blocks BK0n, . . . BKjn and flows to the ground point.

[0312] The other end of the four TMR elements in the block BKik is connected to the read bit line BLj. One end of the read bit lines BLj is connected to the common data line 28 through the column selection switch (MOS transistor) SWA. The common data line 28 is connected to the read circuit (including a sense amplifier) 29B.

[0313] One end of the write bit lines BLj0 and BLj1 is connected to the circuit block 29A including the write bit line driver and the write bit line sinker.

[0314] The other end of the write bit lines BLj0 and BLj1 is connected to the circuit block 31 including the write bit line driver and the write bit line sinker.

[0315] A column selection line signal CSLj (j0, 1, . . . ) is inputted to a gate of the column selection switch SWA. The column decoder 32 outputs the column selection line signal CSL.

[0316] In the magnetic random access memory of this example, one column is constituted by a plurality of blocks and performs reading in units of block. Moreover, one block is constituted by a plurality of TMR elements which are superposed in a plurality of stages and connected to each other in parallel.

[0317] With such a cell array structure, the TMR elements can be three-dimensionally arranged on the semiconductor substrate and associating one MOS transistor (read selection switch) with a plurality of the TMR elements can suffice, and hence this contributes to increase in the memory capacity.

[0318] {circle over (2)} Device Structure 1

[0319] The device structure will now be described.

[0320] FIGS. 21 and 22 show the device structure of one block of the magnetic random access memory as Structure Example 2 according to the present invention.

[0321] FIG. 21 shows a cross section of one block of the magnetic random access memory in the Y-direction, and FIG. 22 shows a cross section of one block of the magnetic random access memory in the X-direction. Elements shown in FIGS. 21 and 22 are denoted by the same reference numerals as those in FIG. 20 so that they can correspond to elements of the circuit in FIG. 20.

[0322] A read selection switch (MOS transistor) RSW is arranged in a surface area of the semiconductor substrate 41. A source of the read selection switch RSW is connected to the ground point through a source line SL. The source line SL extends in, for example, the X-direction straightway.

[0323] A gate of the read selection switch (MOS transistor) RSW is the read word line RWLn. The read word line RWLn extends in the X-direction. Four TMR elements (MTJ (Magnetic Tunnel Junction) elements) MTJ1, MTJ2, MTJ3 and MTJ4 are superposed on the read selection switch RSW.

[0324] The respective TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are arranged between the lower electrodes 41A1, 41A2, 41A3 and 41A4 and the upper electrodes 41B1, 41B2, 41B3 and 41B4. Contact plugs 42C1, 42C2, 42D1, 42E1 and 42E1 are connect the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 to each other in parallel.

[0325] The lower electrode 41A1 of the TMR element MTJ1 on the lowermost stage is connected to a drain of the read selection switch (MOS transistor) RSW through the contact plugs 42A and 42B and an intermediate layer 43. The upper electrode 41B4 of the TMR element MTJ4 on the uppermost stage is connected to the read bit line BLj which extends in the Y-direction through the contact plug 42F.

[0326] The write word line WWL3n is arranged directly below the TMR element MTJ1, the write word line WWL3n1 is arranged between the TMR element MTJ2 and the TMR element MTJ3, and the write word line WWL3n2 is arranged directly above the TMR element MTJ4. The write word lines WWL3n, WWL3n1 and WWL32 extend in the X-direction.

[0327] The write bit line BLj0 is arranged between the TMR element MTJ1 and the TMR element MTJ2, and the write bit line BLj1 is arranged between the TMR element MTJ3 and the TMR element MTJ4. The write bit lines BLj0 and BLj1 extend in the Y-direction.

[0328] According to such a device structure, a plurality of (four in this example) the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are provided to one read selection switch RSW. In addition, these TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are superposed on the read selection switch RSW and connected to each other in parallel.

[0329] Additionally, in this case, providing only one read bit line BLj to, e.g., the uppermost layer can suffice. Further, at least one of the write word lines WWL3n, WWL3n1, WWL3n2 and the write bit lines BLj0 and BLj1 can be shared by two TMR elements.

[0330] Therefore, according to such a device structure, the TMR elements can be arranged on the semiconductor substrate with the high density, which contributes to increase in the memory capacity. Further, since a number of wirings arranged in the array of the TMR elements (for example, the write word lines, the write bit lines, the read bit lines or the like) can be reduced, planation of the insulating film directly below the TMR elements can be realized, thereby improving the characteristic of the TMR elements.

[0331] {circle over (3)} Device Structure 2

[0332] Description will now be given as to a plane layout in each stage (or each wiring layer) of the magnetic random access memory shown in FIGS. 21 and 22.

[0333] FIG. 23 shows a layout of an active regions and read word lines.

[0334] The active regions 42 on the semiconductor substrate 41 is surrounded by the element separation area 43x. The active regions 42 means an area forming the read selection switch (MOS transistor).

[0335] Read word lines RWL0, RWL1 and RWL2 which extend in the X-direction and cut across the active regions 42 are arranged on the semiconductor substrate 41. Each read word lines of RWL0, RWL1 and RWL2 is a gate electrode of a group of the read selection switches (MOS transistors), respectively.

[0336] The active regions on one side of the read word lines RWL0, RWL1 and RWL2 becomes a source of the read selection switch, and the active regions on the other side of the read word lines RWL0, RWL1 and RWL2 becomes a drain of the read selection switch.

[0337] The contact portion 44A is a source contact portion relative to the source of the read selection switch, and the contact portion 44B is a drain contact portion relative to the drain of the read selection switch.

[0338] In this example, as apparent from FIGS. 21 and 22, since the TMR elements are connected to each other in parallel, a number of the contact plugs increases, and it is hard to reduce the distance between the two blocks adjacent to each other in the column direction.

[0339] Thus, in this example, the contact portion 44A with respect to the source of the read selection switch is provided in accordance with each block.

[0340] However, two block which are adjacent to each other in the column direction likewise share one source line. That is, two blocks which are adjacent to each other in the column direction share one source line also in Structure Example 2, as similar to Structure Example 1.

[0341] FIG. 24 shows a layout of the source lines SL and the write word lines WWL3n.

[0342] The source line SL extends in the X-direction. The source line SL is connected to the source of the read selection switch in two blocks which are adjacent to each other in the column direction.

[0343] The intermediate layer 43 is formed in the same wiring layer as that of the source line SL. The intermediate layer 43 serves to prevent a contact hole having a high aspect ratio from being formed. The contact portion 47 represents a contact portion between the intermediate layer 43 and the lower electrode of the TMR element on the first stage (lowermost stage).

[0344] The write word line WWL3n acts as the write word line with respect to the TMR element on the first stage. As apparent from FIGS. 21 and 22, the write word line WWL3n is arranged above the source line SL and the intermediate layer 43 and directly below the TMR element on the first stage. The write word line WWL3n extends in the X-direction.

[0345] FIG. 25 shows a layout of the TMR element MTJ1 on the first stage and its lower electrode 41A1.

[0346] The lower electrode 41A1 is, for example, rectangular and is regularly arranged. The TMR element MTJ1 on the first stage is arranged on the lower electrode 41A1. A position at which the TMR element MTJ1 is arranged is, for example, a position at which it does not overlap the contact portion 47.

[0347] FIG. 26 shows a layout of the upper electrode 41B1 of the TMR element MTJ1 on the first stage and the write bit lines BL00 and BL10.

[0348] The upper electrode 41B1 is, for example, rectangular and is arranged so as to overlap the lower electrode of the TMR element on the first stage. The contact portion 49 represents a contact portion between the upper electrode 41B1 of the TMR element on the first stage and the lower electrode of the TMR element on the second stage.

[0349] The write bit lines BL00 and BL10 are arranged directly above the TMR element on the first stage and extend in the Y-direction. Furthermore, as apparent from FIGS. 21 and 22, the write bit lines BL00 and BL10 are arranged directly below the TMR element on the second stage. The write bit lines BL00 and BL10 act as the write bit lines with respect to the TMR elements on the first and second stages.

[0350] FIG. 27 shows a layout of the TMR element MTJ2 on the second stage and its lower electrode 41A2.

[0351] The lower electrode 41A2 is, for example, rectangular and is regularly arranged. The TMR element MTJ2 on the second stage is arranged on the lower electrode 41A2. A position at which the TMR element MTJ2 is arranged is, for example, a position at which it does not overlap the contact portion 49.

[0352] FIG. 28 shows a layout of the upper electrode 41B2 of the TMR element MTJ2 on the second stage and the write word line WWL3n1.

[0353] The upper electrode 41B2 is, for example, rectangular and is arranged so as to overlap the lower electrode of the TMR element on the second stage. The contact portion 50 represents a contact portion between the upper electrode 41B2 of the TMR element on the second stage and the lower electrode of the TMR element on the third stage.

[0354] The write word line WWL3n1 acts as a write word line with respect to the TMR elements on the second and third stages. The write word line WWL3n1 is, as apparent from FIGS. 21 and 22, arranged between the TMR element MTJ2 on the second stage and the TMR element MTJ3 on the third stage and extends in the X-direction.

[0355] FIG. 29 shows a layout of the TMR element MTJ3 on the third stage and its lower electrode 41A3.

[0356] The lower electrode 41A3 is, for example, rectangular and is regularly arranged. The TMR element MTJ3 on the third stage is arranged on the lower electrode 41A3. A position at which the TMR element MTJ3 is arranged is, for example, a position at which it does not overlap the contact portion 50.

[0357] FIG. 30 shows a layout of the upper electrode 41B3 of the TMR element MTJ3 on the third stage and the write bit lines BL01 and BL11.

[0358] The upper electrode 41B3 is, for example, rectangular and is arranged so as to overlap the lower electrode of the TMR element on the third stage. The contact portion 51 represents a contact portion between the upper electrode 41B3 of the TMR element on the third stage and the lower electrode of the TMR element on the fourth stage.

[0359] The write bit lines BL01 and BL11 are arranged directly above the TMR element on the third stage and extend in the Y-direction. In addition, as apparent from FIGS. 2 and 3, the write bit liens BL01 and BL11 are arranged directly below the TMR element on the fourth stage. The write bit lines BL01 and BL11 act as write bit lines with respect to the TMR elements on the third and fourth stages.

[0360] FIG. 31 shows a layout of the TMR element MTJ4 on the fourth stage and its lower electrode 41A4.

[0361] The lower electrode 41A4 is, for example, rectangular and is regularly arranged. The TMR element MTJ4 on the fourth stage is arranged on the lower electrode 41A4. A position at which the TMR element MTJ4 is arranged is, for example, a position at which it does not overlap the contact portion 51.

[0362] FIG. 32 shows a layout of the upper electrode 41B4 of the TMR element MTJ4 on the fourth stage and the write word line WWL3n2.

[0363] The upper electrode 41B4 is, for example, rectangular and is arranged so as to overlap the lower electrode of the TMR element on the fourth stage. The contact portion 52 represents a contact portion between the upper electrode 41B4 of the TMR element on the fourth stage and the read bit line.

[0364] The write word line WWL3n2 acts as the write word line relative to the TMR element on the fourth stage. The write word line WWL3n2 is, as apparent from FIGS. 2 and 3, arranged directly above the TMR element MTJ4 on the fourth stage and extends in the X-direction.

[0365] FIG. 33 shows a layout of the read bit lines BL0 and BL1.

[0366] The read bit lines BL0 and BL1 extend in the Y-direction. Each one of the read bit lines BL0 and BL1 is arranged in one column and commonly connected to the blocks in one column. The contact portion 52 represents a contact portion between the upper electrode of the TMR element on the fourth stage and the read bit lines BL0 and BL1.

[0367] {circle over (4)} Modifications

[0368] Modifications of Structure Example 2 will now be described.

[0369] FIG. 34 shows a first modification of Structure Example 2.

[0370] This drawing corresponds to FIG. 21. The device structure of this example is different from the device structure shown in FIG. 21 in a position at which the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are superposed.

[0371] That is, in the device structure shown in FIG. 21, the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are superposed directly above the gate electrode of the read selection switch (MOS transistor) RSW, i.e., the read word line RWLn.

[0372] In this case, the lower electrodes 41A1 and 41A3 and the upper electrodes 41B2 and 41B4 extend from the TMR elements to one side, whilst the lower electrodes 41A2 and 41A4 and the upper electrodes 41B1 and 41B3 extend from the TMR elements to the other side. Further, contact portions relative to the lower electrodes and the upper electrodes are provided on the both sides of the TMR element.

[0373] On the contrary, in the device structure of this example, the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are superposed directly above the source line SL connected to the source of the read selection switch (MOS transistor) RSW.

[0374] In this case, the lower electrodes 41A1, 41A2, 41A3 and 41A4 and the upper electrodes 41B1, 41B2, 41B3 and 41B4 are both extend from the TMR elements to one side. Furthermore, a contact portion relative to the lower electrodes and the upper electrodes is provided on only one side of the TMR element.

[0375] FIG. 35 is a plane view showing the positional relationship between the TMR elements, the lower electrodes and the upper electrodes in the device structure illustrated in FIG. 34.

[0376] In this example, the shapes of the lower electrodes 41A1 and 41A3 and the upper electrodes 41B2 and 41B4 are different from those of the lower electrodes 41A2 and 41A4 and the upper electrodes 41B1 and 41B3. Moreover, a part of the lower electrodes 41A1 and 41A3 and the upper electrodes 41B2 and 41B4, namely, a part overlapping the lower electrodes 41A2 and 41A4 and the upper electrodes 41B1 and 41B3 is eliminated.

[0377] FIGS. 36 and 37 show a second modification of Structure Example 2.

[0378] A circuit diagram of FIG. 36 corresponds to the circuit diagram of FIG. 20, and a sectional view of the device structure illustrated in FIG. 37 corresponds to the sectional view of the device structure depicted in FIG. 34. The structure of this example is different from the structures shown in FIGS. 20 and 34 in the element which realizes the read selection switch.

[0379] That is, in the structures depicted in FIGS. 20 and 34, the read selection switch is constituted by the MOS transistor. On the contrary, in the structure of this example, the read selection switch is constituted by a diode DI. Based on this, the read word lines RWL0, . . . , RLWn are connected to a cathode of the diode DI.

[0380] When adopting the structure of this example, in the read operation, the read word line RWLi of a selected row is set to L, namely, a ground potential. At this moment, a read current can be caused to flow to a plurality of TMR elements which constitute the block of the selected row and are connected to each other in series.

[0381] FIGS. 38 and 39 show a third modification of Structure Example 2.

[0382] A circuit diagram of FIG. 38 corresponds to the circuit diagram of FIG. 20, and a sectional view of the device structure illustrated in FIG. 39 corresponds to the sectional view of the device structure depicted in FIG. 34. The structure of this example is different from the structures illustrated in FIGS. 20 and 34 in a type of transistors constituting the memory cell array 11 and its peripheral circuits.

[0383] That is, in the structure of FIGS. 20 and 34, the transistors constituting the memory cell array 11 and its peripheral circuits are MOS transistors. On the contrary, in the structure of this example, the transistors constituting the memory cell array 11 and its peripheral circuits are bipolar transistors.

[0384] In case of the structure of this example, all the transistors constituting the memory cell array 11 and its peripheral circuits may be bipolar transistors, or some of them may be bipolar transistors.

[0385] (3) Structure Example 3

[0386] Structure Example 3 concerns a cell array structure in which a plurality of TMR elements are connected to each other in parallel.

[0387] In Structure Example 3, each of a plurality of blocks in one column does not have a plurality of TMR elements superposed on a plurality of stages in a direction vertical to the surface of the semiconductor substrate (Z-direction). Each block is constituted by a plurality of TMR elements aligned in the Y-direction parallel to the surface of the semiconductor substrate (column direction).

[0388] However, a later-described read operation principle according to the present invention can be applied also in Structure Example 3. Moreover, in such a case, a later-described structure according to the present invention must be adopted with respect to the structure of the TMR element.

[0389] Thus, description will now be given as to Structure Example 3, namely, the structure in which a plurality of TMR elements are connected to each other in series in a direction parallel to the surface of the semiconductor substrate.

[0390]

[0391] {circle over (1)} Circuit Configuration

[0392] The circuit configuration will now be described.

[0393] FIG. 40 shows primary parts of the magnetic random access memory as Structure Example 3 according to the present invention.

[0394] The memory cell array 11 has a plurality of blocks BK arranged in the form of an array in the directions X and Y. In the drawing, however, only one block BK is illustrated in the memory cell array 11 in order to facilitate understanding the figure.

[0395] The block BK is constituted by four TMR elements (MTJ1, MTJ2, MTJ3 and MTJ4) connected to each other in parallel between an upper wiring 26 and a lower wiring 27. Although a number of the TMR elements 12 constituting one block BK is four in this example, it may be any number as long as it is a plural number.

[0396] One end of the upper wiring 26 is connected to a common data line 28 through a column selection switch (MOS transistor) SW. The common data line 28 is connected to a circuit block 29 including a read circuit (including a sense amplifier) and a write bit line driver/sinker.

[0397] The other end of the upper wiring 26 is connected to a common driver line 30 through the column selection switch (MOS transistor) SW. The common driver line 30 is connected to the write bit line driver/sinker 31.

[0398] A column selection line signal CSLj (j0, 1, . . . ) is inputted to a gate of the column selection switch SW. A column decoder 32 outputs the column selection line signal CSLj.

[0399] The upper wiring 26 functions as a read bit line BLj in the read operation, and also serves as a write bit line in the write operation.

[0400] The lower wiring 27 is connected to a ground point through a read selection switch (MOS transistor) RSW. In the read operation, since a level of a read word line RWL0 becomes H in the selected block BK, the read selection switch RSW enters the on state, and a read current flows to a plurality of TMR elements 12 in the block BK.

[0401] In the memory cell array 11, four write word lines WWL0, WWL1, WWL2 and WWL3 which extend in the X-direction are arranged in accordance with the four TMR elements 12 constituting the block BK.

[0402] One end of the write word lines WWL0, WWL1, WWL3 and WWL4 is connected to the write word line driver 23A, and the other end of these lines is connected to the write word line sinker 24. A gate of the read selection switch RSW, namely, the read word line RWL0 extends in the X-direction, and one end of this line is connected to the read word line driver 23B.

[0403] A row decoder 25 selects one of the write word lines WWL0, WWL1, WWL2 and WWL3 based on a row address signal in the write operation. The write word line driver 23A supplies the write current to the selected write word line. The write current flows through the selected word line and is absorbed in the write word line sinker 24.

[0404] The row decoder 25 selects a block in one row based on, e.g., a superior row address signal in the read operation. The read word line driver 23B supplies a read word line voltage (level H) to the read word line RWL0 connected to the selected block BK.

[0405] In the magnetic random access memory of this example, one column is constituted by a plurality of blocks, and the read operation is carried out in units of block. In addition, one block is constituted by a plurality of TMR elements connected to each other in parallel.

[0406] Even in such a cell array structure, since associating one MOS transistor (read selection switch) with a plurality of the TMR elements can suffice, this can consequently contribute to increase in the memory capacity.

[0407] {circle over (2)} Device Structure 1

[0408] The device structure will now be described.

[0409] FIG. 41 shows a device structure of one block of the magnetic random access memory as Structure Example 3 according to the present invention. Elements shown in FIG. 41 are denoted by like reference numerals in FIG. 40 so that they can correspond to elements in the circuit of FIG. 40.

[0410] A read selection switch (MOS transistor) RSW is arranged in the surface area of the semiconductor substrate 41. A source of the read selection switch RSW is connected to a ground point through the source line SL. The source line SL extends in, for example, the X-direction straightway.

[0411] A gate of the read selection switch (MOS transistor) RSW is the read word line RWL0. The read word line RWL0 extends in the X-direction. On the read selection switch RSW, four TMR elements (MTJ (Magnetic Tunnel Junction) elements) MTJ1, MTJ2, MTJ3 and MTJ4 are arranged in a line in the Y-direction.

[0412] Therefore, an area directly below the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 is narrow in the X-direction and wide in the Y-direction. That is, in this example, a channel length of the read selection switch (MOS transistor) RSW can be freely changed. For example, as shown in FIG. 171, a channel width of the read selection switch RSW can be freely set by arranging the read selection switch (MOS transistor) RSW in the hound's-tooth form.

[0413] The respective TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in parallel between the upper electrode 26 and the lower electrode 27. Contact plugs 42A and 42B and an intermediate layer 43 connect the lower wiring 27 and a drain of the read selection switch (MOS transistor) RSW to each other.

[0414] The write word lines WWL0, WWL1, WWL2 and WWL3 correspond to the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4. The write word lines WWL0, WWL1, WWL2 and WWL3 are arranged directly below the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 and extend in the X-direction.

[0415] According to such a device structure, a plurality of (four in this example) the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 correspond to one read selection switch RSW, and one block is constituted by these members. Additionally, these TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in parallel on the read selection switch RSW.

[0416] Therefore, a number of the read selection switches can be reduced, which contributes to realization of the high density of the TMR elements and increase in the memory capacity. Further, since a number of wirings (for example, the write word lines, the write bit lines, the read bit lines or the like) arranged in the array of the TMR element can be reduced, planation of the insulating film directly below the TMR elements can be realized, thereby improving the characteristic of the TMR elements.

[0417] {circle over (3)} Device Structure 2

[0418] Description will now be given as to a plane layout in each wiring layer of the magnetic random access memory shown in FIG. 41.

[0419] FIG. 42 shows a layout of the active regions and the read word line.

[0420] The active regions 42 on the semiconductor substrate 41 is surrounded by an element separation area 43x. The active regions 42 means an area which forms a read selection switch (MOS transistor).

[0421] On the semiconductor substrate 41 are arranged the read word lines RWL0 and RWL1 which extend in the X-direction and cut across the active regions 42. Each read word lines of RWL0, RWL1 and RWL2 is a gate electrode of a group of the read selection switches (MOS transistors), respectively.

[0422] The active regions on one side of the read word lines RWL0 and RWL1 is a source of the read selection switch, and the active regions on the other side of the read word lines RWL0 and RWL1 is a drain of the read selection switch.

[0423] A contact portion 44A is a source contact portion with respect to the source of the read selection switch, and a contact portion 44B is a drain contact portion with respect to the drain of the read selection switch.

[0424] FIG. 43 shows a layout of the source line SL and the write word lines WWL0, WWL1, WWL2 and WWL3.

[0425] The source line SL extends in the X-direction. The source line SL is connected to the source of the read selection switch.

[0426] An intermediate layer 43 is formed in the same wiring layer as the source line SL. The intermediate layer 43 plays a role of preventing a contact hole having a high aspect ratio from being formed. A contact portion 47 represents a contact portion between the intermediate layer 43 and the lower wiring of the TMR elements.

[0427] As apparent from FIG. 41, the write word lines WWL0, WWL1, WW2 and WWL3 are arranged above the source line SL and the intermediate layer 43 and directly below the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4. The write word lines WWL0, WWL1, WWL2 and WWL3 extend in the X-direction.

[0428] FIG. 44 shows a layout of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 and their lower wiring 27.

[0429] The lower wiring 27 has an enough width that the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 can be arranged thereon, and extends in the Y-direction. In the contact portion 47 at one end of the lower wiring 27, a contact plug is connected. The TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are arranged at predetermined intervals in the Y-direction and directly above the write word line.

[0430] FIG. 45 shows a layout of the upper electrode 26 and the lower electrode 27 of the TMR elements.

[0431] The upper electrode 26 is arranged directly above the TMR element and extends in the Y-direction. The upper electrode 26 functions as the write bit line and the read bit line. One upper wiring 26 is arranged in one column and commonly connected to a plurality of the TMR elements in the block in one column.

[0432] {circle over (4)} Device Structure 3

[0433] A modification of the device structure 1 will now be described.

[0434] The device structure 3 relates to the modification of the device structure 1.

[0435] Comparing with the device structure 1, a characteristic of the device structure 3 lines in a direction of the read selection switch RSW. That is, the direction of the read selection switch RSW of the device structure 3 corresponds to that obtained by rotating the direction of the read selection switch RSW of the device structure 1 by 90 in the plane X-Y.

[0436] FIG. 46 shows a device structure of one block of the magnetic random access memory as Structure Example 3 according to the present invention. Elements shown in FIG. 46 are denoted by the same reference numerals as those in FIG. 40 so that they can correspond to elements in the circuit illustrated in FIG. 40.

[0437] A read selection switch (MOS transistor) RSW is arranged in the surface area of the semiconductor substrate 41. A source of the read selection switch RSW is connected to a ground point through the source line SL. The source line SL extends in, e.g., the X-direction straightway.

[0438] A gate of the read selection switch (MOS transistor) RSW is a read word line RWL0. The read word line RWL0 extends in the Y-direction, is bent at 90 in midstream, and further extends in the X-direction.

[0439] In this example, a channel width of the read selection switch (MOS transistor) RSW is parallel with the Y-direction.

[0440] Since the four TMR elements (MTJ (Magnetic Tunnel Junction) elements) MTJ1, MTJ2, MTJ3 and MTJ4 on the read selection switch RSW are arranged in a line in the Y-direction, an area directly below the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 is narrow in the X-direction and wide in the Y-direction.

[0441] Therefore, in this example, a channel width of the read selection switch (MOS transistor) RSW can be freely changed.

[0442] The respective TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in parallel between the upper electrode 26 and the lower electrode 27. Contact plugs 42A and 42B and an intermediate layer 43 connect the lower wiring 27 and the drain of the read selection switch (MOS transistor) RSW with each other.

[0443] Write word lines WWL0, WWL1, WWL2 and WWL3 correspond to the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4. The write word lines WWL0, WWL1, WWL2 and WWL3 are arranged directly below the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 and extend in the X-direction.

[0444] In such a device structure, associating one read selection switch RSW with a plurality of (four in this example) the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 can suffice. Furthermore, the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in parallel on the read selection switch RSW.

[0445] Therefore, a number of the read selection switches can be reduced, which can contribute to realization of the high density of the TMR elements and increase in the memory capacity. Moreover, since a number of wirings (for example, the write word lines, the write bit lines, the read bit lines or the like) arranged in the array of the TMR elements can be reduced, planation of the insulating film directly below the TMR elements can be realized, thereby improving the characteristic of the TMR elements.

[0446] {circle over (5)} Device Structure 4

[0447] Description will be given as to a plane layout in each wiring layer of the magnetic random access memory illustrated in FIG. 46.

[0448] FIG. 47 shows a layout of an active regions and read word lines.

[0449] The active regions 42 on the semiconductor substrate 41 is surrounded by an element separation area 43. The active regions 42 means an area forming the read selection switch (MOS transistor).

[0450] On the semiconductor substrate 41 are arranged read word lines RWL0 and RWL1 which extend in the Y-direction and cut across the active regions 42. In addition, the read word lines RWL0 and RWL1 are bent at 90 and extend in the X-direction on the element separation area 43x.

[0451] Each read word lines of RWL0, RWL1 and RWL2 is a gate electrode of a group of the read selection switches (MOS transistors), respectively. The active regions on one side of the read word lines RWL0 and RWL1 is a source of the read selection switch whilst the active regions on the other side of the read word lines RWL0 and RWL1 is a drain of the read selection switch.

[0452] A contact portion 44A is a source contact portion with respect to the source of the read selection switch, and a contact portion 44B is a drain contact portion with respect to a drain of the read selection switch.

[0453] FIG. 48 shows a layout of the source line SL and the write word lines WWL0, WWL1, WWL2 and WWL3.

[0454] The source line SL extends in the Y-direction, and is bent at 90 and extends in the X-direction in the element separation area. The source line SL is connected to the source of the read selection switch.

[0455] An intermediate layer 43 is formed in the same wiring layer as the source line SL. The intermediate layer 43 plays a role of preventing a contact hole having a high aspect ratio from being formed. A contact portion 47 represents a contact portion between the intermediate layer 43 and the lower wiring of the TMR elements.

[0456] As apparent from FIG. 46, the write word lines WWL0, WWL1, WWL2 and WWL3 are arranged above the source line SL and the intermediate layer 43 and directly below the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4. The write word lines WWL0, WWL1, WWL2 and WWL3 extend in the X-direction.

[0457] FIG. 49 shows a layout of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 and their lower wiring 27.

[0458] The lower wiring 27 has an enough width that the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 can be arranged thereon, and extends in the Y-direction. In a contact portion 47 at one end of the lower wiring 27, a contact plug is connected. The TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are arranged at fixed intervals in the Y-direction and arranged directly above the write word lines.

[0459] FIG. 50 shows a layout of the upper electrode 26 and the lower electrode 27 of the TMR elements.

[0460] The upper electrode 26 is arranged directly above the TMR elements and extends in the Y-direction. The upper electrode 26 functions as the write bit line and the read bit line. One upper wiring 26 is arranged in one column and commonly connected to a plurality of the TMR elements in the block in one column.

[0461] {circle over (6)} Others

[0462] In the above-described Structure Example 3 (device structures 1, 2, 3 and 4), it is presumed that the read selection switch RSW is the MOS transistor. As the read selection switch RSW, however, a diode, a bipolar transistor or the like may be used in place of the MOS transistor.

[0463] 2. Structure of TMR Element

[0464] In the cell array structure mentioned above, a plurality of the TMR elements in one block are connected to each other in series or in parallel.

[0465] In case of presuming such a cell array structure, when the structures of a plurality of the TMR elements in one block are the same, a special read operation principle such as a destructive read operation principle may be adopted. In the destructive read operation principle, however, the read operation for two times and the write operation for two times are required in order to complete the data read operation for one time.

[0466] Thus, here, there is proposed a so-called non-destructive read operation principle by which data is not destroyed when reading data from one of a plurality of the TMR elements connected to each other in series or in parallel.

[0467] The read operation principle will be described later, and the structure of the TMR element for 5 realizing this read operation principle will now be explained.

[0468] (1) Equivalent Circuit in Read Operation

[0469] Description will be first given as to an equivalent circuit of the TMR elements (memory cells) in one block in the read operation.

[0470] FIG. 51 shows an equivalent circuit during the read operation in Structure Example 1 of the cell array structure.

[0471] The four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in series, and one end of these elements is connected to a read bit line BLj.

[0472] The potential of the read bit line BLj is set to, e.g., a power supply potential VDD. A read selection switch (MOS transistor) RSW is connected between the other end of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 connected in series and a source line SL.

[0473] Since the potential of the gate of the read selection switch RSW, namely, the read word line RWLn is set to H, the read selection switch RSW enters the on state. The source line SL is set to, e.g., a ground potential VSS.

[0474] FIG. 52 shows an equivalent circuit during the read operation in Structure Examples 2 and 3 of the cell array structure.

[0475] The four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in parallel, and one end of these elements is connected to the read bit line BLj. The potential of the read bit line BLj is set to, e.g., the power supply potential VDD. The read selection switch (MOS transistor) RSW is connected between the other end of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 connected in parallel and the source line SL.

[0476] Since the potential of the gate of the read selection switch RSW, namely, the read word line RWLn is set to H, the read selection switch RSW enters the on state. The source line SL is set to, e.g., the ground potential VSS.

[0477] FIG. 53 shows an equivalent circuit during the read operation in a second modification of Structure Example 1 of the cell array structure.

[0478] The four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in series, and one end of these elements is connected to the read bit line BLj. The potential of the read bit line BLj is set to, for example, the power supply potential VDD. A diode DI is connected between the other end of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 connected in series and the read word line RWLn.

[0479] Since the potential of the read word line RWLn is set to the ground potential VSS, a read current flows to the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 connected to each other in series.

[0480] FIG. 54 shows an equivalent circuit during the read operation in the third modification of Structure Example 1 of the cell array structure.

[0481] The four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in series, and one end of these elements is connected to the read bit line BLj. The potential of the read bit line BLj is set to, for example, the power supply potential VDD. The read selection switch (bipolar transistor) RWS is connected between the other end of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 connected in series and the source line SL.

[0482] Since the potential of the gate of the read selection switch RSW, namely, the read word line RWLn is set to H, the read selection switch RSW enters the on state. The source line SL is set to, for example, the ground potential VSS.

[0483] FIG. 55 shows an equivalent circuit during the read operation in the second modification of Structure Example 2 of the cell array structure.

[0484] The four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in parallel, and one end of these elements is connected to the read bit line BLj. The potential of the read bit line BLj is set to, for example, the power supply potential VDD. The diode DI is connected between the other end of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 connected in parallel and the read word line RWLn.

[0485] Since the potential of the read word line RWLn is set to the ground potential VSS, the read current flows to the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 connected to each other in parallel.

[0486] FIG. 56 shows an equivalent circuit during the read operation in the third modification of Structure Example 2 of the cell array structure.

[0487] The four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 are connected to each other in parallel, and one end of these elements is connected to the read bit line BLj. The potential of the read bit line BLj is set to, e.g., the power supply potential VDD. The read selection switch (bipolar transistor) RSW is connected between the other end of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 connected in parallel and the source line SL.

[0488] Since the potential of the gate of the read selection switch RSW, namely, the read word line RWLn is set to H, the read selection switch RSW enters the on state. The source line SL is set to, for example, the ground potential VSS.

[0489] (2) Structure of TMR Element

[0490] A characteristic of the structure of the TMR element according to the present invention lies in that the structures of the TMR elements connected to each other in series or in parallel in one block are different from each other.

[0491] Specifically, in the present invention, the structures of a plurality of the TMR elements are determined in such a manner the respective TMR elements have resistance values different from each other when the magnetizing states of a plurality of the TMR elements in one block are all parallel (as to definition of parallel and anti-parallel, see the section of prior art).

[0492] For example, resistance values of the respective TMR elements when the magnetizing states of a plurality of the TMR elements in one block are all parallel are set as follows.

[0493] It is assumed that i (i is a plural number) TMR elements connected to each other in series or parallel are MTJ1, MTJ2, . . . MTJi and their resistance values when the magnetizing states are parallel are RTMR1, RTMR2, . . . RMTRi. At that time, the resistance values RTMR1, RTMR2, . . . RTMRi are set as the following expressions:

[0494] That is, the resistance values of the respective TMR elements when the magnetizing states of a plurality of the TMR elements in one block are doubly different from each other.

[0495] It is to be noted that positions of the i TMR elements MTJ1, MTJ2,. . . MTJi in the block are not fixed. For example, the TMR element closest to the read selection switch RSW may be MTJ1 or any other element.

[0496] In order to realize the relationship between the resistance values of such TMR elements, the structures of a plurality of the TMR elements in the block are determined to be different from each other.

[0497] The relationship represented by the above expression (1) can be realized by changing an area of each TMR element (area of a cap insulator of each TMR element).

[0498] That is, assuming that areas of i TMR elements MTJ1, MTJ2, . . . MTJi connected to each other in series or parallel are STMR1, STMR2, . . . STMRi, the relationship of the above expression (1) can be realized by setting these areas as follows:

[0499] Further, as a method other than that which changes an area of each TMR element, a plurality of the TMR elements which satisfy the relationship of the above expression (1) can be realized by changing a number of the MTJ elements having the same structure and the same area to be superposed (number of cap insulators).

[0500] For example, it is assumed that the MTJ element consisting of a storage layer, a pin layer and a cap insulator is determined as one unit and a resistance value of one unit is R. In this case, the resistance value of the TMR element consisting of two units is 2R, the resistance value of the TMR element consisting of four units is 4R, and the resistance value of the TMR element consisting of eight units is 8R.

[0501] In this manner, the resistance value of the TMR element can be changed by varying a number of units constituting one TMR element (number of cap insulators).

[0502] In case of realizing the relationship of the resistance values of the TMR elements in one block by a method other than that which changes an area of each TMR element, since an area of each TMR element does not change, the degree of the magneto resistive effect of each TMR element remains unchanged. Furthermore, since an area of the TMR element (area in the plane X-Y) is fixed, this is advantageous for realization of high integration of the TMR elements.

[0503] {circle over (1)} Structure Example 1

[0504] FIG. 57 shows an example of the TMR element MTJ1.

[0505] The TMR element MTJ1 is constituted by a basic unit. The basic unit means a unit consisting of a cap insulator, a ferromagnetic layer (storage layer) arranged on one side of the cap insulator, and a ferromagnetic layer arranged on the other side of the cap insulator and an anti-ferromagnetic layer.

[0506] Since the ferromagnetic layer arranged on the other side of the cap insulator is in contact with the anti-ferromagnetic layer, the direction of its magnetization is fixed. The ferromagnetic layer arranged on the other side of the cap insulator and the anti-ferromagnetic layer which is in contact with the ferromagnetic layer constitute the pin layer.

[0507] A resistance value of the TMR element MTJ1 realized by this structure is determined as R.

[0508] FIG. 58 shows an example of the TMR element MTJ2.

[0509] The TMR element MTJ2 is constituted by the two basic units. However, one ferromagnetic layer (storage layer) is shared by the two basic units. That is, the pin layer consisting of the ferromagnetic layer and the anti-ferromagnetic layer is arranged on one side of the ferromagnetic layer as the storage layer through the cap insulator, and the pin layer consisting of the ferromagnetic layer and the anti-ferromagnetic layer is also arranged on the other side of the ferromagnetic layer as the storage layer through the cap insulator.

[0510] The TMR element MTJ2 has a structure in which the cap insulator and the pin layer (the ferromagnetic layer and the anti-ferromagnetic layer) are symmetrically arranged with respect to the ferromagnetic layer as the storage layer.

[0511] A resistance value of the TMR element MTJ2 realized by this structure is 2R.

[0512] FIG. 59 shows an example of the TMR element MTJ3.

[0513] The TMR element MTJ3 is constituted by the four basic units. In addition, the TMR element MTJ3 may be obtained by connecting the two TMR elements MTJ2 to each other in series. That is, the TMR element MTJ3 has a structure that the two TMR elements MTJ2 are connected to each other in series and the anti-ferromagnetic layer at their connection portion is shared by the two TMR elements.

[0514] Although the two storage layers exist in the TMR element MTJ3, the same data is naturally stored in these two storage layers. That is, one-bit data is stored in the TMR element MTJ3 by the two storage layers.

[0515] A resistance value of the TMR element MTJ3 realized by this structure is 4R.

[0516] FIG. 60 shows an example of the TMR element MTJ4.

[0517] The TMR element MTJ4 is constituted by eight basic units. Additionally, the TMR element MTJ4 may be obtained by connecting the two TMR elements MTJ3 to each other in series. That is, the TMR element MTJ4 has a structure in which the two TMR elements MTJ3 are connected to each other in series and the anti-ferromagnetic layer at their connection portion is shared by the two TMR elements MTJ3.

[0518] Although the four storage layers exist in the TMR element MTJ4, the same data is naturally stored in these four storage layers. That is, one-bit data is stored in the TMR element MTJ4 by the four storage layers.

[0519] A resistance value of the TMR element MTJ4 realized by this structure is 8R.

[0520] {circle over (2)} Structure Example 2

[0521] In Structure Example 1, description has been given as to the technique which changes a number of cap insulators in accordance with a number of basic unit (MTJ elements) and varies a resistance value of the TMR element. In this case, however, since a number of the basic units varies in accordance with each TMR element in on block, the thickness of each TMR element differs.

[0522] Thus, in Structure Example 2, in order to solve the problem that the thickness of each TMR element differs in one block, all the TMR elements in one block are constituted by the same number of units and they have the same thickness.

[0523] For example, when one block is constituted by four TMR elements, each TMR element is constituted by eight units.

[0524] Further, a resistance value of the TMR element is adjusted by determining some of a plurality of units constituting that TMR element as dummy units. The dummy unit means a unit in which the cap insulator of the basic unit is changed to non-magnetic metal.

[0525] By doing so, when a resistance value of one basic unit is determined as R for example, a resistance value of the TMR element constituted by eight basic units is 8R (eight cap insulators). Furthermore, a resistance value of the TMR element in which four out of eight units are basic units and the remaining four units are dummy units is 4R (four cap insulators).

[0526] Moreover, a resistance value of the TMR element in which two out of eight units are basic units and the remaining six units are dummy units is 2R (two cap insulators). In addition, a resistance value of the TMR element in which one out of eight units is a basic unit and the remaining seven units are dummy unit is R (one cap insulator).

[0527] A resistance value between the two ferromagnetic layers sandwiching the non-magnetic metal there between is sufficiently smaller than a resistance value between the two ferromagnetic layers sandwiching the cap insulator there between. Therefore, all the TMR elements can have the same thickness by equaling a number of units constituting the respective TMR elements, and a ratio of the resistance values of the TMR elements in one block can be set to, e.g., 1:2:4:8.

[0528] The cap insulator in the basic unit can be formed of, for example, alumina. Alumina is formed by oxidizing aluminium.

[0529] Thus, after forming aluminium, when the unit is formed without oxidizing the aluminium, that unit becomes a dummy unit. Additionally, after forming aluminium, when this aluminium is oxidized to obtain alumina, the finally completed unit becomes a basic unit having the resistance value R.

[0530] It is to be noted that a method for forming a plurality of TMR elements having different resistance values will be described in the section of description of a manufacturing method.

[0531] FIG. 61 shows an example of the TMR element MTJ1.

[0532] The TMR element MTJ1 is constituted by eight units. One in the eight units is a basic unit having the cap insulator, and the remaining seven units are dummy units having no cap insulator (having the non-magnetic metal).

[0533] Thus, the resistance value of the TMR element MTJ1 realized by this structure becomes the resistance value R corresponding to one unit (or cap insulator).

[0534] FIG. 62 shows an example of the TMR element MTJ2.

[0535] The TMR element MTJ2 is constituted by eight units. Two in eight units are basic units having the cap insulators and the remaining six units are dummy units having no cap insulator (having the non-magnetic metal).

[0536] Therefore, the resistance value of the TMR element MTJ2 realized by this structure becomes the resistance value 2R corresponding to two units (or cap insulators).

[0537] FIG. 63 shows an example of the TMR element MTJ3.

[0538] The TMR element MTJ3 is constituted by eight units. Four in eight units are basic units having cap insulators and the remaining four units are dummy units having no cap insulator (having the non-magnetic metal).

[0539] Therefore, the resistance value of the TMR element MTJ3 realized by this structure becomes the resistance value 4R corresponding to four units.

[0540] FIG. 64 shows an example of the TMR element MTJ4.

[0541] The TMR element MTJ4 is constituted by eight units. All of the eight units are the basic units having the cap insulators.

[0542] Therefore, the resistance value of the TMR element MTJ4 realized by this structure becomes the resistance value 8R corresponding to eight units (or cap insulators).

[0543] (3) Others

[0544] The present invention is characterized in that a plurality of the TMR elements in one block have different resistance values by changing a number of the cap insulators assuming that the magnetizing states of a plurality of the TMR elements in that block are the same.

[0545] Therefore, the above-described structure of the TMR element is one example, and various modifications are possible. For example, as to the TMR elements MTJ1, MTJ2 and MTJ3 shown in FIGS. 61 to 63, if a number of the cap insulators is the same, positions of the basic units having the cap insulators or positions of the dummy units having the non-magnetic metal can be arbitrarily changed.

[0546] 3. Read Operation Principle

[0547] The read operation principle according to the present invention will now be described.

[0548] In the read operation principle according to the present invention, when performing the read operation in units of block, the resistance values of a plurality of the TMR elements connected to each other in series or parallel in the block during the read operation are different from each other when the magnetizing states are the same (parallel or anti-parallel). Further, by utilizing a difference in the resistance values, data of all the TMR elements in the block can be read at a time.

[0549] (1) Concrete Example 1

[0550] Concrete Example 1 will now be described.

[0551] In this example, as a prerequisite, one block (read block) is constituted by the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 connected to each other in series.

[0552] It is to be noted that positions of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the block are not restricted and these positions can be freely determined when designing. At least after completion of the memory device, the memory itself, of course, must recognize positions of the respective TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the block.

[0553] If the positions of the respective MTJ1, MTJ2, MTJ3 and MTJ4 are not grasped, the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 used for writing can not be specified during the write operation.

[0554] Furthermore, resistance values of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block are set as shown in Table 1 during the read operation (when the read current is flowing).

TABLE 1
RESISTANCE VALUE OF TMR ELEMENT
IN ONE READ BLOCK IN READ OPERATION
	TMR ELEMENT
STORING DATA	MTJ1	MTJ2	MTJ3	MTJ4
1 (PARALLEL)	R	2R	4R	8R
0 (ANTI-PARALLEL)	R R	2R 2R	4R 4R	8R 8R

[0555] That is, as to the TMR element MTJ1, it is assumed that the resistance value when the magnetizing state is parallel (state of 1) is R and the resistance value when the magnetizing state is anti-parallel (state of 0) is RR.

[0556] Moreover, as to the TMR element MTJ2, it is assumed that the resistance value when the magnetizing state is parallel (state of 1) is 2R and the resistance value when the magnetizing state is anti-parallel (state of 0) is 2R2R.

[0557] In addition, as to the TMR element MTJ3, it is assumed that the resistance value when the magnetizing state is parallel (state of 1) is 4R and the resistance value when the magnetizing state is anti-parallel (state of 0) is 4R4R.

[0558] Additionally, as to the TMR element MTJ4, it is assumed that the resistance value when the magnetizing state is parallel (state of 1) is 8R and the resistance value when the magnetizing state is anti-parallel (state of 0) is 8R8R.

[0559] At this time, the relationship between data of the TMR elements in one block and sum resistance values is as shown in Table 2.

TABLE 2
RELATIONSHIP BETWEEN DATA AND SUM RESISTANCE
VALUE, OF TMR ELEMENTS IN ONE READ BLOCK
	MJT1	MJT2	MJT3	MJT4	SUM RESISTANCE VALUE
	1	1	1	1	15R
	0	1	1	1	15 R
C1
	1	0	1	1	15 2R
	0	0	1	1	15 3R
B1
	1	1	0	1	15 4R
	0	1	0	1	15 5R
C2
	1	0	0	1	15 6R
	0	0	0	1	15 7R
A
	1	1	1	0	15 8R
	0	1	1	0	15 9R
C3
	1	0	1	0	15 10R
	0	0	1	0	15 11R
B2
	1	1	0	0	15 12R
	0	1	0	0	15 13R
C4
	1	0	0	0	15 14R
	0	0	0	0	15 15R

[0560] That is, there are 16 combinations of data values of the four TMR elements MTJ1, MTJ2, NTJ3 and MTJ4 in one block, and there are also 16 combinations of sum resistance values in accordance with 16 combinations of the data values. A minimum value of the sum resistance value is 15R, and a maximum value of the same is 15R15R. In addition, a difference between the sum resistance values is R.

[0561] During the read operation, when the read current (current value I) is caused to flow to the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in this one block, the potential of the read bit line BLj has a value according to the sum resistance value of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in one block.

[0562] Assuming that the current value of the read current is I, a minimum value of the potential which appears in the read bit line BLj is I(15Rr), and a maximum value of the same is I(15R15Rr). Additionally, a difference between the respective potentials which appear in the read bit line BLj is IR.

[0563] Here, r is the sum of some accompanied resistances, for example, the read selection switch (MOS transistor) RSW. When designing the resistance r to be sufficiently smaller than the sum resistance value of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4, this r can be ignored.

[0564] In the read operation principle according to the present invention, when the read current is caused to flow to a plurality of the TMR elements in the read block during the read operation, the read potential Vtotal according to a combination of the data values of a plurality of the TMR elements appears in the read bit line BLj. Therefore, by detecting the read potential Vtotal by using a sense amplifier (for example, an analog/digital converter), data of a plurality of the TMR elements in the read block can be read at a time.

[0565] Tables 3 and 4 show the principle for judging the sum resistance value of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4, concretely, data values of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block from the read potential Vtotal which appears in the read bit line BLj.

TABLE 3
JUDGMENT 1 OF DATA VALUE OF TMR ELEMENT
IN ONE READ BLOCK
	1 (PARALLEL)	0(ANTI-PARALLEL)
MTJ4	[ 1 ] Radd < 15 R + 7 R + R 2	[ 2 ] Radd > 15 R + 7 R + R 2
MTJ3	CASE OF 1	CASE OF 1
	[ 3 ] Radd < 15 R + 3 R + R 2	[ 4 ] Radd > 15 R + 3 R + R 2
	CASE OF 2	CASE OF 2
	[ 5 ] Radd < 15 R + 11 R + R 2	[ 6 ] Radd > 15 R + 11 R + R 2
MTJ2	CASE OF 3	CASE OF 3
	[ 7 ] Radd < 15 R + R + R 2	[ 8 ] Radd > 15 R + R + R 2
	CASE OF 4	CASE OF 4
	[ 9 ] Radd < 15 R + 5 R + R 2	[ 10 ] Radd > 15 R + 5 R + R 2
	CASE OF 5	CASE OF 5
	[ 11 ] Radd < 15 R + 9 R + R 2	[ 12 ] Radd > 15 R + 9 R + R 2
	CASE OF 6	CASE OF 6
	[ 13 ] Radd < 15 R + 13 R + R 2	[ 14 ] Radd > 15 R + 13 R + R 2

[0566]

TABLE 4
JUDGMENT 2 OF DATA VALUE OF TMR
ELEMENT IN ONE READ BLOCK
	1 (PAPALLEL)	0 (ANTI-PARALLEL)
MTJ1	CASE OF 7	CASE OF 7
	Radd < 15 R + R 2	Radd > 15 R + R 2
	CASE OF 8	CASE OF 8
	Radd < 15 R + 2 R + R 2	Radd > 15 R + 2 R + R 2
	CASE OF 9	CASE OF 9
	Radd < 15 R + 4 R + R 2	Radd > 15 R + 4 R + R 2
	CASE OF 10	CASE OF 10
	Radd < 15 R + 6 R + R 2	Radd > 15 R + 6 R + R 2
	CASE OF 11	CASE OF 11
	Radd < 15 R + 8 R + R 2	Radd > 15 R + 8 R + R 2
	CASE OF 12	CASE OF 12
	Radd < 15 R + 10 R + R 2	Radd > 15 R + 10 R + R 2
	CASE OF 13	CASE OF 13
	Radd < 15 R + 12 R + R 2	Radd > 15 R + 12 R + R 2
	CASE OF 14	CASE OF 14
	Radd < 15 R + 14 R + R 2	Radd > 15 R + 14 R + R 2

[0567] In the read operation principle according to the present invention, when the magnetizing states are the same (parallel, for example), the data value of the TMR element having the highest resistance value (in this example, the TMR element MTJ4, the resistance value8R) is judged based on predetermined criteria.

[0568] For example, by setting a threshold value 15R7RR/2 and making judgment upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value in this example, the data value of the TMR element MTJ4 can be determined.

[0569] Subsequently, when the magnetizing states are the same (parallel, for example), the data value of the TMR element having the second highest resistance value (in this example, the TMR element MTJ3, the resistance value4R) is judged based on predetermined criteria.

[0570] The predetermined criteria in this example varies depending on the data value of the TMR element MTJ4.

[0571] For example, when it is determined that the data value of the TMR element MTJ4 is 1, the threshold value 15R3RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0572] Further, when it is determined that the data value of the TMR element MTJ4 is 0, the threshold value 15R11RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0573] With the above-described method, the data value of the TMR element MTJ3 can be determined.

[0574] Then, when the magnetizing states are the same (parallel, for example), the data value of the TMR element having the third highest resistance value (in this example, the TMR element MTJ2, the resistance value2R) is judged based on predetermined criteria.

[0575] The predetermined criteria in this example varies depending on the data values of the two TMR elements MTJ4 and MTJ3.

[0576] For example, when it is determined that the data value of the TMR element MTJ4 is 1 and the data value of the TMR element MTJ3 is 1, the threshold value 15RRR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0577] Furthermore, when it is determined that the data value of the TMR element MTJ4 is 1 and the data the data value of the TMR element MTJ3 is 0, the threshold value 15R5RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0578] Moreover, when it is determined that the data value of the TMR element MTJ4 is 0 and the data value of the TMR element MTJ3 is 1, the threshold value 15R9RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0579] In addition, when it is determined that the data value of the MTJ4 is 0 and the data value of the TMR element MTJ3 is 0, the threshold value 15R13RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0580] With the above-described operation, the data value of the TMR element MTJ2 can be determined.

[0581] Subsequently, when the magnetizing states are the same (parallel, for example), the data value of the TMR element having the lowest resistance value (in this example, the TMR element MTJ1, the resistance valueR) is judged based on predetermined criteria.

[0582] The predetermined criteria in this example varies depending on the data values of the three TMR elements MTJ4, MTJ3 and MTJ2.

[0583] For example, when it is determined that the data value of the TMR element MTJ4 is 1, the data value of the TMR element MTJ3 is 1 and the data value of the TMR element MTJ2 is 1, the threshold value 15RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0584] Additionally, when it is determined that the data value of the TMR element MTJ4 is 1, the data value of the TMR element MTJ3 is 1 and the data value of the TMR element MTJ2 is 0, the threshold value 15R2RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0585] Further, when it is determined that the data value of the TMR element MTJ4 is 1 the data value of the TMR element MTJ3 is 0 and the data value of the TMR element MTJ2 is 1, the threshold value 15R4RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0586] Furthermore, when it is determined that the data value of the TMR element MTJ4 is 1, the data value of the TMR element MTJ3 is 0 and the data value of the TMR element MTJ2 is 0, the threshold value 15R6RR/2 is set, and judgment is made upon whether the sum resistance value of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0587] Moreover, when it is determined that the data value of the TMR element MTJ4 is 0, the data value of the TMR element MTJ3 is 1 and the data value of the TMR element MTJ2 is 1, the threshold value 15R8RR/2 is set, and judgment is made upon the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0588] In addition, when it is determined that the data value of the TMR element MTJ4 is 0, the data value of the TMR element MTJ3 is 1 and the data value of the TMR element MTJ2 is 0, the threshold value 15R10RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0589] Additionally, when it is determined that the data value of the TMR element MTJ4 is 0, the data value of the TMR element MTJ3 is 0 and the data value of the TMR element MTJ2 is 1, the threshold value 15R12RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0590] Further, when it is determined that the data value of the TMR element MTJ4 is 0, the data value of the TMR element MTJ3 is 0 and the data value of the TMR element MTJ2 is 0, the threshold value 15R14RR/2 is set, and judgment is made upon whether the sum resistance value Rtotal of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 exceeds the threshold value or is below the threshold value.

[0591] With the above-described operation, the data value of the TMR element MTJ1 can be determined.

[0592] As described above, in the read operation principle according to the present invention, by detecting the read potential Vtotal read to the read bit line BLj by the sense amplifier (for example, an analog/digital converter), the data of a plurality of the TMR elements in the read block can be read at a time by one read operation.

[0593] Incidentally, in regard to the operation for judging the data values of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4, judgment on data of the respective TMR elements can be carried out in time series, and it can be also simultaneously carried out by using a plurality of reference currents.

[0594] The logic shown in Tables 3 and 4 can be readily realized by a predetermined logic circuit. That is, if the predetermined logic circuit is used, the read potential Vtotal is detected, and immediately thereafter the data values of the four TMR elements MTJ1 , MTJ2, MTJ3 and MTJ4 in the read block can be judged.

[0595] A concrete example of the logic circuit will be described in the section of the read circuit.

[0596] (2) Concrete Example 2

[0597] In Concrete Example 1, it is presumed that a plurality of the TMR elements in the read block are connected to each other in series. On the contrary, in Concrete Example 2, it is presumed that a plurality of the TMR elements in the read block are connected to each other in parallel.

[0598] In cases where a plurality of the TMR elements in the read block are connected to each other in parallel, data values of a plurality of the TMR elements can be likewise judged based on the principle similar to the above-described read operation principle.

[0599] It is assumed that the resistance values of the TMR elements in one block during the read operation are the same as those in Concrete Example 1.

[0600] That is, as shown in Table 1, as to the TMR element MTJ1, it is assumed that the resistance value when the magnetizing state is parallel (state of 1) is R and the resistance value when the magnetizing state is anti-parallel (state of 0) is RR.

[0601] Furthermore, as to the TMR element MTJ2, it is assumed that the resistance value when the magnetizing state is parallel (state of 1) is 2R and the resistance value when the magnetizing state is anti-parallel (state of 0) is 2R2R.

[0602] Moreover, as to the TMR element MTJ3, it is assumed that the resistance value when the magnetizing state is parallel (state of 1) is 4R and the resistance value when the magnetizing state is anti-parallel (state of 0) is 4R4R.

[0603] In addition, as to the TMR element MTJ4, it is assumed that the resistance value when the magnetizing state is parallel (state of 1) is 8R and the resistance value when the magnetizing state is anti-parallel (state of 0) is 8R8R.

[0604] Since there are 16 combinations of the data values of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in one block as similar to Concrete Example 1, there are also 16 sum resistance values in accordance with 16 combinations of the data values.

[0605] In Concrete Example 2, it is presumed that a plurality of the TMR elements in the read block are connected to each other in parallel. Therefore, in order to simplify the explanation, discussion will be given using the concept of a sum of the inverse value of the resistance as different from Concrete Example 1.

[0606] In Concrete Example 2, as shown in Table 5, a minimum value of a sum of the inverse value of the resistance is 15/8 (RR) and a maximum value is 15/8R. Additionally, in Concrete Example 2, as different from Concrete Example 1, a difference in the sum of the inverse value of the resistance becomes fixed instead of a difference in the resistance values. The difference is R/8R(RR).

TABLE 5
				RECIPROCAL
MTJ1	MTJ2	MTJ3	MTJ4	OF SUM RESISTANCE VALUE Radd
1	1	1	1	15/8R (15R 15R)/8R(R R)
1	1	1	0	(15R 14R)/8R(R R)
1	1	0	1	(15R 13R)/8R(R R)
1	1	0	0	(15R 12R)/8R(R R)
1	0	1	1	(15R 11R)/8R(R R)
1	0	1	0	(15R 10R)/8R(R R)
1	0	0	1	(15R 9R)/8R(R R)
1	0	0	0	(15R 8R)/8R(R R)
0	1	1	1	(15R 7R)/8R(R R)
0	1	1	0	(15R 6R)/8R(R R)
0	1	0	1	(15R 5R)/8R(R R)
0	1	0	0	(15R 4R)/8R(R R)
0	0	1	1	(15R 3R)/8R(R R)
0	0	1	0	(15R 2R)/8R(R R)
0	0	0	1	(15R 1R)/8R(R R)
0	0	0	0	15/8(R R) 15R/8R(R R)

[0607] In the read operation, when the read potential (difference in potential between both ends of the TMR element is determined as V) is applied to the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block, the current flowing through the read bit line BLj has a value according to a sum of the inverse value of the resistance of the four TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block.

[0608] Assuming that a difference in potential between both ends of the TMR element (MTJ element) is V, a minimum value of the current which appears in the read bit line BLj is V15/8 (RAR) and a maximum value of the same is V15/8R. It is, however, assumed that the sum of some accompanied resistances, for example, the read selection switch (MOS transistor) RSW r is sufficiently smaller than the combination resistance value of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4.

[0609] In the read operation principle according to the present invention, when the read potential is applied to a plurality of the TMR elements in the read block during the read operation, the read current Itotal corresponding to a combination of the data values of a plurality of the TMR elements flows to the read bit line BLj. Therefore, by detecting the read current Itotal by the sense amplifier (for example, an analog/digital converter), the data of a plurality of the TMR elements in the read block can be read at a time by one read operation as similar to Concrete Example 1.

[0610] In regard to a concrete data judgment method, as contrary to Concrete Example 1, when the magnetizing states are the same (parallel, for example), the data value of the TMR element having the lowest resistance value (in this example, the TMR element MTJ1, the resistance valueR) is judged based on predetermined criteria.

[0611] Subsequently, based on its result, when the magnetizations states are the same (parallel, for example), the data value of the TMR element having the second lowest resistance value (in this example, the TMR element MTJ1, the resistance value2R) is judged based on predetermined criteria.

[0612] Then, based on the two results mentioned above, when the magnetizing states are the same (parallel, for example), the data value of the TMR element having the third lowest resistance value (in this example, the TMR element MTJ3, the resistance value4R) is judged based on predetermined criteria.

[0613] At last, based on all the results obtained thus far, when the magnetizing states are the same (parallel, for example), the data value of the TMR element having the highest resistance value (in this example, the TMR element MTJ4, the resistance value8R) is judged based on predetermined criteria.

[0614] As described above, in the read operation principle according to the present invention, by detecting the current Itotal flowing to the read bit line BLj by the sense amplifier (for example, an analog/digital converter), the data of a plurality of the TMR elements in the read block can be read at a time by one read operation.

[0615] Incidentally, in regard to the operation for judging the data values of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4, judgment on the data of the respective TMR elements can be carried out in time series and also simultaneously performed by using a plurality of reference currents.

[0616] 4. Read Circuit

[0617] Description will now be given as to a circuit example of the read circuit for realizing the read operation principle according to the present invention.

[0618] In the above-described read operation principle (Concrete Example 1), description has been given as to the fact that the read potential Vtotal according to the sum resistance value of a plurality of the TMR elements in the read block appears in the read bit line BLj during the read operation.

[0619] As to this sum resistance value, when a number of the TMR elements in the read block is N (N is a plural number), there are 2^N patterns corresponding to a number of combinations of the data values of the TMR elements as shown in Table 2.

[0620] Therefore, by detecting the read potential Vtotal which has appeared in the read bit line BLj by the read circuit (including the sense amplifier), the data of the TMR elements in the read block can be readily read at a time.

[0621] Further, in the read operation principle (Concrete Example 2), description has been given as to the fact that the read current Itotal according to the sum resistance value of a plurality of the TMR elements in the read block flows through the read bit line BLj during the read operation.

[0622] As to the inverse value of the sum resistance value, when a number of the TMR elements in the read block is N (N is a plural number), there are 2^N patterns corresponding to a number of combinations of the data values of the TMR elements as shown in Table 5.

[0623] Therefore, by detecting the read current Itotal flowing through the read bit line BLj by the read circuit (including the sense amplifier), the data of the TMR elements in the read block can be readily read at a time.

[0624] (1) Circuit Example 1

[0625] {circle over (3)} Sense Amplifier

[0626] FIG. 65 shows Circuit Example 1 of the read circuit concerning the present invention.

[0627] This read circuit is constituted by an analog/digital converter (A/D converter) as a sense amplifier.

[0628] One end of a block BKjn consisting of four TMR elements connected to each other in series is connected to a power supply terminal through an N-channel MOS transistor SWA and a P-channel MOS transistor P2, and the other end of the same is connected to a ground terminal. The four TMR elements in the block BKjn may be connected to each other in parallel rather than series.

[0629] A first current path means a path which runs from the power supply terminal to the ground terminal through the MOS transistors P2 and SWA and a plurality of the TMR elements.

[0630] One end of 14 resistance elements having a resistance value R is connected to the power supply terminal through the P-channel MOS transistor P3, and the other end of the same is connected to the ground terminal through a resistance element having a resistance value 15RR/2. A second current path means a path which runs from the power supply terminal to the ground terminal through the MOS transistor P3 and a plurality of the resistance elements.

[0631] Here, it is assumed that R and R means the same as R and R described in the section of the read operation principle.

[0632] The P-channel MOS transistors P1, P2 and P3 constitute a current mirror circuit. Therefore, a constant current generated by a constant current source I flows to the above-described first and second current paths.

[0633] The current flowing through the first current path becomes a read current, and the read current flows through a plurality of the TMR elements. As a result, a read potential Vtotal according to the data values of the TMR elements in the block BKjn (sum resistance value) appears in a node nr. On the other hand, when the current flows through the second current path, a predetermined reference potential appears at connection points n0, n1, n13, and n14 of the respective resistance elements.

[0634] Differential amplifier DI0, DI2, DI13 and DI14 compare the read potential Vtotal in the node nr with a predetermined reference potential, and output a result of comparison as output signals O0b1, O1b2, . . . O13b14 and O14b15.

[0635] For example, a reference potential in the node n0 is inputted to a plus side input terminal of the differential amplifier DI0, and a read potential Vtotal in the node nr is inputted to a minus side input terminal of the same. Similarly a reference potential in the node n1 is inputted to the plus side input terminal of the differential amplifier DI1, and the read potential Vtotal in the node nr is inputted to the minus side input terminal of the same. The reference potential in the node n14 is inputted to the plus side input terminal of the differential amplifier DI14, and the read potential Vtotal in the node nr is inputted to the minus side input terminal of the same.

[0636] {circle over (2)} Operation

[0637] Table 6 shows the relationship between the data value of the TMR element MTJ4 and the output signal O7b8 of the A/D converter in case of using the read circuit shown in FIG. 65.

TABLE 6
MTJ4
DATA VALUE	1	0
READ POTENTIAL	Vtotal < R7b8	R7b8 < Vtotal
OUTPUT SIGNAL	O7b8	1	0
OF A/D
CONVERTER

[0638] The TMR element MTJ4 is an element having a highest resistance value 2³R and a variation 2³R of the highest resistance value in a plurality of the TMR elements in the read block.

[0639] Therefore, when the data value of the TMR element MTJ4 is 1, the read potential Vtotal depending on the sum resistance value Rtotal of a plurality of the TMR elements in the read block (minus side input signals of the differential amplifiers DI0, . . . , DI14) is a value constantly lower than the reference potential R7b8 of the A/D converter.

[0640] In this case, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, O7b8 to O14b15 are constantly 1.

[0641] Furthermore, when the data value of the TMR element MTJ4 is 0, the read potential Vtotal depending on the sum resistance value Rtotal of a plurality of the TMR elements in the read block is a value constantly higher than the reference potential R7b8 of the A/D converter.

[0642] In this case, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, O0b1 to O7b8 are constantly 0.

[0643] That is, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, O7b8 is constantly 1 when the data value is 1 and it is constantly 0 when the data value is 0.

[0644] Therefore, judgment can be made upon the data value of the TMR element MTJ4 based on O7b8.

[0645] Table 7 shows the relationship between the data value of the TMR element MTJ3 in the read block and the output signals O3b4, O7b8 and O11b12 from the A/D converter when using the read circuit shown in FIG. 65.

TABLE 7
MTJ3
DATA VALUE	1	0	1	0
READ POTENTIAL	Vtotal < R3b4	R3b4 < Vtotal < R7b8	R7b8 < Vtotal < R11b12	R11b12 < Vtotal
OUTPUT SIGNAL	O3b4	1	0	0	0
OF A/D	O7b8	1	1	0	0
CONVERTER	O11b12	1	1	1	0

[0646] The TMR element MTJ3 is an element having the second highest resistance value 2²R and a variation 2²R of the second highest value among a plurality of the TMR elements in the read block.

[0647] Therefore, when the data value of the TMR element MTJ3 is 1, the read potential Vtotal depending on the sum resistance value Rtotal of a plurality of the TMR elements in the read block is any of the following:

[0648] a value lower than the reference potential R3b4; or

[0649] a value higher than the reference potential R7b8 and lower than the reference potential R11b12.

[0650] When the read potential Vtotal depending on the sum resistance value Rtotal is lower than the reference potential R3b4, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O3b4, O7b8 and O11b12 are constantly 1.

[0651] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R7b8 and lower than the reference potential R11b12, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O3b4 and O7b8 are constantly 0 and O11b12 is constantly 1.

[0652] Moreover, when the data value of the TMR element MTJ3 is 0, the read potential Vtotal depending on the sum resistance value Rtotal of a plurality of the TMR elements in the read block is any of the following:

[0653] a value higher than the reference potential R3b4 and lower than the reference potential R7b8, or

[0654] a value higher than the reference potential R11b12.

[0655] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R3b4 and lower than the reference potential R7b8, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O3b4 is constantly 0 and O7b8 and O11b12 are constantly 1.

[0656] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R11b12, at least O3b4, O7b8 and O11b12 are constantly 0 among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter.

[0657] In this manner, the relationship between the data value of the TMR element MTJ3 and the output signals O3b4, O7b8 and O11b12 from the A/D converter has been revealed.

[0658] Therefore, by processing the output signals O3b4, O7b8 and O11b12 from the A/D converter by using a logic circuit (which will be described later), the data value of the TMR element MTJ3 can be judged.

[0659] Tables 8 and 9 show the relationship between the data value of the TMR element MTJ2 in the read block and the output signals O1b2, O3b4, O5b6, O7b8, O9b10, O11b12 and O13b14 from the A/D converter.

TABLE 8
MTJ2
DATA VALUE
READ	1	0	1	0	1
POTENTIAL	Vtotal < R1b2	R1b2 < Vtotal < R3b4	R3b4 < Vtotal < R5b6	R5b6 < Vtotal < R7b8	R7b8 < Vtotal < R9b10
OUTPUT	O1b2	1	0	0	0	0
SIGNAL	O3b4	1	1	0	0	0
OF A/D	O5b6	1	1	1	0	0
CONVERTER	O7b8	1	1	1	1	0
	O9b10	1	1	1	1	1
	O11b12	1	1	1	1	1
	O13b14	1	1	1	1	1

[0660]

TABLE 9
MTJ2
DATA VALUE	0	1	0
READ POTENTIAL	R9b10 < Vtotal < R11b12	R11b12 < Vtotal < R13b14	R13b14 < Vtotal
OUTPUT SIGNAL OF A/D CONVERTER
01b2	0	0	0
03b4	0	0	0
05b6	0	0	0
07b8	0	0	0
09b10	0	0	0
011b12	1	0	0
013b14	1	1	0

[0661] Among a plurality of the TMR elements in the read block, the TMR element MTJ2 has a third highest resistance value 2¹R and a variation 2¹R of the third highest resistance value.

[0662] Therefore, when the data value of the TMR element MTJ2 is 1, the read potential Vtotal depending on the sum resistance value Rtotal of a plurality of the TMR elements in the read block is any one of the following:

[0663] a value lower than the reference potential R1b2; or

[0664] a value higher than the reference potential R3b4 and lower than the reference potential R5b6; or

[0665] a value higher than the reference potential R7b8 and lower than the reference potential R9b10; or

[0666] a value higher than the reference potential R11b12 and lower than the reference potential R12b13.

[0667] When the read potential Vtotal depending on the sum resistance value Rtotal is a value lower than the reference potential R1b2, at least O1b2, O3b4, O5b6, O7b8, O9b10, O11b12 and O13b14 are constantly 1 among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter.

[0668] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R3b4 and lower than the reference potential R5b6, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O1b2 and O3b4 are constantly 0 and O5b6, O7b8, O9b10, O11b12 and O13b14 are constantly 1.

[0669] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R7b8 and lower than the reference potential R9b10, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O1b2, O3b4, O5b6 and O7b8 are constantly 0 and O9b10, O11b12 and O13b14 are constantly 1.

[0670] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R11b12 and lower than the reference potential R13b14, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O1b2, O3b4, O5b6, O7b8, O9b10 and O11b12 are constantly 0 and O13b14 is constantly 1.

[0671] Further, when the data value of the TMR element MTJ2 is 0, the read potential Vtotal depending on the sum resistance value Rtotal of a plurality of the TMR elements in the read block is any one of the following:

[0672] a value higher than the reference potential R1b2 and lower than the reference potential R3b4; or

[0673] a value higher than the reference potential R5b6 and lower than the reference potential R7b8; or

[0674] a value higher than the reference potential R9b10 and lower than the reference potential R11b12; or

[0675] a value higher than the reference potential R13b14.

[0676] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R1b2 and lower than the reference potential R3b4, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O1b2 is constantly 0 and O3b4, O5b6, O7b8, O9b10, O11b12 and O13b14 are constantly 1.

[0677] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R5b6 and lower than the reference potential R7b8, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O1b2, O3b4 and O5b6 are constantly 0 and O7b8, O9b10, O11b12 and O13b14 are constantly 1.

[0678] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R9b10 and lower than the reference potential R11b12, among output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O1b2, O3b4, O5b6, O7b8 and O9b10 are constantly 0 and O11b12 and O13b14 are constantly 1.

[0679] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R13b14, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O1b2, O3b4, O5b6, O7b8, O9b10, O11b12 and O13b14 are constantly 0.

[0680] In this manner, the relationship between the data value of the TMR element MTJ2 and the output signals O1b2, O3b4, O5b6, O7b8, O9b10, O11b12 and O13b14 has been revealed.

[0681] Therefore, by processing the output signals O1b2, O3b4, O5b6, O7b8, O9b10, O11b12 and O13b14 by using a logic circuit (which will be described later), the data value of the TMR element MTJ2 can be judged.

[0682] Tables 10 to 13 show the relationship between the data value of the TMR element MTJ1 in the read block and the output signals O0b1, O1b2, O2b3, O3b4, O4b5, O5b6, O6b7, O7b8, O8b9, O9b10, O10b11, O11b12, O12b3, O13b14 and O14b15 when using the read circuit illustrated in FIG. 65.

TABLE 10
MTJ1
DATA VALUE
READ	1	0	1	0
POTENTIAL	Vtotal < R0b1	R0b1 < Vtotal < R1b2	R1b2 < Vtotal < R2b3	R2b3 < Vtotal < R3b4
OUTPUT	O0b1	1	0	0	0
SIGNAL	O1b2	1	1	0	0
OF A/D	O2b3	1	1	1	0
CONVERTER	O3b4	1	1	1	1
	O4b5	1	1	1	1
	O5b6	1	1	1	1
	O6b7	1	1	1	1
	O7b8	1	1	1	1
	O8b9	1	1	1	1
	O9b10	1	1	1	1
	O10b11	1	1	1	1
	O11b12	1	1	1	1
	O12b13	1	1	1	1
	O13b14	1	1	1	1
	O14b15	1	1	1	1

[0683]

TABLE 11
MTJ1
DATA VALUE
READ	1	0	1	0
POTENTIAL	R3b4 < Vtotal < R4b5	R4b5 < Vtotal < R5b6	R5b6 < Vtotal < R6b7	R6b7 < Vtotal < R7b8
OUTPUT	O0b1	0	0	0	0
SIGNAL	O1b2	0	0	0	0
OF A/D	O2b3	0	0	0	0
CONVERTER	O3b4	0	0	0	0
	O4b5	1	0	0	0
	O5b6	1	1	0	0
	O6b7	1	1	1	0
	O7b8	1	1	1	1
	O8b9	1	1	1	1
	O9b10	1	1	1	1
	O10b11	1	1	1	1
	O11b12	1	1	1	1
	O12b13	1	1	1	1
	O13b14	1	1	1	1
	O14b15	1	1	1	1

[0684]

TABLE 12
MTJ1
DATA VALUE
READ	1	0	1	0
POTENTIAL	R7b8 < Vtotal < R8b9	R8b9 < Vtotal < R9b10	R9b10 < Vtotal < R10b11	R10b11 < Vtotal < R11b12
OUTPUT	O0b1	0	0	0	0
SIGNAL	O1b2	0	0	0	0
OF A/D	O2b3	0	0	0	0
CONVERTER	O3b4	0	0	0	0
	O4b5	0	0	0	0
	O5b6	0	0	0	0
	O6b7	0	0	0	0
	O7b8	0	0	0	0
	O8b9	1	0	0	0
	O9b10	1	1	0	0
	O10b11	1	1	1	0
	O11b12	1	1	1	1
	O12b13	1	1	1	1
	O13b14	1	1	1	1
	O14b15	1	1	1	1

[0685]

TABLE 13
MTJ1
DATA VALUE
READ	1	0	1	0
POTENTIAL	R11b12 < Vtotal < R12b13	R12b13 < Vtotal < R13b14	R13b14 < Vtotal < R14b15	R14b15 < Vtotal < R14b15
OUTPUT	O0b1	0	0	0	0
SIGNAL	O1b2	0	0	0	0
OF A/D	O2b3	0	0	0	0
CONVERTER	O3b4	0	0	0	0
	O4b5	0	0	0	0
	O5b6	0	0	0	0
	O6b7	0	0	0	0
	O7b8	0	0	0	0
	O8b9	0	0	0	0
	O9b10	0	0	0	0
	O10b11	0	0	0	0
	O11b12	0	0	0	0
	O12b13	1	0	0	0
	O13b14	1	1	0	0
	O14b15	1	1	1	0

[0686] Among a plurality of the TMR elements in the read block, the TMR element MTJ1 has a lowest resistance value 2⁰R and a variation 2⁰R of the lowest resistance value.

[0687] Therefore, when the data value of the TMR element is 1, the read potential Vtotal depending on the sum resistance value Rtotal of a plurality of the TMR elements in the read block is any one of the following:

[0688] a value lower than the reference potential R0b1; or

[0689] a value higher than the reference potential R1b2 and lower than the reference potential R2b3; or

[0690] a value higher than the reference potential R3b4 and lower than the reference potential R4b5; or

[0691] a value higher than the reference potential R5b6 and lower than the reference potential R6b7; or

[0692] a value higher than the reference potential R7b8 and lower than the reference potential R8b9;

[0693] a value higher than the reference potential R9b10 and lower than the reference potential R10b11; or

[0694] a value higher than the reference potential R11b12 and lower than the reference potential R12b13; or

[0695] a value higher than the reference potential R13b14 and lower than the reference potential R14b15.

[0696] When the read potential Vtotal depending on the sum resistance value is a value lower than the reference potential R0b1, all of the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter are 1.

[0697] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R1b2 and lower than the reference potential R2b3, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1 and O1b2 are constantly 0 and the remaining output signals O2b3, O3b4, O13b14 and O14b15 are constantly 1.

[0698] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R3b4 and lower than the reference potential R4b5, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, O2b3 and O3b4 are constantly 0 and the remaining output signals O4b5, O5b6, . . . O13b14 and O14b15 are constantly 1.

[0699] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R5b6 and lower than the reference potential R6b7, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, . . . O4b5 and O5b6 are constantly 0 and the remaining output signals O6b7, O7b8, . . . O13b14 and O14b15 are constantly 1.

[0700] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R7b8 and lower than the reference potential R8b9, among the output signals O01b, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, . . . O6b7 and O7b8 are constantly 0 and the remaining output signals O8b9, O9b10, . . . O13b14 and O14b15 are constantly 1.

[0701] When the read potential Vtotal depending on the sum reference value Rtotal is a value higher than the reference potential R9b10 and lower than the reference potential R10b11, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, O8b9 and O9b10 are constantly 0 and the remaining output signals O10b11, O11b12, . . . O13b14 and O14b15 are constantly 1.

[0702] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R11b12 and lower than the reference potential R12b13, among the output signals O01b, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, . . . O10b11 and O11b12 are constantly 0 and the remaining output signals O12b13, O13b14 and O14b15 are constantly 1.

[0703] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R13b14 and lower than the reference potential R14b15, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, . . . O12b13 and O13b14 are constantly 0 and the remaining output signal O14b15 is constantly 1.

[0704] Furthermore, when the data value of the TMR element MTJ1 is 0, the read potential Vtotal depending on the sum resistance value Rtotal of a plurality of the TMR elements in the read block is any one of the following:

[0705] a value higher than the reference potential R0b1 and lower than the reference potential R1b2; or

[0706] a value higher than the reference potential R2b3 and lower than the reference potential R3b4; or

[0707] a value higher than the reference potential R4b5 and lower than the reference potential R5b6; or

[0708] a value higher than the reference potential R6b7 and lower than the reference potential R7b8; or

[0709] a value higher than the reference potential R8b9 and lower than the reference potential R9b10; or

[0710] a value higher than the reference potential R10b11 and lower than the reference potential R11b12; or

[0711] a value higher than the reference potential R12b13 and lower than the reference potential R13b14; or

[0712] a value higher than the reference potential R14b15.

[0713] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R0b1 and lower than the reference potential R1b2, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1 is constantly 0 and the remaining output signals O1b2, O2b3, . . . O13b14 and O14b15 are constantly 1.

[0714] The read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R2b3 and lower than the reference potential R3b4, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, and O2b3 are constantly 0 and the remaining output signals O3b4, O4b5, O13b14 and O14b15 are constantly 1.

[0715] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R4b5 and lower than the reference potential R5b6, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, . . . O3b4 and O4b5 are constantly 0 and the remaining output signals O5b6, O6b7, . . . O13b14 and O14b15 are constantly 1.

[0716] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R6b7 and lower than the reference potential R7b8, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, O5b6 and O6b7 are constantly 0 and the remaining output signals O7b8, O8b9, . . . O13b14 and O14b15 are constantly 1.

[0717] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R8b9 and lower than the reference potential R9b10, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O01b, O1b2, . . . O7b8 and O8b9 are constantly 0 and the remaining output signals O9b10, O10b11, . . . O13b14 and O14b15 are constantly 1.

[0718] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R10b11 and lower than the reference potential R11b12, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, . . . O9b10 and O10b11 are constantly 0 and the remaining output signals O11b12, O12b13, O13b14 and O14b15 are constantly 1.

[0719] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R12b13 and lower than the reference potential R13b14, among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter, at least O0b1, O1b2, . . . O11b12 and O12b13 are constantly 0 and the remaining output signals O13b14 and O14b15 are constantly 1.

[0720] When the read potential Vtotal depending on the sum resistance value Rtotal is a value higher than the reference potential R14b15, all of the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter are 0.

[0721] In this manner, the relationship between the data value of the TMR element MTJ2 and the output signals O0b1, O1b2, O13b14 and O14b15 from the A/D converter has been revealed. Therefore, by processing the output signals O0b1, O1b2, O13b14 and O14b15 from the A/D converter by using a logic circuit (which will be described later), the data value of the TMR element MTJ1 can be judged.

[0722] {circle over (3)} Logic Circuit

[0723] Description has been given as to Circuit Example 1 of the read circuit in {circle over (1)} and the operation of Circuit Example 1, namely, the relationship between the output signals from the A/D converter and the data value of the TMR element in the read block in {circle over (2)}.

[0724] Description will now be given on a logic circuit which actually judges data values of the TMR elements MTJ1, MTJ2, MTJ3 and MTJ4 in the read block based on the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter.

[0725] FIG. 66 shows an example of the logic circuit which judges the data value of the TMR element MTJ4 based on the output signals from the A/D converter.

[0726] This logic circuit is constituted so as to satisfy the relationship shown in Table 6. In this example, the data value of the TMR element MTJ4 is judged based on the output signal O7b8 among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter.

[0727] Since the data value of the TMR element MTJ4 can be judged based on only a value of the output signal O7b8 as described above, the logic circuit which judges the data value of the TMR element MTJ4 is constituted by inverters IV1 and IV2 connected to each other in series.

[0728] FIG. 67 shows an example of the logic circuit which judges the data value of the TMR element MTJ3 based on the output signals from the A/D converter.

[0729] This logic circuit is constituted so as to satisfy the relationship shown in Table 7. In this example, the data value of the TMR element MTJ3 is judged based on the output signals O3b4, O7b8 and O11b12 among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter.

[0730] Since the data value of the TMR element MTJ3 can be judged based on the output signals O3b4, O7b8 and O11b12 as described above, the logic circuit which judges the data value of the TMR element MTJ3 is constituted by inverters IV3 and IV4 and NOR gate circuits NR1 and NR2.

[0731] For example, when O3b41, the data value of the TMR element MTJ3 is judges as 1. Moreover, when O3b40 and O7b81, the data value of the TMR element MTJ3 is judged as 0. When O3b40, O7b80 and O11b121, the data value of the TMR element MTJ3 is judged as 1. When O3b40, O7b80 and O11b120, the data value of the TMR element MTJ3 is judged as 0.

[0732] FIG. 68 shows an example of the logic circuit which judges the data value of the TMR element MTJ12 based on the output signals from the A/D converter.

[0733] This logic circuit is constituted so as to satisfy the relationship shown in Tables 8 and 9. In this example, the data value of the TMR element MTJ2 is judged based on the output signals O1b2, O3b4, O5b6, O7b8, O9b10, O11b12 and O13b14 among the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter.

[0734] The logic circuit which judges the data value of the TMR element MTJ2 is constituted by inverters IV5, IV6, IV7 and IV8 and NOR gate circuits NR3, NR4, NR5 and NR6.

[0735] For example, when O1b21, the data value of the TMR element MTJ2 is judged as 1. Further, when O1b20 and O3b41, the data value of the TMR element MTJ2 is judged as 0. When O1b20, O3b40 and O5b61, the data value of the TMR element MTJ2 is judged as 1.

[0736] FIG. 69 shows an example of the logic circuit which judges the data value of the TMR element MTJ1 based on the output signals from the A/D converter.

[0737] This logic circuit is constituted so as to satisfy the relationship shown in Tables 10 to 13. In this example, the data value of the TMR element MTJ1 is judged based on all the output signals O0b1, O1b2, . . . O13b14 and O14b15 from the A/D converter.

[0738] The logic circuit which judges the data value of the TMR element MTJ1 is constituted by inverters IV9, IV10, IV11, IV12, IV13, IV14, IV15 and IV16 and the NOR gate circuits NR7, NR8, NR9, NR10, NR11, NR12, NR13 and NR14.

[0739] For example, when O0b11, the data value of the TMR element MTJ1 is judged as 1. In addition, when O0b10 and O1b21, the data value of the TMR element MTJ1 is judged as 0. When O0b10, O1b20 and O2b31, the data value of the TMR element MTJ1 is judged as 1.

[0740] Incidentally, there are three patterns of the output signals O0b1, O1b2, O13b14 and O14b15 from the A/D converter, namely, a pattern that all the output signals are 1, a pattern that all the output signals are 0 and a pattern that both 0 and 1 exist.

[0741] Additionally, when both 0 and 1 exist, a border of 0 and 1 always exist. In this case, all the output signals on one side of the border are 0, and all the output signals on the other side of the same are 1.

[0742] (2) Circuit Example 2

[0743] In the above-described Circuit Example 1, a plurality of the reference potentials R0b1, R1b2, . . . R13b14 and R14b15 are generated by using a plurality of resistances connected to each other in series.

[0744] Thus, in Circuit Example 2, description will be given as to a technique which generates a reference potential or a reference current required for judging data of a plurality of the TMR elements in the read block by using the same TMR element as the memory cell.

[0745] {circle over (1)} Sense Amplifier

[0746] FIG. 70 shows Circuit Example 2 of the read circuit concerning the present invention.

[0747] This read circuit is constituted by an analog/digital converter (A/D converter) as a sense amplifier.

[0748] One end of the block BKjn consisting of four TMR elements connected to each other in parallel is connected to the power supply terminal through an N-channel MOS transistor SWA and a P-channel MOS transistor QP, and the other end is connected to the ground terminal. The four TMR elements in the block BKjn may be connected to each other in series rather than parallel.

[0749] A read current path means a path which runs from the power supply terminal to the ground terminal through the MOS transistors QP and SWA and a plurality of the TMR elements.

[0750] A current which is equal to or in proportion to the read current flowing through the read current path is also caused to flow to the first to 15th current paths by a current mirror circuit constituted by P-channel MOS transistors QP, QP0, QP14 and a differential amplifier DI15.

[0751] A reference potential Vclamp is inputted to a minus side input terminal of the differential amplifier DI15, and a potential of a connection node between the MOS transistors QP and SWA is inputted to the plus side input terminal. An output signal from the differential amplifier DI15 is inputted to gates of the P-channel MOS transistors QP, QP0, . . . QP14.

[0752] When the potential of the plus side input terminal of the differential amplifier DI15 is lower than Vclamp, the differential amplifier DI15 operates so as to lower the output potential and increase the current flowing through the P-channel MOS transistors, thereby heightening the potential of the plus side input terminal. Further, when the potential of the plus side input terminal of the differential amplifier DI15 is higher than Vclamp, the differential amplifier DI15 operates so as to heighten the output potential and reduce the current flowing through the P-channel MOS transistors, thereby lowering the potential of the plus side input terminal.

[0753] With such a negative feedback operation, the differential amplifier DI15 operates so as to make the potential of the plus side input terminal equal to Vclamp. When Vclamp is used as the read potential, the read current flows through the P-channel MOS transistor QP. Furthermore, the read current also flows through the P-channel MOS transistors QP0, QP14 by the current mirror circuit.

[0754] The read current flowing through the respective transistors QP0, . . . QP14 is compared with 14 types of the reference current outputted from reference current generation circuits 44-0, . . . 44-14, and its result is outputted as output signals O0b1, . . . O14b15.

[0755] The first current path means a path which runs from the power supply terminal to the ground terminal through the P-channel MOS transistor QP0 and the N-channel MOS transistor QN01. An inverter INV0 outputs an output signal O0b1 based on the potential of a connection node between the MOS transistors QP0 and QN01.

[0756] The N-channel MOS transistor QN00 is connected between the reference current generation circuit 44-0 and the ground point. A gate and a drain of the N-channel MOS transistor QN00 are connected to each other, and the gate is connected to a gate of the N-channel MOS transistor QN01.

[0757] The reference current generation circuit 44-0 outputs a reference potential R0b1. Actually, the reference current generation circuit 44-0 passes the current I00 to the N-channel MOS transistor QN00. Since the current I00 is subjected to current mirror by the N-channel MOS transistors QN00 and QN01, the current I01 equal to the current I00 also flows through the N-channel MOS transistor QN01.

[0758] On the other hand, a current IP0 according to the data values of a plurality of the TMR elements in the read block flows through the P-channel MOS transistor QP0.

[0759] When IP0 is larger than I01, the electric charge is supplied to the input node of the inverter INV0, and the potential of the node node0 hence increases. That is, the input signal of the inverter INV0 becomes 1 and the output signal O0b1 of the same becomes 0.

[0760] Furthermore, when IP0 is smaller than I01, the electric charge of the input node of the inverter INV0 is drawn out, and the potential of the node node0 hence lowers. That is, the input signal of the inverter INV0 becomes 0 and the output signal O0b1 of the same becomes 1.

[0761] In this manner, the output signal O0b1 of the inverter INV0 represents a result of comparison between the current IP0 flowing through the TMR element in the block BKjn and the output current I01 of the reference current generation circuit 44-0.

[0762] That is, when the current IP0 flowing through the TMR element in the block BKjn is larger than the output current I01 of the reference current generation circuit 44-0, the output signal O0b1 becomes 0. On the contrary, when it is smaller, the output signal O0b1 becomes 1.

[0763] The 15th current path is a path running from the power supply terminal to the ground terminal through the P-channel MOS transistor QP14 and the N-channel MOS transistor QN141. The inverter INV14 outputs an output signal O14b15 based on the potential of the connection node between the MOS transistors QP14 and QN141.

[0764] The N-channel MOS transistor QN140 is connected between the reference current generation circuit 44-14 and the ground point. A gate and a drain of the N-channel MOS transistor QN140 are connected to each other, and the gate is also connected to a gate of the N-channel MOS transistor QN141.

[0765] The reference current generation circuit 44-14 outputs a reference potential R14b15. Actually, the reference current generation circuit 44-14 passes the current I140 to the N-channel MOS transistor QN140. Since the current I140 is subjected to current mirror by the N-channel MOS transistors QN140 and QN141, the current I141 equal to the current I140 also flows through the N-channel MOS transistor QN141.

[0766] On the other hand, a current IP14 according to the data values of a plurality of the TMR elements in the read block flows through the P-channel MOS transistor QP14.

[0767] When IP14 is larger than the I141, the electric charge is supplied to the input node of the inverter INV0, and the potential of the node node14 hence increases. That is, the input signal of the inverter INV14 becomes 1 and the output signal O14b15 becomes 0.

[0768] Furthermore, when IP14 becomes smaller than I141, the electric charge of the input node of the inverter INV14 is drawn out, and the potential of the node node14 hence lowers. That is, the input signal of the inverter INV14 becomes 0 and the output signal O14b15 becomes 1.

[0769] In this manner, the output signal O14b15 of the inverter INV14 represents a result of comparison between the current IP14 flowing through the TMR element in the block BKjn and the output current I141 of the reference current generation circuit 44-14.

[0770] That is, when the current IP14 flowing through the TMR element in the block BKjn is larger than the output current I141 of the reference current generation circuit 44-14, the output signal O14b15 becomes 0. On the contrary, when it is smaller, the output signal O14b15 becomes 1.

[0771] Incidentally, in regard to the structures of the second to 14th current paths, these current paths have the same structures as those of the first to 15th current paths except that a value of the reference current outputted from the reference current generation circuit is different.

[0772] FIG. 71 shows a concrete example of the reference current generation circuit illustrated in FIG. 70.

[0773] Each of the reference current generation circuits 44-i (i0, 1, . . . 14) includes eight TMR elements MTJ4A, MTJ3A, MTJ2A, MTJ1A, MTJ4B, MTJ3B, MTJ2B and MTJ1B.

[0774] The TMR elements MTJ4A, MTJ3A, MTJ2A and MTJ1A have substantially the same circuit configuration and substantially the same device structure as those of the TMR elements MTJ4, MTJ3, MTJ2 and MTJ1 in one block in the memory cell array.

[0775] Similarly, the TMR elements MTJ4B, MTJ3B, MTJ2B and MTJ1B have substantially the same circuit configuration and substantially the same device structure as those of the TMR elements MTJ4, MTJ3, MTJ2 and MTJ1 in one block in the memory cell array.

[0776] Therefore, the relationship between the resistance values of the TMR elements MTJ4A, MTJ3A, MTJ2A and MTJ1A and the their storage data is as shown in Table 1. Moreover, the relationship between the resistance values of the TMR elements MTJ4B, MTJ3B, MTJ2B and MTJ1B and their storage data is also as shown in Table 1.

[0777] In this example, the TMR elements MTJ4A, MTJ3A, MTJ2A and MTJ1A are connected to each other in parallel, and the TMR elements MTJ4B, MTJ3B, MTJ2B and MTJ1B are also connected to each other in parallel. That is, this example is applied to the magnetic random access memory in which the TMR elements MTJ4, MTJ3, MTJ2 and MTJ1 in one block in the memory cell array are connected to each other in parallel.

[0778] Incidentally, as shown in FIGS. 172 and 173, when one block is constituted by four TMR elements connected to each other in series, the TMR elements MTJ4A, MTJ3A, MTJ2A and MTJ1A are connected to each other in series, and the TMR elements MTJ4B, MTJ3B, MTJ2B and MTJ1B are also connected to each other in series.

[0779] Predetermined data are stored in the TMR elements MTJ4A, MTJ3A, MTJ2A, MTJ1A, MTJ4B, MTJ3B, MTJ2B and MTJ1B in the reference current generation circuit 44-i in accordance with a value of the output signal (reference current) from the reference current generation circuit 44-i.

[0780] Tables 14 and 15 show the relationship between the output signals R0b1, R1b2, . . . R13b14 and R14b15 of the reference current generation circuit 44-i and the data values stored in the TMR elements MTJ4A, MTJ3A, MTJ2A, MTJ1A, MTJ4B, MTJ3B, MTJ2B and MTJ1B in the reference current generation circuit 44-i.

	TABLE 14
	Rb	MTJ-4A	MTJ-3A	MTJ-2A	MTJ-1A
	R0b1	1	1	1	1
	R1b2	0	1	1	1
	R2b3	1	0	1	1
	R3b4	0	0	1	1
	R4b5	1	1	0	1
	R5b6	0	1	0	1
	R6b7	1	0	0	1
	R7b8	0	0	0	1
	R8b9	1	1	1	0
	R9b10	0	1	1	0
	R10b11	1	0	1	0
	R11b12	0	0	1	0
	R12b13	1	1	0	0
	R13b14	0	1	0	0
	R14b15	1	0	0	0

[0781]

	TABLE 15
	Rb	MTJ-4B	MTJ-3B	MTJ-2B	MTJ-1B
	R0b1	0	1	1	1
	R1b2	1	0	1	1
	R2b3	0	0	1	1
	R3b4	1	1	0	1
	R4b5	0	1	0	1
	R5b6	1	0	0	1
	R6b7	0	0	0	1
	R7bB	1	1	1	0
	R8b9	0	1	1	0
	R9b10	1	0	1	0
	R10b11	0	0	1	0
	R11b12	1	1	0	0
	R12b13	0	1	0	0
	R13b14	1	0	0	0
	R14b15	0	0	0	0

[0782] It is to be noted that 1:1 and 2:1 in the drawing mean ratios of the current flowing through the current path.

[0783] The reference current generation circuit 44-i has the TMR elements having the same structure as that of the memory cell. Since a potential difference between the both ends of the TMR element is the same as a potential difference V between the both ends of the TMR element in the memory cell, the output current corresponds to a mean value (intermediate value) of the current generated by the TMR elements MTJ4A, MTJ3A, MTJ2A and MTJ1A and the current generated by the TMR elements MTJ4B, MTJ3B, MTJ2B and MTJ1B.

[0784] Table 16 shows the relationship between the data values of the memory cells (TMR elements) MTJ1, MTJ2, MTJ3 and MTJ4 in one block and the read current. Table 17 shows the reference current outputted by the reference current generation circuit 44-I (i0, 1, . . . 14).

TABLE 16
MTJ1	MTJ2	MTJ3	MTJ4	READ CURRENT
1	1	1	1	V 15/8R V (15R 15R)/8R(R R)
1	1	1	0	V (15R 14R)/8R(R R)
1	1	0	1	V (15R 13R)/8R(R R)
1	1	0	0	V (15R 12R)/8R(R R)
1	0	1	1	V (15R 11R)/8R(R R)
1	0	1	0	V (15R 10R)/8R(R R)
1	0	0	1	V (15R 9R)/8R(R R)
1	0	0	0	V (15R 8R)/8R(R R)
0	1	1	1	V (15R 7R)/8R(R R)
0	1	1	0	V (15R 6R)/8R(R R)
0	1	0	1	V (15R 5R)/8R(R R)
0	1	0	0	V (15R 4R)/8R(R R)
0	0	1	1	V (15R 3R)/8R(R R)
0	0	1	0	V (15R 2R)/8R(R R)
0	0	0	1	V (15R 1R)/8R(R R)
0	0	0	0	V 15/8(R R) V 15R/8R(R R)

[0785]

	TABLE 17
	44 i	Rb	REFERENCE CURRENT
	i 0	R0b1	V (15R 14.5R)/8R(R R)
	i 1	R1b2	V (15R 13.5R)/8R(R R)
	i 2	R2b3	V (15R 12.5R)/8R(R R)
	i 3	R3b4	V (15R 11.5R)/8R(R R)
	i 4	R4b5	V (15R 10.5R)/8R(R R)
	i 5	R5b2	V (15R 9.5R)/8R(R R)
	i 6	R6b7	V (15R 8.5R)/8R(R R)
	i 7	R7b8	V (15R 7.5R)/8R(R R)
	i 8	R8b9	V (15R 6.5R)/8R(R R)
	i 9	R9b10	V (15R 5.5R)/8R(R R)
	i 10	R10b11	V (15R 4.5R)/8R(R R)
	i 11	R11b12	V (15R 3.5R)/8R(R R)
	i 12	R12b13	V (15R 2.5R)/8R(R R)
	i 13	R13b14	V (15R 1.5R)/8R(R R)
	i 14	R14b15	V (15R 0.5R)/8R(R R)

[0786] Data which can be the criteria for judging a data value of each TMR element can be obtained by judging the relationship of largeness between the read current and a plurality of the reference currents.

[0787] According to the read circuit (sense amplifier) of this example, a plurality of the reference currents required for judging the data values are generated by using the TMR elements having the circuit configuration and the device structure equal to those of the TMR elements in one block in the memory cell array. As a result, the accurate reference currents can be generated, and the read operation can be stably executed.

[0788] Although the sense amplifier which compares the read current with a plurality of the reference currents is presumed in the above description, a plurality of the reference potentials can be also generated by using the TMR elements having the same structure as that of the memory cell in regard to the sense amplifier which compares the read potential with a plurality of the reference potentials.

[0789] FIG. 76 shows a concrete example of the reference potential generation circuit.

[0790] For example, the 15 reference potential generation circuits of this example are used, and the reference potentials R0b1, R1b2, . . . R14b15 of the read circuit shown in FIG. 65 are generated. The structure of the read circuit in this case is as shown in FIG. 174.

[0791] In the drawing, 2:1 represents a ratio of the current flowing through the current path.

[0792] A value of a constant current generated by a current source I is the same as a value of the read current with respect to the memory cell, for example, a value of a constant current generated by a current source I shown in FIG. 65.

[0793] Tables 18 and 19 show data values of the TMR elements MTJ1A, MTJ2A, MTJ3A, MTJ4A, MTJ1B, MTJ2B, MTJ3B and MTJ4B in the 15 reference potential generation circuits which generate the output potential Rb (0, . . . 14, 1, . . . 15).

	TABLE 18
	Rb	MTJ4A	MTJ3A	MTJ2A	MTJ1A
	R0b1	1	1	1	1
	R1b2	1	1	1	0
	R2b3	1	1	0	1
	R3b4	1	1	0	0
	R4b5	1	0	1	1
	R5b6	1	0	1	0
	R6b7	1	0	0	1
	R7b8	1	0	0	0
	R8b9	0	1	1	1
	R9b10	0	1	1	0
	R10b11	0	1	0	1
	R11b12	0	1	0	0
	R12b13	0	0	1	1
	R13b14	0	0	1	0
	R14b15	0	0	0	1

[0794]

	TABLE 19
	Rb	MTJ4B	MTJ3B	MTJ2B	MTJ1B
	R0b1	1	1	1	0
	R1b2	1	1	0	1
	R2b3	1	1	0	0
	R3b4	1	0	1	1
	R4b5	1	0	1	0
	R5b6	1	0	0	1
	R6b7	1	0	0	0
	R7b8	0	1	1	1
	R8b9	0	1	1	0
	R9b10	0	1	0	1
	R10b11	0	1	0	0
	R11b12	0	0	1	1
	R12b13	0	0	1	0
	R13b14	0	0	0	1
	R14b15	0	0	0	0

[0795] Table 20 shows the relationship between a sum resistance of MTJA (MTJ1A, MTJ2A, MTJ3A and MTJ4A) and MTJB (MTJ1B, MTJ2B, MTJ3B and MTJ4B) in the reference potential generation circuit and a potential difference generated by all the MTJs (which represents an output potential when the on resistance of the MOS transistor is ignored).

TABLE 20
	SUN RESISTANCE VALUE	POTENTIAL DIFFERENCE GENERATING
Rb	OF MTJA AND MTJB	BASED ON ALL MTJ ELEMENTS
R0b1	(15R 0.5R)/2	21 (15R 0.5R)/2 I (15R 0.5R)
R1b2	(15R 1.5R)/2	2I (15R 1.5R)/2 I (15R 1.5R)
R2b3	(15R 2.5R)/2	2I (15R 2.5R)/2 I (15R 2.5R)
R3b4	(15R 3.5R)/2	2I (15R 3.5R)/2 I (15R 3.5R)
R4b5	(15R 4.5R)/2	2I (15R 4.5R)/2 I (15R 4.5R)
R5bG	(15R 5.5R)/2	2I (15R 5.5R)/2 I (15R 5.5R)
R6b7	(15R 6.5R)/2	2I (15R 6.5R)/2 I (15R 6.5R)
R7b8	(15R 7.5R)/2	2I (15R 7.5R)/2 I (15R 7.5R)
R8b9	(15R 8.5R)/2	2I (15R 8.5R)/2 I (15R 8.5R)
R9b10	(15R 9.5R)/2	2I (15R 9.5R)/2 I (15R 9.5R)
R10b11	(15R 10.5R)/2	2I (15R 10.5R)/2 I (15R 10.5R)
R11b12	(15R 11.5R)/2	2I (15R 11.5R)/2 I (15R 11.5R)
R12b13	(15R 12.5R)/2	2I (15R 12.5R)/2 I (15R 12.5R)
R13b14	(15R 13.5R)/2	2I (15R 13.5R)/2 I (l5R 13.5R)
R14b15	(15R 14.5R)/2	2I (15R 14.5R)/2 I (15R 14.5R)

[0796] In this example, the sum resistance is reduced to approximately half by the parallel resistance connection of the TMR elements. However, if the current flowing through the TMR elements is, for example, doubled, there occurs no problem, and a plurality of the reference potentials can be generated.

[0797] In such a read circuit (sense amplifier), a plurality of the reference potentials required for judging the data values are also generated by using the TMR elements having the circuit configuration and the device structure equal to those of the TMR elements in one block in the memory cell array. As a result, the accurate reference potentials can be generated, and the read operation can be stably executed.

[0798] {circle over (2)} Operation

[0799] Table 21 shows the relationship between a data value of the TMR element MTJ1 in the read block and an output signal O7b8 from the A/D converter when using the read circuit shown in FIGS. 70 and 71.

TABLE 21
MTJ1
	DATA VALUE	1	0
	OUTPUT SIGNAL OF A/D CONVERTER	O7b8	1	0

[0800] Table 22 shows the relationship between a data value of the TMR element MTJ2 in the read block and output signals O3b4, O7b8 and O11b12 from the A/D converter.

TABLE 22
MTJ2
	DATA VALUE	1	0	1	0
	OUTPUT SIGNAL OF	O3b4	1	0	0	0
	A/D CONVERTER	O7b8	1	1	0	0
		O11b12	1	1	1	0

[0801] Tables 23 and 24 show the relationship between a data value of the TMR element MTJ3 in the read block and output signals O1b2, O3b4, O5b6, O7b8, O9b10, O11b12 and O13b14 from the A/D converter when using the read circuit shown in FIGS. 70 and 71.

TABLE 23
MTJ3
DATA VALUE	1	0	1	0	1
OUTPUT SIGNAL OF	O1b2	1	0	0	0	0
A/D CONVERTER	O3b4	1	1	0	0	0
	O5b6	1	1	1	0	0
	O7b8	1	1	1	1	0
	O9b10	1	1	1	1	1
	O11b12	1	1	1	1	1
	O13b14	1	1	1	1	1

[0802]

TABLE 24
MTJ3
DATA VALUE	0	1	0
OUTPUT SIGNAL OF	O1b2	0	0	0
A/D CONVERTER	O3b4	0	0	0
	O5b6	0	0	0
	O7b8	0	0	0
	O9b10	0	0	0
	O11b12	1	0	0
	O13b14	1	1	0

[0803] Tables 25 to 28 show the relationship between a data value of the TMR element MTJ4 in the read block and output signals O0b1, O1b2, O2b3, O3b4, O4b5, O5b6, O6b7, O7b8, O8b9, O9b10, O10b11, O11b12, O12b13, O13b14 and O14b15 from the A/D converter when using the read circuit shown in FIGS. 70 and 71.

TABLE 25
MTJ4
	DATA VALUE	1	0	1	0
	OUTPUT SIGNAL OF	R0b1	1	0	0	0
	A/D CONVERTER	R1b2	1	1	0	0
		R2b3	1	1	1	0
		R3b4	1	1	1	1
		R4b5	1	1	1	1
		R5b6	1	1	1	1
		R6b7	1	1	1	1
		R7b8	1	1	1	1
		R8b9	1	1	1	1
		R9b10	1	1	1	1
		R10b11	1	1	1	1
		R11b12	1	1	1	1
		R12b13	1	1	1	1
		R13b14	1	1	1	1
		R14b15	1	1	1	1