Wireless LAN receiver synchronization

[0001] 1. Field of the Invention

[0002] The invention generally relates to WLAN (Wireless Local Area Network) receivers, and in particular to synchronization processes in such WLAN receivers.

[0003] 2. Description of the Related Art

[0004] A wireless local area network is a flexible data communications system implemented as an extension to or as an alternative for, a wired LAN. Using radio frequency or infrared technology, WLAN systems transmit and receive data over the air, minimizing the need for wired connections. Thus, WLAN systems combine data connectivity with user mobility.

[0005] Today, most WLAN systems use spread spectrum technology, a wide-band radio frequency technique developed for use in reliable and secure communication systems. The spread spectrum technology is designed to trade-off bandwidth efficiency for reliability, integrity and security. Two types of spread spectrum radio systems are frequently used: frequency hopping and direct sequence systems.

[0006] The standard defining and governing wireless local area networks that operate in the 2.4 GHz spectrum, is the IEEE 802.11 standard. To allow higher data rate transmissions, the standard was extended to 802.11b that allows data rates of 5.5 and 11 Mbps in the 2.4 GHz spectrum. This extension is backwards compatible.

[0007] When operating a WLAN receiver, code synchronization is necessary because the code is the key to despreading the desired information. A good synchronization is achieved when the coded signal arriving at the receiver is accurately timed in both its code pattern position and its rate of chip generation.

[0008] Referring now to FIG. 1, the synchronization process performed in the WLAN receiver can be divided into two phases. First, a synchronization acquisition is performed in step 100 to initially synchronize the receiver with a received signal. The second part of the synchronization follows the initial acquisition since the receiver must continue to operate in such a way that it remains locked with its code reference. That is, the receiver exactly tracks in step 110 the coded incoming signal to cause its own code chip rate to match the incoming code chip rate as precisely as possible.

[0009] With respect to the synchronization algorithms used, receivers may be classified into data-aided and non data-aided receivers. The data-aided approach does not require a prior knowledge of the interference parameters but requires a training data sequence. Non data-aided (or blind) algorithms require no training data sequence but only knowledge of the desired user signal sequence and its timing.

[0010] Synchronization circuits in existing WLAN receivers still have a number of problems. One problem is that conventional circuits may be unstable in operation and sometimes work unreliably. Further, the circuits often are highly involved and therefore lead to high circuit development and manufacturing costs. Another disadvantage of existing synchronization circuits is that the phase adjustment process may be performed with insufficient digital resolution. Moreover, instability situations may occur in synchronization loops when performing the synchronization acquisition.

[0011] An improved WLAN receiver and operation method are provided that may allow for synchronization and mobile radio fading channel compensation particularly in high rate WLAN systems.

[0012] In one embodiment, a WLAN receiver is provided that comprises at least two acquisition units for performing a synchronization acquisition process and at least two tracking units for performing a synchronization tracking process. The at least two acquisition units are arranged for being operated sequentially and the at least two tracking units are arranged for being operated simultaneously.

[0013] In another embodiment, there may be provided a method of operating a WLAN receiver. The method comprises performing a synchronization acquisition and performing a synchronization tracking. The synchronization acquisition includes performing at least two acquisition processes sequentially, and the synchronization tracking includes performing at least two tracking processes simultaneously.

[0014] The accompanying drawings are incorporated into and form a part of the specification for the purpose of explaining the principles of the invention. The drawings are not to be construed as limiting the invention to only the illustrated and described examples of how the invention can be made and used. Further features and advantages will become apparent from the following and more particular description of the invention, as illustrated in the accompanying drawings, wherein:

[0015] FIG. 1 is a flowchart illustrating the phases which can be distinguished in a synchronization process of a WLAN receiver;

[0016] FIG. 2 is a block diagram illustrating the components of a WLAN receiver according to an embodiment;

[0017] FIG. 3 is a flowchart illustrating the process of activating the components shown in FIG. 2;

[0018] FIG. 4 is a timing chart of operating the WLAN receiver of FIG. 2 in a WLAN system that applies long preambles;

[0019] FIG. 5 is a timing chart that corresponds to that of FIG. 4 but applies to WLAN systems where short preambles are used; and

[0020] FIG. 6 is a flowchart illustrating a synchronization process according to an embodiment.

[0021] The illustrative embodiments of the present invention will be described with reference to the figure drawings.

[0022] Referring now to the drawings and particular to FIG. 2 which illustrates the components of a WLAN receiver according to an embodiment, the receiver has a radio-frequency part and a baseband part 200 that is connected to the radio-frequency part. The radio-frequency part is an analog circuit that receives an analog signal and provides a digitized representation thereof to the baseband part 200. For this purpose, the radio-frequency part comprises an analog-to-digital converter (ADC).

[0023] Moreover, the radio-frequency part performs an automatic gain control (AGC) to control the amplification gain dependent on the received signal power or strength. The AGC unit is located in the analog radio-frequency part and interchanges control signals with the digital circuitry of the baseband part 200.

[0024] The baseband part 200 of the WLAN receiver of the present embodiment shown in FIG. 2 has a number of units that are interconnected to form a data path. That is, the baseband part 200 receives the digitized input signal from the radio-frequency part and generates output data that is to be filtered, demodulated, decoded and descrambled for further processing.

[0025] When receiving the digitized input signal in the baseband part 200, a power normalization (PNO) is performed in unit 205 to normalize the power of the input signal. The power normalization may be performed under control of a diversity selection (DIV) unit 240 that controls antenna diversity and which is connected to the automatic gain controller of the radio-frequency part. For performing the diversity selection, unit 240 receives the normalized signal from unit 205.

[0026] The diversity selection unit 240 may further provide a control signal to preamble detection (PDT) unit 215. The preamble detection unit 215 receives the normalized signal from unit 205 and detects a preamble in this signal. A preamble is a special signal pattern used for synchronization acquisition.

[0027] As may be seen from FIG. 2, the preamble detection unit 215 provides output signals to a timing error correction (TEC) unit 210 and a frequency error correction (FEC) unit 220. These units are used to detect and correct timing errors and frequency errors, respectively.

[0028] As mentioned above, the preamble detection unit 215 receives the normalized input signal from power normalization unit 205. In addition, it receives input from the feedforward filter (DFE-F) 250 of a decision feedback equalizer 245. The feedforward filter 250 receives the output signal of the timing error correction unit 210 and filters this signal under control of decision feedback equalization controller (DFE-C) 255. The filtered signal is fed to the preamble detection unit 215.

[0029] As can further be seen from FIG. 2, the decision feedback equalization controller 255 may operate dependent on certain input signals that are received from the frequency error correction unit 220 and/or the non-coherent detection (NCD) unit 225. The non-coherent detection unit 225 filters and demodulates a signal that is received from the phase error correction (PEC) unit 235 to obtain a demodulated binary reference sequence. This binary reference sequence is fed into the decision feedback equalization controller 255 for joint processing with the data signal coming from frequency error correction unit 220.

[0030] The phase error correction unit 235 that provides a signal to the non-coherent detection unit 225 receives an output signal from the frequency error correction unit 220. That is, the frequency control and the phase control is done in two separate stages, and the phase error correction is performed based on a signal that has previously been corrected with respect to a frequency error.

[0031] As apparent from the figure, the phase error correction unit 235 further provides an input signal to the feedback filter 260 of the decision feedback equalizer 245. The feedback filter 260 filters this data to provide output data, and it is controlled by the decision feedback equalization controller 255. Further, the feedback filter 260 may receive a signal which is indicative of the data rate.

[0032] Moreover, there is provided a packet start detection (PST) unit 230 that detects the start of frame delimiter (SFD) portion in the received data signal to generate a packet start control signal. For this purpose, the packet start detection unit 230 receives input from the non-coherent detection unit 225.

[0033] As apparent from the foregoing description of the present embodiment, the receiver comprises a number of units that form a data path. Each unit is for performing a given function in the synchronization (acquisition and tracking) process. As each function of the individual units is required in only a given period of time, the units are activated in the present embodiment in a predetermined sequence. Once the function of a given unit is no longer required, the unit may be deactivated.

[0034] The activation sequence in the present embodiment is depicted in FIG. 3. First, the power normalization unit 205 and the diversity selection unit 240 are activated in steps 300 and 310, respectively. As soon as signals from these units are available, the preamble detection unit 215 is activated (step 320). Next, the non-coherent detection unit 225 is made active in step 330 to prepare for the operation of the frequency error correction unit 220 and the decision feedback equalizer 245 (steps 340 and 350). In step 360, the timing error correction unit 210 is activated, and then, the phase error correction unit 235 is begun to be operated in step 370. The last unit in the baseband part 200 of the WLAN receiver of the present embodiment that is activated is the packet start detection unit 230 (step 380). Activation of phase error correction unit 235 and/or packet start detection unit 230 may also be in parallel to activation of timing error correction unit 210.

[0035] Turning now to FIG. 4 which is a timing chart illustrating in more detail the synchronization procedure of the receiver in the present embodiment, it can be seen that the received input signal comprises a preamble portion 400 which is in the present case a long preamble, a start of frame delimiter (SFD) portion 405 having 16 symbols, a header 410 having 48 symbols, and the payload 415. The synchronization procedure starts with performing the power normalization in time period 420 at the beginning of the preamble 400. Further, the diversity selection unit 240 performs diversity selection in time period 425.

[0036] Once the diversity selection is done, the synchronization acquisition is started. First, there is performed a chip and symbol time acquisition in time period 430 that is of variable length. During that time, the preamble detection unit 215 detects the presence of preamble 400, detects the chip sampling or symbol start index and detects that the preamble is a long preamble. At the threshold event driven end of time period 430, the non-coherent detection unit 225 is given a time period 435 to perform the oscillator frequency acquisition. After about 40 symbols from the beginning of the preamble 400, the first frequency estimate is available so that the tracking phase of the synchronization process can be initiated.

[0037] As can be seen from FIG. 4, the oscillator frequency tracking is performed first in the present embodiment. The frequency tracking may be done in two subperiods 440 and 445.

[0038] Additionally, at the end of the first subperiod 440, operation of the decision feedback equalization controller 255 may be triggered. The decision feedback equalization controller 255 may perform some channel estimation in time period 450 and then compute filter coefficients in period 455 to control the feedforward filter 250 and/or the feedback filter 260.

[0039] At the beginning of period 460 the filter coefficients are frozen, the initial timing offset is corrected, and the initial phase offset is sufficiently corrected as well. The feedforward filter 250 is then operated in time period 460, and the feedback filter 260 is activated to operate in time period 465. Further, the chip and symbol timing tracking is performed in period 470, and also the phase tracking is done simultaneously. As shown in the chart of FIG. 4, the phase tracking may be divided into two subperiods 475 and 480, and it is to be noted that also the chip and symbol time checking may be subdivided.

[0040] Finally, it can be seen from FIG. 4 that an SFD detection is performed in time period 490. This time period starts after expiration of time period 485 which is of fixed length, and it ends up with the SFD portion 405. At the end of time period 490, coherent reception is secured which will take place in period 495.

[0041] Turning now to FIG. 5, a corresponding timing chart is shown in case of using short preambles 500. As can be seen from FIG. 5, most of the elements of the timing chart resemble the corresponding elements of FIG. 4 but may be shorter in time. Instead of using a decision feedback equalizer (DFE), a channel matched filter (CMF) may be used.

[0042] The sequence of the synchronization acquisition and tracking phases performed in the procedures of FIGS. 4 and 5 are illustrated in the flowchart of FIG. 6. First, a chip and symbol time acquisition is performed in step 600 (time period 430 or 530). Then, the oscillator frequency acquisition is done in step 610 that corresponds to time period 435 or 535. That is, the synchronization acquisition includes two separate processes that are performed sequentially. It is to be noted that more than two such acquisition processes may be performed in another embodiment.

[0043] Once acquisition is achieved, the tracking phase starts with step 620 of performing the oscillator frequency tracking in time periods 440, 445 or 540, 545. Then, chip and symbol time tracking and phase tracking are performed simultaneously in steps 630 and 640 (time periods 470-480 or 570-580). Again, it is to be noted that further tracking processes could be added simultaneously with steps 630 and 640. In addition, since there are also tracking processes 620 performed sequentially, further sequential processes could be added as well.

[0044] The embodiments described above may improve over conventional WLAN receivers in a number of aspects. First of all, the receivers according to the above embodiments includes a number of acquisition units 215, 225 that may be activated and deactivated sequentially. This avoids synchronization loops of higher order which could give rise to potential instabilities. Further, frequency and phase control are separately performed in units 220 and 235 and may therefore achieve much higher accuracy at the end of the phase control process. Moreover, those units 210, 250 that require higher sampling rates are arranged in the data path before those units 220, 235 that operate at reduced sampling rates, thus lowering the amount of hardware circuitry that is required. Another improvement may be that acquisition may use data-aided synchronization algorithms since it is done during the preamble portion 400, 500 of the received signal, while the time and phase tracking uses non data-aided synchronization algorithms which may be performed during the payload portions 415, 515 of the input signal. Moreover, the timing error correction unit 210 may be able to perform the time tracking even in case of a complete 50 ppm (parts per million) oscillator frequency offset, thus it may be insensitive or resistant with respect to an oscillator frequency offset.

[0045] As discussed above, the power normalization unit 205 is located in the data path directly behind the analog-to-digital converter of the radio-frequency part of the WLAN receiver so that the digital resolution, i.e. the width of the data words, in each other unit of the digital baseband part 200 may be reduced, thus leading to a significant simplification in the receiver design. Finally, there may be a timing and stability improvement due to the simple interface to the analog radio-frequency part of the receiver since the automatic gain control may entirely be performed in the analog radio-frequency part, thus avoiding a data feedback between the radio-frequency part and the baseband part 200 so that only a time insensitive stop signal is necessary to be fed back from the baseband part 200 to the radio-frequency part.

[0046] From the foregoing, it is apparent that a (timing and frequency) synchronization technique is provided that may be used in high rate, 802.11b compliant WLAN systems and that may further improve over conventional techniques with respect to mobile radio fading channel compensation.

[0047] While the invention has been described with respect to the physical embodiments constructed in accordance therewith, it will be apparent to those skilled in the art that various modifications, variations and improvements of the present invention may be made in the light of the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention. In addition, those areas in which it is believed that those of ordinary skill in the art are familiar, have not been described herein in order to not unnecessarily obscure the invention described herein. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrative embodiments, but only by the scope of the appended claims.