Encryption for a stream file in an FPGA integrated circuit

[0001] 1. Field of the Invention

[0002] The present invention relates to field programmable gate array (FPGA) integrated circuits. More particularly, the present invention relates to a method and apparatus for encrypting a data stream used to program an FPGA device.

[0003] 2. Background of the Invention

[0004] A field-programmable gate array (FPGA) is an integrated circuit (IC) that includes a two-dimensional array of general purpose logic circuits, called cells or blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing all Boolean functions of a few variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain sequential elements such as flip-flops. Two types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for manufacture.

[0005] FPGAs may typically include a physical template that includes an array of circuits, sets of uncommitted routing interconnects, and sets of user programmable switches associated with both the circuits and the routing interconnects. When these switches are properly programmed (set to on or off states), the template or the underlying circuit and interconnect of the FPGA is customized or configured to perform specific customized functions. By reprogramming the on-off states of these switches, an FPGA can perform many different functions. Once a specific configuration of an FPGA has been decided upon, it can be configured to perform that one specific function.

[0006] The user programmable switches in an FPGA can be implemented in various technologies, such as ONO antifuse, M-M antifuse, SRAM memory cell, Flash EPROM memory cell, and EEPROM memory cell. FPGAs that employ fuses or antifuses as switches can be programmed only once. A memory cell controlled switch implementation of an FPGA can be reprogrammed repeatedly. In this scenario, a NMOS transistor may be used as the switch to either connect or leave unconnected two selected points (A,B) in the circuit. The source and drain nodes of the transistor may be connected to points A, B respectively, and its gate node may be directly or indirectly connected to the memory cell. By setting the state of the memory cell to either logical 1 or 0, the switch can be turned on or off and thus point A and B are either connected or remain unconnected. Thus, the ability to program these switches provides for a very flexible device.

[0007] FPGAs may store the program that determines the circuit to be implemented in a RAM or PROM on the FPGA chip. The pattern of the data in this configuration memory (CM) determines the cell's functions and their interconnection wiring. Each bit of CM controls a transistor switch in the target circuit that can select some cell function or make (or break) some connection. By replacing the contents of CM, designers can make design changes or correct design errors. The CM can be downloaded from an external source or stored on-chip. This type of FPGA can be reprogrammed repeatedly, which significantly reduces development and manufacturing costs.

[0008] Design software may be used to program the FPGA. The design software may compile a specific configuration of the programmable switches desired by the end-user, into FPGA configuration data. The design software assembles the configuration data into a bit stream, i.e., a stream of ones and zeros, that is fed into the FPGA and used to program the configuration memories for the programmable switches. The bit stream is the data-pattern to be loaded into the CM that determines whether each memory cell stores a 1 or 0. The stored bit in each CM controls whether its associated transistor switch is turned on or off. End users typically use software to create the bit stream after they simulated, tested the design for the FPGA.

[0009] Referring to the flow chart of FIG. 1, a designer or end user programs an FPGA 100. The design software assembles the configuration data into a data stream 110. This act may also be performed by software personnel. The data stream may be stored on a source external to the FPGA 120. On start up, the external source sends the data stream to the FPGA 130. Once in the FPGA, the data stream configures the RAM or PROM within the FPGA.

[0010] In a FPGA that uses a data stream that is downloaded from an external source, a person may be able to intercept the data stream as it is being loaded onto the FPGA, between acts 120 and 130 of FIG. 1. This may allow such a person to reverse engineer the IC if he or she is able to read the data stream.

[0011] The present invention is directed towards a method and apparatus for encrypting a data stream used to program an FPGA device comprising determining if there is at least one gap in the data stream; determining whether encryption is enabled for the at least one gap in the data stream; and encrypting the data stream, if encryption is enabled for the at least one gap.

[0012] The present invention is also directed towards a method and apparatus for de-encrypting an encrypted data stream used to program an FPGA device comprising determining if there is at least one gap in the data stream; determining whether encryption was enabled for the at least one gap in the data stream; and de-encrypting the data stream, if encryption was enabled for the at least one gap.

[0013] FIG. 1 is a flow chart showing the prior art.

[0014] FIG. 2 is a flow chart showing one embodiment of the disclosed system.

[0015] FIG. 3 is a flow chart showing one embodiment of the disclosed system.

[0016] FIG. 4 is a flow chart showing one embodiment of the disclosed system.

[0017] Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

[0018] FIG. 2 refers to a flow chart describing one embodiment of the disclosed method. In the first act 200 a designer or user programs an FPGA 200. The design software assembles the configuration data into a data stream 210. The design software may inquire as to whether the designer or the user wishes to have the data stream encrypted. If the designer or user wants the data stream to be encrypted, then he or she may select the option for encryption at act 220. The data stream is encrypted at act 230. This act 230 may also be performed by software personnel. The data stream may be stored on a source external to the FPGA 240. The external data source may be a PROM, CPU or any other memory device. On start-up, the external source sends the data stream to the FPGA 250. The FPGA may de-encrypt the data stream prior to configuring the RAM or PROM 260. Once de-encrypted, the data stream configures the RAM or PROM within the FPGA 270. The RAM associated with each programmable transistor on the FPGA may also be referred to as RAM CELLS.

[0019] In many systems, the data stream is loaded into CM which is addressed by X and Y address lines running horizontally and vertically. During the configuration, the data stream bits are loaded sequentially column (Y) by column (Y). Within one column, it is loaded bit by bit from the top to the bottom (stepping through all the rows or X's). Some intersections of X and Y lines or addresses may have no physical CM bits since those locations may be used by logic modules or other components. Although there may be locations with no data stream bits on the FPGA device, the data stream still contains data in the form of 1's or 0's corresponding to those empty locations.

[0020] Consecutive empty locations in the addressing space may be referred to as a GAP. The stream data inside the gap is not written to the CM and therefore has no effect on the functionality of the configured FPGA. An address decoder may signal the beginning and also the end of such a gap. At the end of the gap, the integrity of the configuration data loaded up to this point may be checked by an on-chip 16 bit Cyclic Redundancy Check (CRC) circuit. In another embodiment of the disclosed system that uses a 16 bit CRC, the minimum gap size may be 17 bits. The first bit inside the gap may be the Encryption Enable bit. If the Encryption Enable bit is set, then the subsequent section of the data stream will be encrypted. The section may be defined as all the bits after the Encryption Enable Bit up to the beginning of the next gap. However, the sections may be defined in other ways. If encryption is enabled, every eighth (8th) bit may be complemented (changed from a 1 to a 0 and from a 0 to a 1). It is not necessary that only the 8^th bit be complemented, other bits may be complemented, random patterns or un-random patterns of data may be inserted in the data stream gaps. If the encrypted data stream is loaded into the CM of the FPGA, the FPGA may not function correctly. Thus the data stream may be de-encrypted prior to entering the CM but after entering the FPGA device. The encryption can be optionally set to on or off for each section, thus for a particular design, with a different on/off setting the data stream file can appear very different, thereby making reverse engineering more difficult.

[0021] Referring to FIG. 3, an illustration of one embodiment of the system is shown. The system receives the data stream at act 310. The system determines whether it has received the start of a gap at query 320. In one embodiment of the disclosed system a gap may be as small 2 bits. In an other embodiment of the disclosed system, a gap may be at least 17 bits in length upwards to at least 64 bits in length. The minimum of 17 bits may be due to the use of a 16 bit CRC. The system then determines whether encryption has been enabled for that gap at query 330. If encryption has been enabled, the system then complements every 8^th bit until the beginning of the next gap at act 340. The system performs this method until it determines that it has reached the end of the data stream at query 350.

[0022] Referring to FIG. 4, an other embodiment of the disclosed method is shown. The FPGA receives the encrypted data stream from the external source at act 410. The system then determines if it has received the start of a gap at query 420. If the system determines it has received the start of a gap, then the system determines whether the encryption was enabled at query 430. If the encryption was enabled, the system complements every 8^th bit (or other n^th bit if a number other than 8 was used) until the beginning of the next gap at act 440. Act 440 in effect de-encrypts the data stream. The system then determines whether it has received the end of the data stream at query 450. If the system determines that it has received the end of the data stream, then the system configures the RAM and/or PROM of the FPGA with the de-encrypted data stream at act 460.

[0023] In another embodiment of the present invention, portions of the data stream may be compressed and other portions of the data stream may be encrypted, thereby further altering the data stream and thus hindering those who may attempt to reverse engineer the data stream.

[0024] In another embodiment of the present invention, random bits may be inserted into the gaps of the data stream to further hinder those who may wish to reverse engineer the data stream.

[0025] While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims. Although the claims refer to sending the data stream to RAM CELLS on the FPGA, those skilled in the art are aware that the disclosed system also applies to those devices with other memory devices located in the FPGA, including without limitation PROMs.