Method of fabricating semiconductor memory device and semiconductor memory device driver

[0001] This application is based upon and claims priority of Japanese Patent Application No. 2002-049438, filed on Feb. 26, 2002, the contents being incorporated herein by reference.

[0002] 1. Field of the Invention

[0003] The present invention relates to a method of fabricating a semiconductor memory device and a semiconductor memory device, and more particularly to a method of fabricating a non-volatile semiconductor memory device having the step of erasing charges cumulated in a charge storage part such as a floating gate by irradiating ultraviolet rays onto the surface of a metal wiring line of a bonding pad and such a semiconductor memory device.

[0004] 2. Description of the Related Art

[0005] Semiconductor memories using MOSFETs (Metal Oxide Semiconductor Type Field Effect Transistor) are generally used for storing digital data. Among these semiconductor memories, an EEPROM (Electrically Erasable Programmable Read Only Memory) and a flash memory, which are electrically programmable ROMs, are used to store the program code of the cellular phone and a system BIOS (Basic Input Output System) of the mother board of the personal computer (PC).

[0006] The programmable ROMs as described above have the structure of storing information by accumulating charges in a charge storage part such as a floating gate.

[0007] It is known that hot electrons occur due to plasma used in the etching or aching step of the process for fabricating the semiconductor memory devices with the floating gates and charges resulting from the hot electros are injected in the floating gate. This may cause a memory malfunction. Further, if too many charges are stored, an insulating film that is in contact with the floating gate may be destroyed. In order to avoid these problems, the fabrication process is additionally provided with the step of erasing the charges stored in the floating gate by ultraviolet rays.

[0008] In the fabrication process for the general semiconductor memory devices including the programmable ROMs, it is known that a multilayer metallization is formed by the combination of deposition of a thin insulation or metal film, resist deposition, pattern transfer by photolithography, selective thin film removal by etching, and resist removal. Memory elements are formed by the combination of the multilayer metallization fabrication technique and MOS transistor fabrication technique. Further, the memory elements are packaged in order to prevent age deterioration of the memory elements function and implement the input/output function. In order to interconnect the input/output terminals of the package and the memory input/output signals on the semiconductor substrate, bonding pads electrically coupled with the memory elements formed on the substrate are formed.

[0009] However, the conventional fabrication method has the following problems. As has described, the final step on the substrate is to form the bonding pads. Thereafter, the charges stored in the floating gates are erased by irradiation of ultraviolet rays. In the step of forming the bonding pad parts, dry aching such as plasma aching using oxygen-based gas is employed to remove the resist. Then, wet aching is performed using solution that contains hydroxylamine in order to completely remove the resist. During the above process, the metal oxide film formed on the metallization is removed, so that the metallization is exposed.

[0010] In this case, chlorine (Cl) and another ion are deposited on the metallization exposed during the etching process for the bonding pad parts, and react with moisture in the atmosphere. This causes corrosion of the aluminum metallization after etching. For example, corrosion occurs by the following reaction: Al4CLAlCl₄3e,AlCl₄3H₂OAl(OH)₃3H4Cl.

[0011] Even in the clean room, the density of Cl may exceed a reference situation in which the wafer may be contaminated so that ions of 300E10 molecule/cm² have been deposited thereon after it remains for 24 hours in the uncontrolled state. Further, the solution for use in wet aching may contain slight Cl. These factors may cause corrosion.

[0012] Furthermore, corroding may be enhanced by such a mechanism that Cl ions and a reaction product deposited on the wafer by the resist removal apparatus and from another environment until the process of removing the charges stored in the floating gates by ultraviolet rays after the etching process for the bonding pad parts react with oxygen in the atmosphere with high optical energy of ultraviolet rays being used as activation energy when irradiating.

[0013] Taking into consideration the above, an object of the present invention is to provide a method of fabricating a semiconductor memory device capable of preventing metallization from being corroded and such a device.

[0014] To accomplish the above object, there is provided a method of fabricating a semiconductor memory device having a step of irradiating ultraviolet rays onto a metal interconnection at a bonding pad part and thus erasing charges stored in a charge storage part, the method further comprising the steps of: forming a protection film on a surface of the metal interconnection; and irradiating the ultraviolet rays onto the protection film and thus erasing the charges.

[0015] The above object of the present invention is also accomplished by a semiconductor memory device fabricated by irradiating ultraviolet rays onto a metal interconnection at a bonding pad part and thus erasing charges stored in a charge storage part, the semiconductor memory device comprising a protection film on a surface of the metal interconnection.

[0016] The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.

[0017] FIG. 1 is a view of a structure of a semiconductor memory device of the present invention;

[0018] FIG. 2 is a view of a part of the method of fabricating the semiconductor memory device wherein a bonding pad part and metallization that is patterned into a metal interconnection;

[0019] FIG. 3 is a view of a process following the process shown in FIG. 2 in which resist is coated for formation of wring pattern;

[0020] FIG. 4 is a view of a process following the process shown in FIG. 3 wherein the wiring pattern is exposed and is then etched;

[0021] FIG. 5 is a view of a process following the process shown in FIG. 4 wherein resist is removed and a metal interconnection is formed;

[0022] FIG. 6 is a view of a process following the process of FIG. 5 wherein a film for flattening and a passivation film are formed;

[0023] FIG. 7 is a view of a process following the process of FIG. 6 wherein resist for forming bonding pads is coated;

[0024] FIG. 8 is a view of a process following the process of FIG. 7 wherein the bonding pad part is etched;

[0025] FIG. 9 is a view of a process following the process shown in FIG. 8 wherein a resist hardened part is removed by wet aching;

[0026] FIG. 10 is a view of a process following the process in FIG. 9 wherein oxygen gas based plasma aching is performed;

[0027] FIG. 11 is a view of a status after plasma aching; and

[0028] FIGS. 12(A) and 12(B) show the results of the secondary ion-mass analysis, wherein FIG. 12(A) relates to wet aching following plasma aching, and FIG. 12(B) relates to plasma aching following wet aching.

[0029] A description will now be given of embodiments of the present invention with reference to the accompanying drawings.

[0030] FIG. 1 shows a structure of the semiconductor memory device of the present invention. The semiconductor memory device that is assigned to a reference numeral of 1 in FIG. 1 has a structure of the flash memory.

[0031] The structure of the semiconductor memory device 1 is described. Gates 3 are formed on a silicon (Si) substrate 2, and a film 4 for flattening is formed so as to cover the gates 3. Via wirings 5 are formed for making connections between the silicon substrate 2 and a metal interconnection 6. An interlayer insulating film 7 is formed on the metal interconnection 6. A via wiring 8 is formed to electrically connect the metal interconnection 6 and a metal interconnection 9 located above the interconnection 6. A film 10 for flattening is formed on the interlayer insulating film 7 so as to cover the metal interconnection 9. Another interlayer insulating film 11 is formed on the flattening film 10, and a via wiring 12 is formed to electrically connect the metal interconnection 9 and an upper metal interconnection 13. A film 14 for flattening is formed on the interlayer insulating film 11 so as to cover the metal interconnection 13. A passivation film 15 is formed on the flattening film 14 and is opened at a bonding pad part 17. An oxide coating film 16 is formed on the interconnection 13 at the bonding pad part 17.

[0032] The via wirings 5, 8 and 12 are made of tungsten (W), and the films 4, 10 and 14 for flattening are SOG (Spin On Glass), HSQ (Hydrogen Silse Quioxane) or BPSG (Boron PhosphoSilicate Glass). The interconnections 6, 9 and 13 are made of aluminum (Al), copper (Cu), gold (Au), platinum (Pt) or W. The interlayer insulating films 7 and 11 are silicon oxide films formed by CVD (Chemical Vapor Deposition). The passivation film 15 is a silicon nitride film. The oxide coating film 16 is formed by oxidizing the metal interconnection 13. When the interconnection 13 is made of Al, the film 16 is an aluminum oxide.

[0033] Each of the gates 3 has a structure such that a tunnel oxide film 3a, a floating gate 3b, an insulating film 3c, a control gate 3d and an electrode 3e are stacked on the surface of the silicon substrate 2 in that order. The floating gate 3b may be made of polysilicon, and stores charges by the hot carriers and tunneling effect so that information can be memorized. The control gate 3d may be made of polysilicon, and the electrode 3e may be tungsten silicide (WSI).

[0034] Preferably, the oxide coating film 6 formed on the metal interconnection 13 at the bonding pad part 17 is 3.0 nm thick or more.

[0035] By forming the oxide coating film 16 on the surface of the metal interconnection 13 at the bonding pad part 17, it becomes possible to prevent Cl and Cl ions from being deposited on the metal interconnection 13 and to prevent occurrence of corrosion.

[0036] In order to erase the charges injected in the floating gate 3b at the stage of plasma etching or the like, ultraviolet rays are irradiated onto the metal interconnection 13 at the bonding pad part 17. During irradiation, the surface of the metal interconnection 13 is protected by the oxide coating film 16, so that an element and ionic species that accelerate corrosion of Cl and Cl ions can be prevented from being deposited. Thus, corrosion can be avoided even in the process of irradiating ultraviolet rays that facilitates the occurrence of corrosion.

[0037] The films 4, 10 and 14 for flattening are not limited to SOG, HSQ or BPSG. It is to be noted that it is preferable to employ an insulating film that has a relatively low relative permittivity in order to reduce the wiring capacitance.

[0038] Nitride film may be substituted for the oxide film 16 that is obtained by oxidizing the metal interconnection 13 and serves as the protection film on the metal interconnection 13 at the bonding pad part 17.

[0039] A description will now be given of the method of fabricating the semiconductor memory device according to an embodiment of the present invention.

[0040] FIG. 2 shows a part of the process for fabricating the semiconductor memory device, in which the bonding pad part and growth of the metal interconnection are depicted.

[0041] Referring to FIG. 2, The gates 3 are formed on the silicon substrate 2, and the film 4 for flattening is formed so as to cover the gates 3. The via wiring 5 for connection between the silicon substrate 2 and the metal interconnection 5 is formed. The interlayer insulating film 7 is formed on the metal interconnection 6. The via wiring 8 is formed to electrically connect the metal interconnection 6 and the metal interconnection 9 located above it. The film 10 for flattening is formed on the interlayer insulating film 7 so as to cover the metal interconnection 9. The interlayer insulating film 11 is formed on the flattening film 10, and the via wiring 12 for electrically connecting the metal interconnection 9 and the upper wiring is formed. The gate 3 has the structure in which the tunnel oxide film 3a, the floating gate 3b, the insulating film 3c, the control gate 3d and the electrode 3e are stacked in that order from the surface of the silicon substrate 2. The floating gate 3b may be polysilicon. The charges are stored in the floating gates 3b by hot carriers and tunnel effect so that the storage function can be implemented. The control gate 3d may be polycide, and the electrode 3e is W.

[0042] The above-mentioned layer structure can be formed by the photolithography technique.

[0043] The process shown in FIG. 2 is to grow metal interconnection substance 13a for interconnection on the interlayer insulating film 11.

[0044] The metal interconnection substance 13a is Al with Cu slightly added in order to improve electromigration (EM) and stressmigration (SM). The metal interconnection substance 13a may be grown by CVD. In order to prevent exposure reflection, titanium (Ti) or titanium nitride (TiN) may be sandwiched between Al layers, or TiN or W serving as barrier metal may be formed below the Al film or additionally thereon.

[0045] FIG. 3 shows a process following the process shown in FIG. 2, in which resist is coated for forming interconnection or wiring pattern.

[0046] Resist 20 is coated on the metal interconnection substance 13a in order to shape it into the wiring pattern.

[0047] FIG. 4 shows a process following the process in FIG. 3 in which the interconnection pattern is exposed and is then etched.

[0048] By the photolithography technique, the resist 20 shown in FIG. 3 is developed using mask so as to be formed into a desired pattern. Then, the metal interconnection substance 13a shown in FIG. 3 is etched with the resist pattern 20 used as mask, so that the structure shown in FIG. 4 can be defined. Etching may be RIE (Reactive Ion Etching) using Cl gas.

[0049] FIG. 5 shows a process following the process shown in FIG. 4, in which the resist is removed and a metal interconnection is formed.

[0050] The resist pattern 20a used as mask at the time of etching in FIG. 4 is ached by oxide-based plasma aching. This results in the metal interconnection 13 shown in FIG. 5.

[0051] FIG. 6 shows a process following the process shown in FIG. 5, in which a flattening film and a passivation film are formed.

[0052] The flattening film 14 is formed so as to cover the metal interconnection 13 formed in the process of FIG. 5. The flattening film 14 may be a material having a relatively low relative permittivity such as SOG, HSQ or BPSG. The surface is flattened by CMP (Chemical Mechanical Polishing). A passivation film 15a made of silicon nitride is formed on the flattened surface for surface protection.

[0053] The process in FIG. 6 is followed by a process in FIG. 7, in which resist is coated for forming bonding pads.

[0054] Resist 21 is coated on the passivation film 15a for formation of the bonding pads.

[0055] FIG. 8 shows a process subsequent to that shown in FIG. 7, wherein the bonding pad part is etched.

[0056] Resist 21 in the structure shown in FIG. 7 is patterned into a resist pattern 21a. With the resist pattern 21a used as mask, the passivation film 15a is etched by RIE. The passivation film 15a thus etched is as shown in FIG. 8, in which the metal interconnection 13 is exposed so that the bonding pad part 17 can be defined. At that time, resist-hardened part 22 is defined by the surface of the metal interconnection 13, a sidewall of the etched part of the passivation film 15a, and the surface and sidewall of the resist pattern 21a.

[0057] FIG. 9 shows a process following that shown in FIG. 8, wherein the resist-hardened part is removed by wet aching.

[0058] The resist-hardened part 22 is removed by wet aching, and the structure shown in FIG. 9 is formed. Wet aching is carried out by a spin wet scrubber. In wet aching, a solution that contains hydroxylamine as the primary component. Since the above solution slightly contains corrosion element such as chlorine, the remainder of the solution is deposited on the surface of the metal interconnection 13 at the atom/molecule level.

[0059] FIG. 10 shows a process following that shown in FIG. 9, in which plasma aching with oxygen gas is performed.

[0060] Plasma aching is performed at a O₂ gas pressure of 1 Torr, a flow rate of 1000 sccm, an RF (Radio Frequency) power of 1KW for an aching time of 120 minutes.

[0061] FIG. 11 shows a layer structure available after plasma aching.

[0062] The resist 21 is completely removed, and the corrosion element such as chlorine deposited on the surface of the metal interconnection 13 is removed. In addition, the oxide film 16 is formed by oxidizing the metal interconnection 13 of aluminum. In the aching condition, the aluminum oxide film 16 can be formed 30 angstrom thick.

[0063] Then, ultraviolet rays are irradiated from the bonding pad part 17 in order to erase the charges stored in the floating gate 3b. It is desired that the minimum illuminance of ultraviolet rays is 25 mW/cm , and the amount of illuminance is 108 Wsec/cm².

[0064] The following are the results of the secondary ion-mass spectrography for observation of the surface of the metal interconnection 13.

[0065] The secondary ion-mass spectrography is an analysis method for detecting secondary ions among ionized particles obtained by projecting a condensed high-speed ion beam onto the surface of a solid sample in vacuum and sputtering elements that exist in the sample surface. The secondary ion-mass spectrography is mainly used to analyze quantitative and qualitative analysis of an element that exists in the surface of a semiconductor sample. The spectrography is also used for analyzing the element density distribution in the depth direction by utilizing a phenomenon that the sample is milled by sputtering.

[0066] FIGS. 12(A) and 12(B) show the results of the secondary ion-mass analysis. More particularly, FIG. 12(A) relates to wet aching following plasma aching, and FIG. 12(B) relates to plasma aching following wet aching.

[0067] The samples used in the analysis related to FIG. 12(A) are those obtained by removing resist by performing plasma aching and wet aching in this order after the process shown in FIG. 8 is completed. The samples used in FIG. 12(B) are those obtained by the series of processes shown FIGS. 7 to 11.

[0068] The horizontal axes of FIGS. 12(A) and 12(B) denote depth. The right edges correspond to the surface of the silicon substrate, and the depth increases toward the left edges.

[0069] It can be seen from comparison between FIGS. 12(A) and 12(B) that a process-based difference appears in a depth of 1.5 m to 3 m.

[0070] The thickness of the aluminum oxide film formed from the secondary ion signal is 29 angstroms for FIG. 12(A) and 31 angstroms for FIG. 12(B). Thus, it is possible to form the oxide film 16 that is 3 nm thick or more.

[0071] The oxide film 16 having a thickness of 3 nm or more prevents occurrence of corrosion resulting irradiation of ultraviolet rays.

[0072] Further, the peak of Cl ion for FIG. 12(B) is smaller than that for FIG. 12(A). It is therefore possible to reduce the quantity of wet aching solution and the quantity of Cl deposited from the atmosphere by performing wet aching and plasma aching in this order. It is expected that corrosion resulting from irradiation of ultraviolet rays for erasing of charges stored in the floating gate 3b be suppressed.

[0073] In the above description, the oxide coating film is formed by oxygen gas-based plasma aching. When the metal interconnection 13 is made of aluminum, another aching may be used. For example, high-temperature annealing in an environment containing oxygen gas may be employed. Any way can be employed that is capable of quickly forming the oxide film due to natural oxidization of the wafer that remains in the atmosphere. However, it is desirable to form the oxide film in conjunction with the resist removal process in the bonding pad part formation process since Cl ions and reaction products start to be deposited on the metal interconnection 13 immediately after the insulating film etching process in the bonding pad part formation process. This reduces the wasteful standby time and makes it possible to form the oxide film on the surface of the metal interconnection on which only a small quantity of impurity is deposited. Thus, occurrence of corrosion can be avoided effectively.

[0074] Aluminum used for the metal interconnection 13 may be replaced by a metal that contains a primary component of copper, which is a low resistance than and is superior to aluminum. Cu is likely to be corroded because of its chemical nature, as compared to Al. However, it is possible to prevent copper from being corroded by irradiation of ultraviolet rays by forming the oxide film on the surface by plasma aching. In this case, the oxide film is a copper oxide film.

[0075] Similarly, Au, Pt or W may be used for the metal interconnection 13.

[0076] The present invention is not limited to plasma aching for forming the oxide film 16, but includes a process of forming the oxide film 16 by aching with oxygen.

[0077] The present invention is not limited to the aforementioned process of fabricating the semiconductor memory device having irradiation ultraviolet rays for erasing the charges stored in the floating gate 3b. For instance, the present invention may be applied to the process of irradiating ultraviolet rays for avoiding occurrence of corrosion in the process of fabricating a nonvolatile semiconductor memory device in which electrons are injected at the trap level in SiN while the gate insulating film of the MOSFET is formed by ONO (SiO₂/SiN/SiO₂).

[0078] A nitride coating film may be substituted for the oxide coating film 16 as the protection film formed on the metal interconnection 13.

[0079] It is also possible to employ a process of nitriding the surface of the metal interconnection substance in such a way as to expose the surface of the metallization in N* (nitrogen radical) atmosphere or a mixed atmosphere of N* and H* (hydrogen radical).

[0080] As described above, according to the present invention, the protection film is formed on the metal interconnection at the bonding pad part. It is therefore possible to prevent deposition of corrodent elements such as chlorine and fluorine that corrode the metal interconnection and deposition of chloride ions that facilitates occurrence of corrosion at the time of irradiating ultraviolet rays. Thus, occurrence of corrosion can be avoided.

[0081] The foregoing is considered as illustrative only of the principles of the present invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be regarded as falling within the scope of the invention in the appended claims and their equivalents.