METHOD OF FORMING A GERMANIUM FILM ON A SEMICONDUCTOR SUBSTRATE THAT INCLUDES THE FORMATION OF A GRADED SILICON-GERMANIUM BUFFER LAYER PRIOR TO THE FORMATION OF A GERMANIUM LAYER

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device having a low dislocation defect germanium layer and in particular, to semiconductor devices comprising a low dislocation defect germanium layer grown on an ultra-thin silicon-germanium buffer layer. The present invention further concerns the methods for making and using such devices.

[0003] 2. Discussion of Related Art

[0004] Forming high quality germanium layers on a substrate is desirable. Germanium (Ge) layers grown on a silicon (Si) substrate can be used to make high mobility devices. There is thus increasing interest in using SiGe alloy as a material for microelectronic and optoelectronic device applications. Ge is known to have high carrier mobility (e.g., high hole and electron mobility) and optical absorption as compared to Si. This is one reason why Ge is useful for devices that require enhanced performance and/or high quantum efficiency. Examples of devices that would benefit from the use of a Ge film include metal-oxide-semiconductor (MOS) transistors, optical detectors, and other optoelectronic devices, to name a few.

[0005] There is a large lattice-mismatched of about 4% between the Ge and the Si. The mismatched lattice hinders the growth of coherently strained Ge beyond a critical thickness, at which point there is formation of misfit dislocations. These mistfit dislocations subsequently form threading segments, threading dislocations that penetrate the entire epitaxial layer and terminate at the free surface. Threading dislocations are undesirable defects since they cause highly faulted epitaxial Ge layers which reduces the carrier mobility, adversely affects the electronic quality and performance reliability of various electronic devices. Threading dislocations also increase the dark current in an optical detector, which induces noises in the signal. And, threading dislocations increase current leakage between the source and drain regions of a MOS transistor.

[0006] With lattice mismatch making growing Ge directly on Si a problem, SiGe buffer layers have been used to minimize the effect of this problem. The SiGe buffer layers are often graded, from 0% Ge to 100% Ge, at a low rate of change, typically 10-20% Ge/m. To deposit the Ge layer, SiGe is first deposited as a buffer layer on a substrate (e.g., Si wafer), and Ge is finally deposited on the SiGe. This very low-slope grading scheme enables the gradual increase of the lattice constant of the semiconductor, which minimizes the generation of misfit and threading dislocation. However, the gradual change from 0% Ge to 100% Ge is often slow, and as such, necessitates the use of very thick buffer layers, typically 1-5 m.

[0007] The presence of thick buffer layers poses several problems. Typical deposition times for the buffer layer can be in excess of four hours, which imposes a severe penalty on factory throughput in high volume applications and increases wafer fabrication costs, particularly when single-wafer epitaxial reactors are used. High performance Si CMOS fabrication techniques are moving away from the use of bulk Si. The most promising device structures which will allow the extension of Si CMOS technology below 30 nm are believed to be depleted substrate (DST) and double-gate (DG) devices. Both DST and DG applications require active layers thinner than 500 A (0.005 m). The presence of thick buffer layers required by current state-of-the-art Ge deposition techniques makes Ge incompatible with these high-performance structures. There is also significant interest in using Ge detectors for optical clock applications in conventional CMOS technology. The use of thick buffer layers will result in severe planarity issues between the portion of the chip containing the Ge detector and the parts of the die containing Si-only devices. Films deposited in this manner develop significant surface undulations, which tend to trap dislocations. The trapping of dislocations causes new dislocations to be generated in order to relieve the stress developed due to lattice mismatch, which increases the overall dislocation density in the deposited layer. An intermediate chemical mechanical polishing (CMP) step may be necessary to restore planarity of the surface and relieve dislocation pileup.

[0008] The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

[0009] FIG. 1 illustrates an exemplary method of forming a graded germanium film which comprises a graded SiGe buffer layer and a substantially pure Ge top surface wherein the graded SiGe buffer layer is ultra-thin;

[0010] FIG. 2 illustrates an exemplary pure Ge film deposited on an ultra-thin graded SiGe buffer layer in accordance to the present invention;

[0011] FIG. 3 illustrates an exemplary method of selectively forming a graded germanium film which comprises an ultra-thin graded SiGe buffer;

[0012] FIGS. 4A to 4F illustrate an exemplary electronic device comprising a graded germanium film selectively formed on a substrate;

[0013] FIG. 5 illustrates an exemplary method of selectively forming a graded germanium film which comprises an ultra-thin graded SiGe buffer wherein the a graded germanium film is doped with a dopant, for example, phosphorous;

[0014] FIG. 6 illustrates an exemplary sequencing of dopant, precursor, and HCl flows to achieve heavy doping in selectively deposited Ge layers;

[0015] FIG. 7 illustrates an exemplary method of selectively forming a graded germanium film which comprises an ultra-thin graded SiGe buffer wherein the a graded germanium film is heavily doped with a dopant;

[0016] FIGS. 8A to 8D illustrate an exemplary semiconductor device (e.g., a transistor) that integrates a selectively deposited germanium film made in accordance to the present invention; and

[0017] FIGS. 9A to 9D illustrate an exemplary semiconductor device (e.g., a detector) that integrates a selectively deposited germanium film made in accordance to the present invention;

[0018] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, specific apparatus structures and methods have not been described so as not to obscure the present invention. The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention.

[0019] Germanium (Ge) layers having good surface morphology, low defect density, and thin buffer layers are the key issues in affecting the integration of silicon substrates having Ge layers for silicon integrated circuits in electronic and optoelectronic applications, for example, in making transistors and detectors.

[0020] The present invention directs to electronic devices having an epitaxial Ge film grown on an ultra-thin graded SiGe buffer layer. The epitaxial Ge film has a heavy in situ doping of above 10²⁰ per cm³, a low defect density and a high planarity. In one example, the SiGe buffer layer has a thickness of about 17 nm to 19 nm wherein the SiGe layer is formed directly on a substrate. The Ge film is formed on the ultra-thin SiGe buffer layer. The Ge film can have a threading dislocation density of less than 10⁹/cm². Additionally, the present invention directs to the methods of making the epitaxial Ge film above.

[0021] FIG. 1 illustrates an exemplary method 100 of forming a germanium silicon alloy Ge_xSi_y having an upper surface comprised of substantially pure germanium. The germanium silicon alloy Ge_xSi_y having an upper surface comprised of substantially pure germanium grown on a graded SiGe buffer layer is referred to as a graded SiGeGe film for short. The graded SiGeGe film has a gradient of increasing germanium concentration as the SiGeGe film extends from a substrate. At the top or near the top surface, the film comprised of only germanium and no SiGe alloy. The graded SiGeGe film can be formed in a conventional chemical vapor deposition (CVD) reactor. A silicon source gas, such as silane (SiH₄) and a germanium source gas such as germane (GeH₄) are used to form the graded SiGeGe film. The flow of the silicon source gas and the germanium source gas together with the deposition temperature are controlled to obtain the film gradient. In the method 100, simultaneously, the deposition temperature is linearly and gradually ramped down while the silicon source gas (e.g., SiH₄) is linearly and gradually ramped down and the germanium source gas (e.g., GeH₄) is linearly and gradually ramped up for a predetermined amount of time.

[0022] Continuing with FIG. 1, at box 102, a deposition chamber (e.g., CVD chamber) is prepared. The desired temperature and pressure for the deposition process is obtained. In one example, the temperature of the chamber is set to be about 625 C. to 700 C. and the pressure is set to be at atmospheric pressure (e.g., 1 atm). A carrier gas is injected into the CVD chamber. The carrier gas flow into the CVD chamber is maintained throughout the deposition process. The carrier is typically an inert gas (e.g., H₂, N₂, Ar, or He) but can be other suitable carrier gas depending on application. In one example, the carrier gas flow is introduced into the CVD chamber at a flow rate of about 20 L/minute.

[0023] At box 104 of FIG. 1, a substrate (e.g., silicon wafer) is loaded into the CVD chamber. The substrate can include a monocrystalline semiconductor wafer, a semiconductor-on-insulator wafer, or any other substrate used to form semiconductor devices. At box 106, the silicon source gas (e.g., SiH₄) is introduced into the CVD chamber. In one example, the silicon source gas is introduced at a rate of about 200 sccm.

[0024] Continuing with FIG. 1, at box 108, the graded SiGe buffer layer is formed on the substrate. While ramping down the temperature, simultaneously decrease the silicon source gas flow and increased the germanium source gas flow for a predetermined amount of time. More specifically, the temperature is decreased from a first (initial) temperature to a second temperature which is lower than the first temperature. The silicon source gas is decreased from a first flow rate to a second flow rate wherein the second flow rate for the silicon source gas is lower than the first flow rate. And, the germanium source gas is increased from a third flow rate (which is essentially 0 sccm) to a fourth flow rate. In one example, the predetermined amount of time ranges from 1.5 to 3.5 minutes and preferably, is about 2 minutes. The amount of time depends on the desirable thickness of the SiGe. In another example, for a predetermined amount of time, the temperature is linearly and gradually ramped down, from 625 C. down to 500 C. In yet another example, the silicon source gas is linearly and gradually ramped down, from 200 sccm down to 0 sccm; and, the germanium source gas is linearly and gradually ramped up, from 0 sccm up to 500 sccm. In another example, the silicon source gas is decreased at a rate of 1 sccm to 2 sccm per second. The temperature is decreased at a rate of 1 C. to 1.5 C. per second. And, the germanium source gas is increased at a rate of 3.8 sccm to 4.5 sccm per second. In yet another example, the temperature is decreased while simultaneously decreasing the silicon source gas and decreasing the germanium source gas is set a rate such that the threading dislocation is confined to the area near the substrate. In this example, the lower temperature and the faster decreasing rate for the temperature is preferred.

[0025] Continuing with FIG. 1, at box 110, the Ge film is formed on the graded SiGe buffer layer. To form the Ge film, the temperature is maintained at a predetermined level while the germanium source gas flow is also maintained constant at a predetermined flow rate for a duration necessary to achieve the desired thickness for the Ge film. In one example, the temperature is maintained at 500 C. for the duration of the time necessary to form the Ge film. In another example, the germanium source gas flow is maintained at 500 sccm for that duration. In yet another example, the temperature and the germanium source gas flow is maintained constant for a duration of 5-minute. In this example, an 81 nm Ge film can be formed on the SiGe buffer layer. The time necessary to form the Ge film depends on the desired thickness of the Ge film. At box 112, the substrate now having the SiGeGe film deposited thereon can be removed from the CVD chamber.

[0026] FIG. 2 illustrates a semiconductor substrate 200 the having a SiGeGe film formed using the method 100 described in FIG. 1. The SiGeGe film has a low defect density, low threading dislocation, and an ultra-thin SiGe buffer layer. FIG. 2 shows a substrate 202, (e.g., a semiconductor substrate or a monocrystalline silicon), an ultra-thin graded buffer SiGe layer 204 and a Ge film 206. In some cases, a very thin layer of Si may have been formed between the substrate 202 and the SiGe buffer layer 204 (e.g., when the silicon source is first introduced into the CVD chamber) before the formation of the SiGe buffer layer 204. In one example, the ultra-thin SiGe buffer layer 204 has a thickness less than 0.5 m and preferably, a thickness ranging from 17 nm to 30 nm (0.017 m to 0.030 m). In another example, the Ge film has a dislocation density less than 10⁹ per cm². The Ge film may have any desirable thickness depending on the application of the device that is incorporating the film. In one example, the Ge film has a thickness less than 5 m and preferably, a thickness ranging from 70 nm to 83 nm (0.070 m to 0.083 m).

[0027] FIG. 3 illustrates another exemplary method 300 to selectively form a graded SiGeGe film over a certain regions on a substrate such as a semiconductor wafer. In one example, a mask comprised of a dielectric material such as silicon oxide (SiO₂) is used and is deposited on the semiconductor wafer. The graded SiGeGe film is formed only over the exposed area of the wafer, the area not covered by the mask. A hydrochlorine source gas (e.g., HCl) is used to help to maintain the selectivity in the deposition of the graded SiGeGe film in that the HCl strips off (etches away) any SiGe and/or Ge that may be formed on the SiO₂ layer. The HCl also suppresses the nucleation of the graded SiGeGe over the SiO₂ layer. The resulting graded SiGeGe film is less rough and the film's threading dislocation density is dramatically improved.

[0028] Continuing with FIG. 3, in one example, at box 302, a deposition chamber (e.g., CVD chamber) is prepared. The desired temperature and pressure for the deposition process is obtained. In one example, the temperature of the chamber is set to be about 625 C. to 700 C. and the pressure is set to be at atmospheric pressure (e.g., 1 atm). A carrier gas is injected into the CVD chamber. The carrier gas flow into the CVD chamber is maintained throughout the deposition process. The carrier is typically an inert gas (e.g., H₂, N₂, Ar, or He) but can be other suitable carrier gas depending on application. In one example, the carrier gas flow is introduced into the CVD chamber at a flow rate of about 20 L/minute.

[0029] At box 304, a substrate (e.g., silicon wafer) is loaded into the CVD chamber. The substrate can include a monocrystalline semiconductor wafer, a semiconductor-on-insulator wafer, or any other substrate used to form semiconductor devices. At box 306, the silicon source gas (e.g., SiH₄) is introduced into the CVD chamber. In one example, the silicon source gas is introduced at a rate of about 200 sccm. Also at box 306, an etchant source gas such as hydrochlorine (HCl) is introduced into the CVD chamber. The etchant source gas flow into the CVD chamber is maintained throughout the deposition process. In one example, the etchant source gas is introduced at a rate of about 50 sccm.

[0030] At box 308, the graded SiGe buffer layer is selectively formed on the substrate. The substrate includes a dielectric mask formed thereon. While ramping down the temperature, simultaneously decrease the silicon source gas and increased the germanium source gas for a predetermined amount of time. In one example, the predetermined amount of time ranges from 1.5 to 3.5 minutes and preferably, is about 2 minutes. The amount of time depends on the desirable thickness of the SiGe. In another example, for a predetermined amount of time, the temperature is linearly and gradually ramped down, from 625 C. down to 500 C. In yet another example, the silicon source gas is linearly and gradually ramped down, from 200 sccm down to 0 sccm; and, the germanium source gas is linearly and gradually ramped up, from 0 sccm up to 500 sccm. In another example, the silicon source gas is decreased at a rate of 1 sccm to 2 sccm per second. The temperature is decreased at a rate of 1 C. to 1.5 C. per second. And, the germanium source gas is increased at a rate of 3.8 sccm to 4.5 sccm per second. In yet another example, the temperature is decreased while simultaneously decreasing the silicon source gas and decreasing the germanium source gas is set a rate such that the threading dislocation is confined to the area near the substrate. In this example, the lower temperature and the faster decreasing rate for the temperature is preferred.

[0031] Continuing with FIG. 3, at box 310, the Ge film is formed on the graded SiGe buffer layer. To form the Ge film, the temperature is maintained at a predetermined level while the germanium source gas flow is also maintained constant at a predetermined flow rate for a duration necessary to achieve the desired thickness for the Ge film. In one example, the temperature is maintained at 500 C. for the duration of the time necessary to form the Ge film. In another example, the germanium source gas flow is maintained at 500 sccm for that duration. In yet another example, the temperature and the germanium source gas flow is maintained constant for a duration of 5-minute. In this example, an 81 nm Ge film can be formed on the SiGe buffer layer. The time necessary to form the Ge film depends on the desired thickness of the Ge film. At box 312, the substrate now having the SiGeGe film deposited only in the exposed area of the wafer can be removed from the CVD chamber. Selectively forming the SiGe buffer layer and the Ge film using the method 300 above shows a dramatic improvement in surface planarity.

[0032] FIGS. 4A to 4D illustrate a cross-section of a structure comprising a substrate with a mask made out of dielectric material (e.g., silicon oxide) which is being used for the selective deposition of the graded SiGe buffer layer and the Ge film discussed in the method 300. The substrate can be a silicon wafer 406 as shown in FIG. 4A. Trenches 402 are then etched into the Si substrate 406 with conventional dry etching methods, as shown in FIG. 4B. The trenches 402 are then filled with silicon oxide (SiO₂) with a conventional deposition method, (e.g., plasma enhanced chemical vapor deposition or PE-CVD). A silicon oxide layer 404 is deposited on the entire surface of the wafer, as shown in FIG. 4C. Finally, the silicon oxide layer 404 is polished back with conventional chemical mechanical polishing to expose the silicon substrate 406 between the isolation trenches 402. The reference number 408 illustrates the exposed region in the silicon substrate 406.

[0033] The silicon substrate 406 shown in FIGS. 4A through 4D can then be subjected to selective deposition of the SiGe buffer layer and Ge film discussed in method 300 of FIG. 3. The SiGeGe layer 410 is deposited only on the exposed areas 408 of the substrate 406, as shown in FIG. 4E.

[0034] The use of HCl during the deposition of the SiGe buffer layer and the Ge film results in a significant improvement of the planarity of the deposited layer, as shown in FIG. 4F. As shown in this figure, the substrate 406 has a SiGeGe film with no visible surface undulations. Elimination of surface undulations is an essential feature of any deposition scheme. For example, decrease in surface undulation reduces dislocation pileups and the overall defect density in the Ge film. Furthermore, a conventional chemical mechanical polishing step typically used to reduce the surface undulation is not necessary for the method 300 discussed in FIG. 3.

[0035] FIG. 5 illustrates another exemplary method 500 used to selectively form an in-situ doped Ge layer, which is formed on a SiGe buffer layer which is formed on a substrate. In one example, the Ge layer is doped with boron. In another example, the Ge layer is doped with arsenic or phosphorus.

[0036] At box 502, a deposition chamber (e.g., CVD chamber) is prepared. The desired temperature and pressure for the deposition process is obtained. In one example, the temperature of the chamber is set to be about 625 C. to 700 C. and the pressure is set to be at atmospheric pressure (e.g., 1 atm). A carrier gas is injected into the CVD chamber. The carrier gas flow into the CVD chamber is maintained throughout the deposition process. The carrier is typically an inert gas (e.g., H₂, N₂, Ar, or He) but can be other suitable carrier gas depending on application. In one example, the carrier gas flow is introduced into the CVD chamber at a flow rate of about 20 L/minute.

[0037] At box 504, a substrate (e.g., silicon wafer) is loaded into the CVD chamber. The substrate can include a monocrystalline semiconductor wafer, a semiconductor-on-insulator wafer, or any other substrate used to form semiconductor devices. At box 506, the silicon source gas (e.g., SiH₄) is introduced into the CVD chamber. In one example, the silicon source gas is introduced at a rate of about 200 sccm. Also at box 506, an etchant source gas such as hydrochlorine (HCl) is introduced into the CVD chamber. The etchant source gas flow into the CVD chamber is maintained throughout the deposition process. In one example, the etchant source gas is introduced at a rate of about 50 sccm.

[0038] At box 508, the graded SiGe buffer layer is selectively formed on the substrate. The substrate includes a dielectric mask formed thereon. While ramping down the temperature, simultaneously decrease the silicon source gas and increased the germanium source gas for a predetermined amount of time. In one example, the predetermined amount of time ranges from 1.5 to 3.5 minutes and preferably, is about 2 minutes. The amount of time depends on the desirable thickness of the SiGe. In another example, for a predetermined amount of time, the temperature is linearly and gradually ramped down, from 625 C. down to 500 C. In yet another example, the silicon source gas is linearly and gradually ramped down, from 200 sccm down to 0 sccm; and, the germanium source gas is linearly and gradually ramped up, from 0 sccm up to 500 sccm. In another example, the silicon source gas is decreased at a rate of 1 sccm to 2 sccm per second. The temperature is decreased at a rate of 1 C. to 1.5 C. per second. And, the germanium source gas is increased at a rate of 3.8 sccm to 4.5 sccm per second. In yet another example, the temperature is decreased while simultaneously decreasing the silicon source gas and decreasing the germanium source gas is set a rate such that the threading dislocation is confined to the area near the substrate. In this example, the lower temperature and the faster decreasing rate for the temperature is preferred.

[0039] Continuing with FIG. 5, at box 510, the in-situ doped Ge film is formed on the graded SiGe buffer layer. To form the in-situ doped Ge film, while the temperature is maintained at a predetermined level, the flow of the germanium source gas and the a dopant source gas are maintained constant for a duration necessary to achieve the desired thickness for the in-situ doped Ge film. The dopant source gas can be a boron dopant, an arsenic dopant, a phosphorous dopant, or other suitable doping agents. In one example, the temperature is maintained at 500 C. for the duration of the time necessary to form the in-situ doped Ge film. In another example, the dopant source gas is phosphine (PH₃), which can be introduced into the chamber and maintained at a rate of about 20 sccm. In another example, the germanium source gas flow is maintained at 500 sccm for that duration. The temperature, the flow of the germanium source gas and the dopant source gas can be maintained constant for a duration of 5-minute. In this example, an 81 nm in-situ doped Ge film can be formed on the SiGe buffer layer. The time necessary to form the Ge film depends on the desired thickness of the Ge film. At box 512, the substrate can be removed from the CVD chamber. The substrate now has the in-situ doped Ge deposited on the SiGe buffer layer only in the exposed area of the wafer.

[0040] The use of the methods 300 of FIG. 3 and 500 of FIG. 5 for selectively forming the graded SiGeGe film on substrate present unique issues when attempting to deposit Ge layers that are both selective and in-situ doped. As discussed, selective deposition of the Ge film and the SiGe buffer layers is typically achieved by adding an etchant agent such as HCl to the gas stream. Doping can be performed either in-situ, by adding appropriate gasses to the gas stream, e.g., borane (B₂H₆), phosphine (PH₃), or arsine (AsH₃), or ex-situ through ion implantation. Achieving the highest possible level of doping while tightly controlling the positioning of the dopant species is critical for applications such as heterojunction bipolar transistors (HBT), or raised source/drain, in order to achieve maximum transistor performance. This task can be achieved only with in-situ doping of the layers as they are deposited.

[0041] However, the presence of an etchant agent in the gas stream, which is required to maintain selective deposition, decreases the incorporation of the dopants in the deposited films, and therefore degrades device performance. It is thus, difficult to achieve good dopant incorporation in the presence of an etchant agent. In fact, in extreme cases such as boron doping of Ge with B₂H₆, it is not possible to achieve dopant incorporation higher than 10¹⁶/cm³ in the presence of HCl in the gas stream. Typically only the Ge layer is doped, though the buffer can also be doped if desired. In that case the dopant needs to be turned on at box 506 in FIG. 5.

[0042] In another exemplary embodiment, the difficulty of growing in situ-doped, selective, and graded SiGeGe film is resolved by properly timing the flow of the germanium source gas, the etchant source gas, and the dopant source gas. FIG. 6 illustrates a timing scheme of introducing the germanium source gas, the dopant source gas, and the etchant source gas to achieve heavy in-situ doping of the graded SiGeGe film selectively formed over a substrate. In one example, the portion of the method that is used to deposit the Ge film consists of alternating Ge deposit and Ge etch steps.

[0043] Graph 600 of FIG. 6 illustrates an introducing timing 610 versus a flow rate 608 which shows a timing of the flow of the germanium source gas, the etchant source gas, and the dopant source gas. The etchant source gas for graph 600 is HCl. During the Ge deposit step, the germanium source gas and the dopant source gas are turned on simultaneously while the HCl source gas is turned off. The graph 600 illustrates that during the Ge deposit step, the flows for the germanium source gas (precursor) 602 and the dopant source gas 606 are turned on and the flow for the HCl source gas 606 is turned off (see for example, sections 600a, 600c, and 600e of introducing timing 610). Since there is no HCl present, the deposited Ge layer is doped, but is not selective. The deposition of the Ge is on the entire surface of the substrate, including the dielectric mask. In this example, the deposition rate of the Ge film on the dielectric layer is lower than the deposition of the Ge film on the SiGe buffer layer. Alternatively, the layer deposited on the dielectric is thinner than on the SiGe buffer layer.

[0044] During the Ge etch step, the flow for the germanium source gas 602 and dopant source gas 604 are turned off, and the flow for the hydrochloride source gas 606 is turned on. The graph 600 further illustrates that during the Ge etch step, the flow for the germanium source gas 602 and the dopant source gas 604 are turned off and the flow for the HCl source gas 606 is turned on (see for example, sections 600b, 600d, and 600f of introducing timing 610). The germanium film is etched from the surface of the substrate during the Ge-etch step. Since the Ge film on the dielectric layer is thinner than the Ge film on the graded SiGe buffer layer, the Ge that got deposited on the dielectric layer is etched away or removed from the dielectric layer. Complete selectivity and high dopant concentration can be maintained through appropriate choice for the duration of the Ge deposit and the Ge etch steps.

[0045] FIG. 7 illustrates an exemplary method 700 for selectively forming a heavily-doped and graded SiGeGe upon a wafer. In the method 700, the doping is in-situ. The method 700 selectively forms a heavily doped Ge layer which is formed on a graded SiGe buffer layer which is formed on a substrate.

[0046] At box 702, a deposition chamber (e.g., CVD chamber) is prepared. The desired temperature and pressure for the deposition process is obtained. In one example, the temperature of the chamber is set to be about 625 C. to 700 C. and the pressure is set to be at atmospheric pressure (e.g., 1 atm). A carrier gas is injected into the CVD chamber. The carrier gas flow into the CVD chamber is maintained throughout the deposition process. The carrier is typically an inert gas (e.g., H₂, N₂, Ar, or He) but can be other suitable carrier gas depending on application. In one example, the carrier gas flow is introduced into the CVD chamber at a flow rate of about 20 L/minute.

[0047] At box 704, a substrate (e.g., silicon wafer) is loaded into the CVD chamber. The substrate can include a monocrystalline semiconductor wafer, a semiconductor-on-insulator wafer, or any other substrate used to form semiconductor devices. At box 706, the silicon source gas (e.g., SiH₄) is introduced into the CVD chamber. In one example, the silicon source gas is introduced at a rate of about 200 sccm.

[0048] At box 708, the graded SiGe buffer layer is selectively formed on the substrate. The substrate includes a dielectric mask formed thereon. While ramping down the temperature, simultaneously decrease the silicon source gas and increased the germanium source gas for a predetermined amount of time. In one example, the predetermined amount of time ranges from 1.5 to 3.5 minutes and preferably, is about 2 minutes. The amount of time depends on the desirable thickness of the SiGe. In another example, for a predetermined amount of time, the temperature is linearly and gradually ramped down, from 625 C. down to 500 C. In yet another example, the silicon source gas is linearly and gradually ramped down, from 200 sccm down to 0 sccm; and, the germanium source gas is linearly and gradually ramped up, from 0 sccm up to 500 sccm. In another example, the silicon source gas is decreased at a rate of 1 sccm to 2 sccm per second. The temperature is decreased at a rate of 1 C. to 1.5 C. per second. And, the germanium source gas is increased at a rate of 3.8 sccm to 4.5 sccm per second. In yet another example, the temperature is decreased while simultaneously decreasing the silicon source gas and decreasing the germanium source gas is set a rate such that the threading dislocation is confined to the area near the substrate. In this example, the lower temperature and the faster decreasing rate for the temperature is preferred.

[0049] At box 710, the heavily in-situ doped Ge film is formed on the SiGe buffer layer. To form the heavily doped Ge film, the flow of the germanium source gas, an etchant source gas, and a dopant source gas are properly timed as discussed in FIG. 6. An etchant source gas is introduced into the chamber in a manner such that the flows of etchant source gas and germanium source gas are alternating with the flow of a dopant source gas for a predetermined amount of time. The alternating of the flows of the etchant source gas and the germanium source gas with the flow of the dopant source gas for a predetermined amount of time can be repeated the as necessary depending on the thickness of the desired Ge film. In one example, the sequence of selectively forming the heavily dope Ge film is as followed. (1) The deposition temperature is maintained at about 500 C. throughout the sequence. (2) For about the first 10 seconds of the deposition process, the germanium source gas flow is maintained at 500 sccm and the dopant source gas (e.g., B₂H₆) is maintained at a flow rate of about 100 sccm. (3) For about the next 5 seconds of the deposition process, the germanium source gas and the boron source gas is turned off, and the etchant source gas (e.g., HCl) is introduced and maintained at a flow rate of about 50 sccm. (4) The steps (2) to (3) are repeated for several times as needed to selectively form the heavily dope Ge film of a desirable thickness. For a heavily dope Ge film of about 80 nm, the steps (2) to (3) are repeated for 30 times. It will be appreciated that any of the parameters above can be modified without exceeding the scope of the method 700.

[0050] At box 712, the substrate can be removed from the CVD chamber. The Ge film and the graded SiGe buffer layer are both selectively formed in the exposed area of the two wafers. Furthermore, the Ge film is heavily doped with, for example, borons. In one example, the Ge film that is selectively formed using the method 700 has a dopant level in excess of 110²⁰ per cm³.

[0051] It will be appreciated that the method 700 can be applied to other dopants, for example, phosphorous and arsenic.

[0052] The graded SiGeGe film made in accordance with some of the exemplary embodiments discussed above can be integrated into making electronic devices such as transistors, capacitors, resistors or optical detectors. For purposed of illustration, the following discussion describes briefly exemplary integrations of the graded SiGeGe film into a transistor and a detector.

[0053] FIGS. 8A to 8D illustrate a process of making a Ge body transistor in accordance with the present invention. FIG. 8A illustrates that the silicon wafer substrate 802 may include shallow trench isolations 804 formed using conventional methods to insulate one device from another. For example, the shallow trench isolations 804 are formed by convention etching method to first etch regions for the shallow trench isolation 804 and these regions are filled with an insulator, typically SiO₂. In one example, a conventional chemical mechanical polishing method may be used to polish the substrate 802 to ensure sufficient planarity.

[0054] FIG. 8B illustrates that a germanium film is formed on a graded SiGe buffer layer which is formed on the surface of the semiconductor wafer substrate 802. The germanium film and the graded SiGe buffer layer together are referred to as a graded SiGeGe film 806. The graded SiGeGe film 806 is selectively formed on the semiconductor wafer substrate 802 using the exemplary methods discussed above, for example, the method 500 or the method 700 described in FIG. 5 and FIG. 7, respectively. The graded SiGeGe film 806 is formed only on the exposed regions of the silicon wafer substrate 802. The selectively deposited and graded SiGeGe film 806 will form the body of the device 800, for example, a Ge channel for a transistor, as opposed to the traditional Si channel in a transistor. In one example, the graded SiGeGe film 806 is moderately doped (e.g., 110¹⁶ per cm to 110¹⁸ per cm³). In one example, the doping concentration is chosen to properly target transistor threshold voltage. The graded SiGeGe film 806 can be a channel for the device 800.

[0055] FIG. 8C illustrates that a gate dielectric 810, a gate electrode 812, and spacers 814 can be formed on the top surface of the graded SiGeGe film 806 using conventional methods (e.g., conventional film deposition and patterning). In one example, the gate dielectric 810 can be deposited by a blanket deposition of a high-k oxide film. The deposition of the gate dielectric 810 is necessary since germanium does not form a stable oxide. In one example, the gate dielectric 810 is made out of a high-k dielectric material such as zirconium oxide (ZrO₂). The gate electrode 812 can also be formed by a blanket deposition. The gate electrode 812 can be made out of a metal containing material, such as titanium nitride or tungsten, for a metal gate. The gate electrode 812 can be appropriately doped poly-Silicon such as for a conventional gate. In one example, after the gate dielectric 810 and the gate electrode 812 are blanket deposited over the graded SiGeGe film 806, they are patterned to define the dimension of the gate dielectric 810 and the gate electrode 812. The gate dielectric 810 and the gate electrode 812 are patterned in a single process. The spacers 814, typically comprise of a combination of SiO₂ and Si₃N₄ are also formed, first, by blanket deposition. And then, the spacers 814 are defined using conventional spacer etching method.

[0056] FIG. 8C illustrates that another Ge film 807 can be formed on the graded SiGeGe film 806 using the methods described above (e.g., method 500 or the method 700 described in FIG. 5 and FIG. 7, respectively) for selectively forming the Ge film 807. The Ge film 807 does not need to be formed with the graded SiGe buffer layer. A mask may be used to prevent Ge film forming on the gate electrode 812 that comprises doped poly-Silicon such as for a conventional gate. The Ge film 807 can be heavily doped using the method 700 discussed in FIG. 7. In one example, the Ge film 807 has a dopant concentration of 110²⁰ per cm³. The heavily doped Ge 807 forms the source and drain regions of the transistor.

[0057] FIG. 8D illustrates that a nickel-germanium (NiGe) layer 816 may be formed on the Ge film 807 over the regions that are not covered with the gate dielectric 810 and the spacers 814. In one example, the NiGe is formed by a low-temperature annealing method using an annealing temperature of about 400 C. to 600 C. Depositing a metal (e.g., nickel) that reacts with the material in the transistor body can substantially lower the resistivity of the source and drain contacts. Conventional methods are used to anneal the substrate 802 The annealing temperature for the transistor 800 comprising the Ge film 807 is kept low, 400 C. to 600 C., to prevent the refractory metal from agglomerating, which tends to increase the resistivity of the source and drains 808 and degrade the performance of the transistor 800. The refractory metal used to anneal the transistor 800 comprising the Ge film 807 is preferably nickel (Ni). Alternatively, another metal with low resistivity can be used.

[0058] Those skilled in the art will recognize that the features mentioned in FIGS. 8A to 8D and other features may be used or may be left out, depending upon the particular function of the device. For example, after the formation of the NiGe, the transistor 800 is subjected to convention process of forming interlayer dielectric deposition, contact patterning, metalization, etc.

[0059] FIGS. 9A to 9D illustrate an electronic device 900 made in accordance with the present invention. In one example, the electronic device 900 is an integrated detector comprising germanium that may provide electrical output driven by an optical input to integrated circuits in a substrate. FIG. 9A illustrates that the semiconductor wafer substrate 902 may include shallow trench isolations 904 formed using conventional methods to insulate one device from another. The shallow trench isolations 904 are formed by conventional etching method to first etch regions for the shallow trench isolation 904 and these regions are filled with an insulator, typically SiO₂. In one example, a conventional chemical mechanical polishing method may be used to polish the substrate 902 to ensure sufficient planarity.

[0060] FIG. 9B illustrates that a germanium film is formed on a graded SiGe buffer layer which is formed on the surface of the semiconductor wafer substrate 902. The germanium film and the graded SiGe buffer layer together are referred to as a graded SiGeGe film 906. The graded SiGeGe film 906 is selectively formed on the semiconductor wafer substrate 902 using the exemplary methods discussed above, for example, the method 500. The graded SiGeGe film 906 is formed only on the exposed regions of the substrate 902 as discussed above. The selectively deposited and graded SiGeGe film 906 will form the body of the detector 900. In one example, the SiGeGe film is not doped as in the case of the transistor 800 to ensure maximum performance for the detector.

[0061] FIG. 9C illustrates that a waveguide 908 is formed on the graded SiGeGe film 906 using conventional methods. The waveguide 908 is encapsulated by oxide layers 910 which are dielectric layers. It is common for the integrated structure to have the waveguide 908 be made out of a relatively high-refractive index material (e.g., Si₃N₄ which has a refractive index n2.05). The waveguide 908 is typically encapsulated in a material with lower refractive index (e.g., SiO₂ which has a refractive index n1.46). When light is introduced in the waveguide 908 having the high refractive index material, the light will be confined there. The waveguide 908 then guides the light from the source (typically an external laser) to the detector (in this case the selectively deposited and graded SiGeGe film 906).

[0062] FIG. 9D illustrates that detector electrodes 912 are formed in the top oxide layer 910. In order for the graded SiGeGe film 906 to function as a detector, a bias must be applied across it. Any light shining on the detector 900 then generates electron-hole pairs. These pairs are swept by the bias field, causing current to flow through the SiGeGe film 906. There is an electrical response to a light impulse. The detector electrodes 912 are needed to provide the required bias. In one example, a conductive material, such as metal, is deposited and then patterned using conventional methods. In this example, the detector electrodes 912 are deposited by a damascene process, well practiced in the field. More specifically, a trench is defined with standard litho techniques in the top oxide layer 910; then, a metal is deposited everywhere (so that the trench is completely filled); then, the excess metal on the top surface of the top oxide layer 910 is polished off.

[0063] The methods made in accordance with the present invention, such as those exemplary embodiments discussed above, enable the making of ultra-thin graded SiGe buffer layers upon which low defect Ge films can be grown. The germanium film made according to the present invention can be easily integrated into semiconductor devices. The methods also enable selective deposition of the low defect Ge film that is heavily doped in situ. The methods thus enable the making of semiconductor devices that take advantage of the desirable material properties of Ge and at the same time integrate with Si modem manufacturing techniques.