Magnetic switching element and a magnetic memory

[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.2001-397386, filed on Dec. 27, 2001; the entire contents of which are incorporated herein by reference.

[0002] This invention relates to a magnetic switching element the and a magnetic memory, and more particularly, to the magnetic switching element which can generate magnetization in much lower power consumption than before by controlling a magnetization direction induced in a magnetic semiconductor, and the magnetic memory using the switching element.

[0003] Magnetoresistance effect element using a magnetic film is used for the magnetic head, the magnetic sensor, for example, and there is a proposal to use the magnetoresistance effect elements in a solid-state magnetic memory (magnetoresistance effect memory or MRAM (Magnetic Random Access Memory)).

[0004] Recently, a so-called tunneling magnetoresistance effect element (TMR element) has been proposed as a magnetoresistance effect element configured to flow a current perpendicularly to the film plane in a sandwich-structured film interposing a single dielectric layer between two magnetic metal layers and to use the tunneling current.

[0005] Since tunneling magnetoresistance effect elements have been improved to ensure 20% or higher ratio of change in magnetoresistance (J. Appl. Phys. 79, 4724 (1996)), the possibility of civilian applications of MRAM is increasing.

[0006] A tunneling magnetoresistance effect element can be obtained by first forming a thin Al (aluminum) layer, 0.6 nm through 2.0 nm thick, on a ferromagnetic electrode, and thereafter exposing its surface to a glow discharge of oxygen or oxygen gas to form a tunnel barrier layer of Al₂O₃.

[0007] There is also proposed a ferromagnetic single tunneling junction structure in which an anti-ferromagnetic layer is provided in one of the ferromagnetic layers on one side of the single ferromagnetic tunneling junction and the other ferromagnetic layer is used as a magnetically pinned layer (Japanese Patent Laid-Open Publication No. H10-4227).

[0008] Other type ferromagnetic tunneling junction structures, namely, one having a ferromagnetic tunneling junction via magnetic particles distributed in a dielectric material and one having double ferromagnetic tunneling junctions (continuous film) have been proposed as well (Phys. Rev. B56(10), R5747 (1997), J. The Magnetics Society of Japan 23, 4-2, (1999), Appl. Phys. Lett. 73(19), 2829 (1998), Jpn. J. Appl. Phys, 39, L1035(2001)).

[0009] Also these ferromagnetic tunneling junctions have been improved to ensure a ratio of magnetoresistance change from 20 to 50% and to prevent a decrease of the ratio of magnetoresistance change even upon an increase of the voltage value applied to tunneling magnetoresistance effect elements to obtain a desired output voltage, and there is the possibility of their applications to MRAM. Magnetic recording elements using such a single ferromagnetic tunneling junction or double ferromagnetic tunneling junctions are nonvolatile and have high potentials such as high write and read speed not slower than 10 nanoseconds and programmable frequency not less than 1015 times.

[0010] Especially, ferromagnetic double-tunneling structures ensure large output voltages and exhibit favorable properties as magnetic recording elements because the ratio of magnetoresistance change does not decrease even upon an increase of the voltage value applied to tunneling magnetoresistance effect elements to obtain a desired output voltage value as mentioned above.

[0011] With regard to the memory cell size, however, those existing techniques involve the problem that the size cannot be decreased below semiconductor DRAM (dynamic random access memory) when a 1 Tr (transistor)-1 TMR architecture (disclosed, for example, in U.S. Pat. No. 5,734,605) is employed.

[0012] In order to overcome the problem, there are proposals such as a diode-type architecture in which TMR cells and diodes are serially connected between bit lines and word lines (U.S. Pat. No. 5,640,343), and a simple-matrix architecture in which TMR cells are placed between bit lines and word lines (DE 19744095, WO 9914760). However, in any case, at the time of writing to a record layer, magnetization reversal is performed by applying a current magnetic field generated by a current pulse.

[0013] For this reason, the power consumption of a memory is large, when integrated, and there is a problem that a large scale memory cannot be carried out since there is a current density limit of wiring. If an absolute value of writing current is larger than 1 mA, area of a driver for passing the current will become larger. For this reason, there is a problem that chip size becomes large, in comparison with non-volatile solid memories (for example, FeRAM (ferroelectric random-access memory), FLASH(flash memory), etc.) of other types of memories.

[0014] As mentioned above, in order to realize a super-large scale magnetic memory, an architecture with little power consumption and the new method of writing are needed.

[0015] Moreover, the same demand exists in all the applications that need to switch a magnetic field. For example, also in a magnetic recording head, a magnetic drive type actuator, etc., if it becomes possible to switch a magnetic field, without using a current magnetic field, a greatly improved performance will be obtained. Moreover, various kinds of new magnetic application equipments can be realized.

[0016] According to an embodiment of the invention, there is provided a magnetic switching element comprising:

[0017] a ferromagnetic layer which is substantially pinned in magnetization in one direction; and

[0018] a magnetic semiconductor layer provided within a range where a magnetic field from the ferromagnetic layer reaches, the magnetic semiconductor layer changing its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto,

[0019] a magnetization corresponding to the magnetization of the ferromagnetic layer being induced in the magnetic semiconductor layer by applying a voltage to the magnetic semiconductor layer.

[0020] In the specification, the term a range where a magnetic field reaches means a range where a magnetic interaction exist between a magnetic semiconductor layer and a ferromagnetic layer. As long as such a magnetic interaction exists, the term includes a case where the magnetic semiconductor layer and the ferromagnetic layer are provided adjacently, a case where these layers are apart, and a case where another layer such as a non-magnetic layer is interposed therebetween.

[0021] According to another embodiment of the invention, there is provided a magnetic switching element comprising

[0022] a gate electrode;

[0023] a magnetic semiconductor layer which changes its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto; and

[0024] a ferromagnetic layer provided between the gate electrode and the magnetic semiconductor layer or provided on a opposite side of the magnetic semiconductor layer from the gate electrode, the ferromagnetic layer being substantially pinned in magnetization in one direction,

[0025] a magnetization corresponding to the magnetization of the ferromagnetic layer being induced in the magnetic semiconductor layer by applying a voltage to the magnetic semiconductor layer through the gate electrode.

[0026] According to yet another embodiment of the invention, there is provided a magnetic memory comprising a memory cell having:

[0027] a first magnetic switching element including:

[0028] a first ferromagnetic layer which is substantially pinned in magnetization in a first direction; and

[0029] a first magnetic semiconductor layer provided within a range where a magnetic field from the first ferromagnetic layer reaches, the first magnetic semiconductor layer changing its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto,

[0030] a magnetization corresponding to the magnetization of the first ferromagnetic layer being induced in the first magnetic semiconductor layer by applying a voltage to the first magnetic semiconductor layer;

[0031] a second magnetic switching element including:

[0032] a second ferromagnetic layer which is substantially pinned in magnetization in a second direction; and

[0033] a second magnetic semiconductor layer provided within a range where a magnetic field from the second ferromagnetic layer reaches, the second magnetic semiconductor layer changing its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto,

[0034] a magnetization corresponding to the magnetization of the second ferromagnetic layer being induced in the second magnetic semiconductor layer by applying a voltage to the second magnetic semiconductor layer; and

[0035] a magnetoresistance effect element including a record layer made of a ferromagnetic material,

[0036] a magnetization corresponding to the magnetization of the first magnetic semiconductor layer being recorded in the record layer when the magnetization is induced in the first magnetic semiconductor layer of the first magnetic switching element, and

[0037] a magnetization corresponding to the magnetization of the second magnetic semiconductor layer being recorded in the record layer when the magnetization is induced in the second magnetic semiconductor layer of the second magnetic switching element.

[0038] According to yet another embodiment of the invention, there is provided a magnetic memory comprising a memory cell having:

[0039] a first magnetic switching element including:

[0040] a first gate electrode;

[0041] a first magnetic semiconductor layer which changes its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto; and

[0042] a first ferromagnetic layer provided between the first gate electrode and the first magnetic semiconductor layer or provided on a opposite side of the first magnetic semiconductor layer from the first gate electrode, the first ferromagnetic layer being substantially pinned in magnetization in a first direction,

[0043] a magnetization corresponding to the magnetization of the first ferromagnetic layer being induced in the first magnetic semiconductor layer by applying a voltage to the first magnetic semiconductor layer through the first gate electrode;

[0044] a second magnetic switching element including:

[0045] a second gate electrode;

[0046] a second magnetic semiconductor layer which changes its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto; and

[0047] a second ferromagnetic layer provided between the second gate electrode and the second magnetic semiconductor layer or provided on a opposite side of the second magnetic semiconductor layer from the second gate electrode, the second ferromagnetic layer being substantially pinned in magnetization in a second direction,

[0048] a magnetization corresponding to the magnetization of the second ferromagnetic layer being induced in the second magnetic semiconductor layer by applying a voltage to the second magnetic semiconductor layer through the second gate electrode; and

[0049] a magnetoresistance effect element including a record layer made of a ferromagnetic material,

[0050] a magnetization corresponding to the magnetization of the first magnetic semiconductor layer being recorded in the record layer when the magnetization is induced in the first magnetic semiconductor layer of the first magnetic switching element, and

[0051] a magnetization corresponding to the magnetization of the second magnetic semiconductor layer being recorded in the record layer when the magnetization is induced in the second magnetic semiconductor layer of the second magnetic switching element.

[0052] According to yet another embodiment of the invention, there is provided a magnetic memory comprising a plurality of memory cells in a matrix arrangement, each one of the memory cells having:

[0053] a first magnetic switching element including:

[0054] a first ferromagnetic layer which is substantially pinned in magnetization in a first direction; and

[0055] a first magnetic semiconductor layer provided within a range where a magnetic field from the first ferromagnetic layer reaches, the first magnetic semiconductor layer changing its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto,

[0056] a magnetization corresponding to the magnetization of the first ferromagnetic layer being induced in the first magnetic semiconductor layer by applying a voltage to the first magnetic semiconductor layer;

[0057] a second magnetic switching element including:

[0058] a second ferromagnetic layer which is substantially pinned in magnetization in a second direction; and

[0059] a second magnetic semiconductor layer provided within a range where a magnetic field from the second ferromagnetic layer reaches, the second magnetic semiconductor layer changing its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto,

[0060] a magnetization corresponding to the magnetization of the second ferromagnetic layer being induced in the second magnetic semiconductor layer by applying a voltage to the second magnetic semiconductor layer; and

[0061] a magnetoresistance effect element including a record layer made of a ferromagnetic material,

[0062] a magnetization corresponding to the magnetization of the first magnetic semiconductor layer being recorded in the record layer when the magnetization is induced in the first magnetic semiconductor layer of the first magnetic switching element, and

[0063] a magnetization corresponding to the magnetization of the second magnetic semiconductor layer being recorded in the record layer when the magnetization is induced in the second magnetic semiconductor layer of the second magnetic switching element,

[0064] binary information being recorded as the magnetization in the record layer of the magnetoresistance effect element of a predetermined one of the memory cells by selecting the memory cell and by applying the voltage to either one of the first and second magnetic semiconductor layers.

[0065] According to the invention, it becomes possible to obtain predetermined magnetization by application of voltage, the magnetic switching element of super-power consumption, a magnetic memory or a magnetic probe, a magnetic head, etc. can be realized, and the merit on industry is great.

[0066] The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the embodiments of the invention. However, the drawings are not intended to imply limitation of the invention to a specific embodiment, but are for explanation and understanding only.

[0067] In the drawings:

[0068] FIGS. 1A and 1B are conceptual diagrams for explaining the principal part and its operation of a magnetic switching element according to an embodiment of the invention;

[0069] FIGS. 2A and 2B shows the structure where the stacking order of the magnetic semiconductor layer 10 and the ferromagnetic layer 20 is reversed;

[0070] FIGS. 3A and 3B are conceptual diagrams of a magnetic switching element according to an embodiment of the invention where the gate insulation film and the ferromagnetic layer are unified;

[0071] FIG. 4 is a conceptual diagram for explaining the writing principle of the unit cell of the magnetic memory according to an embodiment of the invention;

[0072] FIG. 5 is a conceptual diagram for explaining the writing principle of the unit cell of the magnetic memory according to an embodiment of the invention;

[0073] FIG. 6 is a conceptual diagram for explaining the writing principle of the unit cell of the magnetic memory according to an embodiment of the invention;

[0074] FIG. 7 is a conceptual diagram for explaining the writing principle of the unit cell of the magnetic memory according to an embodiment of the invention;

[0075] FIGS. 8A through 8D are conceptual diagrams for explaining the writing in the memory element of the first type illustrated in FIG. 5;

[0076] FIGS. 9A and 9B are conceptual diagrams for explaining the writing in the memory element of the first type illustrated in FIG. 6;

[0077] FIG. 10 is a conceptual diagram which illustrates the matrix structure of the magnetic memory according to an embodiment of the invention;

[0078] FIGS. 11A through 11F are diagrams which illustrate the plane forms and their magnetization direction of the record layer 52;

[0079] FIG. 12 is a conceptual diagram showing a cross-sectional structure of the magnetoresistance effect element having a ferromagnetic single tunnel junction;

[0080] FIG. 13 is a conceptual diagram showing a cross-sectional structure of the magnetoresistance effect element having a ferromagnetic single tunnel junction;

[0081] FIG. 14 is a conceptual diagram showing a cross-sectional structure of the magnetoresistance effect element having ferromagnetic double tunnel junctions;

[0082] FIG. 15 is a conceptual diagram showing a cross-sectional structure of the magnetoresistance effect element having ferromagnetic double tunnel junctions;

[0083] FIG. 16 is a conceptual diagram showing a cross-sectional structure of the magnetoresistance effect element having ferromagnetic double tunnel junctions;

[0084] FIG. 17 is a conceptual diagram showing the first example of the architecture for read-out employable for the magnetic memory according to an embodiment of the invention;

[0085] FIG. 18 is a conceptual diagram showing an example of the magnetic memory of a simple matrix type having memory cells of the first type illustrated in FIG. 5 according to an embodiment of the invention;

[0086] FIG. 19 is a conceptual diagram showing an example where the magnetoresistance effect element 50 has ferromagnetic double tunnel junctions;

[0087] FIG. 20 is a conceptual diagram showing an example of the magnetic memory of a simple matrix type having memory cells of the second type illustrated in FIG. 6 according to an embodiment of the invention;

[0088] FIG. 21 is a conceptual diagram showing an example where the magnetoresistance effect element 50 has ferromagnetic double tunnel junctions,

[0089] FIG. 22 is a conceptual diagram showing the second example of the architecture for read-out employable for the magnetic memory according to an embodiment of the invention;

[0090] FIG. 23 is a conceptual diagram showing the second example of the architecture for read-out employable for the magnetic memory according to an embodiment of the invention;

[0091] FIG. 24 is a conceptual diagram showing the third example of the architecture for read-out employable for the magnetic memory according to an embodiment of the invention;

[0092] FIG. 25 is a conceptual diagram showing the third example of the architecture using the memory cell of the first type for read-out employable for the magnetic memory according to an embodiment of the invention;

[0093] FIG. 26 is a conceptual diagram showing the third example of the architecture using the memory cell of the second type for read-out employable for the magnetic memory according to an embodiment of the invention;

[0094] FIG. 27 is a conceptual diagram showing the fourth example of the architecture for read-out employable for the magnetic memory according to an embodiment of the invention;

[0095] FIG. 28 is a conceptual diagram showing the fourth example of the architecture using the memory cell of the first type for read-out employable for the magnetic memory according to an embodiment of the invention;

[0096] FIG. 29 is a conceptual diagram showing the fourth example of the architecture using the memory cell of the second type for read-out employable for the magnetic memory according to an embodiment of the invention;

[0097] FIG. 30 is a conceptual diagram showing a basic structure of a magnetic probe and a magnetic head according to an embodiment of the invention; and

[0098] FIG. 31 is a conceptual diagram which shows a basic structure of a magnetic probe and a magnetic head using a switching element including an anti-ferromagnetic layer according to an embodiment of the invention.

[0099] Some embodiments of the invention will now be explained below with reference to the drawings.

[0100] FIGS. 1A and 1B are conceptual diagrams for explaining the principal part and its operation of a magnetic switching element according to an embodiment of the invention. As expressed in these diagrams, the magnetic switching element of the embodiment has the structure where the magnetic semiconductor layer 10, the ferromagnetic layer 20, the gate insulation film 30, and the gate electrode 40 are stacked.

[0101] The magnetic semiconductor layer 10 has a magnetic character and a semiconducting character as well, and consists of a material in which these two characters have a strong correlation therebetween. Specifically, as the material of the magnetic semiconductor layer 10, such as III-V group compound semiconductors and II-VI group compound semiconductors in which magnetic elements such as manganese (Mn) and chromium (Cr) are added can be used.

[0102] Such a magnetic semiconductor shows a paramagnetic property in the state where voltage is not applied. This is because the concentrations of the magnetic elements, such as manganese (Mn) and chromium (Cr) are low enough to make the interaction between these magnetic elements become slight.

[0103] On the other hand, a ferromagnetism is induced when a voltage is applied to the magnetic semiconductor (Nature 408, 944. (2000)). It is considered that by applying a voltage, the concentration of electrons or holes is changed and the interaction between the added magnetic elements such as manganese and chromium becomes remarkable. As a material of the magnetic semiconductor layer 10, wide gap semiconductors such as (In, Mn)As, (Ga, Mn)As, (Zn, Mn)Te, GaN, ZnO, and TiO₂ which are doped with transition metal elements can be used. (Cd_1xMn_x)GeP₂, CrAs, (Ga, Cr)As, etc. can be also used for the magnetic semiconductor layer 10.

[0104] According to a kind of transition metal doped to the wide gap semiconductor, and concentration thereof, the magnetic semiconductor can realize various magnetic states, such as anti-ferromagnetism, paramagnetizm, and ferromagnetism.

[0105] Therefore, a ferromagnetism can be successfully induced in the magnetic semiconductor layer 10 of the embodiment by adding a suitable element.

[0106] For example, by applying voltage to (InMn)As dilute magnetic semiconductor, the number of holes in the (InMn)As layer can be controlled, and ferromagnetism can be induced by generating the interaction between the manganese (Mn) spins.

[0107] In the embodiment of the invention, as expressed in FIG. 1, a voltage can be applied with the gate electrode 40 through the gate insulation film 30.

[0108] According to this structure, since current does not flow in the switching element, power consumption can be greatly reduced compared with the elements which generates the conventional current magnetic field.

[0109] However, it is not possible to control the direction of the magnetization in the magnetic semiconductor layer 10 only by having applied the voltage thereto.

[0110] In the embodiment, the ferromagnetic magnetization direction of the magnetic semiconductor layer 10 is controlled by providing the ferromagnetic layer 20 adjacent.

[0111] That is, as expressed in FIGS. 1A and 1B, in a magnetic switching element of the embodiment, a ferromagnetic layer 20 which has magnetization M1 is provided to adjoin the magnetic semiconductor layer 10.

[0112] In this structure, when a voltage is applied to the gate electrode 40, the voltage is applied to the magnetic semiconductor layer 10 through the gate insulation film 30, and ferromagnetism is induced in the layer 10.

[0113] The magnetization M2 produced in the layer 10 is formed in the same direction as the magnetization M1 of the adjoining ferromagnetic layer 20.

[0114] Thus, the magnetization M2 of a predetermined direction can be induced in the magnetic semiconductor layer 10, and this magnetic field can be made to act on the object 100 for an action. Here, the object 100 for an action may be a record layer of a magnetic memory, a magnetic recording medium or a subject in the case where the magnetization M2 is used as a magnetic probe.

[0115] It must be noted that the object 100 for an action should be provided in the range which the magnetization M2 induced by the magnetic semiconductor layer 10 reaches. Therefore, the object 100 may be provided near the undersurface of the magnetic semiconductor layer 10 instead of arranging the object 100 near the side edge thereof.

[0116] Thus, according to the embodiment, by applying voltage to the gate electrode 40, magnetization of the predetermined direction can be induced in the magnetic semiconductor layer 10, and the switching element which can control on and off of its magnetization with very low power consumption can be realized.

[0117] It should be noted that FIGS. 1A and 1B merely express the fundamental concept of the switching element of the embodiment. Skilled person can add various modification about each part of the element. For example, as explained in full details below, various kinds of modification such as reversing the magnetization direction by inserting a lamination of an anti-ferromagnetic layer and a ferromagnetic layer between the ferromagnetic layer 20 and the gate insulation film 30, and interposing a non-magnetic layer are possible.

[0118] Moreover, it is not limited to FIGS. 1A and 1B about a stacking order of each layer.

[0119] For example, as illustrated in FIGS. 2A and 2B, the stacking order of a magnetic semiconductor layer 10 and a ferromagnetic layer 20 may be reversed. Also in this case, by applying a voltage to the magnetic semiconductor layer 10 through the gate insulation film 30, ferromagnetism is induced in the layer 10 and that magnetization M2 is formed along the direction of the magnetization M1 of the adjoining ferromagnetic layer 20.

[0120] Thus, the magnetization M2 is switchable to the object 100 for an action provided near the magnetic semiconductor layer 10. Furthermore, in FIGS. 1A and 1B, it is also possible to unity the gate insulation film 30 and the ferromagnetic layer 20. FIGS. 3A and 3B are conceptual diagrams showing the magnetic switching element where the gate insulation film and the ferromagnetic layer are unified.

[0121] That is, if the material which is electrically insulative and has ferromagnetism is used, the ferromagnetic layer 20 and the gate insulation film 30 can be unified and formed as a single common layer, As such a material, a magnetic material of iron oxide systems, such as a ferrite, etc. can be mentioned, for example.

[0122] Hereafter, the magnetic memory using the magnetic switching element of the embodiment of the invention is explained first as an example of the application of the magnetic switching element of the invention.

[0123] FIGS. 4 through 7 are conceptual diagrams for explaining the writing principle of the unit cell of the magnetic memory of the embodiment of the invention.

[0124] First, the structures expressed in FIG. 4 and 5 are of a first type according to an embodiment of the invention, where the switching element of the embodiment is arranged to touch directly with the record layer of a memory record element. That is, the switching elements 1A and 1B of the embodiment are formed in the both sides of the ferromagnetic layer 52. And the magnetoresistance effect element 50 is formed near the center of the ferromagnetic layer 52.

[0125] The magnetoresistance effect element includes a lamination of the insulating tunnel barrier 54 and the ferromagnetic insulating layer 56. That is, the ferromagnetic layer 52 acts as a record layer (free layer), and the ferromagnetic layer 56 acts as a magnetization pinned layer (pinned layer). Now, in a pair of magnetic switching elements 1A and 1B, each ferromagnetic layers 20 has the magnetization M1 of the opposite direction. Therefore, when a voltage is applied to the gate electrode 40, direction of the magnetization M2 produced in these magnetic semiconductor layers 10 and 10 also turns into opposite according to the magnetization direction of these ferromagnetism layers 20 and 20.

[0126] That is, by applying a voltage to either one of the switching elements 1A and 1B, the direction of the writing magnetization M3 of ferromagnetic layer 52 which is a record layer of the TMR element 50 can be chosen, and the writing of binary information is attained.

[0127] According to the embodiment, since a magnetic field is generated without passing current as mentioned above with reference to FIGS. 1A and 1B, power consumption can be greatly reduced.

[0128] Here, as a magnetoresistance effect element 50, a ferromagnetic tunnel junction which includes at least ferromagnetic layers 52 and 56 and at least one tunnel barrier insulation layer 54 can be used. If ferromagnetic tunnel junction is used, a signal output can be controllable by changing spin polarization ratio of a magnetic layer, and also it is advantageous at the point that junction resistance is controllable by changing the thickness and the barrier height of a tunnel barrier insulation layer.

[0129] In these magnetoresistance effect elements 50, it is desirable to approach the ferromagnetic layer (pinned layer) 56 and to form the anti-ferromagnetic layer 58. It is because the magnetization direction of the pinned layer 56 can certainly be fixed by the anti-ferromagnetism layer 58. Thus, the junction resistance changes depending upon the relationship between the direction of the magnetization spin of the pinned layer 56 and the direction of the magnetization spin of the record layer 52. Therefore, the spin information on the record layer 52 can be easily read out by detecting a signal output.

[0130] In order to write by the switching element of the embodiment of the invention, it is desirable that the ferromagnetic record layer 52 of the magnetoresistance effect element 50 has an uniaxial anisotropy. It is because the direction of a writing magnetization spin can be stabilized. Next, in the case of the example expressed in FIG. 5, switching element 1C has ate same composition as what was expressed in FIG. 4, but switching element 1D has the structure where the laminating of the ferromagnetic layer 20, the non-magnetic layer 22, the ferromagnetic layer 24, and the anti-ferromagnetic layer 26 is carried out in this order from the magnetic semiconductor layer 10.

[0131] By combining these non-magnetic layer 22 through the anti-ferromagnetic layer 26, the direction of the magnetization M1 of the ferromagnetic layer 20 which controls the magnetization direction of the magnetic semiconductor layer 10 can be reversed with respect to the switching element 1C. Therefore, when the magnetization pinned process over a ferromagnetic layer is taken into consideration, the advantage that manufacture becomes easy is acquired.

[0132] On the other hand, the structures expressed in FIGS. 6 and 7 are of the second type of the embodiment of the invention, where the switching elements 1E-1H have the ferromagnetic layer 60 for applying a magnetic field to the record layer 52 of the magnetoresistance effect element 50.

[0133] In the case of the memory element with which it expressed in FIG. 6, the principal part of switching element 1E has the same layered structure as the switching elements 1A and 1C with which it expressed in FIGS. 4 and 5.

[0134] The principal part of switching element 1F has the same layered structure as the switching element 1D. Therefore, either of the magnetization M2 of the opposite direction can be formed in each magnetic semiconductor layer 10 by applying a voltage to either of these switching elements 1E and 1F. By making this magnetization act on the record layer 52 of a TMR clement through the ferromagnetic layer 60, binary information can be written freely.

[0135] In the case of the memory element with which it expressed in FIG. 7, the ferromagnetic layer 60 for bias application is formed between the magnetic semiconductor layer 10 and the gate insulation film 30 Also in this case, the magnetic semiconductor layer 10 forms magnetization M2 in the direction according to the magnetization M1 of the ferromagnetic layer 20 by application of a voltage, and magnetization is formed in the ferromagnetic layer 60 of this magnetization M2. By this magnetization in the ferromagnetic layer 60, binary information can be freely written in the record layer 52.

[0136] In the structure illustrated in FIG. 7, it is also possible to unify the gate insulation film 30 and the ferromagnetic layer 60 for bias application. That is, if the material which is electrically insulative and has ferromagnetism is used, these two layers can be unified and formed as a single common layer. As such a material, a magnetic material of iron oxide systems, such as a ferrite, etc. can be mentioned, for example.

[0137] As mentioned above, as illustrated in FIGS. 4 through 7, according to the embodiment of the invention, magnetic spin reversal is enabled not with a current magnetic field but with voltage by making the magnetic field from the switching elements 1A-1H of the invention act on the memory record layer 52.

[0138] As the result, the magnetic memory which greatly reduced power consumption can be realized.

[0139] In the examples expressed in FIGS. 4 through 7, the ferromagnetic tunnel junction TMR (ferromagnetism single tunnel junction) is formed as a magnetoresistance effect element which is a memory record element.

[0140] However, the invention is not restricted to this specific example and it can also use the storage cell of other structures which include a record layer that is a switchable ferromagnetic layer.

[0141] FIGS. 8A through 8D are conceptual diagrams explaining the writing in the memory element of the first type illustrated in FIG. 5. That is, in the case of the memory element illustrated in these diagrams, the bit line BL1 wired in parallel to space is connected to the magnetization pinned layer 56 of the TMR element 50, and the bit line BL2 perpendicularly wired to space is connected to it at the record layer 52.

[0142] Here, FIGS. 8A and 8B express the case where 0 of the binary information is written in, and FIG. 8C and 8D express the case where 1 is written in.

[0143] In order to rewrite the spin information on a memory cell, the voltage of minus is applied to the switching elements 1C or 1D, or the voltage of plus is applied to the bit lines BL1 or BL2. Then, holes are injected into the magnetic semiconductor layer 10, and the magnetic semiconductor layer 10 performs a magnetic phase transition into a ferromagnetic state from a paramagnetic state.

[0144] The direction of the spin of the magnetic semiconductor layer 10 (ferromagnetic state) will be prescribed towards the magnetization M1 of the ferromagnetic layer 20 by the magnetic interaction with the ferromagnetic layer 20 prepared in contact with the magnetic semiconductor layer 10 in that case.

[0145] Since the record layer 52 of a memory cell is also in contact with this magnetic semiconductor layer 10 in the case of the memory element of the first type, by the interaction of the record layer 52 and the magnetic semiconductor layer 10, the record layer 52 of a memory cell isl also specified in the direction of the spin M2 of the magnetic semiconductor layer 10, and carry out the magnetic spin reversal.

[0146] FIGS. 9A and 9B are conceptual diagrams for explaining the writing in the memory element of the second type illustrated in FIG. 6. The same symbols are given to the same elements as what were mentioned above with reference to FIGS. 1A through 8D about these diagrams, and detailed explanation is omitted.

[0147] In the case of the example expressed in FIGS. 9A and 9B, the ferromagnetic layer 60 for applying a magnetic field to the record layer 52 is formed to adjoin the magnetic semiconductor layer 10. And the direction of the spin of the ferromagnetic layer 60 is prescribed by the interaction of the magnetic semiconductor layer 10 and the ferromagnetic layer 60, a magnetic field is applied to the record layer 52 of a memory cell by the magnetic field (stray field) from the ferromagnetic layer 60, and the record layer 52 cries out magnetic spin reversal.

[0148] In the cases of the structures illustrated in FIGS. 8A through 9B, in the switching elements 1D and 1F, in order to specify the direction of the magnetic spin M1 of the ferromagnetic layer 20 prepared in order to specify the direction of the magnetization spin M2 of the magnetic semiconductor layer 10, the anti-ferromagnetic layer 26 is given, and laminating is carried out through the ferromagnetic layer 24 and the non-magnetic layer 22.

[0149] By employing such structures, the direction of the pinned spin of the ferromagnetic layer 20 can be easily reversed 180 degrees to the direction of the pinned spin of the ferromagnetic layer 20 of the opposite switching elements 1C and 1E.

[0150] FIG. 10 is a conceptual diagram which illustrates the matrix structure of the magnetic memory according to an embodiment of the invention. The memory cells which consist of a switching element 1 and a magneto resistance effect element 50 are arranged in the position of the crossing point of the bit lines BL1 and BL2 wired in the shape of a matrix, and the word lines WL1 and WL2, as expressed in this diagram. And ferromagnetism is induced in one magnetic semiconductor layer 10 of a pair of switching elements combined with the magnetoresistance effect element 50, and a predetermined magnetization spin is made to form by applying predetermined voltage to these bit line or a word line suitably. Then it is possible to write in by this magnetization spin by reversing the magnetization of the record layer of the adjoining magnetoresistance effect element 50,

[0151] In order to read the recorded information on the magnetoresistance effect element 50, the bit lines BL1 and BL2 are chosen, and the sense current which flows through the magnetoresistance effect element connected to these is detected.

[0152] As the concrete architecture for read-out, the architecture using a MOS switch, a diode, etc., the architecture (simple matrix type) which has a transistor for selection in the circumference part of the bit lines and the word lines arranged in the shape of a matrix can be used as explained in full detail below.

[0153] By using the magnetic switching element of the embodiment, it becomes possible to control the direction of the magnetic moment of the record layer 52 of the magnetoresistance effect element 50 by applying a gate voltage through the gate insulation film 30. As a result, it becomes possible to write in not by current writing but by applying a voltage, and power consumption becomes remarkably small and can realize the small highly efficient solid-state magnetic memory which also reduced the scale and size of a circumference circuit in connection with it.

[0154] The magnetization direction of the record layer 52 of the magnetoresistance effect element 50 used in the invention does not necessarily need to be of a straight rectangular shape, as explained in full detail below.

[0155] FIGS. 11A through 11F are conceptual diagrams which illustrate the plane forms and their magnetization direction of the record layer 52. The record layer 52 of the magnetoresistance effect element can have various plane form, as illustrated in these diagrams, and the magnetization M3 formed there forms various edge domains according to the form.

[0156] Namely, the magnetic record layer 52 may have a plane form where projects are added to both diagonal edges of a rectangular as shown in FIG. 11A. The magnetic record layer 52 may also have a plane form of a parallelogram as shown in FIG. 11B, a lozenge as shown inf FIG. 11C, an ellipse as shown in FIG. 11D, an edge inclination shape as shown in FIG. 11E or an elongated octagon as shown in FIG. 11F.

[0157] And in the case of the asymmetrical form as shown in FIGS. 11A and 11B, magnetization M3 is crooked by formation of the edge domain instead of the shape of a straight line. In the embodiment of the invention, it is possible to use the record layer which has the magnetization M3 crooked in this way.

[0158] Such asymmetrical form is easily produced by making the reticle used in photo lithography into asymmetrical form pattern. By forming the record layer 52 as shown in FIGS. 11A through 11F, a switching magnetic field can be reduced. According to examination of the Inventors, when the record layer 52 is formed as the elongated octagon as shown in FIG. 11F, it became possible to reduce the switching magnetic field notably.

[0159] In addition, although the angle parts are round in fact in many cases in the form where the magnetic record layer 52 is formed into the shapes as shown in FIGS. 11A-11C, 11E, and 11F when carrying out a patterning process. However, such rounded shape may be acceptable in the invention.

[0160] With regard to the ratio of the length L and the width W, L/W, of the magnetic record layer 52 of the magnetoresistance effect element, it is desirable that the ratio L/W is larger than 1.2. And it is also desirable to give an uniaxial anisotropy in the direction of the length L. It is because the direction of magnetization M3 can be mutually specified in the two directions for the contraries certainly and easily.

[0161] Next, some examples of the laminating structure of the magnetoresistance effect element which can be used for the magnetic memory of the embodiment of the invention are explained.

[0162] FIGS. 12 and 13 are a conceptual diagrams showing the cross-sectional structures of the magnetoresistance effect element of having ferromagnetic single tunnel junction. That is, in the case of the magnetoresistance effect clement shown in FIG. 12, the laminating of the anti-ferromagnetic layer AF, the ferromagnetic layer FM1, the tunnel barrier layer TB, the ferromagnetic layer FM2, and the protection layer PB is carried out to this order on the ground layer BF.

[0163] The ferromagnetic layer FM1 which adjoins the anti-ferromagnetic layer AF acts as a magnetization pinned layer (pinned layer), and the ferromagnetic layer FM2 which is stacked on the tunnel barrier layer TB acts as a record layer (free layer).

[0164] In the case of the magnetoresistance effect element shown in FIG. 13, in the upper and lower sides of the tunnel barrier layer TB, the stacked structures SL having the ferromagnetic layer FM, the non-magnetic layer NM, and the ferromagnetic layer FM are formed, respectively. In this case, the stacked structure SL interposed between the anti-ferromagnetic layer AF and the tunnel barrier layer TB also acts as a magnetization pinned layer, and the stacked structure SL provided on the tunnel barrier layer TB acts as a record layer.

[0165] FIGS. 14 through 16 are concepatual diagrams which illustrate the cross-sectional structure of the magnetoresistance effect elements of having ferromagnetic double tunnel junctions. The same symbols are given to the same elements as what were mentioned with reference to FIGS. 12 and 13, and detailed explanation is omitted.

[0166] In the case of the structure illustrated in FIGS. 14 through 16, the two tunnel barrier layers TB are formed, and the stacked structures SL of the ferromagnetic layer FM, or the ferromagnetic layer FM and the non-magnetism layer NM are formed in the upper and lower sides. In the cases of the double tunnel junction element illustrated here, the ferromagnetic layers FM which adjoin the upper and lower anti-ferromagnetism layer AF respectively act as magnetization pinned layers, and the ferromagnetic layer FM provided between the two tunnel barter layers TB acts as a record layer.

[0167] If such a double tunnel junction structure is adopted, it is advantageous at the point which can increase the current change with respect to the magnetization direction of a record layer.

[0168] In addition, the magnetoresistance effect element used in the magnetic memory of the invention is not limited to what was illustrated in FIGS. 12 through 16, but the so-called magnetoresistance effect element of the spin valve structure to which the laminating of the first ferromagnetic layer, a non-magnetism layer, and the second ferromagnetic layer is carried out can also be used.

[0169] Also when either structure is adopted as a magnetic resistance effect element, one ferromagnetic layer can be used as a magnetization pinned layer in which the magnetization direction is fixed substantially, and another ferromagnetic layer can be used as a magnetic record layer in which the magnetization direction is controllable by applying a magnetic field from the outside.

[0170] Moreover, the ferromagnetic layer formed to adjoin the anti-ferromagnetic layer can also be used as a record layer depending on the read-out method, as explained in full detail below.

[0171] As the ferromagnetic material which can be used as a magnetization pinned layer in these magnetoresistance effect elements, for example, Fe (iron), Co (cobalt), nickel (nickel), or these alloys, magnetite having a large spin polarization ratio, CrO₂, or RXMnO_3y (where R expresses a rare earth element, and X expresses calcium (calcium), Ba (barium), or Sr (strontium)) can be used.

[0172] Further, as the ferromagnetic material which can be used as a magnetization pinned layer in these magnetoresistance effect elements, Heusler alloys, such as NiMnSb (nickel manganese antimony), PtMnSb (platinum manganese antimony), Co2MnGe, and Co2MnSi, can be used. Moreover, the magnetic semiconductors can be used as the material of the pinned layer. Such a magnetic semiconductors include wide gap semiconductors, such as (In, Mn)As, (Ga, Mn)As, (Zn, Mn)Te, GaN, Zno, and TiO₂, (Cd_1xMn_x)GeP₂, CrAs, or (Ga, Cr)As, doped with a transition metal element as mentioned above.

[0173] A magnetic semiconductor can realize various magnetic states such as anti-ferromagnetic state, paramagnetic state, and ferromagnetic state with the kind and concentration of transition metal element doped to the wide gap semiconductor. Therefore, it is also possible to use a magnetic semiconductor for the ferromagnetic layer, the anti-ferromagnetic layer, or the non-magnetic layer in the magnetic resistance effect element illustrated in FIGS. 12 through 16.

[0174] Alternatively, by adding the dopant into the magnetic semiconductor with a dilute doping level, it is possible to induce a magnetic property only when a voltage is applied to the magnetic semiconductor. Such a magnetic semiconductor can be also used. If ZnO is taken for an example, and anti-ferromagnetism can be acquired when Mn is doped to ZnO, ferromagnetism can be acquired when V, Cr, Fe, Co, or nickel is doped, and paramagnetizm can be acquired when Ti or Cu is doped, for example,

[0175] When Mn is doped to GaN, there is no necessity to dope hole as hole is automatically doped unlike ZnO. This is because Ga is trivalence and Mn is divalence.

[0176] When Mn is doped into GaN, ferromagnetism can be acquired. As for the magnetization pinned layer which consists of such material, it is desirable to have unidirectional anisotropy. With regard to the thickness of these layers, it is desirable to range between 0.1 nm and 100 nm. Furthermore, in order to prevent the superparamagnetizm, it is more desirable to make the thickness not smaller than 0.4 nm.

[0177] Moreover, it is desirable to provide an anti-ferromagnetic film near the magnetization pinned layer in order to fix the magnetization thereof. As such an anti-ferromagnetic film, Fe (iron)-Mn (manganese), Pt (platinum)-Mn (manganese), Pt (platinum)-Cr (chromium)-Mn (manganese), Ni (nickel)-Mn (manganese), Ir (iridium)-Mn (manganese), NiO (oxidization nickel) and Fe₂O₃ (iron oxide), or the magnetic semiconductor mentioned above can be mentioned.

[0178] Moreover, in these magnetic materials, non-magnetic elements such as Ag (silver), Cu (copper), Au (gold), Al (aluminum), Mg (magnesium), Si (silicone), Bi (bismuth), Ta (tantalum), B (boron), C (carbon), O (oxygen), N (nitrogen), Pd (palladium), Pt (platinum), Zr (zirconium), Ir (iridium), W (tungsten), Mo (molybdenum), Nb (niobium), or H (hydrogen) can be added in order to adjust the magnetic properties, or other various properties, such as crystallinity, mechanical properties, and the chemical properties.

[0179] On the other hand, a stacked structure having a ferromagnetic layer and a non-magnetic layer can be used as a magnetization pinned layer. For example, the three-layered structure of the (ferromagnetic layer)/(nonmagnetic layer)/(ferromagnetic layer) which is illustrated in FIG. 13 etc. can be used. In this case, it is desirable to make an anti-ferromagnetic interaction work between the ferromagnetic layers on both sides through the non-magnetic layer.

[0180] As a specific method to fix the magnetization of the magnetic layer in one direction, three-layered structure such as Co (CoFe)/Ru/Co (CoFe), Co (CoFe) Ir/Co (CoFe), Co (CoFe)/Os/Co (CoFe) and (ferromagnetic layer)/(magnetic semiconductor nonmagnetic layer)/(magnetic semiconductor ferromagnetic layer) can be used. In this case, it is desirable to provide an anti-ferromagnetic layer to adjoin the three-layered structure.

[0181] As such an anti-ferromagnetic layer, FeMn, PtMn, PtCrMn, NiMn, IrMn, NiO, Fe₂O₃ and magnetic semiconductors can be used. By employing this structure, magnetization of the magnetization pinned layer can be fixed securely, a stray field from the magnetization pinned layer can be reduced (or controlled), and magnetization shift can be controlled by changing the thicknesses of the two ferromagnetic layers of the magnetization pinned layer.

[0182] On the other hand, as the material of a magnetic record layer (free layer), the same as the magnetization pinned layer can be used. For example, Fe (iron), Co (cobalt), nickel (nickel), or these alloys, magnetite having a large spin polarization ratio, CrO₂, or RXMnO_3y (where R expresses a rare earth element, and X expresses calcium (calcium), Ba (barium), or Sr (strontium)) can be used. Further, as the ferromagnetic material which can be used as a magnetic record layer in these magnetoresistance effect elements, Heusler alloys, such as NiMnSb (nickel manganese antimony), PtMnSb (platinum manganese antimony), Co₂MnGe, and CoMnSi, can be used.

[0183] The ferromagnetic layer as the magnetic record layer made of these materials may desirably have an uniaxial anisotropy parallel to its film plane.

[0184] With regard to the thickness of these layers, it is desirable to range between 0.1 nm and 100 nm. Furthermore, in order to prevent the superparamagnetizm, it is more desirable to make the thickness not smaller than 0.4 nm.

[0185] Alternatively, a two-layered structure of (soft magnetic layer)/(ferromagnetic layer), or a three-layered structure of (ferromagnetic layer)/(soft magnetic layer)/(ferromagnetic layer) can be used as the magnetic record layer.

[0186] By using a three-layered structure of (ferromagnetic layer)/(nonmagnetic layer)/(ferromagnetic layer), or five-layered structure of (ferromagnetic layer)/(nonmagnetic layer)/(ferromagnetic layer)/(nonmagnetic layer)/(ferromagnetic layer) as the record layer, and by adjusting the strength of the interaction between the ferromagnetic layers, it becomes possible to suppress an increase of a power consumption even if the cell width of the record layer as the memory cell becomes sub-micron.

[0187] In the case of the five-layered structure, the intermediate ferromagnetic layer may desirably be a soft magnetic layer, or a ferromagnetic layer which is divided by a non-magnetic.

[0188] It is also noted that in the case of the record layer, in these magnetic materials, non-magnetic elements such as Ag (silver), Cu (copper), Au (gold), Al (aluminum), Mg (magnesium), Si (silicone), Bi (bismuth), Ta (tantalum), B (boron), C (carbon), O (oxygen), N (nitrogen), Pd (palladium), Pt (platinum), Zr (zirconium), Ir (iridium), W (tungsten), Mo (molybdenum), Nb (niobium), or H (hydrogen) can be added in order to adjust the magnetic properties, or other various properties, such as crystallinity, mechanical properties, and the chemical properties.

[0189] On the other hand, when a TMR element is used as the magnetoresistance effect element, Al₂O₃ (aluminum oxide), SiO₂ (silicone oxide), MgO (magnesium oxide), AlN (aluminum nitride), Bi₂O₃ (bismuth oxide), MgF₂ (magnesium fluoride), CaF₂ (calcium fluoride), SrTiO₂ (titanium strontium oxide), AlXO₃ (X is rare earth elements, such as La, Hf, and Er), AlNO (aluminum nitride oxide), a non-magnetic semiconductor (InMn, GaN, GaAs, TiO₂, Zn, Te and these doped with transition metal), etc. can be used as the material of the tunnel barrier layer TB prepared between a magnetization pinned layer and a magnetization record layer.

[0190] These compounds may not necessarily have a perfect stoichiometric composition, but may have deficiency or excess of the component elements such as oxygen, nitrogen and fluoride. Moreover, the insulated layer (dielectric layer) may preferably thin enough to make a tunneling current flow therethrough. The practical thickness may preferably equal to or smaller than 10 nm.

[0191] Such a magnetoresistance effect element can be formed on a predetermined substrate using the usual thin film formation means, such as various sputtering methods, vapor-depositing method, the molecule beam epitaxy method, and CVD method.

[0192] As a substrate in this case, various kinds of substrates, such as Si (silicone), SiO₂ (oxidization silicone), Al₂O₃ (aluminum oxide), spinel, AlN (aluminum nitride), GaAs, and GaN, can be used, for example. Moreover, as a base layer of a protective layer, such as Ta (tantalum), Ti (titanium), Pt (platinum), Pd (palladium), Au(gold), Ti/Pt, Ta/Pt, Ti/Pd, Ta/Pd, Cu (copper), AlCu, Ru (ruthenium), Ir (iridium) and Os (osmium), GaAs, GaN, ZnO, TiO₂, etc. can be used.

[0193] Moreover, as the material of the ferromagnetic layers, elements, such as Pt and Pd, may be added into Fe, Co, Ni, or these alloys in order to form a semi-hardmagnetic film.

[0194] In the above, the basic structure of the magnetoresistance effect element in the magnetic memory of the embodiment and a switching element and their materials are explained.

[0195] Next, an example is given and explained about the cell structure of the magnetic memory according to an embodiment of the invention. First, an example of the architecture for read-out employable as the magnetic memory of the embodiment of the invention is explained.

[0196] FIGS. 17 through 21 are conceptual diagrams showing the first example of the architecture for read-out employable as the magnetic memory of the embodiment of the invention. That is, these diagrams shows cross-sectional structures of a memory array. The same symbols are given to the same elements as what was mentioned above about FIGS. 1A through 16 about these drawings, and detailed explanation is omitted.

[0197] The architecture shown in FIG. 17 is a read-out architecture of the so-called simple matrix type by which two or more magnetoresistance effect elements 50 are connected to the bit lines BL1 and BL2 for read-out wired in the shape of a matrix.

[0198] In the case of read-out, by choosing the bit lines BL1 and BL2 with the selection transistor ST (ST1, ST2), sense current can be passed for the target magnetoresistance effect element 50, and the sense amplifier SA can detect it.

[0199] FIG. 18 shows an example of the magnetic simple matrix type memory using the memory cell of the first type illustrated in FIG. 5.

[0200] FIG. 19 shows an example where the magnetoresistance effect element 50 has ferromagnetic double tunnel junctions.

[0201] On the other hand, FIG. 20 shows an example of the magnetic simple matrix type memory using the memory cell of the second type illustrated in FIG. 6.

[0202] FIG. 21 shows an example where the magnetoresistance effect element 50 has ferromagnetic double tunnel junctions.

[0203] In every structure shown in FIGS. 17 through 21, the writing to the record layer 52 impresses voltage to the gate electrode 40, and is performed by pouring an electron or an electron hole (hole) into the magnetic semiconductor layer 10.

[0204] Next, FIGS. 22 and 23 arc conceptual diagrams showing the second example of the architecture for read-out employable as the magnetic memory according to the embodiment of the invention. That is, this example is an example of structure using CMOS as the architecture for read-out

[0205] When CMOS is used, read-out is performed by turning the lower selection transistor ST on and by passing a sense current through the magnetoresistance effect element 50 via the bit line BL1.

[0206] On the other hand, writing is performed by applying a voltage to the gate electrode 40 of one of switching elements, and thereby injecting hole into the magnetic semiconductor layer 10.

[0207] Here, FIG. 22 shows the case where the memory cell of the first type is used, and FIG. 23 shows the case where the memory cell of the second type is used.

[0208] FIGS. 24 through 26 are conceptual diagrams showing the third example of the architecture for read-out employable as the magnetic memory according to an embodiment of the invention. That is, in this architecture, two or more magnetoresistance effect elements 50 are connected in parallel to the bit line BL1 for read-out.

[0209] At the time of read-out, the bit lines BL1 and BL2 connected to the target magnetoresistance effect element 50 are chosen with the selection transistors ST, respectively, and the sense amplifier SA detects the current flog therethrough. Diode D has the role which intercepts the detour current which flows through other magnetoresistance effect elements 50 currently wired in the shape of a matrix when the read-out is performed.

[0210] Writing is performed by applying a voltage to the gate electrode 40 of one of switching elements, and by injecting hole into the magnetic semiconductor.

[0211] FIG. 25 shows the case where the memory cell of the first type is used, and FIG. 26 shows the case where the memory cell of the second type is used, respectively.

[0212] Next, the fourth example of the architecture employable as the magnetic memory according to an embodiment of the invention is explained.

[0213] FIGS. 27 through 29 are conceptual diagrams showing the fourth example of the architecture for read-out. That is, these diagrams show the cross-sectional structure of a memory array. In this architecture, the structure of the ladder type where two or more magnetic resistance effect elements 50 are connected in parallel between the bit line BL1 for read-out and the bit line BL2 for read-out is adopted.

[0214] Writing is performed by applying a voltage to the gate electrode 40 of one of the switching elements that are connected to the magnetoresistance effect element 50, and by injecting hole into the magnetic semiconductor layer 10.

[0215] FIG. 28 shows the case where the memory cell of the first type is used, and FIG. 29 shows the case where the memory cell of the second type is used, respectively.

[0216] On the other hand, in the case of read-out, a voltage is applied between the bit lines BL1 and BL2. Then, current flows for all the magnetoresistance effect elements 50 connected in parallel between these bit lines. While the sense amplifier SA detects the sum total of this current, a writing voltage is applied to a switching element corresponding to the target magnetoresistance effect element 50, and thereby magnetization of the magnetic record layer 52 of the target magnetoresistance effect element 50 is rewritten in the predetermined direction.

[0217] By detecting the current change at this moment, binary information recorded in the record layer 52 of the target magnetoresistance effect element can be read. That is, if the magnetization direction of the magnetic recording layer 52 before rewriting is same as the magnetization direction thereof after rewriting, the current detected with the sense amplifier SA does not change.

[0218] However, in the case where the magnetization direction of the magnetic record layer 52 changes before and after rewriting, the current detected with the sense amplifier SA changes due to a magnetoresistance effect. Thus, the stored data (which corresponds to the magnetization direction of the record layer 52) can be read out. However, this method corresponds to the so-called destructive readout by which stored data is changed in the case of read-out.

[0219] On the other hand, when the magnetoresistance effect element has a layered structure of (magnetization free layer)/(insulated layer or non-magnetic layer)/(magnetic record layer), the so-called nondestructive readout is possible. That is, when using the magnetoresistance effect element of this structure, the magnetization direction is recorded in a magnetic record layer, and reading is performed by changing the magnetization direction of a magnetization free layer suitably, and by comparing the sense currents.

[0220] In this case, it is necessary to design so that the magnetization reversal magnetic field of a magnetization free layer may become smaller than the magnetization reversal magnetic field of the magnetic record layer.

[0221] Next, a magnetic probe and a magnetic head using a switching element of the embodiment of the invention are explained.

[0222] FIG. 30 is a conceptual diagram showing the magnetic probe and a magnetic head according to an embodiment of the invention. In the figure, the same or equivalent components as those already explained with reference to FIGS. 1A through 29 are labeled with common reference numerals, and their detailed explanation is omitted.

[0223] In the magnetic probe of this embodiment, a pair of switching elements are provided in the both sides of a magnetic pole 70.

[0224] In the case of the example shown in this figure, these switching elements corresponds to those shown in FIGS. 1A and 1B. And in these switching elements, the magnetization M1 of the ferromagnetic layers 20 are fixed in the opposite direction each other. Therefore, when voltage is applied to the magnetic semiconductor layer 10 and ferromagnetism is induced, the direction of the magnetization M2 formed in each magnetic semiconductor layers 10 also turn into the opposite direction corresponding to the magnetization M1. Magnetization is formed in a magnetic pole 70 by this magnetization M2, and the stray magnetic field M3 is applied to the object 100 for an action.

[0225] As the magnetic probe, predetermined voltage is applied between V0-V1 or between V0-V2. Then, magnetization M2 is formed in one magnetic semiconductor layer 10 of a pair of the switching elements, and the magnetic field of a predetermined direction can be applied to the object 100 for an action from the magnetic pole 70.

[0226] If a magnetic recording medium is used as the object 100 for an action, for example, the magnetic probe can be used as a magnetic head for writing. Since current is not passed on the occasion of formation of a writing magnetic field in this case, power consumption can be greatly reduced, and it also becomes possible to make the capacity and the scale of a drive circuit much smaller. Furthermore, this magnetic probe can be applied to all the uses for applying a magnetic field, and the same effect is obtained.

[0227] Hereafter, some embodiments of the invention will be explained in more detail, referring to a specific example of the invention.

[0228] First Example

[0229] As the first example of the invention, one memory cell was fabricated on the basis of the memory array of the simple matrix structure shown in FIG. 18, the principle of the operation of the memory cell of the first type was confirmed.

[0230] It will be as the following if the structure of this magnetic memory is explained along with that manufacture procedure.

[0231] On the substrate which is not illustrated, a wiring layer with a thickness of 1 micrometer made of Cu was first produced by the damascene process as a lower layer bit line BL1. After that, an insulated layer was formed by CVD method, and then the surface was flattened by CMP (Chemical Mechanical Polishing),

[0232] Then, the stacking structure of TMR which has a ferromagnetic single tunnel junction structure was formed by a sputtering method. The material and the thickness of each layer were taken as Ta (10 nm)/Ru (3 nm)/IrMn (8 nm)/CoFe (3 nm)/Ru (1 nm)/CoFe (3 nm) AlOx (1 nm)/CoFeNi (2 nm)/Ru (5 nm) from the bottom in this order.

[0233] Next, the isolated pattern of a TMR element was produced by etching the stacking structure down to lower Ta ground layer by RIE (Reactive Ion Etching) using etching gas, while utilizing the top W layer as a hard mask. Then, SiOx was deposited by the low-temperature TEOS (tetra ethyl ortho silicate) method as an insulator, and the surface was flattened by CMP while leaving 1.5 nm of Ru layer.

[0234] Then, a ferromagnetic record layer CoFeNi(2 nm)/Ru(1.5 nm)/Ta (3 nm) were formed and pattered into a predetermined shape. At this moment, a magnetic record layer consists of CoFeNi (2 nm) (having a smaller area)/Ru (1.5 nm)/CoFeNi (2 nm) (having a larger area), and a ferromagnetic interaction is operating through the Ru layer.

[0235] Then, the low-temperature TEOS process was performed to form SiO2 on the patterned CoFeNi/Ru/Ta structure. Then, SiO₂ was removed by RIE down to Ta in the left-hand side of the structure shown in FIG. 18. After that, the stacking structure of magnetic semiconductor (GaMn)N (20 nm)/CoFe (3 nm)/IrMn (8 nm)/Ta (3 nm)/SiO₂ (300 nm)/Ru (10 nm) was formed in this order from the bottom using sputtering method and low temperature MBE (Molecular Beam Epitaxy).

[0236] Next, the switching element on the left-hand side of the structure shown in FIG. 18 was formed with the same procedure using Ru as a hard mask. Furthermore, a stacking structure of magnetic semiconductor (GaMn)N (20 nm)/CoFe (3 nm)/Ru (1 nm)/CoFe (3 nm)/IrMn (8 nm)/Ta (3 nm)/SiO₂ (300 nm)/Ru (10 nm) which corresponds to a right-hand side switching element was formed by the same procedure.

[0237] After having covered by SiO₂, and performing flattening by CMP, via holes were formed, and the gate electrode and the bit line BL2 were formed. Then, the sample was introduced into the heat treatment furnace which can apply a magnetic field, and a uniaxial anisotropy was introduced into the magnetic record layer of a TMR element, and unidirectional anisotropy was introduced into the magnetic pinned layer of a TMR element and a switching element, respectively.

[0238] Thus, in the magnetic memory of this example, a voltage was applied to the gate electrode 40 and the signal output of a TMR element was measured in order to check the principle of the operation of the switching element.

[0239] As a result, when a voltage was applied to two switching elements by turns, 37% change of the MR ratio was confirmed, and thus the effect of the magnetization memory of the invention has been proved.

[0240] Second Example

[0241] Next, as the second example of the invention, one memory cell was fabricated on the basis of the memory array of the simple matrix structure shown in FIG. 20, the principle of the operation of the memory cell of the second type was confirmed.

[0242] It will be as the following if the structure of this magnetic memory is explained along with that manufacture procedure.

[0243] On the substrate which is not illustrated, a wiring layer with a thickness of 1 micrometer made of Cu was first produced by the damascene process as a lower layer bit line BL1. After that, an insulated layer was formed by CVD method, and then the surface was flattened by CMP (Chemical Mechanical Polishing).

[0244] Then, the stacking structure of TMR which has a ferromagnetic single tunnel junction structure was formed by a sputtering method. The material and the thickness of each layer were taken as Ta (2 nm)/Ru (3 nm)/PtMn (12 nm)/CoFe (2.5 nm) 1 Ru (1 nm)/CoFe (3nm)/AlOx (1 nm)/CoFeNi (1.8 nm)/Ru (1.8 m,)/CoFeNe (1.8 nm)/Ta (9 nm)/Ru (30 nm) from the bottom in this order.

[0245] Next, the isolated pattern of a TMR element was produced by etching the stacking structure down to the lower Ru/Ta/Cu wiring layer BL1 by RIE (Reactive Ion Etching) using etching gas, while utilizing the top Ru layer as a hard mask

[0246] Then, the low-temperature TEOS process was performed to form SiO2 on the patterned CoFeNi/Ru/Ta structure. Then, SiO₂ was removed by RIE down to Ta in the left-hand side of the structure shown in FIG. 20. After that, the stacking structure of magnetic semiconductor CoFe (5 nm)/(GaMn)N (200 nm)/CoFe (3 nm)/IrMn (8 nm)/Ta (3 nm)/SiO₂ (300 nm)/Ru (10 nm) was formed in this order from the bottom by using sputtering method and low temperature MBE (Molecular Beam Epitaxy).

[0247] Next, the switching element on the left-hand side of the structure shown in FIG. 20 was formed with the same procedure using the Ru layer as a hard mask. Furthermore, a stacking structure of magnetic semiconductor CoFe (5 nm)/(GaMn)N (20 nm)/CoFe (3 nm)/Ru (1 nm)/CoFe (3 nm)/IrMn (8 nm)/Ta (3 nm)/SiO₂ (300 nm)/Ru (10 nm) which corresponds to a right-hand side switching element was formed by the same procedure.

[0248] After having covered by SiO₂, and performing flattening by CMP, via holes were formed, and the gate electrode and the bit line BL2 were formed. Then, the sample was introduced into the heat treatment furnace which can apply a magnetic field, and a uniaxial anisotropy was introduced into the magnetic record layer of a TMR element, and unidirectional anisotropy was introduced into the magnetic pinned layer of a TMR element and a switching element, respectively.

[0249] Thus, in the magnetic memory of this example, a voltage was applied to the gate electrode 40 and the signal output of a TMR element was measured in order to check the principle of the operation of the switching element.

[0250] As a result, when a voltage was applied to two switching elements by turns, 42% change of the MR ratio was confirmed, and thus the effect of the magnetization memory of the invention has been proved.

[0251] Heretofore, some embodiments of the invention have been explained with reference to specific examples. The invention, however, is not limited to these specific examples. For example, the invention contemplates in its own cope all alternatives concerning materials, thicknesses, shapes, sizes, etc. of the magnetic semiconductor layer, ferromagnetic layer, insulating film, anti-ferromagnetic layer, nonmagnetic metal layer, electrode that are components of the switching elements and/or magnetoresistance effect element as far as persons skilled in the art can appropriately select them and can practically use the invention to obtain substantially the same effects.

[0252] Similarly, the invention contemplates in its own scope all alternatives concerning structures, materials, shapes and sizes of the bit line, digit line, word line, overcoat layer, selection transistor, diode and other composing the magnetic memory according to any embodiment of the invention as far as persons skilled in the art can appropriately select them and can practically use the invention to obtain substantially the same effects.

[0253] Further, the invention contemplates in its scope all magnetic heads including a lateral recording head and a vertical recording head that persons skilled in the at can make by modifying the magnetic memories shown here as embodiments of the invention.

[0254] Furthermore, the invention contemplates in its scope all magnetic memories that persons skilled in the art can make by modifying the magnetic memories shown here as embodiments of the invention.

[0255] While the present invention has been disclosed in terms of the embodiment in order to facilitate better understanding thereof, it should be appreciated that the invention can be embodied in various ways without departing from the principle of the invention. Therefore, the invention should be understood to include all possible embodiments and modification to the shown embodiments which can be embodied without departing from the principle of the invention as set forth in the appended claims.