Method for manufacturing semiconductor device with semiconductor region inserted into trench

[0001] This application is based upon and claims the benefit of Japanese Patent Application No. 2002-12171 filed on Jan. 21, 2002, the contents of which are incorporated herein by reference.

[0002] The present invention relates generally to methods for manufacturing a semiconductor device, more particularly for manufacturing a semiconductor device with a semiconductor region inserted into a trench.

[0003] JP-A-2001-196573 discloses a semiconductor device having a semiconductor region inserted in a trench. Regarding a method for manufacturing a semiconductor device, a first epitaxial layer is grown onto a silicon substrate including the trench by epitaxial growth. A portion of the first epitaxial layer corresponding to an opening of the trench is etched by an HCl gas. Then, a second epitaxial layer is grown onto the first epitaxial layer.

[0004] JP-A-2001-274398 discloses a three-dimension power MOSFET in which an N type drift layer, a P type channel layer and an N type source layer (hereinafter referred to as a three-layered configuration) are formed into a trench formed on a silicon substrate. When the configuration disclosed in JP-A-2001-274398 is applied to the method disclosed in JP-A-2001-196573 and the three-layered configuration is formed in the trench, the P type channel layer is liable to form a thin layer at a bottom portion of the trench.

[0005] For example, as shown in FIG. 22A, an N type layer J3 is formed onto the silicon substrate J1 including the trench J2 by epitaxial growth after the trench J2 is formed on the silicon substrate J1. A surface portion of the N type layer J3 is then removed by HCl gas. Thus, an opening portion of the N type layer J3 is enlarged as shown in FIG. 22B. The N type layer J3 is grown again, and a P type layer J4 and an N type layer J5 are grown onto the N type layer J3 as shown in FIG. 22C. Thereafter, the silicon substrate J1 configured above is heated to 1150 C. for 10 minutes. As a result, the three-layered configuration (J3-J5) shown in FIG. 22D is completed. Upon SCM analysis performed on the silicon substrate with the three-layered configuration, a portion of the P type layer (P type channel layer) J4 located at the bottom portion of the trench J2 is transformed into an N type layer. Accordingly, the N source layer and the N type drift layer are electrically connected one another, increasing a leak current when the three-dimensional MOSFET is OFF and decreasing a withstanding voltage of a drain region that approximately equals a withstanding voltage of a source region.

[0006] It is therefore an object of the present invention to provide a method for manufacturing a semiconductor device that is capable of obviating the above problem.

[0007] It is another object of the present invention to provide a method for manufacturing a semiconductor device which includes a three-layered configuration having a first conductive layer/a second conductive layer/a first conductive layer formed in a trench, to prevent the second conductive layer from being too thin.

[0008] It is another object of the present invention to provide a method for manufacturing a semiconductor device having increased reliability relative to a withstanding voltage.

[0009] According to a first aspect of the present invention, a portion of a first epitaxial layer formed in a trench in a silicon substrate is removed by vapor phase etching using a halogenated compound or hydrogen. In this removal process, the portion of the first epitaxial layer is removed at a predetermined temperature higher than that during epitaxial growth of the first epitaxial layer and under a predetermined pressure higher than that during epitaxial growth of the first epitaxial layer.

[0010] Therefore, stress that would otherwise be concentrated at a bottom portion of the trench is relaxed because rearrangement of the silicon atoms increases. The semiconductor device including a three-layered configuration having a first conductive layer/a second conductive layer/a frist conductive layer formed in the trench can prevent the second conductive layer from being too thin.

[0011] According to a second aspect of the present invention, heating is performed on the semiconductor substrate for relaxing stress that would otherwise be concentrated at a bottom portion of the trench. The heating is performed between the forming of the second epitaxial layer and the forming of the third epitaxial layer. The heating can alternatively be performed after the forming the third epitaxial layer. Accordingly, as mentioned above, stress that would otherwise be concentrated at a bottom portion of the trench is relaxed.

[0012] According to a third aspect of the present invention, an ion diffusion layer formed of second conductive type semiconductor is formed at a surface portion of the second epitaxial layer including that in the trench by vapor diffusion. Therefore, stress which is generated if a second conductive type semiconductor layer is formed by epitaxial growth is not applied to a bottom portion of the trench.

[0013] According to a fourth aspect of the present invention, corner portions of the trench are rounded by, for example, heat treatment after the portion of the first epitaxial layer is removed. Accordingly, as mentioned above, stress that would otherwise be concentrated at a bottom portion of the trench is relaxed.

[0014] According to a fifth aspect of the present invention, the trench is formed in a semiconductor substrate so that an aspect ratio thereof is set at most to 1.6. Therefore, the semiconductor device including a three-layered configuration having a first conductive layer/a second conductive layer/a first conductive layer formed in the trench can prevent the second conductive layer from being too thin.

[0015] Other objects, features and advantages of the present invention will be understood more fully from the following detailed description made with reference to the accompanying drawings. In the drawings:

[0016] FIGS. 1A to 1C are cross sectional views showing production processes of a semiconductor device according to a first embodiment of the present invention;

[0017] FIGS. 2A to 2C are cross sectional views showing production processes of the semiconductor device following FIG. 1C;

[0018] FIGS. 3A to 3D are cross sectional views showing production processes of a semiconductor device according to a second embodiment of the present invention;

[0019] FIGS. 4A to 4C are cross sectional views showing production processes of the semiconductor device following FIG. 3D;

[0020] FIGS. 5A to 5C are cross sectional views showing production processes of a semiconductor device according to a third embodiment of the present invention;

[0021] FIGS. 6A to 6C are cross sectional views showing production processes of the semiconductor device following FIG. 5C;

[0022] FIGS. 7A to 7C are cross sectional views showing production processes of a semiconductor device according to a fourth embodiment of the present invention;

[0023] FIGS. 8A to 8C are cross sectional views showing production processes of the semiconductor device following FIG. 7C;

[0024] FIGS. 9A to 9C are cross sectional views showing production processes of a semiconductor device according to a fifth embodiment of the present invention;

[0025] FIGS. 10A to 10C are cross sectional views showing production processes of the semiconductor device following FIG. 9C;

[0026] FIGS. 11A to 11D are cross sectional views showing production processes of a semiconductor device according to a sixth embodiment of the present invention;

[0027] FIGS. 12A to 12C are cross sectional views showing production processes of the semiconductor device following FIG. 11D;

[0028] FIGS. 13A to 13D are cross sectional views showing production processes of a semiconductor device according to a seventh embodiment of the present invention;

[0029] FIGS. 14A to 14C are cross sectional views showing production processes of the semiconductor device following FIG. 13D;

[0030] FIGS. 15A and 15B show cross sectional views showing the semiconductor device of the first embodiment and a related art semiconductor device based on SCM analyses;

[0031] FIG. 16 shows a cross sectional view showing the semiconductor device based on the SCM analysis according to the first embodiment;

[0032] FIG. 17 shows a relationship between a voltage and a current of semiconductor device of the first embodiment and the related art semiconductor;

[0033] FIG. 18 shows a cross sectional view showing the semiconductor device based on the SCM analysis according to the fourth embodiment;

[0034] FIG. 19 shows a relationship between a pressure during heat treating and a curvature radius of a trench according to fifth embodiment;

[0035] FIGS. 20A to 20C show cross sectional views showing the semiconductor device based on the SCM analysis when an aspect ratio changes according to the seventh embodiment;

[0036] FIG. 21 shows a relationship between a depth of a trench and a thickness of a P type layer according to the seventh embodiment;

[0037] FIGS. 22A to 22D are cross sectional views showing production processes according to a related art semiconductor device; and

[0038] FIG. 23 is a cross sectional view showing the semiconductor device based on the SCM analysis according to the related art semiconductor device.

[0039] The present invention will be described further with reference to various embodiments shown in the drawings.

[0040] (First Embodiment)

[0041] A semiconductor device of a first embodiment will now be described with reference to FIGS. 1, 2. The semiconductor device corresponds to a three-dimension power MOSFET such as that disclosed in, for example, JP-A-2001-274398, and a manufacturing method thereof will be described in the first embodiment.

[0042] FIG. 2C shows a completed three-dimension power MOSFET. As shown in FIG. 2C, an N type silicon layer 3a, 3b corresponding to a drift layer, a P type silicon layer 4 corresponding to a channel layer and an N type silicon layer 5 corresponding to a source layer are disposed on an inner surface of a trench 2 formed in an N type silicon substrate 1 corresponding to a drain region.

[0043] A manufacturing process will now be described. As shown in FIG. 1A, the trench 2 is formed in a predetermined region of the silicon substrate 1 formed of N type single crystal by dry etching or anisotropic wet etching. A silicon oxide layer, a silicon nitride layer or a two-layered configuration formed by a silicon oxide layer and a silicon nitride layer may be used as an etching mask for a trench etching. A silicon oxide layer naturally formed on the silicon substrate 1, the etching mask and a reaction product due to the trench etching are then removed by hydrofluoric acid (HF).

[0044] As shown in FIG. 1B, the silicon substrate 1 is inserted in a heat furnace and is heated by an annealing treatment to round corners of a bottom portion and an opening portion of the trench 2. The N silicon layer 3a is then formed on the silicon substrate 1 including the trench 2 by epitaxial growth.

[0045] As shown in FIG. 2A, a part of the silicon layer 3a is removed by etching based on vapor phase etching effects of hydrogen chloride (HCl) with an atmospheric gas including HCl. As a result, because a portion of the N silicon layer 3a located on the opening portion of the trench 2 is deeply removed, side walls of the trench 2 are tapered. For example, the etching is conducted by introducing an etching gas into a vacuum atmosphere with a non-oxidizing and non-nitrizing gas (e.g., hydrogen or a noble gas).

[0046] In the first embodiment, an LP-CVD apparatus is used to continuously perform the epitaxial growth and the etching in a significant vacuum chamber thereof. Further, the etching in which the etching gas is introduced into the vacuum atmosphere with the non-oxidizing and non-nitrizing gas is performed under a condition as follows.

[0047] (1) Etching temperature is defined at not less than a temperature at which the epitaxial growth can be performed, is specifically set at temperature between 850 C. and 1300 C., and is preferably set at temperature between 1100 C. and 1200 C.

[0048] (2) A pressure in the vacuum chamber is set to at least a pressure during the epitaxial growth, is specifically set to a pressure between 10 torr and 760 torr (equal to atmospheric pressure), and is preferably set to a pressure between 300 torr and 600 torr.

[0049] (3) A flow rate of H₂ or a noble gas as the non-oxidizing and non-nitrizing gas is set at 10-50 liters per minute.

[0050] (4) A flow rate of HCl as the etching gas is set at 1 liter per minute.

[0051] In this condition, a stress that would otherwise be concentrated at the bottom portion of the trench 2 is relaxed. A halogenated compound or hydrogen (H₂) may alternatively be adapted as an etching gas to remove the part of the silicon layer 3a using gas phase etching effects of the halogenated compound or hydrogen.

[0052] Successively, as shown in FIG. 2B, the N type layer 3b is formed onto the silicon substrate 1 including the trench 2 by eptaxial growth to cover the N type silicon layer 3a. The P type silicon layer 4 is then formed on the silicon substrate 2 including the trench 2 by eptaxial growth to cover the N type silicon layer 3b. Further, the N type silicon layer 5 is formed on the silicon substrate 1 including the trench 2 by eptaxial growth to cover the P type silicon layer 4.

[0053] A heat treatment is performed on the silicon substrate 1 to decrease voids formed in the trench 2. Surfaces of the respective layers 3a, 3b, 4 and 5 are flattened by, for example, etching back, anisotropic wet etching or a combination thereof.

[0054] Experimental results will now be described with reference to FIGS. 15-17 and 23. FIGS. 15A and 15B show cross sectional views showing the semiconductor of the first embodiment and a related art semiconductor based on SCM analyses. Specifically, FIGS. 15A and 15B show experimental results in which the pressure in the vacuum chamber is set to pressures of 80 torr and 600 torr, respectively, when the N type silicon layer 3a is etched by HCl under the vacuum atmosphere with the non-oxidizing and non-nitrizing gas. The SCM analyses show that the bottom portion of the trench 2 etched under 600 torr is rounded by moving silicon atoms compared with that etched under 80 torr. This is because a pressure of H₂ as the non-oxidizing and non-nitrizing gas under 600 torr is larger than that under 80 torr, and rearrangement of the silicon atoms increases and stress generated around the bottom portion of the trench 2 is automatically relaxed.

[0055] FIGS. 16 and 23 are cross sectional views showing the semiconductor based on the SCM analyses according to the first embodiment and a related art semiconductor device. Specifically, FIGS. 16 and 23 show experimental results in which the pressure in the vacuum chamber is set to pressures of 600 torr and 80 torr, respectively, when the N type silicon layer 3a (FIG. 1) is etched by HCl under the vacuum atmosphere with the non-oxidizing and non-nitrizing gas, and a three-layered configuration is then formed in the trench 2. The analyses show that the P type silicon layer 4 located at the bottom portion of the trench 2 under 600 torr is restricted to transform into an N type silicon compared with that under 80 torr. This is because the stress generated around the bottom portion of the trench 2 may decrease.

[0056] FIG. 17 shows electrical characteristics of the semiconductor device of the first embodiment and the related art semiconductor device. A solid line L1 corresponds to plots showing a relationship between a reverse direction current and a voltage when a voltage applied between a channel region and a source region illustrated in FIG. 16 (equal to a portion between Pc and Ps illustrated in FIG. 16) is gradually increased. A solid line L2 corresponds to plots showing a relationship between a reverse direction current and a voltage when a voltage applied between the channel region and a drain region illustrated in FIG. 16 (equal to a portion between Pc and Pd illustrated in FIG. 16) is gradually increased. A solid line L3 corresponds to plots showing a relationship between a reverse direction current and a voltage when a voltage applied between a channel region and a source region illustrated in FIG. 23 (equal to a portion between Pc and Ps illustrated in FIG. 23) is gradually increased. A solid line L4 corresponds to plots showing a relationship between a reverse direction current and a voltage when a voltage applied between the channel region and a drain region illustrated in FIG. 23 (equal to a portion between Pc and Pd illustrated in FIG. 23) is gradually increased.

[0057] As illustrated by the solid lines L3, L4, a withstand voltage V1 between the channel region and the source region equals a withstand voltage V2 between the channel region and the drain region. To the contrary, as illustrated by the solid lines L1, L2, a withstand voltage V1 between the channel region and the source region is different from a withstand voltage V2 between the channel region and the drain region. In other words, regarding PN diode characteristics, the related art semiconductor device in which the etching is performed under 80 torr is defined so that the withstand voltage V1 equals the withstand voltage V2 (V1V2), while the semiconductor device of the first embodiment in which the etching is performed under 600 torr is defined so that the withstand voltage V1 does not equal the withstand voltage V2 (V1V2). Therefore, in the semiconductor device of the first embodiment, the source region and the drain region (a drift region) are electrically isolated. This shows that the P type silicon layer 4 located at the bottom portion of the trench 2 is restricted to transform into an N type silicon.

[0058] According to the above mentioned analyses, when the heat treatment under the vacuum atmosphere with the non-oxidizing and non-nitrizing gas, the stress that would otherwise be concentrated at the bottom portion of the trench 2 is relaxed because rearrangement of the silicon atoms increases. In the heat treatment, the temperature is set at not less than a temperature at which the epitaxial growth can be performed, and a pressure of the non-oxidizing and non-nitrizing gas is set larger than that during the epitaxial growth process. Accordingly, the semiconductor device of the first embodiment can be completed without additional manufacturing equipment as is needed for the related art semiconductor device disclosed in JP-A-2001-274398. The channel region (the P type silicon layer 4) is not enlarged due to ion diffusion caused by high temperature and high pressure of the hydrogen because the heat treatment is performed before the P type silicon layer 4 is formed. Further, the heat treatment can decrease stress and crystalline defections.

[0059] As mentioned above, in the manufacturing process of the semiconductor device of the first embodiment, the etching of the N silicon layer 3a is performed under conditions in which temperature and pressure are higher than those during formation of the N silicon layer 3a. Therefore, the stress that would otherwise be concentrated at the bottom portion of the trench 2 is relaxed. As a result, a semiconductor device including the three-layered configuration having a first conductive layer/a second conductive layer/a first conductive layer formed in a trench can prevent the second conductive layer from being too thin.

[0060] (Second Embodiment)

[0061] The manufacturing process of a semiconductor device of a second embodiment will now be described with reference to FIGS. 3, 4. In the second embodiment, portions of the manufacturing process different from the first embodiment will be primarily described.

[0062] As shown in FIG. 3A, a trench 12 is formed in a predetermined region of a silicon substrate 11 formed of an N type single crystal. A silicon oxide layer naturally formed on the silicon substrate 11, an etching mask and a reaction product due to the trench etching are then removed by hydrofluoric acid (HF).

[0063] As shown in FIG. 3B, the silicon substrate 11 is inserted in a heat furnace and is heated by an annealing treatment to round corners of a bottom portion and an opening portion of the trench 12. As shown in FIG. 3C, an N silicon layer 13a is then formed on the silicon substrate 11 including in the trench 12 by epitaxial growth.

[0064] As shown in FIG. 3D, a part of the silicon layer 13a is removed by etching based on vapor phase etching effects of hydrogen chloride (HCl) or a halogenated compound with an atmospheric gas including HCl or a halogenated compound. As a result, because a portion of the N silicon layer 13a located on the opening portion of the trench 12 is deeply removed, side walls of the trench 12 are tapered.

[0065] Successively, as shown in FIG. 4A, an N type layer 13b is formed on the silicon substrate 11 including the trench 12 by eptaxial growth to cover the N type silicon layer 13a. A P type silicon layer 14 is then formed on the silicon substrate 12 including the trench 12 by eptaxial growth to cover the N type silicon layer 13b. Further, an N type silicon layer 15 is formed on the silicon substrate 11 including the trench 12 by eptaxial growth to cover the P type silicon layer 14.

[0066] A heat treatment is performed on the silicon substrate 11 to decrease voids formed in the trench 12. Surfaces of the respective layers 13a, 13b, 14 and 15 are flattened.

[0067] In the second embodiment, an annealing treatment under an atmospheric gas with a non-oxidizing and non-nitrizing gas is performed before the P type silicon layer 14 illustrated in FIG. 4B is formed under a condition as follows.

[0068] (1) An annealing temperature is defined at not less than temperature at which the epitaxial growth can be performed, is specifically set at temperature between 850 C. and 1300 C., and is preferably set at temperature between 1100 C. and 1200 C.

[0069] (2) A pressure in the vacuum chamber is set to at least a pressure during the epitaxial growth, is specifically set to a pressure between 10 torr and 760 torr (equal to to atmospheric pressure), and is preferably set to a pressure between 300 torr and 600 torr.

[0070] (3) H₂ or a noble gas is used as the non-oxidizing and non-nitrizing gas.

[0071] In this condition, stress that would otherwise be concentrated at the bottom portion of the trench 12 is relaxed.

[0072] As mentioned above, in the manufacturing process of the semiconductor device of the second embodiment, the annealing treatment (heat treatment) is performed on the N silicon layers 13a, 13b after the part of the N silicon layer 13a is removed and the N silicon layer 13b is formed. Therefore, the stress that would otherwise be concentrated at the bottom portion of the trench 12 is relaxed. As a result, a semiconductor device including the three-layered configuration having a first conductive layer/a second conductive layer/a first conductive layer formed in a trench can prevent the second conductive layer from being too thin.

[0073] (Third Embodiment)

[0074] The manufacturing processes of a semiconductor device of a third embodiment will now be described with reference to FIGS. 5, 6. In the third embodiment, portions of the manufacturing processes different from the first embodiment will be primarily described.

[0075] As shown in FIG. 5A, a trench 22 is formed in a predetermined region of a silicon substrate 21 formed of N type single crystal. A silicon oxide layer naturally formed on the silicon substrate 21, an etching mask and a reaction product due to the trench etching are then removed by hydrofluoric acid (HF).

[0076] As shown in FIG. 5B, the silicon substrate 21 is inserted in a heat furnace and is heated by an annealing treatment to round corners of a bottom portion and an opening portion of the trench 22. As shown in FIG. 5C, an N silicon layer 23a is then formed on the silicon substrate 21 including in the trench 22 by epitaxial growth.

[0077] As shown in FIG. 6A, a part of the silicon layer 23a is removed by etching based on vapor phase etching effects of hydrogen chloride (HCl) or a halogenated compound with an atmospheric gas including HCl or a halogenated compound. As a result, because a portion of the N silicon layer 23a located on the opening portion of the trench 22 is deeply removed, side walls of the trench 22 are tapered.

[0078] Successively, as shown in FIG. 6B, an N type layer 23b is formed on the silicon substrate 21 including the trench 22 by eptaxial growth to cover the N type silicon layer 23a. A P type silicon layer 24 is then formed on the silicon substrate 22 including the trench 22 by eptaxial growth to cover the N type silicon layer 23b.

[0079] In the third embodiment, a formation process of the P type silicon layer 24 and an annealing treatment under an atmospheric gas with a non-oxidizing and non-nitrizing gas are repeatedly performed several times. That is, the annealing treatment is performed after the formation process of the P type silicon layer 24 is partially completed, and the rest of the forming process of the P type silicon layer 24 is performed after the annealing treatment.

[0080] The formation process of the P type silicon layer 24 and the annealing treatment are performed under conditions as follows.

[0081] (1) Epitaxial growth temperature of the P type silicon layer 24 is set at temperature between 800 C. and 950 C. Annealing temperature is set at temperature between 850 C. and 1300 C., and is preferably set at temperature between 1100 C. and 1200 C.

[0082] (2) A pressure in the vacuum chamber is set to a pressure between 1 torr and 100 torr during epitaxial growth, is set to a pressure between 1 torr and 760 torr (equal to atmospheric pressure) during the annealing treatment, and is preferably set to a pressure between 300 torr and 600 torr during the annealing treatment.

[0083] (3) SiH₄, SiH₂Cl₂, SiHCl₃ or SiCl₄ is used as a material gas during the epitaxial growth. H₂ or a noble gas is used as the non-oxidizing and non-nitrizing gas during the annealing treatment.

[0084] According to the manufacturing process, the annealing treatment is performed while during the P type silicon layer 24 is formed. In this condition, stress that would otherwise be concentrated at the bottom portion of the trench 22 is relaxed.

[0085] Further, as shown in FIG. 6C, an N type silicon layer 25 is formed onto the silicon substrate 21 including the trench 22 by eptaxial growth to cover the P type silicon layer 24. A heat treatment is performed on the silicon substrate 21 to decrease voids formed in the trench 22. Surfaces of the respective layers 23a, 23b, 24 and 25 are flattened.

[0086] As mentioned above, in the manufacturing process of the semiconductor device of the third embodiment, the annealing treatment (heat treatment) is performed on the silicon layers 23a, 23b and 24. Therefore, the stress that would otherwise be concentrated at the bottom portion of the trench 22 is relaxed. As a result, a semiconductor device including the three-layered configuration having a first conductive layer/a second conductive layer/a first conductive layer formed in a trench can prevent the second conductive layer from being too thin.

[0087] A formation process of the P type silicon layer 24 is divided into several portions, and the annealing process is performed after each portion of the formation process of the P type silicon layer 24. Therefore, since the silicon layers 23-25 can more appropriately be filled in the trench 22, faults in the semiconductor device caused when the silicon layers 23-25 are not filled in the trench 22 can be prevented.

[0088] (Fourth Embodiment)

[0089] The manufacturing process of a semiconductor device of a fourth embodiment will now be described with reference to FIGS. 7, 8. In the fourth embodiment, portions of the manufacturing process different from the first embodiment will be primarily described.

[0090] As shown in FIG. 7A, a trench 32 is formed in a predetermined region of a silicon substrate 31 formed of N type single crystal. A silicon oxide layer naturally formed on the silicon substrate 31, an etching mask and a reaction product due to the trench etching are then removed by hydrofluoric acid (HF).

[0091] As shown in FIG. 7B, the silicon substrate 31 is inserted in a heat furnace and is heated by an annealing treatment to round corners of a bottom portion and an opening portion of the trench 32. As shown in FIG. 7C, an N silicon layer 33a is then formed on the silicon substrate 31 including in the trench 32 by epitaxial growth.

[0092] As shown in FIG. 8A, a part of the silicon layer 33a is removed by etching based on vapor phase etching effects of hydrogen chloride (HCl) or a halogenated compound with an atmospheric gas including HCl or a halogenated compound. As a result, because a portion of the N silicon layer 33a located on the opening portion of the trench 32 is deeply removed, side walls of the trench 32 are tapered.

[0093] Successively, as shown in FIG. 8B, an N type layer 33b is formed on the silicon substrate 31 including the trench 32 by eptaxial growth to cover the N type silicon layer 33a.

[0094] A P type silicon layer 34 is then formed on a surface region of the N type silicon layers 33a, 33b by vapor diffusion. The P type silicon layer 34 is formed during heat treatment under an atmospheric gas with a non-oxidizing and non-nitrizing gas and with B₂H₆ being introduced as a doping gas. Specifically, the formation process of the P type silicon layer 34 is performed under the following conditions.

[0095] (1) A temperature of the heat treatment is defined at not less than a temperature at which the epitaxial growth can be performed, is specifically set at temperature between 850 C. and 1300 C., and is preferably set at temperature between 1100 C. and 1200 C.

[0096] (2) A pressure in the vacuum chamber is set to at least a pressure during the epitaxial growth, is specifically set to a pressure between 10 torr and 760 torr (equals to atmosphere pressure), and is preferably set to a pressure between 300 torr and 600 torr.

[0097] (3) H₂ or a noble gas is used as the non-oxidizing and non-nitrizing gas.

[0098] (4) B₂H₆ as the doping gas is diluted with H₂.

[0099] Further, as shown in FIG. 8C, an N type silicon layer 35 is formed on the silicon substrate 31 including the trench 32 by eptaxial growth to cover the P type silicon layer 34. Heat treatment is performed on the silicon substrate 31 to decrease voids formed in the trench 32. Surfaces of the respective layers 33a, 33b, 34 and 35 are flattened.

[0100] According to the manufacturing processes of the fourth embodiment, the P type silicon layer 34 is formed by heat treatment under an atmospheric gas with B₂H₆ after the N type silicon layers 33a, 33b are formed. In this heat treatment, the B₂H₆ gas is mixed in H₂ (or a noble gas) used as a carrier gas, and a pressure in the vacuum chamber in which an atmospheric gas including the B₂H₆ and H₂ is introduced is decreased. Temperature of the heat treatment is set at more than 1000 C. (more preferably 1100 C. ) to increase automatic stress relaxation due to rearrangement of silicon atoms though boron (B) ions can be diffused at more than 800 C.

[0101] FIG. 18 is a cross sectional view showing the semiconductor device, to which a heat treatment at 1150 C. is performed for 10 minutes after the silicon layers 33a, 33b, 34 and 35 are formed, based on the SCM analysis. A thickness of the P type layer 34 is uniform from portions on side walls of the trench 32 to a portion on a bottom portion of the trench 32. This is because the automatic stress relaxation due to rearrangement of silicon atoms increases by the annealing treatment using B₂H₆ gas at high temperature and with high hydrogen pressure, and therefore the stress generated around the bottom portion of the trench 32 may decrease.

[0102] According to the above mentioned manufacturing process of the fourth embodiment, the P type silicon layer 34 is formed in N type silicon layers 33a, 33b by vapor diffusion with the heat treatment under the non-oxidizing and non-nitrizing gas (pressure decreased atmospheric gas) using B₂H₆. The vapor diffusion process also acts as heat treatment under the non-oxidizing and non-nitrizing gas so that rearrangement of the silicon atoms in a portion of silicon layers 33a, 33b and 34, at which stress is concentrated, increases and stress generated around the bottom portion of the trench 32 is automatically relaxed. Temperature during the diffusion process is set to a temperature higher than that during epitaxial growth, and a pressure of the non-oxidizing and non-nitrizing gas is set to a pressure higher than that during epitaxial growth. Therefore, the semiconductor device of the fourth embodiment can be completed without additional manufacturing equipment and can decrease stress and crystalline defects with respect to the related art semiconductor device disclosed in JP-A-2001-274398.

[0103] As mentioned above, the P type silicon layer 34 is formed in the surface region of the N type silicon layer 33a, 33b by vapor diffusion. Therefore, stress which is generated if the P type silicon layer 34 is formed by epitaxial growth is not applied to a bottom portion of the trench 32. As a result, a semiconductor device including the three-layered configuration having a first conductive layer/a second conductive layer/a first conductive layer formed in a trench can prevent the second conductive layer from being too thin. In addition, when the vapor diffusion process in which the P type silicon layer 34 is formed is performed at 1000 C. or more, and more preferably performed at 1100 C. or more, stress is effectively relaxed by the heat treatment.

[0104] (Fifth Embodiment)

[0105] The manufacturing process of a semiconductor device of a fifth embodiment will now-be described with reference to FIGS. 9, 10. In the fifth embodiment, portions of the manufacturing process different from the first embodiment will be primarily described.

[0106] As shown in FIG. 9A, a trench 42 is formed in a predetermined region of a silicon substrate 41 formed of N type single crystal. A silicon oxide layer naturally formed on the silicon substrate 41, an etching mask and a reaction product due to the trench etching are then removed by hydrofluoric acid (HF).

[0107] As shown in FIG. 9B, the silicon substrate 41 is inserted in a heat furnace and is heated by an annealing treatment to round corners of a bottom portion and an opening portion of the trench 42. As shown in FIG. 9C, an N silicon layer 43a is then formed on the silicon substrate 41 including in the trench 42 by epitaxial growth.

[0108] As shown in FIG. 10A, a part of the silicon layer 43a is removed by etching based on vapor phase etching effects of hydrogen chloride (HCl) or a halogenated compound with an atmospheric gas including HCl or a halogenated compound. As a result, because a portion of the N silicon layer 43a located on the opening portion of the trench 42 is deeply removed, side walls of the trench 42 are tapered.

[0109] Successively, as shown in FIG. 10B, an N type layer 43b is formed onto the silicon substrate 41 including the trench 42 by eptaxial growth to cover the N type silicon layer 43a. A P type silicon layer 44 is then formed on the silicon substrate 42 including the trench 42 by eptaxial growth to cover the N type silicon layer 43b.

[0110] Further, as shown in FIG. 10C an N type silicon layer 45 is formed onto the silicon substrate 41 including the trench 42 by eptaxial growth to cover the P type silicon layer 44. Heat treatment is performed to the silicon substrate 41 to decrease voids formed in the trench 42. Surfaces of the respective layers 43a, 43b, 44 and 45 are flattened.

[0111] In the fifth embodiment, an annealing treatment under an atmospheric gas with a non-oxidizing and non-nitrizing gas is performed during rounding of the bottom portion and the opening portion of the trench 42 as shown in FIG. 9B. The annealing treatment is performed in an identical chamber in which epitaxial growth of the respective silicon layers 43a, 43b, 44 and 45 is formed under conditions as follows.

[0112] (1) Temperature of the annealing treatment is defined at not less than temperature at which the epitaxial growth can be performed, is specifically set at temperature between 850 C. and 1300 C., and is preferably set at temperature between 1100 C. and 1200 C.

[0113] (2) A pressure in the vacuum chamber (degree of vacuum) is set to at least a pressure during the epitaxial growth, is specifically set to a pressure between 10 torr and 760 torr (equals to atmosphere pressure), and is preferably set to a pressure between 300 torr and 600 torr.

[0114] (3) A flow rate of H₂ or a noble gas as the non-oxidizing and non-nitrizing gas is set in 10-50 liters per minute.

[0115] Under those conditions, a stress that would otherwise be concentrated at the bottom portion of the trench 2 is relaxed.

[0116] According to the manufacture processes, the silicon substrate 41 is inserted in a vacuum chamber of an LP-CVD apparatus after the oxide layer naturally formed on the silicon substrate 41 is removed. Then, corners of the bottom portion of the trench 42 are rounded in the chamber of the LP-CD apparatus by an annealing treatment (heat treatment) with an atmospheric gas including the non-oxidizing and non-nitrizing gas (specifically, H₂ is introduced) before the silicon layers 43a, 43b, 44 and 45 is formed. Therefore, the rounding treatment of the corners decreases stress because the stress generated at the bottom portion of the trench 42 may be concentrated in the corners at which plural epitaxial layers are grown on surfaces of silicon having different planar directions. The annealing treatment is performed at a temperature during epitaxial growth (e.g., 850 C.) for moving silicon atoms, is preferably set at 1100 C. or more. A pressure of H₂ is set high for effectively removing an oxide layer that is formed on a surface of the silicon substrate 41 and restricts movement of the silicon atoms. The degree of vacuum is set to at least a pressure during the epitaxial growth (e.g., 80 torr or more), and is preferably set to a pressure between 200 torr and atmospheric pressure. As a result, as shown in FIG. 19, radii of the corners after the annealing treatment are larger than before the annealing treatment so that the corners are rounded.

[0117] Incidentally, when an additional annealing treatment is performed before the P type silicon layer 44 is formed, crystalline defects of the semiconductor device are decreased and electrical field concentrations are restricted as well as stress because the corners of the trench 42 are rounded.

[0118] As mentioned above, the corners of the trench 42 are rounded after the trench 42 is formed in the silicon substrate 41. Therefore, the stress that would otherwise be concentrated at the bottom portion of the trench 42 is relaxed based on a shape of the trench 42. As a result, a semiconductor device including the three-layered configuration having a first conductive layer/a second conductive layer/a first conductive layer formed in a trench can prevent the second conductive layer from being too thin.

[0119] (Sixth Embodiment)

[0120] The manufacturing process of a semiconductor device of a sixth embodiment will now be described with reference to FIGS. 11, 12. In the sixth embodiment, portions of the manufacturing process different from the first embodiment will be primarily are described.

[0121] As shown in FIG. 11A, a trench 52 is formed in a predetermined region of a silicon substrate 51 formed of N type single crystal. A silicon oxide layer naturally formed on the silicon substrate 51, an etching mask and a reaction product due to the trench etching are then removed by hydrofluoric acid (HF).

[0122] As shown in FIG. 11B, the silicon substrate 51 is inserted in a heat furnace and is heated by an annealing treatment to round corners of a bottom portion and an opening portion of the trench 52. As shown in FIG. 11C, an N silicon layer 53a is then formed on the silicon substrate 51 including the trench 52 by epitaxial growth.

[0123] As shown in FIG. 11D, a part of the silicon layer 53a is removed by etching based on vapor phase etching effect of hydrogen chloride (HCl) or a halogenated compound with an atmospheric gas including HCl or a halogenated compound. As a result, because a portion of the N silicon layer 53a located on the opening portion of the trench 52 is deeply removed, side walls of the trench 52 are tapered.

[0124] Successively, as shown in FIG. 12A, an N type layer 53b is formed on the silicon substrate 51 including the trench 52 by eptaxial growth to cover the N type silicon layer 53a. As shown in FIG. 12B, a P type silicon layer 54 is then formed on the silicon substrate 52 including the trench 52 by eptaxial growth to cover the N type silicon layer 53b.

[0125] Further, as shown in FIG. 12C, an N type silicon layer 55 is formed on the silicon substrate 51 including the trench 52 by eptaxial growth to cover the P type silicon layer 54. A heat treatment is performed on the silicon substrate 51 to decrease voids formed in the trench 52. Surfaces of the respective layers 53a, 53b, 54 and 55 are flattened.

[0126] In the sixth embodiment, a shape of the trench 52 is changed during the aforementioned process so that stress that would otherwise be concentrated at the bottom portion of the trench 52 is relaxed based on a shape of the trench 52. In addition, the shape of the trench 52 is further changed during a second process after the part of the N type silicon layer 53b is etched as illustrated in FIG. 11D.

[0127] Specifically, in the first process, corners of the trench 52 are rounded by isotropic etching using, for example, nitric-fluoric acid or CDE after the trench 52 is formed by etching illustrated in FIG. 11A. The corners of the trench 52 can alternatively be rounded by removing a thermal oxide layer after a surface of the silicon substrate 51 including inside walls of the trench 52 is sacrificially oxidized.

[0128] In the second process, to change the shape of the corners of the trench 52 (the N type silicon layer 53a), the silicon substrate 51 is etched by isotropic etching using, for example, nitric-fluoric acid or CDE after the silicon substrate 51 is etched by HCl or the like illustrated in FIG. 11D. In the second process, the corners of the trench 52 can alternatively be rounded by removing a thermal oxide layer after a surface of the silicon substrate 51 including inside walls of the trench 52 is sacrificially oxidized. The corners of the trench 52 can alternatively be rounded by an annealing treatment (heat treatment).

[0129] As mentioned above, the corners of the trench 52 are rounded after the trench 52 is formed in the silicon substrate 51 and after the part of the N type silicon layer 53a is etched. Therefore, the stress that would otherwise be concentrated at the bottom portion of the trench 52 is relaxed based on a shape of the trench 52. As a result, a semiconductor device including the three-layered configuration having a first conductive layer/a second conductive layer/a first conductive layer formed in a trench can prevent the second conductive layer from being too thin.

[0130] (Seventh Embodiment)

[0131] The manufacturing process of a semiconductor device of a seventh embodiment will now be described with reference to FIGS. 13, 14. In the seventh embodiment, portions of the manufacturing process different from the first embodiment will be primarily described.

[0132] As shown in FIG. 13A, a trench 62 is formed in a predetermined region of a silicon substrate 61 formed of N type single crystal so that an aspect ratio of the trench 62, which is defined as a ratio A/B, where A is a depth of the trench 62 and B is a width of the trench 62, is low. Specifically, the aspect ratio of the trench 62 is set to a value between 0.2 and 1.6. According to the seventh embodiment, a P type silicon layer 64 formed in the trench 62 illustrated in FIG. 14C can be prevented from transforming into an N type silicon layer and can be formed with a predetermined thickness.

[0133] A silicon oxide layer naturally formed on the silicon substrate 61, an etching mask and a reaction product due to the trench etching are then removed by hydrofluoric acid (HF).

[0134] As shown in FIG. 13B, the silicon substrate 61 is inserted in a heat furnace and is heated by an annealing treatment to round corners of a bottom portion and an opening portion of the trench 62. As shown in FIG. 13C, an N silicon layer 63a is then formed on the silicon substrate 61 including the trench 62 by epitaxial growth.

[0135] As shown in FIG. 13D, a part of the silicon layer 63a is removed by etching based on vapor phase etching effect of hydrogen chloride (HCl) or a halogenated compound with an atmospheric gas including HCl or a halogenated compound. As a result, because a portion of the N silicon layer 63a located on the opening portion of the trench 62 is deeply removed, side walls of the trench 62 are tapered.

[0136] Successively, as shown in FIG. 14A, an N type layer 63b is formed onto the silicon substrate 61 including the trench 62 by eptaxial growth to cover the N type silicon layer 63a. As shown in FIG. 14B, a P type silicon layer 64 is then formed onto the silicon substrate 62 including the trench 62 by eptaxial growth to cover the N type silicon layer 63b.

[0137] Further, as shown in FIG. 14C, an N type silicon layer 65 is formed onto the silicon substrate 61 including the trench 62 by eptaxial growth to cover the P type silicon layer 64. A heat treatment is performed on the silicon substrate 61 to decrease voids formed in the trench 62. Surfaces of the respective layers 63a, 63b, 64 and 65 are flattened.

[0138] In the sixth embodiment, the aspect ratio of the trench 62 is defined to be low. The lower the aspect ratio of the trench 62 is defined, the fewer the P type silicon layer 64 is transformed in N type at the bottom portion of the trench 62.

[0139] FIGS. 20A to 20C show cross sectional views showing SCM analysis of semiconductor devices in which depths of the trench 62 are defined in 4.2 m, 10.5 m and 19.5 m, respectively. FIG. 21 shows a relationship between a depth of the trench 62 and a thickness of portions of the P type silicon layer 64 located at the bottom portion and the side walls of the trench 62.

[0140] As shown in FIG. 21, when the aspect ratio of the trench 62 is set to more than 1, the P type silicon layer 64 is exponentially transformed to an N type silicon layer at the bottom portion of the trench 62, and a change of a thickness t2 thereof exponentially decreases. Therefore, the aspect ratio of the trench 62 is preferably set to more than 1.

[0141] From a practical standpoint, in order to electrically isolate a source region and a drain region, a portion of the P type silicon layer 62 at which a channel is formed is set to at least 0.2 m. Therefore, the depth of the trench 62 is preferably set to 30 m or less. That is, the aspect ratio of the trench 62 is set to 1.6 (30 m/19 m).

[0142] Incidentally, an integration of the semiconductor device is restricted in a direction perpendicular to the silicon substrate 61 due to the low aspect ratio of the trench 62. Therefore, characteristics of a three-dimensional power MOSFET are also restricted. However, if the three-dimension power MOSFET is formed by a simple ion diffusion process from a surface of the silicon substrate 61, the aspect ratio of the trench 62 is basically at most 0.5 because ions are isotropically diffused. Substantially, criteria of stable machining, heat treatment period and the like restrict the aspect ratio to be at most 0.2. Therefore, the three-dimensional power MOSFET formed by the manufacturing process of the seventh embodiment is superior to that formed by simple ion diffusion processes even if the aspect ratio of the trench 62 is set to a value between 0.2 and 1.6.

[0143] According to the seventh embodiment, the semiconductor device can be completed without additional manufacturing equipment with respect to the related art semiconductor device disclosed in JP-A-2001-274398.

[0144] The trench 62 having an aspect ratio of 1.6 or less is formed in the silicon substrate 61. As a result, a semiconductor device including the three-layered configuration having a first conductive layer/a second conductive layer/a first conductive layer formed into a trench can prevent the second conductive layer from being too thin.

[0145] (Modification)

[0146] In the fourth embodiment, the P type silicon layer 34 can alternatively be formed by additional epitaxial growth. That is, after a part of the P type silicon layer 34 is formed by vapor diffusion, another part of the P type silicon layer 34 can be formed by epitaxial growth. In this case, the P type layer is formed by vapor diffusion and epitaxial growth, both of which are preferably performed in an identical vacuum chamber.

[0147] In the fourth embodiment, P type doping impurities including, for example, boron (B) or a composition including the P type doping impurities can alternatively be adopted to a source of the vapor diffusion instead of the B₂H₆ gas. When the conductivity type of the respective components 31-35 is reversed, an N type silicon layer corresponding to the P type silicon layer 34 of the fourth embodiment can be formed with N type doping impurities or with a composition including the N type doping impurities such as PH₃ or AsH₃. In other words, an impurity layer formed by vapor diffusion can be formed by introducing doping impurities or a composition including doping impurities into an atmospheric gas.

[0148] In the fifth embodiment, the corners of the trench 42 can alternatively be rounded by isotropic etching or by removing a thermal oxide layer after a surface of the silicon substrate 41 including inside walls of the trench 42 is sacrificially oxidized.

[0149] While the above description is of the preferred embodiments of the present invention, it should be appreciated that the invention may be modified, altered, or varied without deviating from the scope and fair meaning of the following claims.