Multi-phase oscillator and multi-phase oscillation signal generation method

[0001] This application claims the priority benefit of Taiwan application serial no. 91100850, filed Jan. 21, 2002.

[0002] 1. Field of Invention

[0003] The present invention generally relates to an oscillator and an oscillation signal generation method, and more particularly, to a multi-phase oscillator and a multi-phase oscillation signal generation method.

[0004] 2. Description of Related Art

[0005] The oscillator plays a very important role in both communication systems and digital circuits now. In digital circuits, the oscillator provides multi-phase clock signals to the system. In communication systems, the multi-phase oscillation output of the oscillator can be used as a carrier in the modulation operation or as a local oscillator in the demodulation operation.

[0006] Generally speaking, there are two major methods to design the oscillator: (1) using the LC charge-discharge circuit that consists of an inductor (L) and a capacitor (C); (2) connecting an odd number of the inverters in serial to generate an oscillation signal by the contribution of the time delay in between the inverters. Recently, along with the great progress of the CMOS manufacture process, and also considering of the system integrity, the design method that includes the inductor elements is seldom used because the Q value cannot be increased and a great area is required for the on-chip inductor. The researches of the multi-phase output method mostly concentrate on the study of the outputs have a 180 or a 90 phase difference.

[0007] The configuration having a 180 phase difference is shown in FIG. 1, FIG. 1 schematically shows a circuit diagram of a conventional regeneration ring oscillator (please refer to T. Kwasniewski et al., Inductorless oscillator design for personal communication device a 1.2 um CMOS process case study, Proc. of IEEE Custom Integrated Circuit Conference, pp 327-330, 1995 and M. Thamsirianunt and T. A. Kwasniewski, CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications, IEEE journal of Solid-State Circuits, vol. 32, no. 10, pp. 1511-1524, October 1997.). Each of the inverter latches using a two-stage regenerator 102, 104, is connected with the ring oscillator that consists of two sets of the three-stage inverters (such as 106, 108, 110 and 112, 114, 116 as shown in FIG. 1) that are coupled each other to generate the oscillation signals. The two-stage regenerators 102 and 104 of the present configuration provide the energy to the ring oscillator that consists of the three-stage inverters that consists of the inverters connected in series, so that the oscillator 100 obtains a lower phase noise. However, the more elements it uses result in greater time delay and larger power consumption.

[0008] The first configuration having a 90 phase difference is shown in FIG. 2, FIG. 2 schematically shows a circuit diagram of a conventional RC-CR oscillator having a 90 phase difference (please refer to Qiuting Huang, The design of a direct-conversion paging receiver quadrature converter for wrist watch application electronics, Proc. of IEEE International Conference on Circuits and Systems, vol.3, pp 29-32,1998.). It is a system configuration consists of a single resistor capacitor-capacitor resistor (RC-CR). Although the RC-CR configuration can achieve the function of outputting a 90 phase difference signal, since each of the RC-CR in the configuration is coupled to the input nodes of the differential configuration, the distortion is easily occurred due to the mismatch of the input nodes.

[0009] The second configuration having a 90 phase difference is shown in FIG. 3. FIG. 3 schematically shows a circuit diagram of a conventional ring oscillator that generates a 90 phase difference (please refer to Chung-Yu Wu and Hong-Sing Kao, A 1.8 GHz CMOS quadrature voltage-controlled oscillator (VCO) using the constant-current LC ring oscillator structure, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems vol. 4, pp. 378-381,1998.). It utilizes a two-stage LC tank that consists of an inductor and a capacitor connected in serial and the negative resistance circuit to obtain the oscillation signals on the nodes I and Q.

[0010] The third configuration having a 90 phase difference is shown in FIG. 4. FIG. 4 schematically shows a circuit diagram of a conventional ring oscillator that consists of a six-stage differential amplifier including six differential amplifiers connected in serial (please refer to Y. Sugimoto and T. Ueno, The design of 1 V, 1 GHz CMOS VCO circuit with in-phase and quadrature-phase output, Proceedings of IEEE International Symposium on Circuits and Systems vol.1, pp. 269-272, 1997.). It utilizes three currents that are generated by the first, the third and the fifth differential amplifiers to generate the outputs having a 90 phase difference, and to obtain the expected oscillation signals on the nodes I and Q. However, the present method easily results in an oscillation signal error due to the mismatch of the three output currents that have a 120 phase difference.

[0011] FIG. 5 schematically shows a circuit diagram of a conventional ring oscillator that consists of a four-stage differential amplifier (please refer to U.S. Pat. No. 5,635,880). It utilizes the microwave theory of the differential amplifier to appropriately adjust the circuit bias. In this circuit, the Miller effect is used to constitute a RC loop to configure a ring oscillator circuit that consists of a four-stage differential amplifier to generate multi-phase oscillation signals.

[0012] FIG. 6 schematically shows a circuit diagram of a conventional ring oscillator that consists of branch feedback loops (please refer to U.S. Pat. No. 6,075,419). The proper branch feedback loops are added to the ring oscillator consisting of the inverters that are connected in serial, so that the output signals are evenly feedback applied to each input node of the serially connected oscillator to generate the multi-phase oscillator signals.

[0013] FIG. 7 schematically shows a circuit diagram of the conventional injection phase locked oscillation signal generator (please refer to U.S. Pat. No. 6,188,291). It uses two or more than two serially connected ring oscillators having the same time period to generate and output the signals. The total phase 360 is formed by the serially connected ring oscillator that generates a phase difference having the same degree. It is based on the theory that a set of the oscillation signals is injected to lock another set of the signals, so that the expected phase difference can be obtained efficiently. Moreover, the present configuration also reduces the phase noise by adding a periodic low noise oscillation signal source 702.

[0014] The cases shown in FIG. 5 through FIG. 7 mentioned above are all the multi-phase oscillators. However, they can only provide the oscillation signals with limited varieties of the phase differences.

[0015] Therefore, the present invention provides a multi-phase oscillator to output the oscillation signals having a phase difference of any degree. Fewer elements are used to save the power consumption. Furthermore, the output mismatch is avoided, so that the precision of the phase difference of the output oscillation signal can be relatively increased.

[0016] The present invention provides a multi-phase oscillator, comprising a delay loop buffer and a plurality of oscillators. The delay loop buffer has N units of the delay unit, the output node of the first delay unit is electrically coupled to the input node of the second delay unit, the output node of the second delay unit is electrically coupled to the input node of the third delay unit, . . . , the output node of the N^th delay unit is electrically coupled to the input node of the first delay unit. Moreover, since the N units of the delay unit constitute a 360 phase shift mesh configuration, the time delay of each delay unit has equal size and is divided from a 360 phase. So that the oscillation signals generated by the oscillators have a phase difference that is divided from a 360 phase and is not variable. Furthermore, the plural oscillators provide the plural oscillation signals to the delay loop buffer, the N units of the delay unit are used to evenly divide a 360 phase, so that the oscillation signals generated by the oscillators have a phase difference that is divided from a 360 phase and is not variable.

[0017] The present invention further provides an oscillator having a 180 phase difference. The oscillator comprises a first oscillation signal output terminal and a second oscillation signal output node and the oscillator is composed of a plurality of inverters and a regenerator. The output node of the first inverter is electrically coupled to the first oscillation signal output node, the input node of the second inverter is electrically coupled to the second oscillation signal output node; the output node of the second inverter is electrically coupled to the input node of the first inverter; the input node of the third inverter is electrically jointly coupled to the output node of the first inverter and the first oscillation signal output node; the input node of the fourth inverter is electrically coupled to the output node of the third inverter, the output node of the fourth inverter is electrically jointly coupled to the input node of the second inverter and the second oscillation signal output node; the first electrode of the regenerator is electrically jointly coupled to the output node of the first inverter, the input node of the third inverter and the first oscillation signal output node; the second electrode of the regenerator is jointly coupled to the input node of the second inverter, the output node of the fourth inverter and the second oscillation signal output node; the regenerator is used to generate a 180 phase difference on its both electrodes. Wherein, the regenerator further comprises a fifth inverter and a sixth inverter, the input node of the fifth inverter is electrically coupled to the first oscillation signal output node, the output node of the fifth inverter is electrically coupled to the second oscillation signal output node; the input node of the sixth inverter is electrically jointly coupled to the output node of the fifth inverter and the second oscillation signal output node, the output node of the sixth inverter is electrically jointly coupled to the input node of the fifth inverter and the first oscillation signal output node.

[0018] Moreover, the present invention further provides a multi-phase oscillation signal generation method. The method evenly divides a fixed phase into multiple corresponding equal size portions by using plural delay times that have the same length of time. Afterwards, the multiple independent oscillation sources respectively provide the driving signal to each equal size portion.

[0019] In an embodiment of the present invention, each oscillation source must provide a driving signals to more than two equal size portions simultaneously. Wherein, the driving signal output from any of the oscillation sources can be generated by an oscillator or multiple oscillators in a multi-level structure. In the other case, as for the other embodiment of the present invention, the driving signal received by any equal size portion is generated by a hierarchical level configuration. In this level configuration, the most upper level oscillation source provides the oscillation signals to the equal size portions. Furthermore, the upper level oscillation source is driven by the plural lower-level oscillation sources simultaneously.

[0020] Therefore, the multi-phase oscillator provided by the present invention is able to output the oscillation signals having a phase difference of any degree. Fewer elements are used to save the power consumption. Furthermore, the output mismatch is avoided, so that the precision of the phase difference of the output oscillation signals can be relatively increased.

[0021] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention. In the drawings,

[0022] FIG. 1 schematically shows a circuit diagram of the conventional regeneration ring oscillator;

[0023] FIG. 2 schematically shows a circuit diagram of the conventional RC-CR oscillator having a 90 phase difference;

[0024] FIG. 3 schematically shows a circuit diagram that uses the conventional ring oscillator to generate signals having a 90 phase difference;

[0025] FIG. 4 schematically shows a circuit diagram of the conventional circular oscillator that includes a six-stage differential amplifier that consists of six differential amplifiers connected in serial;

[0026] FIG. 5 schematically shows a circuit diagram of the conventional ring oscillator that consists of a four-stage differential amplifier;

[0027] FIG. 6 schematically shows a circuit diagram of the conventional ring oscillator that consists of a branch feedback loops;

[0028] FIG. 7 schematically shows a circuit diagram of the conventional injection phase locked oscillation signal generator;

[0029] FIG. 8 schematically shows a sketch map of the multi-phase oscillator of the present invention;

[0030] FIG. 9A schematically shows a sketch map of the configuration of a preferred embodiment of the multi-phase oscillator driven by the oscillation signals having multiple phase differences according to the present invention;

[0031] FIG. 9B schematically shows a sketch map of the configuration of another preferred embodiment of the multi-phase oscillator driven by the oscillation signals having multiple phase differences according to the present invention;

[0032] FIG. 9C schematically shows a sketch map of the configuration of another preferred embodiment of the multi-phase oscillator driven by the oscillation signals having multiple phase differences according to the present invention;

[0033] FIG. 10 schematically shows a sketch map of the multi-phase oscillator driven by the oscillation signals having a 180 phase difference according to the present invention;

[0034] FIG. 11 schematically shows a circuit diagram of the multi-phase oscillator that consists of a 180 phase difference oscillator and a delay loop buffer;

[0035] FIG. 12A schematically shows a dual-port circuit diagram of the regenerator current configuration;

[0036] FIG. 12B schematically shows a two-stage feed-feeding block diagram of the regenerator;

[0037] FIG. 12C schematically shows an equivalent circuit diagram of FIG. 12B;

[0038] FIG. 12D schematically shows a small signal equivalent circuit diagram of FIG. 12C;

[0039] FIG. 13A schematically shows the simulation result of the oscillator driven by a single phase oscillation signals;

[0040] FIG. 13B schematically shows the simulation result of the oscillator driven by the two-phase oscillation signals having a 180 phase difference;

[0041] FIG. 14 schematically shows the measured waveforms of the oscillator having a 180 phase difference from the manufacture process of TSMC 0.35 um CMOS;

[0042] FIG. 15 schematically shows the measured waveforms of the oscillator having a 90 phase difference from the manufacture process of TSMC 0.35 um CMOS;

[0043] FIG. 16 schematically shows the measured waveforms of the oscillator having a 180 phase difference from the manufacture process of UMC 0.5 um CMOS;

[0044] FIG. 17 schematically shows the measured waveforms of the oscillator having a 90 phase difference from the manufacture process of UMC 0.5 um CMOS.

[0045] Please refer to FIG. 8, FIG. 8 schematically shows a sketch map of the multi-phase oscillator of the present invention. In FIG. 8, the multi-phase oscillator 800 comprises a N-level delay loop buffer 808 and N single-phase oscillators (such as 802, 804, 806 shown in FIG. 8). The delay loop buffer 808 that has N-level RC time constants, is able to generate the phase difference in between the oscillation signals, and to constitute a mesh configuration having a 360 phase shift via the N units of the delay unit (not shown in the diagram) loop that are connected in serial inside the delay loop buffer 808. Since each delay unit has the same length of the delay time, it means each of the two contiguous delay units has a phase difference that is 360/N and is not variable. The oscillation signals (such as T₁, T_N/21, T_N shown in FIG. 8) generated by the N units of the oscillator (such as 802, 804, 806 shown in FIG. 8) are input into the delay loop buffer 808. When the whole circuit comes to a steady state, the oscillation signals generated by the N units of the oscillator have a fixed phase difference on each other. Moreover, this phase difference is the same as the phase difference formed by the delay loop buffer 808, so that the function of outputting the multi-phase oscillation signal can be achieved.

[0046] The present invention further provides a configuration that is driven by the oscillation signals having more phases, FIG. 9A schematically shows a sketch map of the configuration of the multi-phase oscillator driven by the oscillation signals having multiple phase differences according to the present invention. The oscillator 902, 904 that have a precise 360/M phase difference are electrically coupled to the N-level delay loop buffer 808, each oscillator 902,904 has M units of the oscillation signal output, and the outputs of the oscillator 902 are electrically coupled to the 1^st, the (1N/M)^th, . . . ,the 1N(M1)/M delay unit by the T_j, T_1N/M, T_1N)M1)/M driving signal respectively. Since each position with interva lof N/M is precisely set to have a 360/M phase difference, number of the oscillators to trigger the delay loop buffer 808 is reduced from the original N to N/M. Therefore, the time needed to reach the steady state for the whole circuit is reduced comparing with the signal triggering scheme. The design also successfully enhances the performance of the multi-phase oscillator. Consequently, the configuration of FIG. 9 can be extended continuously to generate and output the oscillation signals having more phases.

[0047] Moreover, the embodiment of the present invention is further described via FIG. 8, FIG. 9A and FIG. 9B herein. First, as shown in FIG. 8, the N-level delay loop buffer uses a phase difference value as the basis to divide a specific fixed phase (such as 360 shown in these two diagrams) into N portions. Then, in the present embodiment, the output of each buffer (i.e. each equal size portion) is in charged by each oscillator. In other words, in the present embodiment, the oscillation signal output from each equal size portion is provided by an oscillator (one of the oscillators from 802 to 806).

[0048] However, in another embodiment such as the one shown in FIG. 9A, the situation is not as simple as this. In FIG. 9A, similarly, the N-level delay loop buffer uses a phase difference value as the basis to divide a specific fixed phase (such as 360 shown in FIG. 9A) into N portions. Since the oscillation source (oscillators 902-904) may generate M units of the oscillation signal, the difference between these two embodiments is that there are only NIM oscillators in the present embodiment. Therefore, as shown in FIG. 9A, the M-phase oscillator is used as the oscillation source in the present embodiment. However, this is not the only method we can use. As shown in FIG. 9B, the driving signal provided to the N-level delay loop buffer 808 are generated by a level configuration 910. In the level configuration 910, the most upper level oscillation sources 912-914 are still in charge of providing the driving signals to the N-level delay loop buffer 808. However, the driving signal source of each oscillation source is generated by the multiple lower level oscillation sources. For example, in FIG. 9B, the lower level oscillation sources 9000-9010 provide the driving signals to the upper level oscillation source 912, and the lower-level oscillation sources 9090-9100 also provide the driving signals to the corresponding upper level oscillation source 914. Of course, those who are skilled in the related art should understand the multi-level configuration is not limited by the two-level as shown in FIG. 9B, it can be any number of the levels such as the one shown in FIG. 9C. The spirit is as long as the oscillation signals output from the upper level oscillation source driven by the multiple lower level oscillation sources. That is, the driving signals of the upper level oscillation source 912 (it is the most upper level oscillation source in the present embodiment) are provided by the lower level oscillation sources 920-922, and the driving signals of the oscillation source 914 are provided by the lower-level oscillation sources 924-926. With consideration of the lower-level oscillation sources 930-938, the oscillation source 920 is the corresponding upper-level oscillation source. Therefore, the driving signal input by the oscillation source 920 are provided by the oscillation sources 930-938. Similarly, the driving signal input by the oscillation source 926 are provided by the oscillation sources 950-958.

[0049] In order to understand the performance of the multi-phase oscillator more easily, the oscillator having a 180 phase difference is exemplified herein, its output oscillation signals are used as the driving signals to drive the N-level delay loop buffer 808. FIG. 10 schematically shows a sketch map of the multi-phase oscillator driven by the oscillation signals having a 180 phase difference according to the present invention. As shown in FIG. 10, the oscillators 1002, 1004 that have output signals with a precise 180 phase difference are electrically coupled to the N-level delay loop buffer 808. Each oscillator 1002,1004 has two sets of the oscillation signal outputs, where the 0 output of the oscillator 1002 is electrically coupled to the first delay unit (not shown in the diagram) to be a driving signal T₁, the 180 output of the oscillator 1002 is electrically coupled to the (1N/2) delay unit (not shown in the diagram) to be a driving signal T_1N/2. Any two positions in the entire circuit with the interval of N/2 delay units are precisely set to have a 180 phase difference. The number of the oscillators required in the delay loop buffer 808 that needs to be adjusted is reduced to a half of the original number. Therefore, the time needed to reach the steady state for the entire circuit is reduced comparing with the single phase signal driving method.

[0050] FIG. 11 schematically shows a circuit diagram of the multi-phase oscillator that consists of a 180 phase differences oscillator and a delay loop buffer. In FIG. 11, the N-level delay loop buffer 808 has N units of the delay unit 1102, 1104, 1106, 1108. The output node OPI of the delay units 1102 is electrically coupled to the input node IP2 of the delay unit 1104, the output node OP2 of the delay unit 1104 is electrically coupled to the input node IP3 of the next delay unit (not shown in the diagram), the output node OPN of the delay unit 1108 is electrically coupled to the input node IP1 of the delay unit 1102. The N units of the delay units 1102, 1104, 1106, 1108 constitute a mesh configuration having a 360 phase shift. Every delay unit has the same delay time and phase shift. The expected neighboring oscillation signals having a 360/N phase difference can be obtained. Each delay unit is composed of a PMOS and a NMOS. The delay unit 1102 is exemplified herein, the source of the PMOS 1110 is electrically coupled to the power supply VCC, the gate of the PMOS 1110 is coupled to the ground, and the drain of the PMOS 1110 is electrically coupled to the output node OPI of the delay unit 1102; the drain of the NMOS 1112 is electrically jointly coupled to the drain of the PMOS 1110 and the output node OP1 of the delay unit 1102, the gate of the NMOS 1112 is electrically coupled to the input node IP1 of the delay unit 1102, the source of the NMOS 1112 is electrically coupled to the oscillation signal T₁ output node of the oscillator 1120. The connection layouts of the other delay units such as 1104, 1106, 1108 are similar to that of the layout of the delay unit 1102.

[0051] In FIG. 11, the plural NMOS of the Mn_11112Mn_N 1114 that are in the delay unit 1102, 1104, 1106, 1108 and connected to the oscillator 1120, 1122 are used to adjust the operation of the oscillator 1120, 1122. The NMOS itself is not in the loops of oscillators, so that the output frequencies of the oscillators 1120, 1122 are not impacted. Therefore, there is a better isolation effect between the oscillation signal generation and the phase shift control, so that the quality of the oscillation signals can be improved.

[0052] In FIG. 11, the oscillator 120, 1122 provides the oscillation signals to the delay loop buffer 808. The N units of the delay unit 1102, 1104,1106,1108 are used to evenly divide a 360 phase, so that the neighboring oscillation signals generated by the oscillator 1120,1122 have the same phase difference. The oscillator 1120, 1122 uses the new circuit configuration that is composed of six inverters. The oscillator 1120 is exemplified herein, the output node of the inverter 124 is electrically coupled to the oscillation signal T₁ output node of the oscillator 1120; the input node of the inverter 1126 is electrically coupled to the oscillation signal T_1N/2 output node of the oscillator 1120; the output node of the inverter 1126 is electrically coupled to the input node of the inverter 1124; the input node of the inverter 1128 is electrically jointly coupled to the output node of the inverter 1124 and the oscillation signal T₁ output node of the oscillator 1120; the input node of the inverter 1130 is electrically coupled to the output node of the inverter 1128, the output node of the inverter 1130 is electrically jointly coupled to the input node of the inverter 1126 and the oscillation signal T_1N/2 output node of the oscillator 1120; the first electrode of the regenerator 1136 is electrically jointly coupled to the output node of the inverter 1124, the input node of the inverter 1128 and the oscillation signal T₁ output node of the oscillator 1120; the second electrode of the regenerator 1136 is electrically jointly coupled to the input node of the inverter 1126, the output node of the inverter 1130 and the oscillation signal T_1N/2 output node of the oscillator 1120; the regenerator 1136 is used to generate a 180 phase difference on its both electrodes. Wherein, the regenerator 1136 is composed of an inverter 1132 and an inverter 1134. The input node of the inverter 1132 is electrically coupled to the oscillation signal T₁ output node of the oscillator 1120, the output node of the inverter 1132 is electrically coupled to the oscillation signal T_1N2 output node of the oscillator 1120; the input node of the inverter 1134 is electrically jointly coupled to the output node of the inverter 1132 and the oscillation signal T_1N/2 output node of the oscillator 1120, the output node of the inverter 1134 is electrically jointly coupled to the input node of the inverter 1132 and the oscillation signal T₁ output node of the oscillator 1120. The connection layout of the other oscillator such as oscillator 1122 is similar to the layout of the oscillator 1120.

[0053] As for using the regenerator to constitute an oscillator having a 180 phase difference, in comparison with the oscillator in FIG. 1, the oscillator 1120 shown in FIG. 11 uses fewer elements and outputs higher frequency oscillation signals. The regenerator 1136 uses the equivalent capacitors (not shown in the diagram) of the transistors inside the inverter 1132, 134 and two adjustable trans-conductors (not shown in the diagram) that have the same specification and are jointly coupled together to constitute a feedback configuration. FIG. 12A schematically shows a dual-port circuit diagram of the regenerator current configuration. The regenerator 1136 works as a gyroscope, therefore, the transition matrix of the regenerator 1136 can be represented as following equation: $\left[\begin{array}{c}{I}_x\\ I_y\end{array}\right]=\left[\begin{array}{cc}0& -\mathrm{gm}\\ -\mathrm{gm}& 0\end{array}\right]\left[\begin{array}{c}{V}_x\\ V_y\end{array}\right].$

[0054] In the configuration of the new fashion 180 phase difference oscillator, the delay time elements (not shown in the diagram) of the inverter 1132, 1134 are used to constitute a two-stage self-feeding circuit as shown in FIG. 12B. FIG. 12C schematically shows an equivalent circuit diagram of FIG. 12B. From FIG. 12B and FIG. 12C, the regenerator 1136 can be treated as a two-stage ring unit having the equivalent capacitor C 1202 and 1204. FIG. 12D schematically shows a small signal equivalent circuit diagram of FIG. 12C. The open loop transfer function and the gain equation of the regenerator 1136 can be obtained from FIG. 12D, as follows: $T\left(j\right)={\left(\frac{-\mathrm{gmR}}{1+j\mathrm{RC}}\right)}^2$ $H\left(j\right)=\frac{\frac{-\mathrm{gmR}}{1+j\mathrm{RC}}}{1-{\left(\begin{array}{c}-\mathrm{gmR}\\ 1+j\mathrm{RC}\end{array}\right)}^2}$

[0055] From the equations mentioned above, the phase of the circuit proposed by FIG. 12A through FIG. 1 2D can be obtained as following equations:

[0056] $\mathrm{Phase}\left[{\left(\frac{-\mathrm{gmR}}{1+j\mathrm{RC}}\right)}^2\right]=2kk\mathrm{is}a\mathrm{positive}\mathrm{integer}$

[0057] The output oscillation signals having different phase are used as the oscillation signal sources to address multiple-phase generation unit that is the delay loop buffer. FIG. 13A schematically shows the simulation result of the 45 phase generation unit, the current waveform is changed from a great current variation when the output oscillation signal dose not come to a stable condition when the output oscillation signal comes to the steady state. FIG. 13B schematically shows the simulation result of the 45 phase generation unit driven by the two-phase oscillation signals in which each pair has a 180 phase difference. FIG. 13B schematically shows the variation of the current waveform from the initial state to the steady state when each pair of the signals having a 180 phase difference are input into the phase generation unit. From FIG. 13A and FIG. 13B, if the oscillation signals having a stable multiple phases can be used as. the driving signals to address the phase generation unit, the time needed for the oscillator to come to a steady state can be reduced.

[0058] VLSI technology is used herein to implement the configuration of the present invention where the TSMC 0.35 um 1P4M and the UMC 0.5 urn 2P2M CMOS are respectively applied in design, manufacture, and physical measurement, so that all the functionalities can be tested and proved. FIG. 14 schematically shows the output waveform of the oscillator having a 180 phase difference from the manufacture process of TSMC 0.35 um CMOS. When the supply voltage is 2.0V, the measured waveform frequency is 509 MHz. From FIG. 14, the phase difference of the output waveforms is 180 exactly. The measured waveforms of the proposed 90 phase difference oscillator are as shown in FIG. 15. FIG. 15 schematically shows the output waveforms of the oscillator having a 90 phase difference from the manufacture process of TSMC 0.35 um CMOS. As shown in the diagram, the 614 MHz output frequency of the designed circuit can be obtained. Therefore, the oscillator can precisely provide the 90 phase-difference oscillation signal outputs.

[0059] As for the manufacture process of the UMC 0.5 um 2P2M CMOS, FIG. 16 schematically shows the measurement result of the oscillator having a 180 phase difference from the manufacture process of UMC 0.5 urn CMOS. When the supply voltage is 2.0V, the measured output waveforms are as shown in FIG. 16, the operation frequency is 504 MHz, and the output waveforms of the oscillator exactly have a 180 phase difference. FIG. 17 schematically shows the measurement result of the oscillator having a 90 phase difference from the manufacture process of UMC 0.5 um CMOS. When the supply voltage is 2.0V, the frequency of the oscillation signal generated by the oscillator is 415 MHz.

[0060] From the simulation result and the measurement result mentioned above, the device provided by the present invention can achieve the function of outputting the multi-phase oscillation signals. Along with the usage of the more advanced semiconductor manufacture process, the frequency of the oscillation signal output from the present device can be increased, thus it is suitable for the variety of the radio frequency receiving systems to enhance the operating performance.

[0061] Therefore, the advantage of the present invention is to provide a new fashion 180 phase difference oscillator. It uses fewer elements, provides higher frequency and has less power consumption.

[0062] The other advantage of the present invention is to change the number of levels of the delay loop buffer to output the signal with any degree of the phase difference, so that the oscillator can generate and output the multi-phase oscillation signals.

[0063] The further advantage of the present invention is that there is a better isolation effect between the delay loop buffer and the oscillator to avoid the output mismatch, so that the quality of the oscillation signal output can be enhanced. Furthermore, the oscillator and the multiple-phase difference generation unit are totally independent, so that the oscillation frequency can be effectively maintained.

[0064] Although the invention has been described with reference to a particular embodiment thereof, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed description.