Frequency modulated self-oscillating switching power supply

[0001] 1. Technical Field

[0002] This invention relates generally to a power supply, more particularly, to a self-oscillating switching power supply (SOP) adapted to supply DC current to wide range of loads.

[0003] 2. Related Art

[0004] A switch-mode power supply (SMPS) can operate in or between two current-conduction modes, continuous conduction mode (CCM), and discontinuous conduction mode (DCM). By controlling the power switch with a flyback (feedback signal) to monitor the energy (e.g., current) remaining in an inductor coil, a self-oscillating switching power supply (SOP) can operate at the critical-conduction point between the continuous and discontinuous conduction modes, wherein the power supply begins a new switching cycle at the exact point in time when an output-current inductor coil's (e.g., a transformer's secondary coil's) current (i.e., energy) falls to zero (i.e., approaches zero or is zero). A self-oscillating (flyback-driven) switching power supply (SOP) will include an input-current inductor coil and an output-current inductor coil, but may be implemented with or without a transformer. In a transformer-less (i.e., no transformer) SOP, the input-current inductor coil will also be the output-current inductor coil (e.g., a there will be only a single inductor coil for energy input and output).

[0005] FIG. 1A is circuit diagram depicting a typical topology of a transformer (T1)-based self-oscillating (i.e., flyback) switching power supply (SOP) 100 of the related art. The SOP 100 includes a power switch SW1 for interrupting a current I₁ through an input-current inductor coil (e.g., primary winding L1 of transformer T1). The power switch SW1 may be implemented as a metal oxide semiconductor field effect transistor (MOSFET) or a insulated gate bipolar transistor (IGBT), or a mechanical switch, etc, or by any suitable presently know or future electrical current-switching device. The power switch SW1 has two states, an ON state characterized by a low impedance, and an OFF state characterized by a high impedance. The power switch SW1 is generally cyclically turned ON and OFF in a periodic manner, such that the power switch SW1 is ON during a first ON-time period and then OFF during a first OFF-time period, and then ON again during a second ON-time period (t_ON) and then OFF during a second OFF-time period (t_OFF), and so forth. The switching frequency F_SW of the SOP 100 is calculated as the inverse of the sum of the ON-time plus the subsequent OFF-time (i.e., F_SW1/(ON-timeOFF-time). The duty cycle (Q_S) of the SOP 100 is calculated as the ratio of the ON-time to the sum of the ON-time plus the subsequent OFF-time (i.e., Q_SON-time/(ON-timeOFF-time)).

[0006] In general, because there is inductive energy storage in the SOP 100, and a capacitance associated with the GATE terminal of the power switch SW1, a minimum ON-time (t_ONMIN) will be characterized by the characteristics of the power switch SW1 and other characteristics of the SOP 100. During normal operation (e.g., critical conduction mode operation) of the SOP 100, the OFF-time will be characterized by (and equal to) the time it takes for the current (i.e., energy) in an output inductor coil (e.g., a transformer secondary coil L2 and/or transformer auxiliary secondary coil L3) to fall to zero (i.e., to approach zero or to be zero). During any discontinuous conduction mode (DCM) operation of the SOP 100, the OFF-time will be longer than the time it takes for the current (i.e., energy) in an output inductor coil (e.g., a transformer secondary coil L2 and/or transformer auxiliary secondary coil L3) to fall to zero. During any continuous conduction mode (CCM) operation of the SOP 100, the OFF-time will be substantially less than the time it would otherwise take for the current (i.e., energy) in an output inductor coil (e.g., a transformer secondary coil L2 and/or transformer auxiliary secondary coil L3) to fall to zero, and the current will not fall all the way to zero.

[0007] The power switch SW1 is gated (i.e. controlled ON and OFF) by a switch-control signal asserted on the GATE node of the power switch SW1 by a switch-driver circuit, such as the Frequency Clamped Flyback Driver 110. Frequency clamped flyback switch driver 110 can be implemented with an integrated circuit chip manufactured by Motorola Corp. known as an MC33364 critical-conduction mode controller chip (See, e.g., FIG. 1C).

[0008] The power switch SW1 alternately opens and closes, alternately passing and interrupting an input current (I₁) which is driven through the transformer's primary coil L1 by the voltage potential difference (V₁) between a power source input voltage V_IN and power switch SW1. (In most real circuits, the ON resistance of the power switch SW1 will be negligibly small, such that V₁ is approximately equal to voltage V_IN when the power switch SW1 is closed). Power source voltage V_IN may be a fixed DC voltage or a variable DC voltage (e.g., a DC voltage having a ripple due to lack of filtering of a rectified AC). Persons skilled in the art will recognize that V_IN may be provided as a substantially direct current (DC) voltage produced from an alternating current (AC) input voltage (i.e., a line voltage) source via a diode bridge rectifier (not shown) that full-wave rectifies the alternating current and a filter capacitor (not shown) that filters and smooths current pulses received from the bridge rectifier.

[0009] The SOP 100 includes an input-current inductor coil (e.g., primary winding L1) connected in series with a power switch SW1 and between a power source (V_IN) and a reference potential (ground). As is commonly known, closing and opening of the power switch SW1 causes energy to be stored as a magnetic field in the input-current inductor coil (e.g., in the primary winding L1) which is transferred to an output-current inductor coil (e.g, the magnetically coupled secondary winding L2) and thereupon output substantially as an output current (I₂) driven at a secondary voltage V₂ and dissipated through a load associated with an impedance, and/or with a resistance (R_LOADEQ). A very small, (i.e., negligible) amount of the input energy is output as an auxiliary output current (I_AUX) and dissipated through a sensing circuit within or operatively coupled to the switch-driver circuit (e.g, 110). Because the transformer-based SOP 100 operates by transferring energy between the primary and secondary windings L1 and L2, the turns ratio N_T of the windings L1 and L2 may be adjusted to either increase or decrease the output voltage (V_OUT) associated with the power source V_IN, as needed for a particular application. A rectifier diode D1, and a filter capacitor C1 are connected to output-current inductor coil (e.g, secondary winding L2) as shown in FIG. 1A. The rectifier diode D1 rectifies the current pulses (I₂) provided by the output-current inductor coil (e.g, secondary winding L2) and the filter capacitor C2 filters and smooths the rectified current pulses to form a substantially direct current (DC) output voltage V_OUT.

[0010] The transformer T1 includes a primary winding (L1) (connected in series to the power switch SW1), and at least one secondary winding (e.g., L2 and/or L3). A first secondary winding L2 is provided to output at voltage V₂ all, or substantially all, of the energy input to the transformer T1 (e.g., energy input as current I₁ in the primary winding L1 at voltage V₁). The voltages V₁ and V₂ are generally related by the equation V₂N_T*V₁. An auxiliary secondary winding L3 is provided to output, at voltage V_AUX, a very small portion, (i.e., a negligible amount or none) of the energy input to the transformer T1. The voltage V_AUX across the auxiliary secondary winding L3 is related to the voltage across the first secondary winding L2 by the ratio of turns in each of coils L2 and L3 (when the current I₂ is decaying in coil L2). Therefore, voltage V_AUX is a fixed proportion of V₂ (when a current is flowing in coil L2). When the power switch SW1 is OFF (e.g., following an ON-time), and while energy is being dissipated as a decaying (but non-zero) current I₂ in the first secondary winding L2, the voltage V_AUX will be non-zero. The magnitude of the voltage V_AUX will approach zero (or be zero) at the moment that the current I₂ falls to zero. At that moment, during normal (critical conduction mode) operation of the SOP 100, power switch SW1 will be closed, and thereafter, the voltage V_AUX will be affected by the voltage V₁ and the current I₁ across the primary winding L1.

[0011] By using the voltage V_AUX, and/or associated current I_AUX as a feedback (i.e., flyback) signal to the switch-driver circuit (e.g., 110), the SOP 100 can operate in critical conduction mode, wherein the next conduction (i.e., ON-time) of the next cycle is initiated by a Zero Current Detector operatively connected to the auxiliary winding L3. The Zero Current Detector is a circuit for detecting (or anticipating) the occurrence of a zero-current condition in the output-current inductor coil (e.g, secondary winding L2). Various other known alternative methods and circuits for detecting the zero-current condition of the output current I₂ in the output-current inductor (L2) can be substituted in the SOP 100 to sustain critical conduction mode operation.

[0012] As is understood by persons skilled in the art, the conduction (i.e., ON-time) of current (I₁), of each cycle, is terminated when the peak inductor current I₁ reaches a threshold level (I_TH), as performed by circuits known to persons skilled in the art. The threshold level I_TH may be dynamically varied (e.g., for power factor correction) by use of a Multiplier output for comparing to a feedback signal commensurate with the current I₁. The Zero Current Detector within (as shown) or associated with or connected to the switch driver (e.g., 110) may indirectly sense a zero-current condition of current I₂ in the output-current inductor coil (e.g, secondary winding L2) by monitoring an auxiliary voltage V_AUX across a magnetically coupled coil (e.g., auxiliary winding L3).

[0013] FIG. 1B is a timing diagram depicting currents and voltages in the SOP 100 of FIG. 1A while operating for several cycles in critical conduction mode. FIG. 1B illustrates the method of the critical-conduction mode operation of the SOP 100 of FIG. 1A. FIG. 1B shows the general shape of the currents I₁ and I₂ flowing through the coils L1 and L2, and of feedback voltage V_AUX during a few representative cycles. When the power switch (SW1 of FIG. 1A) closes, a voltage V₁ (i.e., V₁ is approximately equal to voltage V_IN) is asserted across coil L1 and current I₁ ramps up (from zero at the end of the previous cycle), until a threshold current magnitude I_TH is reached. During this first ON-time (t_ON1), a magnetic field builds up in the core (e.g., T_CORE) of the input current inductor (e.g., the core of coil L1, which is shared with coils L2 and L3). When the power switch SW1 opens, which begins the OFF-time (t_OFF1), the magnetic field collapses, and, according to Lenz's law, the voltage V₁ across the input-current inductor (L1) reverses. In this case, the current (I₁) has to find some way to continue its flow and begin its decreasefor example, as current I₂ by magnetic coupling through the core T_CORE of transformer T1.

[0014] Time t_AUX is the time required for the current I₂ in the output-current inductor coil L2 to fall to zero, sensed as the voltage V_AUX across the auxiliary secondary coil L3 approaching zero. If the power switch SW1 turns ON again during the ramp-down phase and before the current I₂ reaches zero (i.e., t_OFF is less than t_AUX), then the supply 100 is operating in continuous-conduction mode (CCM). Alternatively, if the energy-storage capability of the input-current inductor coil (e.g., L1) is such that its magnetically coupled current I₁/I₂ dries out to zero during the switch's OFF-time (i.e., t_OFF greater than t_AUX), the supply 100 is operating in discontinuous-conduction mode (DCM). The amount of dead time (the difference that t_OFF exceeds t_AUX) for which the magnetically coupled current I₁/I₂ stays at a null level defines how strongly the supply 100 operates in DCM. If the current through the coil L2 reaches zero and the power switch SW1 turns on immediately (no dead time), the supply 100 operates in critical-conduction mode.

[0015] The operation of the supply 100 is comparable to someone (a bucket operator 110) filling a bucket (transformer T1) with water (electrical current) and then flushing the water into a pressurized water tank (capacitor C1) through a check-valve (D1). The water (current) flows down (as current I₁) into the bucket (T1) from a source (V_IN), and is flushed out (as current I₂) under (higher or lower) pressure V₂. In this analogy, the bucket operator (110) first presents the bucket (transformer T1) to the source (ON-time) until its inner level (magnetically coupled current I₁/I₂) reaches a defined limit. Then, the bucket operator (110) removes the bucket (T1) from the spring (OFF-time) and flushes the water (as current I2) into a tank (C1) that supplies a fire hose nozzle (at V_OUT). The bucket (T1) can be totally empty (i.e., zero magnetically coupled current I1/I2) before refilling (DCM), or some water (e.g., current I₂) can remain in the bucket (T1) before the user presents the bucket (T1) back to the spring (CCM). Suppose that the bucket operator (110) is skillful such that at each cycle he presents the bucket (T1) to the source (V_IN) at the precise instant that the water in the bucket (T1) from the previous cycle is completely flushed (thus operating in critical conduction mode).

[0016] The end user is a firefighter (such as a brave fireman of the New York City Fire Department, NYFD) who provides the feedback to the bucket operator (110) via his voice, shouting for more or less flow into the pressure tank (C1). If the flames increases, the firefighter applies water faster (higher load) and requires more pressurized water from the tank (C1) and thus asks the bucket operator (110) to provide the bucket (transformer T1), and therefore the tank (C1), with a higher flow. In other words, the bucket operator (110) will fills his container (T1) longer (ON-time increases).

[0017] If the flames decreases, the firefighter requires less pressurized water from the water tank (C1) and thus asks the bucket operator (110) to conserve water (conserve energy) by reducing the flow to the bucket (transformer T1), and thereby reducing the flow into the tank (C1). By reducing the filling time (ON-time) during which the flow (current I₁) from the source V_IN is filling the bucket (T1), the flushing time (OFF-time) required to flush the water (as current I₂) into the tank (C1) is reduced. Thus, while the critical conduction mode is maintained, the cycle period (ON-time plus OFF-time) is reduced, thereby increasing the switching frequency F_SW. (Note: Increased switching frequency F_SW is associated with increased switching losses, that is, the higher the switching frequency F_SW, the more energy is wasted, e.g., as heat in the power switch SW1.) The bucket operator (110) of the related art is very strict about limiting the maximum switching frequency, and he (110) clamps the switching frequency F_SW to a predetermined maximum value F_SWCLAMPED, and the filling/flushing process leaves the critical conduction (flyback-SOP) mode of operation and remains in DCM at that predetermined fixed frequency F_SWCLAMPED. There is a generally practical limit on how quickly the bucket operator (110) can cut (turn-OFF) the flow of current (I₁) into the bucket (T1) from the source V_IN, and thus there is a minimum time (t_ONMIN is the shortest practical ON-time) that filling the bucket (T1) can be performed.

[0018] In the frequency clamped SOP 100 of the related art, the predetermined maximum frequency F_SWCLAMPED of the switching frequency (F_SW), is predetermined by the minimum ON-time (t_ONMIN) and by a fixed predetermined minimum OFF-time (t_OFFCLAMPED, e.g., where t_OFFCLAMPED is fixed by an RC time-constant circuit including resistor R_FREQCLAMP and capacitor C_FREQCLAMP, as shown in FIG. 1A). In the Frequency Clamped SOP 100 of the related art, the OFF-time is clamped to a predetermined minimum value which remains fixed by a time-constant circuit (e.g., R_FREQCLAMP & C_FREQCLAMP of FIG. 1A) even while the load approaches zero or becomes zero (i.e., the load is deemed zero when zero current is output from the power supply 100). The switching frequency F_SW is clamped to a predetermined fixed frequency F_SWCLAMPED in this manner in order to prevent the switching frequency F_SW from shifting to a high value, which otherwise can happen in the absence of a load (i.e., zero load). When operating below this predetermined fixed frequency F_SWCLAMPED, the SOP 100 operates in critical conduction mode, with a varying frequency but generally constant duty-cycle. The power (P) consumed by the SOP 100 operating in critical conduction mode is governed by the equation:

[0019] where t_ON is the ON-time; and L is the primary inductance of the transformer. When operating at the predetermined fixed frequency F_SWCLAMPED, the SOP 100 operates in a discontinuous conduction mode (DCM) with a generally constant duty-cycle. The power (P) consumed by the SOP 100 operating in discontinuous conduction mode (DCM) at the predetermined fixed frequency F_SWCLAMPED is governed by the following equation:

[0020] where F_SWCLAMPED1/(t_ONt_OFF), and t_ONt_ONMIN, and t_OFF is the fixed OFF-time t_OFFCLAMPED.

[0021] FIG. 1C is a block diagram depicting the internal functions of the Frequency Clamped Flyback Driver 110 of FIG. 1A. The functions of the Frequency Clamped Flyback Driver 110 of FIG. 1C may be performed by a Motorola Corp. switch driver chip known as an MC33368 controller. A switch driver 110 for controlling the ON/OFF state of the power switch SW1 (of FIG. 1A) may include a flip-flop (e.g., set-dominant latch) 118 and a combinatorial logic gate (e.g., NOR-gate 112) connected as shown in FIG. 1A. The combinatorial logic gate (112) combines control signals (e.g., latched zero-current detection signals from the latch 118, and minimum OFF-time signals from the frequency clamp 116 ) to effectively control the power switch (SW1 of FIG. 1A). Effective control of the power switch SW1 (for critical conduction mode operation) includes closing the switch SW1 immediately upon the occurrence of a zero-current condition of the output-current inductor coil (L2 of the SOP of FIG. 1A), which can be effected by outputting a control signal from the Zero Current Detector (130) to the combinatorial logic gate (112) and resetting the flip-flop 118. The flip-flop (118) latches the (switch-ON) control signal from the Zero-Current Detector (130) so that the switch will stay closed (ON) until the current (I₁) through the input-current inductor coil (L1) reaches a threshold current magnitude I_TH or until an Output Overvoltage or other undesired condition is detected. Accordingly, the power switch (SW1 of FIG. 1A) will thereafter remain closed (ON) until: the current (I₁) through the input-current inductor coil (L1) reaches a threshold current magnitude I_TH, the value of I_TH being determined by the external Mult control signal into a Multiplier (134); or until an Output Overvoltage is detected by circuit 132 based on feedback signal FB (from the output V_OUT of the SOP 100 of FIG. 1A). After the power switch (SW1) opens (i.e., turns OFF), it will be closed again immediately upon the occurrence of a zero-current condition of the output-current inductor coil (L2 of the SOP of FIG. 1A), if and only if the OFF-time associated with switching frequency F_SW that would occur during critical conduction mode operation is equal to or greater than the OFF-time associated with a predetermined fixed frequency F_SWCLAMPED. Regardless of the magnitude of the load (e.g., no matter how small the magnitude of the current out of the power supply), if the switching frequency F_SW that would otherwise occur during critical conduction mode operation is greater than the predetermined fixed frequency F_SWCLAMPED, then the switching frequency F_SW will be clamped to the predetermined fixed frequency F_SWCLAMPED. The Frequency Clamp 116, when controlled (via the Frequency Clamp Pin) by a time-constant circuit (e.g., R_FREQCLAMP & C_FRQCLAMP of FIG. 1A), will clamp the switching frequency F_SW to the predetermined fixed frequency F_SWCLAMPED by delaying the termination of the OFF-time (i.e., termination of the OFF-time is commencement of the ON-time) that otherwise would be effected by a zero-current-indicating signal from the Zero-Current Detector (130). An optional amplifying buffer 114 provides amplification of the current and/or voltage necessary to rapidly gate (i.e., turn ON/OFF) the power switch (SW1 of FIG. 1A).

[0022] FIG. 1D is a graph depicting the general relationship of switching frequency (F_SW) to a (slowly changing) load (e.g., a current I_SUP out of the power supply indicated generally by V_OUT/R_LOADEQ) during medium-load and small-load conditions of the SOP 100 of FIG. 1A. The graph (FIG. 1D) is not drawn to scale, and the scaling factor x in each abscissa point along the logarithmic R_LOADEQ axis depends upon the designed power-rating of a particular power supply made in accordance with the topology of SOP (100) of the related art. As illustrated in FIG. 1D, the SOP 100 of FIG. 1A will operate in critical conduction mode, with switching frequency (F_SW) increasing as the load decreases, until the switching frequency (F_SW) in critical conduction mode would exceed the predetermined fixed frequency F_SWCLAMPED (due to small-load conditions), and F_SW is thereafter clamped to the predetermined fixed frequency F_SWCLAMPED. The operation of the SOP (100 of FIG. 1A) under small load conditions, including zero-load conditions, incurs avoidable switching losses and consumes unnecessary electrical power.

[0023] The present invention overcomes the disadvantages of the self-oscillating switching power supply (SOP) 100 of the related art.

[0024] In a first aspect, the present invention provides a switching power supply having an output voltage (V_OUT) for supplying a supply current to a dynamically variable load, the switching power supply comprising:

[0025] an input-current inductor coil connected in series with an input voltage source (V_IN) and a power switch;

[0026] an output-current inductor coil for outputting an output current at at least the output voltage (V_OUT);

[0027] a zero-current detector having a detector-output being activated when the output current falls to zero;

[0028] a switch-driver circuit for closing and opening the power switch, the switch-driver circuit including:

[0029] a flip-flop adapted to latch the activated detector-output and having a first flip-flop input connected to the detector-output, and having a flip-flop output, the flip-flop output being activated while the activated detector-output is latched;

[0030] a combinatorial logic gate, having a first logic gate input connected to the flip-flop output and a second logic gate input and a logic gate output, the logic gate output being activated if the flip-flop output is activated and if the second logic gate input is not inhibited, the power switch being closed while the logic gate output is activated.;

[0031] a pulse generator having a pulse generator-output for outputting an OFF-pulse having a dynamically variable load-modulated pulse width that corresponds to the dynamically variable load, the pulse generator-output being connected to the second logic gate input and inhibiting the second logic gate input during the pulse-width of the load-modulated OFF-pulse.

[0032] In a second aspect, the present invention provides a method for operating a switching power supply adapted to supply a load current through a dynamically variable load, the method comprising:

[0033] operating the supply in discontinuous current mode (DCM) while the supply is supplying load current having a first load current magnitude, and increasing the extent (E_DCM) that the supply operates in DCM as the load current decreases from the first load current magnitude; and

[0034] operating the supply in critical current mode while the supply is supplying load current having a second load current magnitude that is larger than the first load current magnitude.

[0035] In a third aspect, the present invention provides a switching power supply adapted to operate in a critical conduction mode and in a discontinuous conduction mode, comprising:

[0036] a power switch connected in series to an input-current inductor coil and operatively coupled to an output-current inductor coil, the power switch adapted to interrupt an input current through the input-current inductor coil, the power switch being either in an OFF or an ON state and conducting the input current when in its ON state;

[0037] a switching controller adapted to control the state of the power switch, the switching controller being operatively coupled to:

[0038] a first feedback signal for indicating a zero-current condition in the output-current inductor coil, wherein the switching controller turns the power switch ON in response to the first feedback signal while the supply operates in the critical conduction mode;

[0039] a second feedback signal indicating a threshold current magnitude in the input-current inductor coil, wherein the switching controller turns the power switch OFF in response to the second feedback signal; and

[0040] a third feedback signal, wherein the switching controller holds the power switch OFF notwithstanding the first feedback signal during a dynamically variable OFF-time that is varied in response to the third feedback signal while the supply operates in the discontinuous conduction mode.

[0041] The foregoing and other features and advantages of the present invention will be apparent from the following description of embodiments of the present invention.

[0042] The features and inventive aspects of the present invention will become more apparent upon reading the following detailed description, claims, and drawings, of which the following is a brief description.

[0043] FIG. 1A is a circuit diagram depicting a typical topology of a self-oscillating (i.e., flyback) switching power supply (SOP) of the related art;

[0044] FIG. 1B is a timing diagram depicting currents and voltages in the SOP of FIG. 1A operating in critical conduction mode;

[0045] FIG. 1C is a block diagram depicting internal functions of the Flyback Driver of the self-oscillating switching power supply (SOP) of FIG. 1A;

[0046] FIG. 1D is a graph depicting the general relationship of switching frequency (F_SW) to load during medium-load and small-load conditions of the SOP of FIG. 1A;

[0047] FIG. 2A is a block diagram depicting a first general topology of a frequency modulated self-oscillating switching power supply (FMSOP) in accordance with embodiments of the present invention;

[0048] FIG. 2B is a circuit diagram depicting a switching frequency modulator circuit with optical isolation adapted to modulate the switching frequency of the FMSOP of FIG. 2A;

[0049] FIG. 2C is a timing diagram depicting currents and voltages in the FMSOP of FIG. 2A operating in critical conduction mode and in load-modulated discontinuous-conduction mode;

[0050] FIG. 2D is a graph depicting ON-time and OFF-time as functions of load on the output of the FMSOP of FIG. 2A.;

[0051] FIG. 2E is a graph depicting the general relationship of switching frequency (F_SW) to load during medium-load and small-load conditions of the FMSOP of FIG. 2A;

[0052] FIG. 3 is a block diagram depicting a second general topology of a frequency modulated self-oscillating switching power supply (FMSOP) in accordance with embodiments of the present invention;

[0053] FIG. 4A is a block diagram depicting an FMSOP regulating small-load switching frequency with a voltage-controlled pulse generator (VCPG) included within the switch-driver 410 circuit, in accordance with embodiments of the present invention;

[0054] FIG. 4B is a block diagram depicting internal functions of the switch-driver for the FMSOP of FIG. 4A.

[0055] It should be noted that the same element numbers are assigned to components having or which may have the same, or approximately the same functions and structural features. Thus, elements in different figures and labeled with the same element number may be identical, or substantially similar in composition, structure and/or function, and where the function of such element has been explained, there is no necessity for repeated explanation thereof in the detailed description.

[0056] FIG. 2A is a block diagram depicting a first general topology of a frequency modulated self-oscillating switching power supply (FMSOP) 200 in accordance with embodiments of the present invention. The FMSOP 200 embodiment of FIG. 2A is an improvement of the related art SOP 100 of FIG. 1A, and has many elements in common, as indicated by the common element numbers. The FMSOP 200 includes a switching-frequency controller (FC) 220, instead of a time-constant circuit (e.g., R_FREQCLAMP & C_FREQCLAMP of FIG. 1A), coupled by a line (241) to the switch driver (e.g. 110 of FIG. 1A). The frequency controller (FC) 220 provides a load-modulated time reference t_OFFMIN (during small loads, t_OFFt_OFFMIN) to the switch driver 210, instead of the time-constant (t_OFFCLAMPED) of FIG. 1A. (Switch driver 210 can be implemented with the same Motorola MC33364 chip as used to implement driver 110 of FIG. 1A, if, for example, used in conjunction with a load-modulated-current-injecting frequency-controller (FC) 220 circuit such as the circuit depicted in FIG. 2B).

[0057] The load-modulated time reference (t_OFFMIN) will constitute the OFF-time (t_OFF) of the power switch (SW1) during small-load conditions (t_OFFSL) when the FMSOP 200 operates in discontinuous conduction mode (DCM). Thus, the switching frequency (F_SW) during small-load conditions will vary as a function of the load, instead of remaining constant (e.g., clamped to the predetermined fixed frequency F_SWCLAMPED). Thus, during small-load conditions, the switching frequency F_SW of the FMSOP 200 is a load-modulated switching frequency (F_LMSW) calculated as the inverse of the sum of the minimum ON-time (t_ONt_ONMIN) plus the load-modulated OFF-time (t_OFFt_OFFMIN)(i.e., F_LMSW1/(t_ONMIMt_OFFMIN).

[0058] During small-load conditions, the frequency controller (FC) 220 modulates the small-load OFF-time (t_OFFSL) so that t_OFFSL (t_OFFt_OFFSLt_OFFMIN) will increase as the small load further decreases. Thus, as the small load decreases, the load-modulated switching frequency F_LMSW decreases (e.g., approximately linearly with decreasing load current, i.e., current through the load having resistance R_LOADEQ), thus reducing power (P) consumption, preventing output overvoltage, and further reducing switching losses. The more that t_OFFMIN exceeds t_AUX of a cycle, the more dead time will be in that cycle, and the more strongly the supply 200 operates in DCM. The dead time (i.e., the time difference that t_OFFSL exceeds t_AUX under small load conditions) is the time (t_OFFDELAY) during which the OFF-time is extended and the next ON-time is delayed, measured between the moment which the output current in the output-current inductor coil falls to zero and the commencement of the next ON-time. Thus, dead timet_OffDELAY(t_OFFSLt_AUX). Thus, the variable extent (E_DCM) to which an FMSOP (e.g., 200 of FIG. 2A, or 300 of FIG. 3, or 400 of FIG. 4A) operates in DCM can be objectively calculated and expressed as the ratio of t_OFFDELAY to either t_ONMIN, t_OFFMiN, t_AUX, or (t_ONMINt_OFFMIN) or (t_ONMINt_AUX). The extent (E_DCM), by whichever ratio it is defined, will generally increase monotonicly under small-load conditions as the small load is monotonicly decreased further.

[0059] As the load approaches zero, (e.g., R_LOADEQ approaches infinity), the load-modulated OFF-time (t_OFFSL) will approach a maximum value t_OFFMAX, which may be predetermined. Thus, as the load approaches zero, (i.e., R_LOADEQ approaches infinity), the switching frequency F_SW (F_SWF_LMSW) will approach a minimum value F_SWMIN which may be predetermined. The minimum frequency F_SWMIN may be selected to be effective to maintain the appropriate output voltage _OUT while consuming minimal electrical power (P) supplied from V_IN. Thus, when there is no load on the frequency-modulated self-oscillating switching power supply (FMSOP) 200, the supply 200 can maintain an appropriate output voltage _OUT while consuming only minimal electrical power (P).

[0060] When the supply (FMSOP) 200 is operating in critical conduction mode, (e.g., at medium and high load conditions), the power (P) consumed by the FMSOP 200 is governed by the equation:

[0061] and F_SW is governed by the flyback feedback signal (via line 130) at the Zero-Current Detector of switch driver 210, and t_OFFt_ON*(N_T*_OUT/V_IN). When operating at the load-modulated switching frequency F_LMSW, the FMSOP 200 operates in a discontinuous conduction mode (DCM) with a switching frequency and duty-cycle that generally decreases as the load decreases to zero. The power (P) consumed by the FMSOP 200 operating in discontinuous conduction mode at the load-modulated switching frequency F_LMSW is governed by the equation:

[0062] P0.5*F_LMSW*(t_ONMIN{circumflex over ()}2)*V_IN²/L,

[0063] where F_LMSW1/(t_ONt_OFF), while t_ONt_ONMIN, and t_OFF is the load-modulated minimum OFF-time t_OFFMIN. Accordingly, as the load approaches zero, the power consumption (P) will decrease and approach a minimum.

[0064] The load-modulated time reference (t_OFFMIN) is produced in the load-modulated frequency controller (FC) 220 or, in alternative embodiments, by circuitry integrated within the switch driver 210 (see, e.g., FIGS. 4A & 4B). The time reference (t_OFFMIN) can be produced by analog circuits or by digital circuits.

[0065] FIG. 2B is a circuit diagram depicting a load-modulated frequency controller (FC) 220-a, with optical isolation, adapted to load-modulate the switching frequency of the FMSOP 200 of FIG. 2A during small-load conditions. The frequency controller (FC) 220-a of FIG. 2B can be employed as the frequency controller (FC) 220 of FIG. 2A when the switch driver 210 (of FIG. 2A) is implemented by the Motorola Corp. controller chip known as an MC33368 or by other flyback driver circuits having similar frequency-clamping functions.

[0066] The frequency controller (FC) 220-a employs analog circuits to generate a load-modulated OFF-time reference signal encoding the time reference t_OFFMIN (during small loads, t_OFFt_OFFSLt_OFFMIN) supplied to the switch driver 210 in FIG. 2A, instead of supplying a time-constant (t_OFFCLAMPED) as used in the related art SOP 100 FIG. 1A. The FC 220-a receives a feedback signal (e.g., voltage _OUT) via a line (240) from a load-sensing circuit (e.g., the entire voltage _OUT across the load (e.g., R_LOADEQ) itself, or a voltage-divided portion thereof). A small-load condition (including zero-load) is characterized by a high value of _OUT as compared to the magnitude of voltage _OUT during medium load or highest rated load. The small-load condition can be defined as beginning at the point when switching losses that would be incurred during critical current mode operation of an SOP (e.g., 100 of FIG. 1A) at that load are unacceptably high, and as ending at zero-load. The elements of the FC 220-a circuit translate variations in the small-load into a load-modulated current I_LM that is used to contribute to the filling of the capacitor C_F1. The filling of the capacitor C_F1 establishes an enabling voltage at node FCNODE which when sensed at the Frequency Clamp Pin can release an inhibition by the Frequency Clamp of the commencement of the ON-time.

[0067] The drive output (GATE) of switch driver 210 (e.g., the Motorola MC33368 chip) is inhibited (i.e. commencement of the ON-time is inhibited) when the voltage at its frequency clamp pin (being equipotential with FCNODE) is less than 2.0 volts. When the driver output (GATE) is High (during ON-time), C_F1 is discharged through an internal 100 uA current source. When the drive output goes Low (i.e., OFF-time commences), C_F1 is charged through R_F1 and by current I_LM. Activation of the switch driver (210) output (GATE) (i.e., commencement of the ON-time) is inhibited until the voltage across C_F1 (at node FCNODE) reaches 2.0 volts, establishing a minimum OFF-time (t_OFFMIN) which is modulated by the current I_LM which fills the capacitor C_F1. The larger the current I_LM is, the faster the capacitor C_F1 will rise above 2.0 volts, and the shorter the minimum OFF-time (t_OFFMIN) will be. Thus, during medium load and high load conditions, the current I_LM is at a high value, (so that the FMSOP 200 can operate in critical conduction mode), and during zero-load conditions the current I_LM will be at a relatively low or zero-current, with varying load-modulated magnitudes in between (so that the FMSOP 200 can operate in a load-modulated discontinuous conduction mode) during small load conditions. The minimum OFF-time (t_OFFMIN) controlled by a load-modulated signal (e.g., current I_LM) is the small-load OFF-time (t_OFFSL).

[0068] During normal operation of the FMSOP 200 (e.g., in critical conduction mode under medium load), the output voltage (_OUT) drops or sags (relative to its zero-load value) under increasing load. Thus, the output voltage _OUT is generally a function of the load. The voltage at Node1 of the voltage divider (R₉ & R₁₀) falls proportionately with the drop of _OUT. The three-terminal adjustable shunt regulator TL431 controls the current through the PhotoDiode in the OptoIsolator (and through resistor R₇) as a function of the voltage at Node1. The light emitted by the PhotoDiode is a function of the load. The phototransistor (PT) is optically coupled to the PhotoDiode. A current (I_PD) that passes through the photo diode PhotoDiode causes photons to be emitted by PhotoDiode. The photons are coupled to the photo transistor (PT), which conducts a current (I_PT) through the photo transistor (PT). The phototransistor (PT) forms a part of a voltage-divider (R₆ & PT).

[0069] The voltage-divider (R₆ & PT) generates a load-modulated voltage signal that propagates through diode D2, past resistor R₅, and through resistor R3 into the non-inverting () terminal of the error amplifier ErrorAmp. The error amplifier ErrorAmp has an inverting terminal () connected to a constant voltage node (Node2) and a non-inverting terminal () connected to the voltage-divider (R₆ & PT) through diode D2 and resistor R₃ and Node4. The inverting terminal () of the error amplifier ErrorAmp is connected to a constant-voltage circuit (zener & resistor R4 dividing reference voltage V_REF), and to a series RC feedback (through R_FB & C_FB) from its output at Node3. The output of ErrorAmp at Node 3 is the load-modulated current I_LM.

[0070] Current I_LM passes through diode D1 and resistor R_F2 into capacitor C_F1, as aforesaid. Thus, those skilled in the art will recognize that the circuit of FC 220-a including error amplifier ErrorAmp, the photo diode PhotoDiode, and the photo transistor PT form an optoisolated voltage-controlled current source.

[0071] The load-modulated frequency controller (FC) 220 (see FIG. 2A) and circuits connected thereto within the Frequency Clamp circuit (116 of FIG. 1C) of the switch-driver (210) constitute an analog-to-digital converter (ADC) that outputs a load-modulated pulse (P_OFFMIN) into the combinatorial logic gate (112, see FIG. 1C), wherein the width of the pulse (P_OFFMIN) is equal to or approximately equal to a load-modulated time reference (t_OFFMIN) that corresponds to the magnitude of the load (e.g., corresponds inversely to resistance R_LOADEQ). The time reference (t_OFFMIN) can be supplied directly to an input to the combinatorial logic gate (e.g., 112 in FIG. 1B) in switch driver 210 (of FIG. 2A), as a binary pulse-width modulated signal (P_OFFMIN) that is width-modulated by the load upon the FMSOP (200). (In alternative embodiments of the FC 220-a, the output of the combinatorial logic gate (112) can be gated (i.e., interrupted or passed) by the pulse P_OFFMIN (e.g., AND-ed or NAND-ed with the pulse P_OFFMIN) to inhibit the activation of the switch driver (210) output (GATE) (i.e., to inhibit the commencement of the next ON-time) during the period t_OFFMIN. If the output of the combinatorial logic gate (112) is gated by the the pulse P_OFFMIN (instead of having pulse P_OFFMIN as an input to combinatorial logic gate (112) ), the resulting combinatorial circuit will constitute a combinatorial logic gate that is functionally equivalent in the material aspects to combinatorial logic gate (112) with each of its original inputs.

[0072] The pulse (P_OFFMIN) will begin (i.e., go active) when the binary output of the combinatorial logic gate (e.g., 112) turns the switch OFF, (via the power switch's GATE). Thus a feedback signal (192 in FIG. 1C, from the combinatorial logic gate (e.g., 112)) to the time-reference generating circuitry (e.g., frequency controller 220 & frequency clamp 116) may be provided for synchronization. The pulse (P_OFFMIN) will end when the time t_OFFMIN has elapsed after the pulse (P_OFFMIN) began, the width of the pulse (P_OFFMIN) being equal or approximately equal to the load-modulated time reference (t_OFFMIN).

[0073] Certainly, various other analog circuits can be adapted by persons skilled in the art to load-modulate the minimum OFF-time (t_OFFMIN) of the switch, and therefore load-modulate the switching frequency (F_SW), during small-load conditions. For example, in alternative embodiments of the FC 220-a circuit, the voltage-controlled current source could be replaced (i.e., I_LM0) with a circuit to modulate voltage V_CC according to the output voltage _OUT (e.g., increasing V_CC when _OUT increases, in order to dynamically reduce the time t_OFFMIN needed to fill capacitor C_F1). While the FC 220-a of FIG. 2B is optoisolated from the output voltage (_OUT), in some embodiments of a FMSOP, isolation might be unnecessary (see, e.g., FIGS. 4A & 4B), or other isolation methodologies may be employed (such as magnetic isolation).

[0074] FIG. 2C is a timing diagram depicting currents and voltages in the FMSOP 200 of FIG. 2A operating in critical conduction mode (e.g., during large load) and in a load-modulated discontinuous-conduction mode (during small-load). A transition from large-load conditions (e.g., critical current mode, which is indicated by the absence of dead-time after OFF-time, t_OFFLL) to small-load conditions (i.e., with a substantial dead-time t_D1) generally will not be abrupt, (i.e., not as abrupt as depicted in FIG. 2C). FIG. 2C depicts large-load operating conditions (critical current mode) adjacent to small-load operating conditions (e.g., strongly discontinuous current mode) for purposes of side-by-side comparison. While in critical current mode (e.g., during medium load and some large load conditions), the FMSOP 200 will operate in the same SOP manner as the SOP manner of SOP 100 of FIG. 1A, and the switching frequency F_SW will governed by the flyback feedback signal (e.g., V_AUX).

[0075] As the load decreases, the load-modulated minimum OFF-time (t_OFFMIN) will reach a point when the resulting OFF-time (e.g., t_OFFSL1) will be (slightly) longer than t_AUX. At and beyond this load-point each ON-time (e.g., t_ONSL1 & t_ONSL2) may be expected to be near, approaching or, fixed at or around its practical minimum t_ONMIN. When the load-modulated minimum OFF-time (t_OFFMIN) is greater than t_AUX there will be a DeadTime period (e.g., t_D1) within the real OFF-time (e.g., t_OFFSL1) before the next ON-time (e.g., t_ONSL2). As the load decreases further (i.e., approaches zero-load), the load-modulated minimum OFF-time (t_OFFMIN) will increase, and consequently, the DeadTime within the OFF-time will increase, and the switching frequency F_SW will decrease. As the load approaches zero, the switching frequency F_SW (i.e., F_SW1/(t_ONMINt_OFFMIN)) will decrease until F_SW reaches a minimum switching frequency F_SWMIN, which may be predetermined.

[0076] FIG. 2D is a graph depicting ON-time (t_ON) and OFF-time (t_OFF) as functions of the load on the output of an FMSOP (e.g., 200 of FIG. 2A, 300 of FIG. 3, or 400 of FIG. 4A). As illustrated in FIG. 2D, the OFF-time (t_OFF) of the power switch (SW1 of FIG. 2A) during critical current mode operation (e.g., flyback operation under medium and large load conditions) is governed by and substantially equal to t_AUX as previously defined (i.e., t_OFFt_AUX). As further illustrated in FIG. 2D, the OFF-time (t_OFF) of the power switch (SW1 of FIG. 2A) during load-modulated DCM operation (LM-DCM) (e.g., under small load conditions) is governed by and is substantially equal to the load-modulated minimum OFF-time t_OFFMIN as previously defined (i.e., t_OFFSLt_OFFMIN). The transition point between critical current mode operation and DCM operation is the point when the load-modulated minimum OFF-time (t_OFFMIN) is equal to t_AUX. This transition point can be shifted up or down (along the load axis) by persons of ordinary skill in the art by changing the values of t_OFFMIN as a function of the load, such as by changing the resistance ratio between the values of resistors R9 and R10 in the FC 220-a of FIG. 2B, and by various other adjustments and modifications. Because the switching frequency F_SW is a function of the ON-time and the OFF-time of each cycle (i.e., F_SW1/(t_ONt_OFF)), the switching frequency F_SW and power consumption (P) will generally decrease with decreasing load in LM-DCM operation under small-load conditions. The duty cycle (Q_FM) of the FMSOP 200 is calculated as the ratio of the ON-time to the sum of the ON-time plus the subsequent OFF-time (i.e., Q_FMON-time/(ON-time plus OFF-time)). Thus, under small-load conditions, the duty cycle (Q_FM) of the FMSOP 200 will generally decrease as the load is decreased, even while the ON-time is fixed at its practical minimum value t_ONMIN.

[0077] FIG. 2E is a graph depicting the general relationship of switching frequency (F_SW) to load (load being indicated by R_LOADEQ) under medium-load and small-load conditions of an FMSOP (e.g., 200 of FIG. 2A, 300 of FIG. 3, or 400 of FIG. 4A). The graph (FIG. 2E) is not drawn to scale, and the scaling factor x in each abscissa point along the logarithmic R_LOADEQ axis depends upon the designed power-rating of a particular power supply made in accordance with the topology of a FMSOP (e.g., 200 of FIG. 2A, 300 of FIG. 3, or 400 of FIG. 4A). As illustrated in FIG. 2E in conjunction with FIG. 2D, the FMSOP will operate in critical conduction mode, with switching frequency (F_SW) generally increasing as the load decreases until the point at which the OFF-time component of the switching frequency (F_SW) in critical conduction mode would exceed the load-modulated minimum OFF-time (t_OFMIN), and F_SW is decreased as the load is further decreased. The operation of the FMSOP (e.g., 200 of FIG. 2A, 300 of FIG. 3, or 400 of FIG. 4A) under small load conditions can minimize power (P) consumption, and minimize switching losses, while maintaining the output voltage _OUT at a proper level.

[0078] FIG. 3 is a block diagram depicting a second general topology of a frequency modulated self-oscillating switching power supply (FMSOP) in accordance with embodiments of the present invention. The FMSOP 300 of FIG. 3 generally operates in the same manner as the FMSOP 200 of FIG. 2A except that in FMSOP 300 the input-current inductor coil and the output-current inductor coil are the same coil (L1) rather than two distinct coils. Thus, while operating in the critical conduction mode, the input-current inductor's current (I₁) ramps up (ON-time) to a peak value (e.g., I_TH), ramps down (OFF-time) to zero, and then immediately begins ramping up (ON-time) again. While the input-current (I₁) is ramping up, the input-output current inductor coil L1 is charging (i.e., storing energy) from the source V_IN. While the input-current (I₁) is ramping down, the switch SW1 is open and the input-output current inductor coil L1 is discharging energy and current into the capacitor C1, and through the load, through diode D1.

[0079] When the power switch (SW1) closes (beginning of ON-time), a voltage V₁ (i.e., V₁ is approximately equal to voltage V_IN) is asserted across coil L1 and current I₁ ramps up (from zero at the end of the previous cycle) through the switch SW1 as current I_ON, until a threshold current magnitude I_TH is reached (i.e., I₁I_ON while SW1 is ON and I₁<I_TH). During this ON-time (t_ON), a magnetic field builds up in the core (e.g., T_CORE) of the input-output current inductor coil L1 (which is shared with auxiliary secondary coil L3). When the power switch SW1 opens, which begins the OFF-time (t_OFF), the magnetic field collapses, and, according to Lenz's law, the voltage V₁ across the input-output current inductor (L1) reverses polarity and attains the voltage magnitude necessary (e.g., the sum of voltages V₁V_IN becomes greater than _OUT) to maintain the flow of current I₁ through the path of least resistance (e.g., through diode D1 and into capacitor C1). In this case, there is no secondary winding (as there was L2 in FMSOP 200 of FIG. 2A) offering a path of least resistance, and the current (I₁) has to find some way to continue its flow and to begin its decrease-for example, as current I_OFF through diode D1 and into capacitor C1 and through the load.

[0080] The Zero Current Detector within or associated with the switch driver (e.g., 210) may indirectly sense a zero-current condition of current I₁ through the output-current inductor coil (L1) by monitoring an auxiliary voltage V_AUX across a magnetically coupled auxiliary coil (e.g., auxiliary winding L3). A very small, (i.e., negligible) amount of the input energy is output as an auxiliary output current (I_AUX) and dissipated through a sensing circuit within or operatively coupled to the switch-driver circuit (e.g, 210). The FMSOP (300) of FIG. 3 can have the same load-modulated timing (e.g., t_OFFMIN) and switching frequency (F_SW) characteristics as were depicted in FIGS. 2D and 2E for the FMSOP (200) of FIG. 2A.

[0081] FIG. 4A is a block diagram depicting an alternative embodiment of the present invention wherein load-modulation of the small-load OFF-time (t_OFFSL) in the FMSOP (400) is performed with a voltage-controlled pulse generator (VCPG) included within the switch-driver 410 circuit. The FMSOP (400) of FIG. 4A may be constructed in accordance with the first general topology shown in FIG. 2A, or in accordance with the second general topology shown in FIG. 3. Thus, the input-current inductor coil (L1) of the FMSOP (400) may be magnetically coupled to a separate output-current inductor coil (as in FMSOP 200 of FIG. 2A) or may be the same coil as the output-current inductor coil (as in FMSOP 300 of FIG. 3). An auxiliary coil (L3) magnetically coupled to the output-current inductor coil through a transformer core (T_CORE) provides the flyback signal (a signal indicating the zero-current condition in the output-current inductor coil) to support critical current mode operation.

[0082] The FMSOP (400) includes a (flyback) switch driver (410) which can be a modification of the Motorola MC33368 controller chip. In this embodiment, the frequency controller (420) external to the switch-driver 410 circuit may be simply implemented as a voltage divider comprised of two resistors (R_D1 & R_D2) connected between the output voltage (_OUT) and ground. The voltage divider's output line (441) is connected to a feedback (FB) pin of the switch-driver 410 circuit. The FB pin of the switch driver 410 may also be used for controlling a multiplier (134) and Output Overvoltage (132) circuits as in FIG. 1C of the related art. In various embodiments of the present invention, the Output Overvoltage circuit (132) present in the switch driver (110 of FIG. 1C) of the related art may not be needed, since the output voltage (_OUT) may be continuously monitored and regulated by the switching frequency modulating circuits of the present invention) and may be eliminated (see, e.g., switch driver 410 in FIG. 4B).

[0083] FIG. 4B is a block diagram depicting internal functions of the (flyback) switch driver (410) for the FMSOP 400 of FIG. 4A. The switch driver (410) can be fabricated on a single chip as a modification of a Motorola MC33368-based switch driver 210 of FIG. 2A. The voltage-controlled pulse generator (VCPG 416) outputs a pulse-width modulated (PWM) load-modulated OFFMIN-pulse (P_OFFMIN) having width t_OFFMIN. The VCPG (416) monitors the load, by monitoring the output voltage _OUT through a voltage divider (see R_D1 and R_D2 of FIG. 4A), and outputs load-modulated OFFMIN-pulse (P_OFFMIN) having a width (t_OFFIN) that generally increases with decreasing load under small-load conditions. The load can also be monitored by monitoring the magnitude of current output from the FMSOP (e.g., at voltage _OUT). The load-modulated OFFMIN-pulse (P_OFFMIN) may be of the same form (e.g., same active-voltage, and same shape, rise/fall time, etc.) as the output of Frequency Clamp circuit (116) to the combinatorial logic gate (112) in the driver circuit 110 of FIG. 1C.

[0084] The load-modulated OFFMIN-pulse (P_OFFMIN) of width t_OFFMIN thusly produced may be input directly to a combinatorial logic gate (e.g. 112) for inhibiting the activation of the output of the switch driver (e.g., 410) (i.e., for inhibiting the turning ON of the power switch SW1 thereby inhibiting the commencement of the next ON-time). The switch driver 410 including VCPG (416) requires fewer external components to perform the methods of the present invention, than the switch driver 210 of FIG. 2A. The load-modulated OFFMIN-pulse (P_OFFMIN) output by the VCPG (416) may be active-High or active-Low (depending upon whether the output of the switch driver 410 is active High or active Low), and is considered to be inhibiting while it is outputting a signal of width t_OFFMIN that inhibits the beginning of the next ON-time.

[0085] In alternative embodiments, the load-modulated pulse (P_OFFMIN) having width t_OFFMIN can be generated by a digitally controlled programable pulse generator (PPG) circuit of the related art (e.g., TTL-interfaced 8-bit PPG model PPG38F manufactured by data delay devices, inc., of Clifton, N.J.) that is operatively coupled (e.g., directly connected pin-to-pin, or through a look-up table, or through a microprocessor, etc.) to an analog-to-digital converter (ADC) which monitors the load. The ADC can be configured to sense the load by sensing the output voltage _OUT, for example, through a voltage divider (see, e.g., voltage divider R_D1 & R_D2 in FIG. 4A). The load-modulated OFFMIN-pulse (P_OFFMIN) of width t_OFFMIN thusly produced may then be input directly to a combinatorial logic gate (e.g. 112 of FIG. 4B) for inhibiting the activation of the output of the switch driver (e.g., 410) (i.e., for inhibiting the turning ON of the power switch SW1 thereby inhibiting the commencement of the next ON-time).

[0086] In other alternative embodiments, either a voltage controlled pulse generator (e.g., a VCPG as in FIG. 4B) or a digitally controlled programable pulse generator (PPG) may be used to delay the commencement of the next ON-time by being configured to implement a selectively triggered delay-block between the output of the combinatorial logic gate (112) (i.e., instead of as an input to gate 112), and the buffer 114. The delay block may follow buffer 114 or even include buffer 114, and therefore may be connected between the combinatorial logic gate 112 and the power switch SW1. The voltage-controlled delay block would pass either a rising (or falling) edge signal (i.e., the signal causing the commencement of the ON-time) without delay, but would delay the falling (or rising) edge signal (i.e., the signal causing the commencement of the OFF-time) by an amount of time (t_OFFDELAY) that increases with decreasing load, such that t_OFFt_AUXt_OFFDELAY. The delay time t_OFFDELAY equals dead time. Thus, t_OFFDELAY0 when critical current mode operation is desired. The delay-block would have the equivalent function of a combinatorial logic gate (e.g., a NAND-gate or AND-gate, etc., at the output of combinatorial logic gate 112), passing the ON voltage signal as soon as and while it is expressed at the delay block's input, but suppressing the propagation of the OFF voltage signal until an inhibiting signal of duration t_OFFDELAY has ceased to be asserted in or to the delay block. As previously noted, this arrangement (cascaded combinatorial logic gates) provides an equivalent combinatorial logic gate that is functionally equivalent in material aspects to combinatorial logic gate (112) with each of its original inputs (e.g., Q from flip-flop 418, and pulse P_OFFMIN from a VCPG or a PPG.

[0087] While various certain embodiments of the present invention have been disclosed, a person of ordinary skill in the art would realize that certain modifications would come within the teachings of the present invention. Therefore, the claims which follow should be studied to determine the true scope and content of the present invention.