Voltage controlled quadrature oscillator with phase tuning

[0001] FIG. 1 is a block diagram of a differential 2 stage ring oscillator with variable quadrature output phases according to the present invention.

[0002] FIG. 2 is a schematic of the circuit of FIG. 1.

[0003] FIG. 3 is a schematic of a differential regenerative frequency divider according to the present invention.

[0004] FIG. 4 is a block diagram of an image reject mixer.

[0005] FIG. 5 is a block diagram of an improved image reject mixer according to the present invention.

[0006] FIG. 1 shows a differential 2 stage ring oscillator 20 with quadrature output phases. Oscillator 20 includes a ring oscillator 21 and two current sources 28, 30. Ring oscillator 21 includes a pair of differential amplifiers 22 and 24 which are connected together as a ring oscillator. The propagation delay _A of amplifier 22 is controlled by varying the current of controllable current source 28 and the propagation delay _B of amplifier 24 is controlled by varying the current of controllable current source 30. The oscillation frequency of ring oscillator 21 is inversely related to the total propagation delay (_AB) of amplifiers 22 and 24. Signal V₁ is measured across nodes V₁ and V₁. Signal V₂ is measured across nodes V₂ and V₂. If the propagation delays, _A and _B, of amplifiers 22 and 24 are equal, then signal V₂ will lag 90 behind signal V₁ (i.e. signals V₁ and V₂ will be quadrature signals). Propagation delay _A of amplifier 22 can be changed by adjusting the current of current source 28. Similarly, propagation delay _B of amplifier 24 can be changed by adjusting the current of current source 30.

[0007] The frequency of ring oscillator 21 may be varied, without affecting the phase difference between signals V₁ and V₂, by adjusting the currents of current sources 28 and 30 proportionally.

[0008] The phase difference between signals V₁ and V₂ may be varied by differentially adjusting the propagation delays, _A and _B, of amplifiers 22 and 24. This is done by differentially adjusting the currents of current sources 28 and 30.

[0009] FIG. 2 is a schematic diagram of circuit 10. Amplifier 22 comprises a pair of emitter coupled amplifiers Q₁ and Q₂. Amplifier 24 comprises a pair of emitter coupled transistors Q₃ and Q₄. The collectors and bases of transistors Q₁- Q₄ are connected to form differential ring 21. The collectors of Q₁ and Q₂ are coupled to a voltage source V_cc1 through resistors R₁ and R₂. The collectors of Q₃ and Q₄ are coupled to voltage source V_cc2 through resistors R₃ and R₄.

[0010] Current source 28 comprises a transistor Q₅. The base of transistor Q₅ is coupled to at input voltage V_bias1, which controls the current of current source 28. Similarly, current source 30 comprises a transistor Q₆. The current of current source 30 is controlled by voltage signal V_bias2. Voltage signals V_bias1 and V_bias2 must have a

[0011] As the level of voltage signal V_bias1 is increased, the current of current source 28 will increase. This will increase the switching speed and decrease the propagation delay of differential amplifier 22. Similarly, the switching speed and propagation delay of differential amplifier 24 are controlled by varying the level of voltage signal V_bias2.

[0012] Although the propagation delays of amplifiers 22 and 24 are described here as being controlled by varying the bias currents of the amplifiers (i.e. the currents of current sources 28 and 30), the same results may be attained by creating any imbalance in the electrical symmetry between amplifiers 22 and 24. For example: a bias voltage or current may be altered at any node of ring oscillator 21. Alternatively, a controllable capacitor, inductor or resistor may be coupled to any node to differentially alter the internal impedances in amplifiers 22 and 24.

[0013] Ring oscillator 21 may also be implemented as a pair of quadrature coupled differential oscillators.

[0014] FIG. 3 shows a differential regenerative (i.e. dynamic) divider 50 with quadrature output. This circuit is identical to circuit 20, except that the bases of transistors Q₅ and Q₆ are additionally coupled to an input signal V_in at nodes 52 and 54 through coupling capacitors C_c1 and C_c2.

[0015] Signal V_in is received at nodes 52, 54 and has a frequency f_in. Transistors Q₅ and Q₆ convert input signal V_in into an alternating current signal i_in which is injected into emitter coupled nodes 56 and 58 of amplifiers 22 and 24. The frequency of current signal i_in is the same as the frequency f_in of input signal V_in. This injection locks ring oscillator 21 such that the oscillation frequency f_osc of the ring oscillator is half the input frequency f_in of input signal V_in.

[0016] If the propagation delays _A and _B of amplifiers 22 and 24 are configured to be the same, then signals V₁ and V₂ will be quadrature phased signals (i.e. they will be separated in phase by 90).

[0017] The phase relationship between V₁ and V₂ can be altered, without altering the frequency of ring oscillator 21 by differentially altering input voltages V_bias1 and V_bias2. Since ring oscillator 21 is injection locked to frequency f_in/2, it is only necessary to vary one of the input voltages V_bias1 or V_bias2, with respect to the other, to vary the phase relationship between V₁ and V₂.

[0018] In radio system architectures, image reject mixing requires accurate quadrature local oscillator signal generators to attain high image rejection performance. This is required for both up (transmitter) and down (receiver) conversions. Known designs attempt to design the quadrature signal generator (frequency divider) to produce as accurately as possible a pair of signals (generally referred to as the inphase (I) and quadrature (Q) signals) which are separated by precisely 90. It is impossible to account for all process tolerances which can impair the image rejection performance of an image reject architecture. Approximately 1 of phase error is common. This translates to a maximum image rejection of about 46 dB. Including other sources of phase and amplitude error in the quadrature down conversion path a typical specification for image rejection is approximately 35 dB. In order to improve image rejection beyond this level, a system is required for controlling the phase relation between the I and Q local oscillator signals with a high degree of precision. This system may be used to provide I and Q signals which have a phase relation which compensates for the other sources of phase error. In a particular case, the phase relation between the I and Q signals may be greater or less than 90.

[0019] FIG. 4 is a block diagram of an image reject mixer 100 using the Hartley topology. Signal RF_in comprises a RF signal having a frequency f_RF and an image signal having a frequency f_IM. Signal generator 101 provides a pair of local oscillator signals V₁ (which takes the place of the I signal) and V₂ (which takes the place of the Q signal), both having the same frequency f_LO. Signals V₁ and V₂ have phase angles _V1 and _V2. _V1 is arbitrarily chosen as a reference for 0 phase. Signals V₁ and V₂ are mixed with the received signal RF_in in mixers 102 and 104 to provide a pair of signals IF₁ and IF₂. When high side injection is used (f_LO is greater than f_RF), the IF₁ signal comprises the RF signal converted to frequency (f_LOf_RF) and the image signal (sideband) converted to frequency (f_IMf_LO). Signal IF₂ comprises the RF signal converted to frequency (f_LOf_RF) and shifted in phase by _V2 and the image signal converted to frequency (f_IMf_LO) and shifted in phase by _V2.

[0020] The amplified signals IF₁ and IF₂ are combined by a quadrature combiner 110. Quadrature combiner 110 is designed to complete the image rejection by providing a phase shift _QC1 to signal IF₁ and a phase shift _QC2 to signal IF₂. Ideally, to maximize suppression of the image signal, _QC1V10 and _QC2V2180 (assuming high side injection). Ideally, _V2V190, _QC2QC190. In known quadrature combiners, _QC2QC1 is generally not 90. Typically a phase error exists, and the image is not maximally suppressed. In addition, known quadrature combiners also introduce amplitude errors in the IF₁ and/or IF₂ signal paths. For example, both signal IF₁ may be reduced in amplitude by N dB.

[0021] Current state of the art systems attempt to maintain the 90 phase separations between _V1 and _v2 and between _QC1 and _QC2. It has been found that image rejection performance can be substantially increased by adjusting the phase difference to compensate for the phase error in the quadrature combiner 110. In addition, amplitude errors in the IF₁ and IF₂ signal paths can be compensated for.

[0022] FIG. 5 shows an improved image reject mixer 200. Components of image reject mixer 200 which correspond to components of image reject 100 are identified by the same reference numerals. Signal generator 101 of image reject mixer has been replaced with circuit 50 (FIG. 3). Nodes 52 and 54 of circuit 50 are coupled to a signal generator 202.

[0023] Output signal IF_out is received by a carrier level detector 203. Carrier level detector provides a signal to feedback controller 204. Feedback controller provides control signals to switches SW₁ and SW₂, calibration signal transmitter 206, signal generator 202, amplifiers 210, 212 and provides voltage signal V_bias1 and V_bias2. Image reject mixer has a calibration mode and operation mode.

[0024] Initially, in the calibration mode the following configuration is set by controller 204:

[0025] (a) switches SW₁ and SW₂ are configured to connect calibration signal transmitter 206 to input node RF_in;

[0026] (b) signal generator 202 is configured to produce a signal with a frequency twice that required for the local oscillator signals V₁ and V₂; and

[0027] (c) voltage signals V_bias1 and V_bias2 are configured to initiate the operation of circuit 50 with the phase delays of amplifiers 22 and 24 being approximately equal; and

[0028] (d) calibration signal transmitter 206 is configured to generate a signal at the frequency of the image;

[0029] (e) the gains of amplifiers 210 and 212 are set equal.

[0030] Controller 204 then runs a calibration algorithm. Signal IF_out is generated as in image reject mixer 100. Signal IF_out will contain the image signal generated by calibration signal generator 206. The level of signal IF_out will correspond to phase and amplitude errors introduced in quadrature combiner 110 and other components of image reject mixer 200. Carrier level detector provides a signal corresponding to the level of signal IF_out to controller 204.

[0031] Controller 204 then adjusts the relative propagation delays of amplifier 22 and 24 (within circuit 50) to control the relative phase difference between V1 and V2 to reduce the signal level of IF_out as much as possible. Controller 204 than adjusts the relative gains of amplifiers 210 and 212 to reduce the signal level of IF_out as much as possible. Controller 204 then alternately attempts to reduce the signal level of IF_out by adjusting the phase difference between V₁ and V₂ and by adjusting the relative gains of amplifiers 210 and 212. When no further reduction of IF_out is attained for several iterations, the calibration mode is terminated by configuring switches SW₁ and SW₂ to disconnect the calibration signal transmitter 206 from node RF_in and to connect the antenna to node RF_in.

[0032] Image reject mixer 200 then enters the operation mode. The setting for the phase difference between V₁ and V₂ and the relative gains of amplifiers 210 and 212 determined during the calibration mode are retained during the operation mode to maintain the improved image reject performance of image reject mixer 200 attained during calibration mode.

[0033] Image reject mixer 200 may be integrated. The functionality of the elements of image reject mixer 200 contained within dashed boundary 216 may wholly or partially implemented using analog or digital technology.

[0034] In addition, image reject mixer 200 may be used with a transmitter.

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