Multiple photolithographic exposures with different clear patterns

[0001] The present invention relates to photolithography.

[0002] Photolithography is widely used to form patterns on semiconductor wafers in fabrication of integrated circuits. A wafer 110 (FIG. 1) is coated with a photoresist layer 120. Photoresist 120 is irradiated from a light source 130. A mask or reticle 140 is placed between source 130 and resist 120. Mask 140 carries a pattern consisting of opaque and clear features. This pattern defines which areas of resist 120 are exposed to the light from source 130. After the exposure, the resist 120 is developed so that some of the resist is removed to uncover the underlying substrate 110. If the resist is positive, then the resist is removed where it was exposed to the light. If the resist is negative, the resist is removed where it was not exposed. In either case, the remaining resist and the exposed (uncovered) areas of substrate 110 reproduce the pattern on mask 140. The wafer is then processed as desired (e.g. the exposed areas of substrate 110 can be etched, implanted with dopant, etc.).

[0003] The resist pattern on wafer 110 is not always a faithful reproduction of the mask. In FIG. 2, an opaque feature 210M on mask 140 has a concave corner 220M. Feature 210M should ideally be printed (reproduced) in resist 120 as feature 210R, with a corner 220R. In fact, the resist region 230 in the corner's cavity gets underexposed. As a result, the corner is smoothened in the resist pattern, as shown by line 240. See U.S. Pat. No. 6,280,887 issued Aug. 28, 2001 to Lu.

[0004] The resist pattern can be corrected with a serif 310 (FIG. 3). The serif is a region cut out in opaque feature 210M to increase the exposure of region 230. However, if the feature 210M is narrow, i.e. the dimensions D1, D2 are small, the serif can be difficult to form on the mask.

[0005] The invention is defined by the appended claims which are incorporated into this section in their entirety. The rest of this section summarizes some features of the invention.

[0006] Some embodiments of the present invention provide alternative techniques to reduce underexposure of the resist. In some embodiments, the resist is exposed twice. One exposure is through a mask like in the prior art, for example, as in FIG. 2 or 3. The other exposure is conducted through a different (modified) mask which exposes resist regions which correspond to opaque regions of the first mask. This modified exposure is not conducted with a sufficient light energy dose to create a resist pattern on the wafer. For example, in the case of the positive resist, the modified exposure dose is insufficient to cause the resist to be removed during the developing process. However, the modified exposure increases the total energy dose delivered to regions such as 230. A more faithful pattern reproduction results in some cases.

[0007] The modified and non-modified exposures can be performed in any order.

[0008] In some embodiments, the modified exposure does not use a mask. The entire resist surface is exposed.

[0009] Other features and embodiments are described below.

[0010] FIG. 1 is a side view illustrating a prior art photoresist exposure system suitable for some embodiments of the present invention.

[0011] FIG. 2 is plan view of a prior art mask and a corresponding pattern formed in photoresist.

[0012] FIG. 3 is a plan view of a prior art mask.

[0013] FIG. 4 is a plan view of a mask used in some embodiments of the present invention.

[0014] FIG. 5 is a plan view of a resist pattern corresponding to the mask of FIG. 4.

[0015] FIGS. 6-10 are plan views of masks used in some embodiments of the present invention.

[0016] FIG. 4 illustrates an exemplary mask or reticle 140 which will now be used to illustrate some aspects of the invention. (The terms mask and reticle are used interchangeably herein.) The mask has a number of clear regions 410M surrounded by an opaque region 420M. In one embodiment, the mask was used with a positive resist to define isolation trenches formed in a monocrystalline silicon substrate for a memory array. Exemplary dimensions are as follows. Each clear region 410M is a rectangle of a height H1.38 m and a width W0.18 m. The vertical gaps 430M between the adjacent rectangles 410M have each a height of V0.22 m. Each horizontal gap A is 0.3 m. Light source 130 (FIG. 1) is a deep ultraviolet light source (DUV) having a wave length of 248 nm. (The dimensions and other details are given for illustration and are not limiting. Also, in one embodiment, the dimensions were 4 times larger than given above because the mask was used with a projection lens reducing the image on the wafer by a factor of 4.)

[0017] Of note, each rectangle 410M has two convex ends 440. Each end 440 defines a cavity in opaque region 420M. Each angle 450 of rectangle 410M also defines a cavity in region 420M.

[0018] The resist pattern formed on the wafer is shown in FIG. 5. Regions 410R, 420R, 430R correspond to respective mask regions 410M, 420M, 430M. The rectangles 410R are rounded, their height H is reduced, and the width W is increased. In one embodiment using a prior art resist exposure, the vertical gap V was 0.456 m in the resist pattern, i.e. more than twice as large as the 0.22 m gap on mask 140.

[0019] A more faithful image can be obtained with an additional exposure through a modified mask 602 (FIG. 6). In mask 602, each clear region 610 extends vertically through an area corresponding to an entire column of rectangles 410M (FIG. 4). The positions of the short sides of rectangles 410M are shown by dashed lines. Each region 610 covers the areas corresponding to the rectangles 410M and the vertical gaps 430M in one column. The clear regions 610 do not have cavities at the position of rectangle ends 440 (FIG. 4).

[0020] In one embodiment, the resist pattern is formed as follows:

TABLE 1
1. Coat the wafer 110 with a 0.078 m layer of antireflective coating (not
shown) of type AR2 available from Shipley Company, L.L.C., of
Marlborough, Massachusetts. Bake and cool down the wafer.
(This is a standard step.)
2. Deposit a 0.0609 m layer of a positive photoresist of type UV6
(Trademark) available from Shipley.
3. Expose the wafer through mask 602 of FIG. 6 to ultraviolet light with
one half of the dose normally used in prior art. In some embodiments,
the exposure is performed with a scanner of type ASML 500 available
from ASML. The best dose recommended by ASML is 27.5 mJ/cm2,
so the exposure at this step occurs with a dose of 13.75 mJ/cm2.
This dose is insufficient for the subsequent development step (step 7
below) to remove the resist in the exposed regions and uncover the wafer.
4. Bake and cool down the wafer.
5. Expose the wafer through the mask 140 of FIG. 4 to ultraviolet light
with a dose of 13.75 mJ/cm2.
6. Bake and cool down the wafer.
7. Develop the resist.

[0021] In one embodiment, the resist exposure is conducted with a scanner of type ASML 500 available from ASML of Tempe, Ariz., which uses a 248 nm light source. The resist exposure is performed with the zero and first order illumination and a 0.1 focus. The numerical aperture (NA) of the projection lens is 0.6. It is believed that this embodiment is capable of reducing the height V of the vertical gaps 430R in the resist pattern to about 0.317 m.

[0022] If the mask 140 features are narrow, creating the modified mask 602 of FIG. 6 can be easier than forming a serif. In particular, if the width W of rectangles 410M is the minimum feature size, the serif would require sub-lithographic dimensions (i.e., smaller than the minimum feature size) but mask 602 can be formed without sub-lithographic features. However, some embodiments of the present invention combine the mask layout of FIG. 4 with serifs. Also, the invention is not limited to the embodiments in which no sub-lithographic features are needed in the modified mask 602.

[0023] Removal of gaps 430M in mask 602 eliminates diffraction and light destructive interference at the short sides of rectangles 410M, so better resolution can be obtained.

[0024] In some embodiments, the exposure at step 3 of Table 1 is conducted without a mask. In some embodiments, more than two exposures are conducted. For example, the process of Table 1 can be augmented with an additional step of exposing the resist without a mask.

[0025] Steps 3 and 5 in Table 1 can be interchanged.

[0026] In another embodiment, the width W of rectangles 410M in mask 140 is 0.14 m. The exposure through mask 602 is conducted using off-axis illumination. (Off-axis illumination is described in Handbook of Microlithography, Micromachining, and Microfabrication edited by P. Rai-Choudhury, vol. 1 (1997), pages 71-73, incorporated herein by reference.) Also, an annular pupil is used to block some of the zero order light. In some embodiments, the rectangles' height H in mask 140 is 0.956 m, the gap height V0.156 m, and the horizontal gap width A0.210 m. The width of each feature 610 can be slightly larger than 0.14 m to accommodate a possible misalignment between the masks 602 and 140. A 0.16 m width dimension can be used.

[0027] FIGS. 7-10 show alternative designs for mask 602. In FIG. 7, the mask is identical to that of FIG. 6 except that each clear region 610 has a horizontal extension 730 at each gap 430M. Each extension 730 extends horizontally and vertically beyond the corresponding rectangles 410M (i.e. beyond the positions of rectangles 410M on mask 140) in both directions (left and right). Extensions 730 increase the light exposure at corners 450 and alleviate the need for serifs 310 (FIG. 3) in mask 140 at these corners. Serifs 310 are used in some embodiments however.

[0028] FIG. 8 shows an identical mask except that the extensions 730 are merged into horizontal strips each of which traverses the entire array of rectangles 410M. The strips 730 are greater in height than gaps 430M, so the strips 730 overlap the positions of rectangles 410M. In other embodiments, the strips 730 do not overlap the rectangles.

[0029] The mask of FIG. 8 may be easier and faster to write than the mask of FIG. 6. Also, the mask of FIG. 8 advantageously provides higher exposure in gaps 430 (i.e. the areas corresponding to gaps 430M). In addition, compared to FIG. 7, diffraction and destructive light interference at the vertical edges of extensions 730 are eliminated.

[0030] In FIG. 9, the clear region consists of isolated regions 930. Each region 930 covers a gap 430M (FIG. 4) and may extend beyond the gap vertically and/or horizontally, but regions 930 do not cover the rectangles 410M. During the exposure through mask 140, the radiation dose is 100% of the best dose.

[0031] This design is advantageous because there may be a slight misalignment (about 20 nm for example) between the masks 602 and 140. This misalignment may reduce the contrast along the long edges of rectangles 410M if these edges are exposed twice (as with the masks of FIGS. 6-8).

[0032] With the mask of FIG. 9, the contrast loss is less of a problem, so a higher dose (e.g. more than 50% of the best dose) can be used with mask 602.

[0033] In FIG. 10, regions 930 are merged into strips each of which traverses the array of rectangles 410M and covers one row of gaps 430M. 100% of the best dose is used at step 5 (with mask 140), and more than 50% can be used at step 3. This mask can be faster to write than the mask of FIG. 9. Also, diffraction and destructive light interference are eliminated at the vertical edges of regions 930 compared to FIG. 8.

[0034] The above techniques can be combined with other photolithographic techniques. For example, some or all of the opaque regions can be replaced with partially transmitting non-clear regions. See the aforementioned Handbook of Microlithography, Micromachining, and Microfabrication, volume 1, page 79, incorporated herein by reference. The masks involved can be binary masks, phase shift masks, or other types of masks, known or to be invented. The invention is not limited to any particular mask patterns or dimensions, resist types, exposure doses, wavelengths, or other parameters, or any particular materials or equipment. The invention is not limited to baking and cooling cycles or use of antireflective coatings. The invention is defined by the appended claims.